1*1da177e4SLinus Torvalds /* 2*1da177e4SLinus Torvalds * Copyright (C) 2004 IBM Corporation 3*1da177e4SLinus Torvalds * 4*1da177e4SLinus Torvalds * Authors: 5*1da177e4SLinus Torvalds * Leendert van Doorn <leendert@watson.ibm.com> 6*1da177e4SLinus Torvalds * Dave Safford <safford@watson.ibm.com> 7*1da177e4SLinus Torvalds * Reiner Sailer <sailer@watson.ibm.com> 8*1da177e4SLinus Torvalds * Kylene Hall <kjhall@us.ibm.com> 9*1da177e4SLinus Torvalds * 10*1da177e4SLinus Torvalds * Maintained by: <tpmdd_devel@lists.sourceforge.net> 11*1da177e4SLinus Torvalds * 12*1da177e4SLinus Torvalds * Device driver for TCG/TCPA TPM (trusted platform module). 13*1da177e4SLinus Torvalds * Specifications at www.trustedcomputinggroup.org 14*1da177e4SLinus Torvalds * 15*1da177e4SLinus Torvalds * This program is free software; you can redistribute it and/or 16*1da177e4SLinus Torvalds * modify it under the terms of the GNU General Public License as 17*1da177e4SLinus Torvalds * published by the Free Software Foundation, version 2 of the 18*1da177e4SLinus Torvalds * License. 19*1da177e4SLinus Torvalds * 20*1da177e4SLinus Torvalds */ 21*1da177e4SLinus Torvalds 22*1da177e4SLinus Torvalds #include "tpm.h" 23*1da177e4SLinus Torvalds 24*1da177e4SLinus Torvalds /* National definitions */ 25*1da177e4SLinus Torvalds #define TPM_NSC_BASE 0x360 26*1da177e4SLinus Torvalds #define TPM_NSC_IRQ 0x07 27*1da177e4SLinus Torvalds 28*1da177e4SLinus Torvalds #define NSC_LDN_INDEX 0x07 29*1da177e4SLinus Torvalds #define NSC_SID_INDEX 0x20 30*1da177e4SLinus Torvalds #define NSC_LDC_INDEX 0x30 31*1da177e4SLinus Torvalds #define NSC_DIO_INDEX 0x60 32*1da177e4SLinus Torvalds #define NSC_CIO_INDEX 0x62 33*1da177e4SLinus Torvalds #define NSC_IRQ_INDEX 0x70 34*1da177e4SLinus Torvalds #define NSC_ITS_INDEX 0x71 35*1da177e4SLinus Torvalds 36*1da177e4SLinus Torvalds #define NSC_STATUS 0x01 37*1da177e4SLinus Torvalds #define NSC_COMMAND 0x01 38*1da177e4SLinus Torvalds #define NSC_DATA 0x00 39*1da177e4SLinus Torvalds 40*1da177e4SLinus Torvalds /* status bits */ 41*1da177e4SLinus Torvalds #define NSC_STATUS_OBF 0x01 /* output buffer full */ 42*1da177e4SLinus Torvalds #define NSC_STATUS_IBF 0x02 /* input buffer full */ 43*1da177e4SLinus Torvalds #define NSC_STATUS_F0 0x04 /* F0 */ 44*1da177e4SLinus Torvalds #define NSC_STATUS_A2 0x08 /* A2 */ 45*1da177e4SLinus Torvalds #define NSC_STATUS_RDY 0x10 /* ready to receive command */ 46*1da177e4SLinus Torvalds #define NSC_STATUS_IBR 0x20 /* ready to receive data */ 47*1da177e4SLinus Torvalds 48*1da177e4SLinus Torvalds /* command bits */ 49*1da177e4SLinus Torvalds #define NSC_COMMAND_NORMAL 0x01 /* normal mode */ 50*1da177e4SLinus Torvalds #define NSC_COMMAND_EOC 0x03 51*1da177e4SLinus Torvalds #define NSC_COMMAND_CANCEL 0x22 52*1da177e4SLinus Torvalds 53*1da177e4SLinus Torvalds /* 54*1da177e4SLinus Torvalds * Wait for a certain status to appear 55*1da177e4SLinus Torvalds */ 56*1da177e4SLinus Torvalds static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data) 57*1da177e4SLinus Torvalds { 58*1da177e4SLinus Torvalds int expired = 0; 59*1da177e4SLinus Torvalds struct timer_list status_timer = 60*1da177e4SLinus Torvalds TIMER_INITIALIZER(tpm_time_expired, jiffies + 10 * HZ, 61*1da177e4SLinus Torvalds (unsigned long) &expired); 62*1da177e4SLinus Torvalds 63*1da177e4SLinus Torvalds /* status immediately available check */ 64*1da177e4SLinus Torvalds *data = inb(chip->vendor->base + NSC_STATUS); 65*1da177e4SLinus Torvalds if ((*data & mask) == val) 66*1da177e4SLinus Torvalds return 0; 67*1da177e4SLinus Torvalds 68*1da177e4SLinus Torvalds /* wait for status */ 69*1da177e4SLinus Torvalds add_timer(&status_timer); 70*1da177e4SLinus Torvalds do { 71*1da177e4SLinus Torvalds set_current_state(TASK_UNINTERRUPTIBLE); 72*1da177e4SLinus Torvalds schedule_timeout(TPM_TIMEOUT); 73*1da177e4SLinus Torvalds *data = inb(chip->vendor->base + 1); 74*1da177e4SLinus Torvalds if ((*data & mask) == val) { 75*1da177e4SLinus Torvalds del_singleshot_timer_sync(&status_timer); 76*1da177e4SLinus Torvalds return 0; 77*1da177e4SLinus Torvalds } 78*1da177e4SLinus Torvalds } 79*1da177e4SLinus Torvalds while (!expired); 80*1da177e4SLinus Torvalds 81*1da177e4SLinus Torvalds return -EBUSY; 82*1da177e4SLinus Torvalds } 83*1da177e4SLinus Torvalds 84*1da177e4SLinus Torvalds static int nsc_wait_for_ready(struct tpm_chip *chip) 85*1da177e4SLinus Torvalds { 86*1da177e4SLinus Torvalds int status; 87*1da177e4SLinus Torvalds int expired = 0; 88*1da177e4SLinus Torvalds struct timer_list status_timer = 89*1da177e4SLinus Torvalds TIMER_INITIALIZER(tpm_time_expired, jiffies + 100, 90*1da177e4SLinus Torvalds (unsigned long) &expired); 91*1da177e4SLinus Torvalds 92*1da177e4SLinus Torvalds /* status immediately available check */ 93*1da177e4SLinus Torvalds status = inb(chip->vendor->base + NSC_STATUS); 94*1da177e4SLinus Torvalds if (status & NSC_STATUS_OBF) 95*1da177e4SLinus Torvalds status = inb(chip->vendor->base + NSC_DATA); 96*1da177e4SLinus Torvalds if (status & NSC_STATUS_RDY) 97*1da177e4SLinus Torvalds return 0; 98*1da177e4SLinus Torvalds 99*1da177e4SLinus Torvalds /* wait for status */ 100*1da177e4SLinus Torvalds add_timer(&status_timer); 101*1da177e4SLinus Torvalds do { 102*1da177e4SLinus Torvalds set_current_state(TASK_UNINTERRUPTIBLE); 103*1da177e4SLinus Torvalds schedule_timeout(TPM_TIMEOUT); 104*1da177e4SLinus Torvalds status = inb(chip->vendor->base + NSC_STATUS); 105*1da177e4SLinus Torvalds if (status & NSC_STATUS_OBF) 106*1da177e4SLinus Torvalds status = inb(chip->vendor->base + NSC_DATA); 107*1da177e4SLinus Torvalds if (status & NSC_STATUS_RDY) { 108*1da177e4SLinus Torvalds del_singleshot_timer_sync(&status_timer); 109*1da177e4SLinus Torvalds return 0; 110*1da177e4SLinus Torvalds } 111*1da177e4SLinus Torvalds } 112*1da177e4SLinus Torvalds while (!expired); 113*1da177e4SLinus Torvalds 114*1da177e4SLinus Torvalds dev_info(&chip->pci_dev->dev, "wait for ready failed\n"); 115*1da177e4SLinus Torvalds return -EBUSY; 116*1da177e4SLinus Torvalds } 117*1da177e4SLinus Torvalds 118*1da177e4SLinus Torvalds 119*1da177e4SLinus Torvalds static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count) 120*1da177e4SLinus Torvalds { 121*1da177e4SLinus Torvalds u8 *buffer = buf; 122*1da177e4SLinus Torvalds u8 data, *p; 123*1da177e4SLinus Torvalds u32 size; 124*1da177e4SLinus Torvalds __be32 *native_size; 125*1da177e4SLinus Torvalds 126*1da177e4SLinus Torvalds if (count < 6) 127*1da177e4SLinus Torvalds return -EIO; 128*1da177e4SLinus Torvalds 129*1da177e4SLinus Torvalds if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) { 130*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, "F0 timeout\n"); 131*1da177e4SLinus Torvalds return -EIO; 132*1da177e4SLinus Torvalds } 133*1da177e4SLinus Torvalds if ((data = 134*1da177e4SLinus Torvalds inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_NORMAL) { 135*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, "not in normal mode (0x%x)\n", 136*1da177e4SLinus Torvalds data); 137*1da177e4SLinus Torvalds return -EIO; 138*1da177e4SLinus Torvalds } 139*1da177e4SLinus Torvalds 140*1da177e4SLinus Torvalds /* read the whole packet */ 141*1da177e4SLinus Torvalds for (p = buffer; p < &buffer[count]; p++) { 142*1da177e4SLinus Torvalds if (wait_for_stat 143*1da177e4SLinus Torvalds (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) { 144*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, 145*1da177e4SLinus Torvalds "OBF timeout (while reading data)\n"); 146*1da177e4SLinus Torvalds return -EIO; 147*1da177e4SLinus Torvalds } 148*1da177e4SLinus Torvalds if (data & NSC_STATUS_F0) 149*1da177e4SLinus Torvalds break; 150*1da177e4SLinus Torvalds *p = inb(chip->vendor->base + NSC_DATA); 151*1da177e4SLinus Torvalds } 152*1da177e4SLinus Torvalds 153*1da177e4SLinus Torvalds if ((data & NSC_STATUS_F0) == 0) { 154*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, "F0 not set\n"); 155*1da177e4SLinus Torvalds return -EIO; 156*1da177e4SLinus Torvalds } 157*1da177e4SLinus Torvalds if ((data = inb(chip->vendor->base + NSC_DATA)) != NSC_COMMAND_EOC) { 158*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, 159*1da177e4SLinus Torvalds "expected end of command(0x%x)\n", data); 160*1da177e4SLinus Torvalds return -EIO; 161*1da177e4SLinus Torvalds } 162*1da177e4SLinus Torvalds 163*1da177e4SLinus Torvalds native_size = (__force __be32 *) (buf + 2); 164*1da177e4SLinus Torvalds size = be32_to_cpu(*native_size); 165*1da177e4SLinus Torvalds 166*1da177e4SLinus Torvalds if (count < size) 167*1da177e4SLinus Torvalds return -EIO; 168*1da177e4SLinus Torvalds 169*1da177e4SLinus Torvalds return size; 170*1da177e4SLinus Torvalds } 171*1da177e4SLinus Torvalds 172*1da177e4SLinus Torvalds static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count) 173*1da177e4SLinus Torvalds { 174*1da177e4SLinus Torvalds u8 data; 175*1da177e4SLinus Torvalds int i; 176*1da177e4SLinus Torvalds 177*1da177e4SLinus Torvalds /* 178*1da177e4SLinus Torvalds * If we hit the chip with back to back commands it locks up 179*1da177e4SLinus Torvalds * and never set IBF. Hitting it with this "hammer" seems to 180*1da177e4SLinus Torvalds * fix it. Not sure why this is needed, we followed the flow 181*1da177e4SLinus Torvalds * chart in the manual to the letter. 182*1da177e4SLinus Torvalds */ 183*1da177e4SLinus Torvalds outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND); 184*1da177e4SLinus Torvalds 185*1da177e4SLinus Torvalds if (nsc_wait_for_ready(chip) != 0) 186*1da177e4SLinus Torvalds return -EIO; 187*1da177e4SLinus Torvalds 188*1da177e4SLinus Torvalds if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { 189*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, "IBF timeout\n"); 190*1da177e4SLinus Torvalds return -EIO; 191*1da177e4SLinus Torvalds } 192*1da177e4SLinus Torvalds 193*1da177e4SLinus Torvalds outb(NSC_COMMAND_NORMAL, chip->vendor->base + NSC_COMMAND); 194*1da177e4SLinus Torvalds if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) { 195*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, "IBR timeout\n"); 196*1da177e4SLinus Torvalds return -EIO; 197*1da177e4SLinus Torvalds } 198*1da177e4SLinus Torvalds 199*1da177e4SLinus Torvalds for (i = 0; i < count; i++) { 200*1da177e4SLinus Torvalds if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { 201*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, 202*1da177e4SLinus Torvalds "IBF timeout (while writing data)\n"); 203*1da177e4SLinus Torvalds return -EIO; 204*1da177e4SLinus Torvalds } 205*1da177e4SLinus Torvalds outb(buf[i], chip->vendor->base + NSC_DATA); 206*1da177e4SLinus Torvalds } 207*1da177e4SLinus Torvalds 208*1da177e4SLinus Torvalds if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { 209*1da177e4SLinus Torvalds dev_err(&chip->pci_dev->dev, "IBF timeout\n"); 210*1da177e4SLinus Torvalds return -EIO; 211*1da177e4SLinus Torvalds } 212*1da177e4SLinus Torvalds outb(NSC_COMMAND_EOC, chip->vendor->base + NSC_COMMAND); 213*1da177e4SLinus Torvalds 214*1da177e4SLinus Torvalds return count; 215*1da177e4SLinus Torvalds } 216*1da177e4SLinus Torvalds 217*1da177e4SLinus Torvalds static void tpm_nsc_cancel(struct tpm_chip *chip) 218*1da177e4SLinus Torvalds { 219*1da177e4SLinus Torvalds outb(NSC_COMMAND_CANCEL, chip->vendor->base + NSC_COMMAND); 220*1da177e4SLinus Torvalds } 221*1da177e4SLinus Torvalds 222*1da177e4SLinus Torvalds static struct file_operations nsc_ops = { 223*1da177e4SLinus Torvalds .owner = THIS_MODULE, 224*1da177e4SLinus Torvalds .llseek = no_llseek, 225*1da177e4SLinus Torvalds .open = tpm_open, 226*1da177e4SLinus Torvalds .read = tpm_read, 227*1da177e4SLinus Torvalds .write = tpm_write, 228*1da177e4SLinus Torvalds .release = tpm_release, 229*1da177e4SLinus Torvalds }; 230*1da177e4SLinus Torvalds 231*1da177e4SLinus Torvalds static struct tpm_vendor_specific tpm_nsc = { 232*1da177e4SLinus Torvalds .recv = tpm_nsc_recv, 233*1da177e4SLinus Torvalds .send = tpm_nsc_send, 234*1da177e4SLinus Torvalds .cancel = tpm_nsc_cancel, 235*1da177e4SLinus Torvalds .req_complete_mask = NSC_STATUS_OBF, 236*1da177e4SLinus Torvalds .req_complete_val = NSC_STATUS_OBF, 237*1da177e4SLinus Torvalds .base = TPM_NSC_BASE, 238*1da177e4SLinus Torvalds .miscdev = { .fops = &nsc_ops, }, 239*1da177e4SLinus Torvalds 240*1da177e4SLinus Torvalds }; 241*1da177e4SLinus Torvalds 242*1da177e4SLinus Torvalds static int __devinit tpm_nsc_init(struct pci_dev *pci_dev, 243*1da177e4SLinus Torvalds const struct pci_device_id *pci_id) 244*1da177e4SLinus Torvalds { 245*1da177e4SLinus Torvalds int rc = 0; 246*1da177e4SLinus Torvalds 247*1da177e4SLinus Torvalds if (pci_enable_device(pci_dev)) 248*1da177e4SLinus Torvalds return -EIO; 249*1da177e4SLinus Torvalds 250*1da177e4SLinus Torvalds if (tpm_lpc_bus_init(pci_dev, TPM_NSC_BASE)) { 251*1da177e4SLinus Torvalds rc = -ENODEV; 252*1da177e4SLinus Torvalds goto out_err; 253*1da177e4SLinus Torvalds } 254*1da177e4SLinus Torvalds 255*1da177e4SLinus Torvalds /* verify that it is a National part (SID) */ 256*1da177e4SLinus Torvalds if (tpm_read_index(NSC_SID_INDEX) != 0xEF) { 257*1da177e4SLinus Torvalds rc = -ENODEV; 258*1da177e4SLinus Torvalds goto out_err; 259*1da177e4SLinus Torvalds } 260*1da177e4SLinus Torvalds 261*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, "NSC TPM detected\n"); 262*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, 263*1da177e4SLinus Torvalds "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n", 264*1da177e4SLinus Torvalds tpm_read_index(0x07), tpm_read_index(0x20), 265*1da177e4SLinus Torvalds tpm_read_index(0x27)); 266*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, 267*1da177e4SLinus Torvalds "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n", 268*1da177e4SLinus Torvalds tpm_read_index(0x21), tpm_read_index(0x25), 269*1da177e4SLinus Torvalds tpm_read_index(0x26), tpm_read_index(0x28)); 270*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, "NSC IO Base0 0x%x\n", 271*1da177e4SLinus Torvalds (tpm_read_index(0x60) << 8) | tpm_read_index(0x61)); 272*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, "NSC IO Base1 0x%x\n", 273*1da177e4SLinus Torvalds (tpm_read_index(0x62) << 8) | tpm_read_index(0x63)); 274*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, "NSC Interrupt number and wakeup 0x%x\n", 275*1da177e4SLinus Torvalds tpm_read_index(0x70)); 276*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, "NSC IRQ type select 0x%x\n", 277*1da177e4SLinus Torvalds tpm_read_index(0x71)); 278*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, 279*1da177e4SLinus Torvalds "NSC DMA channel select0 0x%x, select1 0x%x\n", 280*1da177e4SLinus Torvalds tpm_read_index(0x74), tpm_read_index(0x75)); 281*1da177e4SLinus Torvalds dev_dbg(&pci_dev->dev, 282*1da177e4SLinus Torvalds "NSC Config " 283*1da177e4SLinus Torvalds "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 284*1da177e4SLinus Torvalds tpm_read_index(0xF0), tpm_read_index(0xF1), 285*1da177e4SLinus Torvalds tpm_read_index(0xF2), tpm_read_index(0xF3), 286*1da177e4SLinus Torvalds tpm_read_index(0xF4), tpm_read_index(0xF5), 287*1da177e4SLinus Torvalds tpm_read_index(0xF6), tpm_read_index(0xF7), 288*1da177e4SLinus Torvalds tpm_read_index(0xF8), tpm_read_index(0xF9)); 289*1da177e4SLinus Torvalds 290*1da177e4SLinus Torvalds dev_info(&pci_dev->dev, 291*1da177e4SLinus Torvalds "NSC PC21100 TPM revision %d\n", 292*1da177e4SLinus Torvalds tpm_read_index(0x27) & 0x1F); 293*1da177e4SLinus Torvalds 294*1da177e4SLinus Torvalds if (tpm_read_index(NSC_LDC_INDEX) == 0) 295*1da177e4SLinus Torvalds dev_info(&pci_dev->dev, ": NSC TPM not active\n"); 296*1da177e4SLinus Torvalds 297*1da177e4SLinus Torvalds /* select PM channel 1 */ 298*1da177e4SLinus Torvalds tpm_write_index(NSC_LDN_INDEX, 0x12); 299*1da177e4SLinus Torvalds tpm_read_index(NSC_LDN_INDEX); 300*1da177e4SLinus Torvalds 301*1da177e4SLinus Torvalds /* disable the DPM module */ 302*1da177e4SLinus Torvalds tpm_write_index(NSC_LDC_INDEX, 0); 303*1da177e4SLinus Torvalds tpm_read_index(NSC_LDC_INDEX); 304*1da177e4SLinus Torvalds 305*1da177e4SLinus Torvalds /* set the data register base addresses */ 306*1da177e4SLinus Torvalds tpm_write_index(NSC_DIO_INDEX, TPM_NSC_BASE >> 8); 307*1da177e4SLinus Torvalds tpm_write_index(NSC_DIO_INDEX + 1, TPM_NSC_BASE); 308*1da177e4SLinus Torvalds tpm_read_index(NSC_DIO_INDEX); 309*1da177e4SLinus Torvalds tpm_read_index(NSC_DIO_INDEX + 1); 310*1da177e4SLinus Torvalds 311*1da177e4SLinus Torvalds /* set the command register base addresses */ 312*1da177e4SLinus Torvalds tpm_write_index(NSC_CIO_INDEX, (TPM_NSC_BASE + 1) >> 8); 313*1da177e4SLinus Torvalds tpm_write_index(NSC_CIO_INDEX + 1, (TPM_NSC_BASE + 1)); 314*1da177e4SLinus Torvalds tpm_read_index(NSC_DIO_INDEX); 315*1da177e4SLinus Torvalds tpm_read_index(NSC_DIO_INDEX + 1); 316*1da177e4SLinus Torvalds 317*1da177e4SLinus Torvalds /* set the interrupt number to be used for the host interface */ 318*1da177e4SLinus Torvalds tpm_write_index(NSC_IRQ_INDEX, TPM_NSC_IRQ); 319*1da177e4SLinus Torvalds tpm_write_index(NSC_ITS_INDEX, 0x00); 320*1da177e4SLinus Torvalds tpm_read_index(NSC_IRQ_INDEX); 321*1da177e4SLinus Torvalds 322*1da177e4SLinus Torvalds /* enable the DPM module */ 323*1da177e4SLinus Torvalds tpm_write_index(NSC_LDC_INDEX, 0x01); 324*1da177e4SLinus Torvalds tpm_read_index(NSC_LDC_INDEX); 325*1da177e4SLinus Torvalds 326*1da177e4SLinus Torvalds if ((rc = tpm_register_hardware(pci_dev, &tpm_nsc)) < 0) 327*1da177e4SLinus Torvalds goto out_err; 328*1da177e4SLinus Torvalds 329*1da177e4SLinus Torvalds return 0; 330*1da177e4SLinus Torvalds 331*1da177e4SLinus Torvalds out_err: 332*1da177e4SLinus Torvalds pci_disable_device(pci_dev); 333*1da177e4SLinus Torvalds return rc; 334*1da177e4SLinus Torvalds } 335*1da177e4SLinus Torvalds 336*1da177e4SLinus Torvalds static struct pci_device_id tpm_pci_tbl[] __devinitdata = { 337*1da177e4SLinus Torvalds {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0)}, 338*1da177e4SLinus Torvalds {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12)}, 339*1da177e4SLinus Torvalds {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0)}, 340*1da177e4SLinus Torvalds {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12)}, 341*1da177e4SLinus Torvalds {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0)}, 342*1da177e4SLinus Torvalds {PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_LPC)}, 343*1da177e4SLinus Torvalds {0,} 344*1da177e4SLinus Torvalds }; 345*1da177e4SLinus Torvalds 346*1da177e4SLinus Torvalds MODULE_DEVICE_TABLE(pci, tpm_pci_tbl); 347*1da177e4SLinus Torvalds 348*1da177e4SLinus Torvalds static struct pci_driver nsc_pci_driver = { 349*1da177e4SLinus Torvalds .name = "tpm_nsc", 350*1da177e4SLinus Torvalds .id_table = tpm_pci_tbl, 351*1da177e4SLinus Torvalds .probe = tpm_nsc_init, 352*1da177e4SLinus Torvalds .remove = __devexit_p(tpm_remove), 353*1da177e4SLinus Torvalds .suspend = tpm_pm_suspend, 354*1da177e4SLinus Torvalds .resume = tpm_pm_resume, 355*1da177e4SLinus Torvalds }; 356*1da177e4SLinus Torvalds 357*1da177e4SLinus Torvalds static int __init init_nsc(void) 358*1da177e4SLinus Torvalds { 359*1da177e4SLinus Torvalds return pci_register_driver(&nsc_pci_driver); 360*1da177e4SLinus Torvalds } 361*1da177e4SLinus Torvalds 362*1da177e4SLinus Torvalds static void __exit cleanup_nsc(void) 363*1da177e4SLinus Torvalds { 364*1da177e4SLinus Torvalds pci_unregister_driver(&nsc_pci_driver); 365*1da177e4SLinus Torvalds } 366*1da177e4SLinus Torvalds 367*1da177e4SLinus Torvalds module_init(init_nsc); 368*1da177e4SLinus Torvalds module_exit(cleanup_nsc); 369*1da177e4SLinus Torvalds 370*1da177e4SLinus Torvalds MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); 371*1da177e4SLinus Torvalds MODULE_DESCRIPTION("TPM Driver"); 372*1da177e4SLinus Torvalds MODULE_VERSION("2.0"); 373*1da177e4SLinus Torvalds MODULE_LICENSE("GPL"); 374