1 /****************************************************************************** 2 * Nuvoton TPM I2C Device Driver Interface for WPCT301/NPCT501/NPCT6XX, 3 * based on the TCG TPM Interface Spec version 1.2. 4 * Specifications at www.trustedcomputinggroup.org 5 * 6 * Copyright (C) 2011, Nuvoton Technology Corporation. 7 * Dan Morav <dan.morav@nuvoton.com> 8 * Copyright (C) 2013, Obsidian Research Corp. 9 * Jason Gunthorpe <jgunthorpe@obsidianresearch.com> 10 * 11 * This program is free software: you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation, either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see http://www.gnu.org/licenses/>. 23 * 24 * Nuvoton contact information: APC.Support@nuvoton.com 25 *****************************************************************************/ 26 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/moduleparam.h> 30 #include <linux/slab.h> 31 #include <linux/interrupt.h> 32 #include <linux/wait.h> 33 #include <linux/i2c.h> 34 #include <linux/of_device.h> 35 #include "tpm.h" 36 37 /* I2C interface offsets */ 38 #define TPM_STS 0x00 39 #define TPM_BURST_COUNT 0x01 40 #define TPM_DATA_FIFO_W 0x20 41 #define TPM_DATA_FIFO_R 0x40 42 #define TPM_VID_DID_RID 0x60 43 /* TPM command header size */ 44 #define TPM_HEADER_SIZE 10 45 #define TPM_RETRY 5 46 /* 47 * I2C bus device maximum buffer size w/o counting I2C address or command 48 * i.e. max size required for I2C write is 34 = addr, command, 32 bytes data 49 */ 50 #define TPM_I2C_MAX_BUF_SIZE 32 51 #define TPM_I2C_RETRY_COUNT 32 52 #define TPM_I2C_BUS_DELAY 1000 /* usec */ 53 #define TPM_I2C_RETRY_DELAY_SHORT (2 * 1000) /* usec */ 54 #define TPM_I2C_RETRY_DELAY_LONG (10 * 1000) /* usec */ 55 #define TPM_I2C_DELAY_RANGE 300 /* usec */ 56 57 #define OF_IS_TPM2 ((void *)1) 58 #define I2C_IS_TPM2 1 59 60 struct priv_data { 61 int irq; 62 unsigned int intrs; 63 wait_queue_head_t read_queue; 64 }; 65 66 static s32 i2c_nuvoton_read_buf(struct i2c_client *client, u8 offset, u8 size, 67 u8 *data) 68 { 69 s32 status; 70 71 status = i2c_smbus_read_i2c_block_data(client, offset, size, data); 72 dev_dbg(&client->dev, 73 "%s(offset=%u size=%u data=%*ph) -> sts=%d\n", __func__, 74 offset, size, (int)size, data, status); 75 return status; 76 } 77 78 static s32 i2c_nuvoton_write_buf(struct i2c_client *client, u8 offset, u8 size, 79 u8 *data) 80 { 81 s32 status; 82 83 status = i2c_smbus_write_i2c_block_data(client, offset, size, data); 84 dev_dbg(&client->dev, 85 "%s(offset=%u size=%u data=%*ph) -> sts=%d\n", __func__, 86 offset, size, (int)size, data, status); 87 return status; 88 } 89 90 #define TPM_STS_VALID 0x80 91 #define TPM_STS_COMMAND_READY 0x40 92 #define TPM_STS_GO 0x20 93 #define TPM_STS_DATA_AVAIL 0x10 94 #define TPM_STS_EXPECT 0x08 95 #define TPM_STS_RESPONSE_RETRY 0x02 96 #define TPM_STS_ERR_VAL 0x07 /* bit2...bit0 reads always 0 */ 97 98 #define TPM_I2C_SHORT_TIMEOUT 750 /* ms */ 99 #define TPM_I2C_LONG_TIMEOUT 2000 /* 2 sec */ 100 101 /* read TPM_STS register */ 102 static u8 i2c_nuvoton_read_status(struct tpm_chip *chip) 103 { 104 struct i2c_client *client = to_i2c_client(chip->dev.parent); 105 s32 status; 106 u8 data; 107 108 status = i2c_nuvoton_read_buf(client, TPM_STS, 1, &data); 109 if (status <= 0) { 110 dev_err(&chip->dev, "%s() error return %d\n", __func__, 111 status); 112 data = TPM_STS_ERR_VAL; 113 } 114 115 return data; 116 } 117 118 /* write byte to TPM_STS register */ 119 static s32 i2c_nuvoton_write_status(struct i2c_client *client, u8 data) 120 { 121 s32 status; 122 int i; 123 124 /* this causes the current command to be aborted */ 125 for (i = 0, status = -1; i < TPM_I2C_RETRY_COUNT && status < 0; i++) { 126 status = i2c_nuvoton_write_buf(client, TPM_STS, 1, &data); 127 if (status < 0) 128 usleep_range(TPM_I2C_BUS_DELAY, TPM_I2C_BUS_DELAY 129 + TPM_I2C_DELAY_RANGE); 130 } 131 return status; 132 } 133 134 /* write commandReady to TPM_STS register */ 135 static void i2c_nuvoton_ready(struct tpm_chip *chip) 136 { 137 struct i2c_client *client = to_i2c_client(chip->dev.parent); 138 s32 status; 139 140 /* this causes the current command to be aborted */ 141 status = i2c_nuvoton_write_status(client, TPM_STS_COMMAND_READY); 142 if (status < 0) 143 dev_err(&chip->dev, 144 "%s() fail to write TPM_STS.commandReady\n", __func__); 145 } 146 147 /* read burstCount field from TPM_STS register 148 * return -1 on fail to read */ 149 static int i2c_nuvoton_get_burstcount(struct i2c_client *client, 150 struct tpm_chip *chip) 151 { 152 unsigned long stop = jiffies + chip->timeout_d; 153 s32 status; 154 int burst_count = -1; 155 u8 data; 156 157 /* wait for burstcount to be non-zero */ 158 do { 159 /* in I2C burstCount is 1 byte */ 160 status = i2c_nuvoton_read_buf(client, TPM_BURST_COUNT, 1, 161 &data); 162 if (status > 0 && data > 0) { 163 burst_count = min_t(u8, TPM_I2C_MAX_BUF_SIZE, data); 164 break; 165 } 166 usleep_range(TPM_I2C_BUS_DELAY, TPM_I2C_BUS_DELAY 167 + TPM_I2C_DELAY_RANGE); 168 } while (time_before(jiffies, stop)); 169 170 return burst_count; 171 } 172 173 /* 174 * WPCT301/NPCT501/NPCT6XX SINT# supports only dataAvail 175 * any call to this function which is not waiting for dataAvail will 176 * set queue to NULL to avoid waiting for interrupt 177 */ 178 static bool i2c_nuvoton_check_status(struct tpm_chip *chip, u8 mask, u8 value) 179 { 180 u8 status = i2c_nuvoton_read_status(chip); 181 return (status != TPM_STS_ERR_VAL) && ((status & mask) == value); 182 } 183 184 static int i2c_nuvoton_wait_for_stat(struct tpm_chip *chip, u8 mask, u8 value, 185 u32 timeout, wait_queue_head_t *queue) 186 { 187 if ((chip->flags & TPM_CHIP_FLAG_IRQ) && queue) { 188 s32 rc; 189 struct priv_data *priv = dev_get_drvdata(&chip->dev); 190 unsigned int cur_intrs = priv->intrs; 191 192 enable_irq(priv->irq); 193 rc = wait_event_interruptible_timeout(*queue, 194 cur_intrs != priv->intrs, 195 timeout); 196 if (rc > 0) 197 return 0; 198 /* At this point we know that the SINT pin is asserted, so we 199 * do not need to do i2c_nuvoton_check_status */ 200 } else { 201 unsigned long ten_msec, stop; 202 bool status_valid; 203 204 /* check current status */ 205 status_valid = i2c_nuvoton_check_status(chip, mask, value); 206 if (status_valid) 207 return 0; 208 209 /* use polling to wait for the event */ 210 ten_msec = jiffies + usecs_to_jiffies(TPM_I2C_RETRY_DELAY_LONG); 211 stop = jiffies + timeout; 212 do { 213 if (time_before(jiffies, ten_msec)) 214 usleep_range(TPM_I2C_RETRY_DELAY_SHORT, 215 TPM_I2C_RETRY_DELAY_SHORT 216 + TPM_I2C_DELAY_RANGE); 217 else 218 usleep_range(TPM_I2C_RETRY_DELAY_LONG, 219 TPM_I2C_RETRY_DELAY_LONG 220 + TPM_I2C_DELAY_RANGE); 221 status_valid = i2c_nuvoton_check_status(chip, mask, 222 value); 223 if (status_valid) 224 return 0; 225 } while (time_before(jiffies, stop)); 226 } 227 dev_err(&chip->dev, "%s(%02x, %02x) -> timeout\n", __func__, mask, 228 value); 229 return -ETIMEDOUT; 230 } 231 232 /* wait for dataAvail field to be set in the TPM_STS register */ 233 static int i2c_nuvoton_wait_for_data_avail(struct tpm_chip *chip, u32 timeout, 234 wait_queue_head_t *queue) 235 { 236 return i2c_nuvoton_wait_for_stat(chip, 237 TPM_STS_DATA_AVAIL | TPM_STS_VALID, 238 TPM_STS_DATA_AVAIL | TPM_STS_VALID, 239 timeout, queue); 240 } 241 242 /* Read @count bytes into @buf from TPM_RD_FIFO register */ 243 static int i2c_nuvoton_recv_data(struct i2c_client *client, 244 struct tpm_chip *chip, u8 *buf, size_t count) 245 { 246 struct priv_data *priv = dev_get_drvdata(&chip->dev); 247 s32 rc; 248 int burst_count, bytes2read, size = 0; 249 250 while (size < count && 251 i2c_nuvoton_wait_for_data_avail(chip, 252 chip->timeout_c, 253 &priv->read_queue) == 0) { 254 burst_count = i2c_nuvoton_get_burstcount(client, chip); 255 if (burst_count < 0) { 256 dev_err(&chip->dev, 257 "%s() fail to read burstCount=%d\n", __func__, 258 burst_count); 259 return -EIO; 260 } 261 bytes2read = min_t(size_t, burst_count, count - size); 262 rc = i2c_nuvoton_read_buf(client, TPM_DATA_FIFO_R, 263 bytes2read, &buf[size]); 264 if (rc < 0) { 265 dev_err(&chip->dev, 266 "%s() fail on i2c_nuvoton_read_buf()=%d\n", 267 __func__, rc); 268 return -EIO; 269 } 270 dev_dbg(&chip->dev, "%s(%d):", __func__, bytes2read); 271 size += bytes2read; 272 } 273 274 return size; 275 } 276 277 /* Read TPM command results */ 278 static int i2c_nuvoton_recv(struct tpm_chip *chip, u8 *buf, size_t count) 279 { 280 struct priv_data *priv = dev_get_drvdata(&chip->dev); 281 struct device *dev = chip->dev.parent; 282 struct i2c_client *client = to_i2c_client(dev); 283 s32 rc; 284 int expected, status, burst_count, retries, size = 0; 285 286 if (count < TPM_HEADER_SIZE) { 287 i2c_nuvoton_ready(chip); /* return to idle */ 288 dev_err(dev, "%s() count < header size\n", __func__); 289 return -EIO; 290 } 291 for (retries = 0; retries < TPM_RETRY; retries++) { 292 if (retries > 0) { 293 /* if this is not the first trial, set responseRetry */ 294 i2c_nuvoton_write_status(client, 295 TPM_STS_RESPONSE_RETRY); 296 } 297 /* 298 * read first available (> 10 bytes), including: 299 * tag, paramsize, and result 300 */ 301 status = i2c_nuvoton_wait_for_data_avail( 302 chip, chip->timeout_c, &priv->read_queue); 303 if (status != 0) { 304 dev_err(dev, "%s() timeout on dataAvail\n", __func__); 305 size = -ETIMEDOUT; 306 continue; 307 } 308 burst_count = i2c_nuvoton_get_burstcount(client, chip); 309 if (burst_count < 0) { 310 dev_err(dev, "%s() fail to get burstCount\n", __func__); 311 size = -EIO; 312 continue; 313 } 314 size = i2c_nuvoton_recv_data(client, chip, buf, 315 burst_count); 316 if (size < TPM_HEADER_SIZE) { 317 dev_err(dev, "%s() fail to read header\n", __func__); 318 size = -EIO; 319 continue; 320 } 321 /* 322 * convert number of expected bytes field from big endian 32 bit 323 * to machine native 324 */ 325 expected = be32_to_cpu(*(__be32 *) (buf + 2)); 326 if (expected > count) { 327 dev_err(dev, "%s() expected > count\n", __func__); 328 size = -EIO; 329 continue; 330 } 331 rc = i2c_nuvoton_recv_data(client, chip, &buf[size], 332 expected - size); 333 size += rc; 334 if (rc < 0 || size < expected) { 335 dev_err(dev, "%s() fail to read remainder of result\n", 336 __func__); 337 size = -EIO; 338 continue; 339 } 340 if (i2c_nuvoton_wait_for_stat( 341 chip, TPM_STS_VALID | TPM_STS_DATA_AVAIL, 342 TPM_STS_VALID, chip->timeout_c, 343 NULL)) { 344 dev_err(dev, "%s() error left over data\n", __func__); 345 size = -ETIMEDOUT; 346 continue; 347 } 348 break; 349 } 350 i2c_nuvoton_ready(chip); 351 dev_dbg(&chip->dev, "%s() -> %d\n", __func__, size); 352 return size; 353 } 354 355 /* 356 * Send TPM command. 357 * 358 * If interrupts are used (signaled by an irq set in the vendor structure) 359 * tpm.c can skip polling for the data to be available as the interrupt is 360 * waited for here 361 */ 362 static int i2c_nuvoton_send(struct tpm_chip *chip, u8 *buf, size_t len) 363 { 364 struct priv_data *priv = dev_get_drvdata(&chip->dev); 365 struct device *dev = chip->dev.parent; 366 struct i2c_client *client = to_i2c_client(dev); 367 u32 ordinal; 368 size_t count = 0; 369 int burst_count, bytes2write, retries, rc = -EIO; 370 371 for (retries = 0; retries < TPM_RETRY; retries++) { 372 i2c_nuvoton_ready(chip); 373 if (i2c_nuvoton_wait_for_stat(chip, TPM_STS_COMMAND_READY, 374 TPM_STS_COMMAND_READY, 375 chip->timeout_b, NULL)) { 376 dev_err(dev, "%s() timeout on commandReady\n", 377 __func__); 378 rc = -EIO; 379 continue; 380 } 381 rc = 0; 382 while (count < len - 1) { 383 burst_count = i2c_nuvoton_get_burstcount(client, 384 chip); 385 if (burst_count < 0) { 386 dev_err(dev, "%s() fail get burstCount\n", 387 __func__); 388 rc = -EIO; 389 break; 390 } 391 bytes2write = min_t(size_t, burst_count, 392 len - 1 - count); 393 rc = i2c_nuvoton_write_buf(client, TPM_DATA_FIFO_W, 394 bytes2write, &buf[count]); 395 if (rc < 0) { 396 dev_err(dev, "%s() fail i2cWriteBuf\n", 397 __func__); 398 break; 399 } 400 dev_dbg(dev, "%s(%d):", __func__, bytes2write); 401 count += bytes2write; 402 rc = i2c_nuvoton_wait_for_stat(chip, 403 TPM_STS_VALID | 404 TPM_STS_EXPECT, 405 TPM_STS_VALID | 406 TPM_STS_EXPECT, 407 chip->timeout_c, 408 NULL); 409 if (rc < 0) { 410 dev_err(dev, "%s() timeout on Expect\n", 411 __func__); 412 rc = -ETIMEDOUT; 413 break; 414 } 415 } 416 if (rc < 0) 417 continue; 418 419 /* write last byte */ 420 rc = i2c_nuvoton_write_buf(client, TPM_DATA_FIFO_W, 1, 421 &buf[count]); 422 if (rc < 0) { 423 dev_err(dev, "%s() fail to write last byte\n", 424 __func__); 425 rc = -EIO; 426 continue; 427 } 428 dev_dbg(dev, "%s(last): %02x", __func__, buf[count]); 429 rc = i2c_nuvoton_wait_for_stat(chip, 430 TPM_STS_VALID | TPM_STS_EXPECT, 431 TPM_STS_VALID, 432 chip->timeout_c, NULL); 433 if (rc) { 434 dev_err(dev, "%s() timeout on Expect to clear\n", 435 __func__); 436 rc = -ETIMEDOUT; 437 continue; 438 } 439 break; 440 } 441 if (rc < 0) { 442 /* retries == TPM_RETRY */ 443 i2c_nuvoton_ready(chip); 444 return rc; 445 } 446 /* execute the TPM command */ 447 rc = i2c_nuvoton_write_status(client, TPM_STS_GO); 448 if (rc < 0) { 449 dev_err(dev, "%s() fail to write Go\n", __func__); 450 i2c_nuvoton_ready(chip); 451 return rc; 452 } 453 ordinal = be32_to_cpu(*((__be32 *) (buf + 6))); 454 rc = i2c_nuvoton_wait_for_data_avail(chip, 455 tpm_calc_ordinal_duration(chip, 456 ordinal), 457 &priv->read_queue); 458 if (rc) { 459 dev_err(dev, "%s() timeout command duration\n", __func__); 460 i2c_nuvoton_ready(chip); 461 return rc; 462 } 463 464 dev_dbg(dev, "%s() -> %zd\n", __func__, len); 465 return len; 466 } 467 468 static bool i2c_nuvoton_req_canceled(struct tpm_chip *chip, u8 status) 469 { 470 return (status == TPM_STS_COMMAND_READY); 471 } 472 473 static const struct tpm_class_ops tpm_i2c = { 474 .flags = TPM_OPS_AUTO_STARTUP, 475 .status = i2c_nuvoton_read_status, 476 .recv = i2c_nuvoton_recv, 477 .send = i2c_nuvoton_send, 478 .cancel = i2c_nuvoton_ready, 479 .req_complete_mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID, 480 .req_complete_val = TPM_STS_DATA_AVAIL | TPM_STS_VALID, 481 .req_canceled = i2c_nuvoton_req_canceled, 482 }; 483 484 /* The only purpose for the handler is to signal to any waiting threads that 485 * the interrupt is currently being asserted. The driver does not do any 486 * processing triggered by interrupts, and the chip provides no way to mask at 487 * the source (plus that would be slow over I2C). Run the IRQ as a one-shot, 488 * this means it cannot be shared. */ 489 static irqreturn_t i2c_nuvoton_int_handler(int dummy, void *dev_id) 490 { 491 struct tpm_chip *chip = dev_id; 492 struct priv_data *priv = dev_get_drvdata(&chip->dev); 493 494 priv->intrs++; 495 wake_up(&priv->read_queue); 496 disable_irq_nosync(priv->irq); 497 return IRQ_HANDLED; 498 } 499 500 static int get_vid(struct i2c_client *client, u32 *res) 501 { 502 static const u8 vid_did_rid_value[] = { 0x50, 0x10, 0xfe }; 503 u32 temp; 504 s32 rc; 505 506 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) 507 return -ENODEV; 508 rc = i2c_nuvoton_read_buf(client, TPM_VID_DID_RID, 4, (u8 *)&temp); 509 if (rc < 0) 510 return rc; 511 512 /* check WPCT301 values - ignore RID */ 513 if (memcmp(&temp, vid_did_rid_value, sizeof(vid_did_rid_value))) { 514 /* 515 * f/w rev 2.81 has an issue where the VID_DID_RID is not 516 * reporting the right value. so give it another chance at 517 * offset 0x20 (FIFO_W). 518 */ 519 rc = i2c_nuvoton_read_buf(client, TPM_DATA_FIFO_W, 4, 520 (u8 *) (&temp)); 521 if (rc < 0) 522 return rc; 523 524 /* check WPCT301 values - ignore RID */ 525 if (memcmp(&temp, vid_did_rid_value, 526 sizeof(vid_did_rid_value))) 527 return -ENODEV; 528 } 529 530 *res = temp; 531 return 0; 532 } 533 534 static int i2c_nuvoton_probe(struct i2c_client *client, 535 const struct i2c_device_id *id) 536 { 537 int rc; 538 struct tpm_chip *chip; 539 struct device *dev = &client->dev; 540 struct priv_data *priv; 541 u32 vid = 0; 542 543 rc = get_vid(client, &vid); 544 if (rc) 545 return rc; 546 547 dev_info(dev, "VID: %04X DID: %02X RID: %02X\n", (u16) vid, 548 (u8) (vid >> 16), (u8) (vid >> 24)); 549 550 chip = tpmm_chip_alloc(dev, &tpm_i2c); 551 if (IS_ERR(chip)) 552 return PTR_ERR(chip); 553 554 priv = devm_kzalloc(dev, sizeof(struct priv_data), GFP_KERNEL); 555 if (!priv) 556 return -ENOMEM; 557 558 if (dev->of_node) { 559 const struct of_device_id *of_id; 560 561 of_id = of_match_device(dev->driver->of_match_table, dev); 562 if (of_id && of_id->data == OF_IS_TPM2) 563 chip->flags |= TPM_CHIP_FLAG_TPM2; 564 } else 565 if (id->driver_data == I2C_IS_TPM2) 566 chip->flags |= TPM_CHIP_FLAG_TPM2; 567 568 init_waitqueue_head(&priv->read_queue); 569 570 /* Default timeouts */ 571 chip->timeout_a = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT); 572 chip->timeout_b = msecs_to_jiffies(TPM_I2C_LONG_TIMEOUT); 573 chip->timeout_c = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT); 574 chip->timeout_d = msecs_to_jiffies(TPM_I2C_SHORT_TIMEOUT); 575 576 dev_set_drvdata(&chip->dev, priv); 577 578 /* 579 * I2C intfcaps (interrupt capabilitieis) in the chip are hard coded to: 580 * TPM_INTF_INT_LEVEL_LOW | TPM_INTF_DATA_AVAIL_INT 581 * The IRQ should be set in the i2c_board_info (which is done 582 * automatically in of_i2c_register_devices, for device tree users */ 583 priv->irq = client->irq; 584 if (client->irq) { 585 dev_dbg(dev, "%s() priv->irq\n", __func__); 586 rc = devm_request_irq(dev, client->irq, 587 i2c_nuvoton_int_handler, 588 IRQF_TRIGGER_LOW, 589 dev_name(&chip->dev), 590 chip); 591 if (rc) { 592 dev_err(dev, "%s() Unable to request irq: %d for use\n", 593 __func__, priv->irq); 594 priv->irq = 0; 595 } else { 596 chip->flags |= TPM_CHIP_FLAG_IRQ; 597 /* Clear any pending interrupt */ 598 i2c_nuvoton_ready(chip); 599 /* - wait for TPM_STS==0xA0 (stsValid, commandReady) */ 600 rc = i2c_nuvoton_wait_for_stat(chip, 601 TPM_STS_COMMAND_READY, 602 TPM_STS_COMMAND_READY, 603 chip->timeout_b, 604 NULL); 605 if (rc == 0) { 606 /* 607 * TIS is in ready state 608 * write dummy byte to enter reception state 609 * TPM_DATA_FIFO_W <- rc (0) 610 */ 611 rc = i2c_nuvoton_write_buf(client, 612 TPM_DATA_FIFO_W, 613 1, (u8 *) (&rc)); 614 if (rc < 0) 615 return rc; 616 /* TPM_STS <- 0x40 (commandReady) */ 617 i2c_nuvoton_ready(chip); 618 } else { 619 /* 620 * timeout_b reached - command was 621 * aborted. TIS should now be in idle state - 622 * only TPM_STS_VALID should be set 623 */ 624 if (i2c_nuvoton_read_status(chip) != 625 TPM_STS_VALID) 626 return -EIO; 627 } 628 } 629 } 630 631 return tpm_chip_register(chip); 632 } 633 634 static int i2c_nuvoton_remove(struct i2c_client *client) 635 { 636 struct tpm_chip *chip = i2c_get_clientdata(client); 637 638 tpm_chip_unregister(chip); 639 return 0; 640 } 641 642 static const struct i2c_device_id i2c_nuvoton_id[] = { 643 {"tpm_i2c_nuvoton"}, 644 {"tpm2_i2c_nuvoton", .driver_data = I2C_IS_TPM2}, 645 {} 646 }; 647 MODULE_DEVICE_TABLE(i2c, i2c_nuvoton_id); 648 649 #ifdef CONFIG_OF 650 static const struct of_device_id i2c_nuvoton_of_match[] = { 651 {.compatible = "nuvoton,npct501"}, 652 {.compatible = "winbond,wpct301"}, 653 {.compatible = "nuvoton,npct601", .data = OF_IS_TPM2}, 654 {}, 655 }; 656 MODULE_DEVICE_TABLE(of, i2c_nuvoton_of_match); 657 #endif 658 659 static SIMPLE_DEV_PM_OPS(i2c_nuvoton_pm_ops, tpm_pm_suspend, tpm_pm_resume); 660 661 static struct i2c_driver i2c_nuvoton_driver = { 662 .id_table = i2c_nuvoton_id, 663 .probe = i2c_nuvoton_probe, 664 .remove = i2c_nuvoton_remove, 665 .driver = { 666 .name = "tpm_i2c_nuvoton", 667 .pm = &i2c_nuvoton_pm_ops, 668 .of_match_table = of_match_ptr(i2c_nuvoton_of_match), 669 }, 670 }; 671 672 module_i2c_driver(i2c_nuvoton_driver); 673 674 MODULE_AUTHOR("Dan Morav (dan.morav@nuvoton.com)"); 675 MODULE_DESCRIPTION("Nuvoton TPM I2C Driver"); 676 MODULE_LICENSE("GPL"); 677