1 /* 2 * 3 * 3780i.c -- helper routines for the 3780i DSP 4 * 5 * 6 * Written By: Mike Sullivan IBM Corporation 7 * 8 * Copyright (C) 1999 IBM Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 * 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 * 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 43 * 44 * 45 * 10/23/2000 - Alpha Release 46 * First release to the public 47 */ 48 49 #include <linux/config.h> 50 #include <linux/kernel.h> 51 #include <linux/unistd.h> 52 #include <linux/delay.h> 53 #include <linux/ioport.h> 54 #include <linux/init.h> 55 #include <linux/bitops.h> 56 #include <linux/sched.h> /* cond_resched() */ 57 58 #include <asm/io.h> 59 #include <asm/uaccess.h> 60 #include <asm/system.h> 61 #include <asm/irq.h> 62 #include "smapi.h" 63 #include "mwavedd.h" 64 #include "3780i.h" 65 66 static DEFINE_SPINLOCK(dsp_lock); 67 static unsigned long flags; 68 69 70 static void PaceMsaAccess(unsigned short usDspBaseIO) 71 { 72 cond_resched(); 73 udelay(100); 74 cond_resched(); 75 } 76 77 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO, 78 unsigned long ulMsaAddr) 79 { 80 unsigned short val; 81 82 PRINTK_3(TRACE_3780I, 83 "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n", 84 usDspBaseIO, ulMsaAddr); 85 86 spin_lock_irqsave(&dsp_lock, flags); 87 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); 88 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); 89 val = InWordDsp(DSP_MsaDataDSISHigh); 90 spin_unlock_irqrestore(&dsp_lock, flags); 91 92 PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val); 93 94 return val; 95 } 96 97 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO, 98 unsigned long ulMsaAddr, unsigned short usValue) 99 { 100 101 PRINTK_4(TRACE_3780I, 102 "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n", 103 usDspBaseIO, ulMsaAddr, usValue); 104 105 spin_lock_irqsave(&dsp_lock, flags); 106 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); 107 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); 108 OutWordDsp(DSP_MsaDataDSISHigh, usValue); 109 spin_unlock_irqrestore(&dsp_lock, flags); 110 } 111 112 static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex, 113 unsigned char ucValue) 114 { 115 DSP_ISA_SLAVE_CONTROL rSlaveControl; 116 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; 117 118 119 PRINTK_4(TRACE_3780I, 120 "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n", 121 usDspBaseIO, uIndex, ucValue); 122 123 MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); 124 125 PRINTK_2(TRACE_3780I, 126 "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n", 127 MKBYTE(rSlaveControl)); 128 129 rSlaveControl_Save = rSlaveControl; 130 rSlaveControl.ConfigMode = TRUE; 131 132 PRINTK_2(TRACE_3780I, 133 "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n", 134 MKBYTE(rSlaveControl)); 135 136 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); 137 OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); 138 OutByteDsp(DSP_ConfigData, ucValue); 139 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); 140 141 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n"); 142 143 144 } 145 146 #if 0 147 unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO, 148 unsigned uIndex) 149 { 150 DSP_ISA_SLAVE_CONTROL rSlaveControl; 151 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; 152 unsigned char ucValue; 153 154 155 PRINTK_3(TRACE_3780I, 156 "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n", 157 usDspBaseIO, uIndex); 158 159 MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); 160 rSlaveControl_Save = rSlaveControl; 161 rSlaveControl.ConfigMode = TRUE; 162 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); 163 OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); 164 ucValue = InByteDsp(DSP_ConfigData); 165 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); 166 167 PRINTK_2(TRACE_3780I, 168 "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue); 169 170 171 return ucValue; 172 } 173 #endif /* 0 */ 174 175 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, 176 unsigned short *pIrqMap, 177 unsigned short *pDmaMap) 178 { 179 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 180 int i; 181 DSP_UART_CFG_1 rUartCfg1; 182 DSP_UART_CFG_2 rUartCfg2; 183 DSP_HBRIDGE_CFG_1 rHBridgeCfg1; 184 DSP_HBRIDGE_CFG_2 rHBridgeCfg2; 185 DSP_BUSMASTER_CFG_1 rBusmasterCfg1; 186 DSP_BUSMASTER_CFG_2 rBusmasterCfg2; 187 DSP_ISA_PROT_CFG rIsaProtCfg; 188 DSP_POWER_MGMT_CFG rPowerMgmtCfg; 189 DSP_HBUS_TIMER_CFG rHBusTimerCfg; 190 DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable; 191 DSP_CHIP_RESET rChipReset; 192 DSP_CLOCK_CONTROL_1 rClockControl1; 193 DSP_CLOCK_CONTROL_2 rClockControl2; 194 DSP_ISA_SLAVE_CONTROL rSlaveControl; 195 DSP_HBRIDGE_CONTROL rHBridgeControl; 196 unsigned short ChipID = 0; 197 unsigned short tval; 198 199 200 PRINTK_2(TRACE_3780I, 201 "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n", 202 pSettings->bDSPEnabled); 203 204 205 if (!pSettings->bDSPEnabled) { 206 PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" ); 207 return -EIO; 208 } 209 210 211 PRINTK_2(TRACE_3780I, 212 "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n", 213 pSettings->bModemEnabled); 214 215 if (pSettings->bModemEnabled) { 216 rUartCfg1.Reserved = rUartCfg2.Reserved = 0; 217 rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow; 218 rUartCfg1.IrqPulse = pSettings->bUartIrqPulse; 219 rUartCfg1.Irq = 220 (unsigned char) pIrqMap[pSettings->usUartIrq]; 221 switch (pSettings->usUartBaseIO) { 222 case 0x03F8: 223 rUartCfg1.BaseIO = 0; 224 break; 225 case 0x02F8: 226 rUartCfg1.BaseIO = 1; 227 break; 228 case 0x03E8: 229 rUartCfg1.BaseIO = 2; 230 break; 231 case 0x02E8: 232 rUartCfg1.BaseIO = 3; 233 break; 234 } 235 rUartCfg2.Enable = TRUE; 236 } 237 238 rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0; 239 rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow; 240 rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse; 241 rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq]; 242 rHBridgeCfg1.AccessMode = 1; 243 rHBridgeCfg2.Enable = TRUE; 244 245 246 rBusmasterCfg2.Reserved = 0; 247 rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma]; 248 rBusmasterCfg1.NumTransfers = 249 (unsigned char) pSettings->usNumTransfers; 250 rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest; 251 rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16; 252 rBusmasterCfg2.IsaMemCmdWidth = 253 (unsigned char) pSettings->usIsaMemCmdWidth; 254 255 256 rIsaProtCfg.Reserved = 0; 257 rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY; 258 259 rPowerMgmtCfg.Reserved = 0; 260 rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt; 261 262 rHBusTimerCfg.LoadValue = 263 (unsigned char) pSettings->usHBusTimerLoadValue; 264 265 rLBusTimeoutDisable.Reserved = 0; 266 rLBusTimeoutDisable.DisableTimeout = 267 pSettings->bDisableLBusTimeout; 268 269 MKWORD(rChipReset) = ~pSettings->usChipletEnable; 270 271 rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0; 272 rClockControl1.N_Divisor = pSettings->usN_Divisor; 273 rClockControl1.M_Multiplier = pSettings->usM_Multiplier; 274 275 rClockControl2.Reserved = 0; 276 rClockControl2.PllBypass = pSettings->bPllBypass; 277 278 /* Issue a soft reset to the chip */ 279 /* Note: Since we may be coming in with 3780i clocks suspended, we must keep 280 * soft-reset active for 10ms. 281 */ 282 rSlaveControl.ClockControl = 0; 283 rSlaveControl.SoftReset = TRUE; 284 rSlaveControl.ConfigMode = FALSE; 285 rSlaveControl.Reserved = 0; 286 287 PRINTK_4(TRACE_3780I, 288 "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n", 289 usDspBaseIO, DSP_IsaSlaveControl, 290 usDspBaseIO + DSP_IsaSlaveControl); 291 292 PRINTK_2(TRACE_3780I, 293 "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n", 294 MKWORD(rSlaveControl)); 295 296 spin_lock_irqsave(&dsp_lock, flags); 297 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 298 MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); 299 300 PRINTK_2(TRACE_3780I, 301 "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval); 302 303 304 for (i = 0; i < 11; i++) 305 udelay(2000); 306 307 rSlaveControl.SoftReset = FALSE; 308 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 309 310 MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); 311 312 PRINTK_2(TRACE_3780I, 313 "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval); 314 315 316 /* Program our general configuration registers */ 317 WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1)); 318 WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2)); 319 WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1)); 320 WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2)); 321 WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg)); 322 WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg)); 323 WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg)); 324 325 if (pSettings->bModemEnabled) { 326 WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1)); 327 WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2)); 328 } 329 330 331 rHBridgeControl.EnableDspInt = FALSE; 332 rHBridgeControl.MemAutoInc = TRUE; 333 rHBridgeControl.IoAutoInc = FALSE; 334 rHBridgeControl.DiagnosticMode = FALSE; 335 336 PRINTK_3(TRACE_3780I, 337 "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n", 338 DSP_HBridgeControl, MKWORD(rHBridgeControl)); 339 340 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 341 spin_unlock_irqrestore(&dsp_lock, flags); 342 WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable)); 343 WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1)); 344 WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2)); 345 WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset)); 346 347 ChipID = ReadMsaCfg(DSP_ChipID); 348 349 PRINTK_2(TRACE_3780I, 350 "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n", 351 ChipID); 352 353 return 0; 354 } 355 356 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) 357 { 358 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 359 DSP_ISA_SLAVE_CONTROL rSlaveControl; 360 361 362 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n"); 363 364 rSlaveControl.ClockControl = 0; 365 rSlaveControl.SoftReset = TRUE; 366 rSlaveControl.ConfigMode = FALSE; 367 rSlaveControl.Reserved = 0; 368 spin_lock_irqsave(&dsp_lock, flags); 369 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 370 371 udelay(5); 372 373 rSlaveControl.ClockControl = 1; 374 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 375 spin_unlock_irqrestore(&dsp_lock, flags); 376 377 udelay(5); 378 379 380 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n"); 381 382 return 0; 383 } 384 385 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) 386 { 387 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 388 DSP_BOOT_DOMAIN rBootDomain; 389 DSP_HBRIDGE_CONTROL rHBridgeControl; 390 391 392 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n"); 393 394 spin_lock_irqsave(&dsp_lock, flags); 395 /* Mask DSP to PC interrupt */ 396 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); 397 398 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n", 399 MKWORD(rHBridgeControl)); 400 401 rHBridgeControl.EnableDspInt = FALSE; 402 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 403 spin_unlock_irqrestore(&dsp_lock, flags); 404 405 /* Reset the core via the boot domain register */ 406 rBootDomain.ResetCore = TRUE; 407 rBootDomain.Halt = TRUE; 408 rBootDomain.NMI = TRUE; 409 rBootDomain.Reserved = 0; 410 411 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n", 412 MKWORD(rBootDomain)); 413 414 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 415 416 /* Reset all the chiplets and then reactivate them */ 417 WriteMsaCfg(DSP_ChipReset, 0xFFFF); 418 udelay(5); 419 WriteMsaCfg(DSP_ChipReset, 420 (unsigned short) (~pSettings->usChipletEnable)); 421 422 423 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n"); 424 425 return 0; 426 } 427 428 429 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) 430 { 431 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 432 DSP_BOOT_DOMAIN rBootDomain; 433 DSP_HBRIDGE_CONTROL rHBridgeControl; 434 435 436 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n"); 437 438 439 /* Transition the core to a running state */ 440 rBootDomain.ResetCore = TRUE; 441 rBootDomain.Halt = FALSE; 442 rBootDomain.NMI = TRUE; 443 rBootDomain.Reserved = 0; 444 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 445 446 udelay(5); 447 448 rBootDomain.ResetCore = FALSE; 449 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 450 udelay(5); 451 452 rBootDomain.NMI = FALSE; 453 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 454 udelay(5); 455 456 /* Enable DSP to PC interrupt */ 457 spin_lock_irqsave(&dsp_lock, flags); 458 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); 459 rHBridgeControl.EnableDspInt = TRUE; 460 461 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n", 462 MKWORD(rHBridgeControl)); 463 464 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 465 spin_unlock_irqrestore(&dsp_lock, flags); 466 467 468 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n"); 469 470 return 0; 471 } 472 473 474 int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer, 475 unsigned uCount, unsigned long ulDSPAddr) 476 { 477 unsigned short __user *pusBuffer = pvBuffer; 478 unsigned short val; 479 480 481 PRINTK_5(TRACE_3780I, 482 "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 483 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 484 485 486 /* Set the initial MSA address. No adjustments need to be made to data store addresses */ 487 spin_lock_irqsave(&dsp_lock, flags); 488 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 489 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 490 spin_unlock_irqrestore(&dsp_lock, flags); 491 492 /* Transfer the memory block */ 493 while (uCount-- != 0) { 494 spin_lock_irqsave(&dsp_lock, flags); 495 val = InWordDsp(DSP_MsaDataDSISHigh); 496 spin_unlock_irqrestore(&dsp_lock, flags); 497 if(put_user(val, pusBuffer++)) 498 return -EFAULT; 499 500 PRINTK_3(TRACE_3780I, 501 "3780I::dsp3780I_ReadDStore uCount %x val %x\n", 502 uCount, val); 503 504 PaceMsaAccess(usDspBaseIO); 505 } 506 507 508 PRINTK_1(TRACE_3780I, 509 "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n"); 510 511 return 0; 512 } 513 514 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, 515 void __user *pvBuffer, unsigned uCount, 516 unsigned long ulDSPAddr) 517 { 518 unsigned short __user *pusBuffer = pvBuffer; 519 unsigned short val; 520 521 522 PRINTK_5(TRACE_3780I, 523 "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 524 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 525 526 527 /* Set the initial MSA address. No adjustments need to be made to data store addresses */ 528 spin_lock_irqsave(&dsp_lock, flags); 529 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 530 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 531 spin_unlock_irqrestore(&dsp_lock, flags); 532 533 /* Transfer the memory block */ 534 while (uCount-- != 0) { 535 spin_lock_irqsave(&dsp_lock, flags); 536 val = InWordDsp(DSP_ReadAndClear); 537 spin_unlock_irqrestore(&dsp_lock, flags); 538 if(put_user(val, pusBuffer++)) 539 return -EFAULT; 540 541 PRINTK_3(TRACE_3780I, 542 "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n", 543 uCount, val); 544 545 PaceMsaAccess(usDspBaseIO); 546 } 547 548 549 PRINTK_1(TRACE_3780I, 550 "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n"); 551 552 return 0; 553 } 554 555 556 int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer, 557 unsigned uCount, unsigned long ulDSPAddr) 558 { 559 unsigned short __user *pusBuffer = pvBuffer; 560 561 562 PRINTK_5(TRACE_3780I, 563 "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 564 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 565 566 567 /* Set the initial MSA address. No adjustments need to be made to data store addresses */ 568 spin_lock_irqsave(&dsp_lock, flags); 569 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 570 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 571 spin_unlock_irqrestore(&dsp_lock, flags); 572 573 /* Transfer the memory block */ 574 while (uCount-- != 0) { 575 unsigned short val; 576 if(get_user(val, pusBuffer++)) 577 return -EFAULT; 578 spin_lock_irqsave(&dsp_lock, flags); 579 OutWordDsp(DSP_MsaDataDSISHigh, val); 580 spin_unlock_irqrestore(&dsp_lock, flags); 581 582 PRINTK_3(TRACE_3780I, 583 "3780I::dsp3780I_WriteDStore uCount %x val %x\n", 584 uCount, val); 585 586 PaceMsaAccess(usDspBaseIO); 587 } 588 589 590 PRINTK_1(TRACE_3780I, 591 "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n"); 592 593 return 0; 594 } 595 596 597 int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer, 598 unsigned uCount, unsigned long ulDSPAddr) 599 { 600 unsigned short __user *pusBuffer = pvBuffer; 601 602 PRINTK_5(TRACE_3780I, 603 "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 604 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 605 606 /* 607 * Set the initial MSA address. To convert from an instruction store 608 * address to an MSA address 609 * shift the address two bits to the left and set bit 22 610 */ 611 ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); 612 spin_lock_irqsave(&dsp_lock, flags); 613 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 614 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 615 spin_unlock_irqrestore(&dsp_lock, flags); 616 617 /* Transfer the memory block */ 618 while (uCount-- != 0) { 619 unsigned short val_lo, val_hi; 620 spin_lock_irqsave(&dsp_lock, flags); 621 val_lo = InWordDsp(DSP_MsaDataISLow); 622 val_hi = InWordDsp(DSP_MsaDataDSISHigh); 623 spin_unlock_irqrestore(&dsp_lock, flags); 624 if(put_user(val_lo, pusBuffer++)) 625 return -EFAULT; 626 if(put_user(val_hi, pusBuffer++)) 627 return -EFAULT; 628 629 PRINTK_4(TRACE_3780I, 630 "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n", 631 uCount, val_lo, val_hi); 632 633 PaceMsaAccess(usDspBaseIO); 634 635 } 636 637 PRINTK_1(TRACE_3780I, 638 "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n"); 639 640 return 0; 641 } 642 643 644 int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, 645 unsigned uCount, unsigned long ulDSPAddr) 646 { 647 unsigned short __user *pusBuffer = pvBuffer; 648 649 PRINTK_5(TRACE_3780I, 650 "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 651 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 652 653 654 /* 655 * Set the initial MSA address. To convert from an instruction store 656 * address to an MSA address 657 * shift the address two bits to the left and set bit 22 658 */ 659 ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); 660 spin_lock_irqsave(&dsp_lock, flags); 661 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 662 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 663 spin_unlock_irqrestore(&dsp_lock, flags); 664 665 /* Transfer the memory block */ 666 while (uCount-- != 0) { 667 unsigned short val_lo, val_hi; 668 if(get_user(val_lo, pusBuffer++)) 669 return -EFAULT; 670 if(get_user(val_hi, pusBuffer++)) 671 return -EFAULT; 672 spin_lock_irqsave(&dsp_lock, flags); 673 OutWordDsp(DSP_MsaDataISLow, val_lo); 674 OutWordDsp(DSP_MsaDataDSISHigh, val_hi); 675 spin_unlock_irqrestore(&dsp_lock, flags); 676 677 PRINTK_4(TRACE_3780I, 678 "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n", 679 uCount, val_lo, val_hi); 680 681 PaceMsaAccess(usDspBaseIO); 682 683 } 684 685 PRINTK_1(TRACE_3780I, 686 "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n"); 687 688 return 0; 689 } 690 691 692 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO, 693 unsigned short *pusIPCSource) 694 { 695 DSP_HBRIDGE_CONTROL rHBridgeControl; 696 unsigned short temp; 697 698 699 PRINTK_3(TRACE_3780I, 700 "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n", 701 usDspBaseIO, pusIPCSource); 702 703 /* 704 * Disable DSP to PC interrupts, read the interrupt register, 705 * clear the pending IPC bits, and reenable DSP to PC interrupts 706 */ 707 spin_lock_irqsave(&dsp_lock, flags); 708 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); 709 rHBridgeControl.EnableDspInt = FALSE; 710 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 711 712 *pusIPCSource = InWordDsp(DSP_Interrupt); 713 temp = (unsigned short) ~(*pusIPCSource); 714 715 PRINTK_3(TRACE_3780I, 716 "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n", 717 *pusIPCSource, temp); 718 719 OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource)); 720 721 rHBridgeControl.EnableDspInt = TRUE; 722 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 723 spin_unlock_irqrestore(&dsp_lock, flags); 724 725 726 PRINTK_2(TRACE_3780I, 727 "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n", 728 *pusIPCSource); 729 730 return 0; 731 } 732