1 /* 2 * 3 * 3780i.c -- helper routines for the 3780i DSP 4 * 5 * 6 * Written By: Mike Sullivan IBM Corporation 7 * 8 * Copyright (C) 1999 IBM Corporation 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * NO WARRANTY 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is 25 * solely responsible for determining the appropriateness of using and 26 * distributing the Program and assumes all risks associated with its 27 * exercise of rights under this Agreement, including but not limited to 28 * the risks and costs of program errors, damage to or loss of data, 29 * programs or equipment, and unavailability or interruption of operations. 30 * 31 * DISCLAIMER OF LIABILITY 32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY 33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND 35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED 38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES 39 * 40 * You should have received a copy of the GNU General Public License 41 * along with this program; if not, write to the Free Software 42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 43 * 44 * 45 * 10/23/2000 - Alpha Release 46 * First release to the public 47 */ 48 49 #include <linux/kernel.h> 50 #include <linux/unistd.h> 51 #include <linux/delay.h> 52 #include <linux/ioport.h> 53 #include <linux/init.h> 54 #include <linux/bitops.h> 55 #include <linux/sched.h> /* cond_resched() */ 56 57 #include <asm/io.h> 58 #include <asm/uaccess.h> 59 #include <asm/system.h> 60 #include <asm/irq.h> 61 #include "smapi.h" 62 #include "mwavedd.h" 63 #include "3780i.h" 64 65 static DEFINE_SPINLOCK(dsp_lock); 66 static unsigned long flags; 67 68 69 static void PaceMsaAccess(unsigned short usDspBaseIO) 70 { 71 cond_resched(); 72 udelay(100); 73 cond_resched(); 74 } 75 76 unsigned short dsp3780I_ReadMsaCfg(unsigned short usDspBaseIO, 77 unsigned long ulMsaAddr) 78 { 79 unsigned short val; 80 81 PRINTK_3(TRACE_3780I, 82 "3780i::dsp3780I_ReadMsaCfg entry usDspBaseIO %x ulMsaAddr %lx\n", 83 usDspBaseIO, ulMsaAddr); 84 85 spin_lock_irqsave(&dsp_lock, flags); 86 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); 87 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); 88 val = InWordDsp(DSP_MsaDataDSISHigh); 89 spin_unlock_irqrestore(&dsp_lock, flags); 90 91 PRINTK_2(TRACE_3780I, "3780i::dsp3780I_ReadMsaCfg exit val %x\n", val); 92 93 return val; 94 } 95 96 void dsp3780I_WriteMsaCfg(unsigned short usDspBaseIO, 97 unsigned long ulMsaAddr, unsigned short usValue) 98 { 99 100 PRINTK_4(TRACE_3780I, 101 "3780i::dsp3780i_WriteMsaCfg entry usDspBaseIO %x ulMsaAddr %lx usValue %x\n", 102 usDspBaseIO, ulMsaAddr, usValue); 103 104 spin_lock_irqsave(&dsp_lock, flags); 105 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulMsaAddr); 106 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulMsaAddr >> 16)); 107 OutWordDsp(DSP_MsaDataDSISHigh, usValue); 108 spin_unlock_irqrestore(&dsp_lock, flags); 109 } 110 111 static void dsp3780I_WriteGenCfg(unsigned short usDspBaseIO, unsigned uIndex, 112 unsigned char ucValue) 113 { 114 DSP_ISA_SLAVE_CONTROL rSlaveControl; 115 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; 116 117 118 PRINTK_4(TRACE_3780I, 119 "3780i::dsp3780i_WriteGenCfg entry usDspBaseIO %x uIndex %x ucValue %x\n", 120 usDspBaseIO, uIndex, ucValue); 121 122 MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); 123 124 PRINTK_2(TRACE_3780I, 125 "3780i::dsp3780i_WriteGenCfg rSlaveControl %x\n", 126 MKBYTE(rSlaveControl)); 127 128 rSlaveControl_Save = rSlaveControl; 129 rSlaveControl.ConfigMode = TRUE; 130 131 PRINTK_2(TRACE_3780I, 132 "3780i::dsp3780i_WriteGenCfg entry rSlaveControl+ConfigMode %x\n", 133 MKBYTE(rSlaveControl)); 134 135 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); 136 OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); 137 OutByteDsp(DSP_ConfigData, ucValue); 138 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); 139 140 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_WriteGenCfg exit\n"); 141 142 143 } 144 145 #if 0 146 unsigned char dsp3780I_ReadGenCfg(unsigned short usDspBaseIO, 147 unsigned uIndex) 148 { 149 DSP_ISA_SLAVE_CONTROL rSlaveControl; 150 DSP_ISA_SLAVE_CONTROL rSlaveControl_Save; 151 unsigned char ucValue; 152 153 154 PRINTK_3(TRACE_3780I, 155 "3780i::dsp3780i_ReadGenCfg entry usDspBaseIO %x uIndex %x\n", 156 usDspBaseIO, uIndex); 157 158 MKBYTE(rSlaveControl) = InByteDsp(DSP_IsaSlaveControl); 159 rSlaveControl_Save = rSlaveControl; 160 rSlaveControl.ConfigMode = TRUE; 161 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl)); 162 OutByteDsp(DSP_ConfigAddress, (unsigned char) uIndex); 163 ucValue = InByteDsp(DSP_ConfigData); 164 OutByteDsp(DSP_IsaSlaveControl, MKBYTE(rSlaveControl_Save)); 165 166 PRINTK_2(TRACE_3780I, 167 "3780i::dsp3780i_ReadGenCfg exit ucValue %x\n", ucValue); 168 169 170 return ucValue; 171 } 172 #endif /* 0 */ 173 174 int dsp3780I_EnableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings, 175 unsigned short *pIrqMap, 176 unsigned short *pDmaMap) 177 { 178 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 179 int i; 180 DSP_UART_CFG_1 rUartCfg1; 181 DSP_UART_CFG_2 rUartCfg2; 182 DSP_HBRIDGE_CFG_1 rHBridgeCfg1; 183 DSP_HBRIDGE_CFG_2 rHBridgeCfg2; 184 DSP_BUSMASTER_CFG_1 rBusmasterCfg1; 185 DSP_BUSMASTER_CFG_2 rBusmasterCfg2; 186 DSP_ISA_PROT_CFG rIsaProtCfg; 187 DSP_POWER_MGMT_CFG rPowerMgmtCfg; 188 DSP_HBUS_TIMER_CFG rHBusTimerCfg; 189 DSP_LBUS_TIMEOUT_DISABLE rLBusTimeoutDisable; 190 DSP_CHIP_RESET rChipReset; 191 DSP_CLOCK_CONTROL_1 rClockControl1; 192 DSP_CLOCK_CONTROL_2 rClockControl2; 193 DSP_ISA_SLAVE_CONTROL rSlaveControl; 194 DSP_HBRIDGE_CONTROL rHBridgeControl; 195 unsigned short ChipID = 0; 196 unsigned short tval; 197 198 199 PRINTK_2(TRACE_3780I, 200 "3780i::dsp3780I_EnableDSP entry pSettings->bDSPEnabled %x\n", 201 pSettings->bDSPEnabled); 202 203 204 if (!pSettings->bDSPEnabled) { 205 PRINTK_ERROR( KERN_ERR "3780i::dsp3780I_EnableDSP: Error: DSP not enabled. Aborting.\n" ); 206 return -EIO; 207 } 208 209 210 PRINTK_2(TRACE_3780I, 211 "3780i::dsp3780i_EnableDSP entry pSettings->bModemEnabled %x\n", 212 pSettings->bModemEnabled); 213 214 if (pSettings->bModemEnabled) { 215 rUartCfg1.Reserved = rUartCfg2.Reserved = 0; 216 rUartCfg1.IrqActiveLow = pSettings->bUartIrqActiveLow; 217 rUartCfg1.IrqPulse = pSettings->bUartIrqPulse; 218 rUartCfg1.Irq = 219 (unsigned char) pIrqMap[pSettings->usUartIrq]; 220 switch (pSettings->usUartBaseIO) { 221 case 0x03F8: 222 rUartCfg1.BaseIO = 0; 223 break; 224 case 0x02F8: 225 rUartCfg1.BaseIO = 1; 226 break; 227 case 0x03E8: 228 rUartCfg1.BaseIO = 2; 229 break; 230 case 0x02E8: 231 rUartCfg1.BaseIO = 3; 232 break; 233 } 234 rUartCfg2.Enable = TRUE; 235 } 236 237 rHBridgeCfg1.Reserved = rHBridgeCfg2.Reserved = 0; 238 rHBridgeCfg1.IrqActiveLow = pSettings->bDspIrqActiveLow; 239 rHBridgeCfg1.IrqPulse = pSettings->bDspIrqPulse; 240 rHBridgeCfg1.Irq = (unsigned char) pIrqMap[pSettings->usDspIrq]; 241 rHBridgeCfg1.AccessMode = 1; 242 rHBridgeCfg2.Enable = TRUE; 243 244 245 rBusmasterCfg2.Reserved = 0; 246 rBusmasterCfg1.Dma = (unsigned char) pDmaMap[pSettings->usDspDma]; 247 rBusmasterCfg1.NumTransfers = 248 (unsigned char) pSettings->usNumTransfers; 249 rBusmasterCfg1.ReRequest = (unsigned char) pSettings->usReRequest; 250 rBusmasterCfg1.MEMCS16 = pSettings->bEnableMEMCS16; 251 rBusmasterCfg2.IsaMemCmdWidth = 252 (unsigned char) pSettings->usIsaMemCmdWidth; 253 254 255 rIsaProtCfg.Reserved = 0; 256 rIsaProtCfg.GateIOCHRDY = pSettings->bGateIOCHRDY; 257 258 rPowerMgmtCfg.Reserved = 0; 259 rPowerMgmtCfg.Enable = pSettings->bEnablePwrMgmt; 260 261 rHBusTimerCfg.LoadValue = 262 (unsigned char) pSettings->usHBusTimerLoadValue; 263 264 rLBusTimeoutDisable.Reserved = 0; 265 rLBusTimeoutDisable.DisableTimeout = 266 pSettings->bDisableLBusTimeout; 267 268 MKWORD(rChipReset) = ~pSettings->usChipletEnable; 269 270 rClockControl1.Reserved1 = rClockControl1.Reserved2 = 0; 271 rClockControl1.N_Divisor = pSettings->usN_Divisor; 272 rClockControl1.M_Multiplier = pSettings->usM_Multiplier; 273 274 rClockControl2.Reserved = 0; 275 rClockControl2.PllBypass = pSettings->bPllBypass; 276 277 /* Issue a soft reset to the chip */ 278 /* Note: Since we may be coming in with 3780i clocks suspended, we must keep 279 * soft-reset active for 10ms. 280 */ 281 rSlaveControl.ClockControl = 0; 282 rSlaveControl.SoftReset = TRUE; 283 rSlaveControl.ConfigMode = FALSE; 284 rSlaveControl.Reserved = 0; 285 286 PRINTK_4(TRACE_3780I, 287 "3780i::dsp3780i_EnableDSP usDspBaseIO %x index %x taddr %x\n", 288 usDspBaseIO, DSP_IsaSlaveControl, 289 usDspBaseIO + DSP_IsaSlaveControl); 290 291 PRINTK_2(TRACE_3780I, 292 "3780i::dsp3780i_EnableDSP rSlaveContrl %x\n", 293 MKWORD(rSlaveControl)); 294 295 spin_lock_irqsave(&dsp_lock, flags); 296 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 297 MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); 298 299 PRINTK_2(TRACE_3780I, 300 "3780i::dsp3780i_EnableDSP rSlaveControl 2 %x\n", tval); 301 302 303 for (i = 0; i < 11; i++) 304 udelay(2000); 305 306 rSlaveControl.SoftReset = FALSE; 307 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 308 309 MKWORD(tval) = InWordDsp(DSP_IsaSlaveControl); 310 311 PRINTK_2(TRACE_3780I, 312 "3780i::dsp3780i_EnableDSP rSlaveControl 3 %x\n", tval); 313 314 315 /* Program our general configuration registers */ 316 WriteGenCfg(DSP_HBridgeCfg1Index, MKBYTE(rHBridgeCfg1)); 317 WriteGenCfg(DSP_HBridgeCfg2Index, MKBYTE(rHBridgeCfg2)); 318 WriteGenCfg(DSP_BusMasterCfg1Index, MKBYTE(rBusmasterCfg1)); 319 WriteGenCfg(DSP_BusMasterCfg2Index, MKBYTE(rBusmasterCfg2)); 320 WriteGenCfg(DSP_IsaProtCfgIndex, MKBYTE(rIsaProtCfg)); 321 WriteGenCfg(DSP_PowerMgCfgIndex, MKBYTE(rPowerMgmtCfg)); 322 WriteGenCfg(DSP_HBusTimerCfgIndex, MKBYTE(rHBusTimerCfg)); 323 324 if (pSettings->bModemEnabled) { 325 WriteGenCfg(DSP_UartCfg1Index, MKBYTE(rUartCfg1)); 326 WriteGenCfg(DSP_UartCfg2Index, MKBYTE(rUartCfg2)); 327 } 328 329 330 rHBridgeControl.EnableDspInt = FALSE; 331 rHBridgeControl.MemAutoInc = TRUE; 332 rHBridgeControl.IoAutoInc = FALSE; 333 rHBridgeControl.DiagnosticMode = FALSE; 334 335 PRINTK_3(TRACE_3780I, 336 "3780i::dsp3780i_EnableDSP DSP_HBridgeControl %x rHBridgeControl %x\n", 337 DSP_HBridgeControl, MKWORD(rHBridgeControl)); 338 339 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 340 spin_unlock_irqrestore(&dsp_lock, flags); 341 WriteMsaCfg(DSP_LBusTimeoutDisable, MKWORD(rLBusTimeoutDisable)); 342 WriteMsaCfg(DSP_ClockControl_1, MKWORD(rClockControl1)); 343 WriteMsaCfg(DSP_ClockControl_2, MKWORD(rClockControl2)); 344 WriteMsaCfg(DSP_ChipReset, MKWORD(rChipReset)); 345 346 ChipID = ReadMsaCfg(DSP_ChipID); 347 348 PRINTK_2(TRACE_3780I, 349 "3780i::dsp3780I_EnableDSP exiting bRC=TRUE, ChipID %x\n", 350 ChipID); 351 352 return 0; 353 } 354 355 int dsp3780I_DisableDSP(DSP_3780I_CONFIG_SETTINGS * pSettings) 356 { 357 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 358 DSP_ISA_SLAVE_CONTROL rSlaveControl; 359 360 361 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP entry\n"); 362 363 rSlaveControl.ClockControl = 0; 364 rSlaveControl.SoftReset = TRUE; 365 rSlaveControl.ConfigMode = FALSE; 366 rSlaveControl.Reserved = 0; 367 spin_lock_irqsave(&dsp_lock, flags); 368 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 369 370 udelay(5); 371 372 rSlaveControl.ClockControl = 1; 373 OutWordDsp(DSP_IsaSlaveControl, MKWORD(rSlaveControl)); 374 spin_unlock_irqrestore(&dsp_lock, flags); 375 376 udelay(5); 377 378 379 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_DisableDSP exit\n"); 380 381 return 0; 382 } 383 384 int dsp3780I_Reset(DSP_3780I_CONFIG_SETTINGS * pSettings) 385 { 386 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 387 DSP_BOOT_DOMAIN rBootDomain; 388 DSP_HBRIDGE_CONTROL rHBridgeControl; 389 390 391 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset entry\n"); 392 393 spin_lock_irqsave(&dsp_lock, flags); 394 /* Mask DSP to PC interrupt */ 395 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); 396 397 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rHBridgeControl %x\n", 398 MKWORD(rHBridgeControl)); 399 400 rHBridgeControl.EnableDspInt = FALSE; 401 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 402 spin_unlock_irqrestore(&dsp_lock, flags); 403 404 /* Reset the core via the boot domain register */ 405 rBootDomain.ResetCore = TRUE; 406 rBootDomain.Halt = TRUE; 407 rBootDomain.NMI = TRUE; 408 rBootDomain.Reserved = 0; 409 410 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Reset rBootDomain %x\n", 411 MKWORD(rBootDomain)); 412 413 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 414 415 /* Reset all the chiplets and then reactivate them */ 416 WriteMsaCfg(DSP_ChipReset, 0xFFFF); 417 udelay(5); 418 WriteMsaCfg(DSP_ChipReset, 419 (unsigned short) (~pSettings->usChipletEnable)); 420 421 422 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Reset exit bRC=0\n"); 423 424 return 0; 425 } 426 427 428 int dsp3780I_Run(DSP_3780I_CONFIG_SETTINGS * pSettings) 429 { 430 unsigned short usDspBaseIO = pSettings->usDspBaseIO; 431 DSP_BOOT_DOMAIN rBootDomain; 432 DSP_HBRIDGE_CONTROL rHBridgeControl; 433 434 435 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run entry\n"); 436 437 438 /* Transition the core to a running state */ 439 rBootDomain.ResetCore = TRUE; 440 rBootDomain.Halt = FALSE; 441 rBootDomain.NMI = TRUE; 442 rBootDomain.Reserved = 0; 443 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 444 445 udelay(5); 446 447 rBootDomain.ResetCore = FALSE; 448 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 449 udelay(5); 450 451 rBootDomain.NMI = FALSE; 452 WriteMsaCfg(DSP_MspBootDomain, MKWORD(rBootDomain)); 453 udelay(5); 454 455 /* Enable DSP to PC interrupt */ 456 spin_lock_irqsave(&dsp_lock, flags); 457 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); 458 rHBridgeControl.EnableDspInt = TRUE; 459 460 PRINTK_2(TRACE_3780I, "3780i::dsp3780i_Run rHBridgeControl %x\n", 461 MKWORD(rHBridgeControl)); 462 463 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 464 spin_unlock_irqrestore(&dsp_lock, flags); 465 466 467 PRINTK_1(TRACE_3780I, "3780i::dsp3780i_Run exit bRC=TRUE\n"); 468 469 return 0; 470 } 471 472 473 int dsp3780I_ReadDStore(unsigned short usDspBaseIO, void __user *pvBuffer, 474 unsigned uCount, unsigned long ulDSPAddr) 475 { 476 unsigned short __user *pusBuffer = pvBuffer; 477 unsigned short val; 478 479 480 PRINTK_5(TRACE_3780I, 481 "3780i::dsp3780I_ReadDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 482 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 483 484 485 /* Set the initial MSA address. No adjustments need to be made to data store addresses */ 486 spin_lock_irqsave(&dsp_lock, flags); 487 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 488 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 489 spin_unlock_irqrestore(&dsp_lock, flags); 490 491 /* Transfer the memory block */ 492 while (uCount-- != 0) { 493 spin_lock_irqsave(&dsp_lock, flags); 494 val = InWordDsp(DSP_MsaDataDSISHigh); 495 spin_unlock_irqrestore(&dsp_lock, flags); 496 if(put_user(val, pusBuffer++)) 497 return -EFAULT; 498 499 PRINTK_3(TRACE_3780I, 500 "3780I::dsp3780I_ReadDStore uCount %x val %x\n", 501 uCount, val); 502 503 PaceMsaAccess(usDspBaseIO); 504 } 505 506 507 PRINTK_1(TRACE_3780I, 508 "3780I::dsp3780I_ReadDStore exit bRC=TRUE\n"); 509 510 return 0; 511 } 512 513 int dsp3780I_ReadAndClearDStore(unsigned short usDspBaseIO, 514 void __user *pvBuffer, unsigned uCount, 515 unsigned long ulDSPAddr) 516 { 517 unsigned short __user *pusBuffer = pvBuffer; 518 unsigned short val; 519 520 521 PRINTK_5(TRACE_3780I, 522 "3780i::dsp3780I_ReadAndDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 523 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 524 525 526 /* Set the initial MSA address. No adjustments need to be made to data store addresses */ 527 spin_lock_irqsave(&dsp_lock, flags); 528 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 529 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 530 spin_unlock_irqrestore(&dsp_lock, flags); 531 532 /* Transfer the memory block */ 533 while (uCount-- != 0) { 534 spin_lock_irqsave(&dsp_lock, flags); 535 val = InWordDsp(DSP_ReadAndClear); 536 spin_unlock_irqrestore(&dsp_lock, flags); 537 if(put_user(val, pusBuffer++)) 538 return -EFAULT; 539 540 PRINTK_3(TRACE_3780I, 541 "3780I::dsp3780I_ReadAndCleanDStore uCount %x val %x\n", 542 uCount, val); 543 544 PaceMsaAccess(usDspBaseIO); 545 } 546 547 548 PRINTK_1(TRACE_3780I, 549 "3780I::dsp3780I_ReadAndClearDStore exit bRC=TRUE\n"); 550 551 return 0; 552 } 553 554 555 int dsp3780I_WriteDStore(unsigned short usDspBaseIO, void __user *pvBuffer, 556 unsigned uCount, unsigned long ulDSPAddr) 557 { 558 unsigned short __user *pusBuffer = pvBuffer; 559 560 561 PRINTK_5(TRACE_3780I, 562 "3780i::dsp3780D_WriteDStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 563 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 564 565 566 /* Set the initial MSA address. No adjustments need to be made to data store addresses */ 567 spin_lock_irqsave(&dsp_lock, flags); 568 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 569 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 570 spin_unlock_irqrestore(&dsp_lock, flags); 571 572 /* Transfer the memory block */ 573 while (uCount-- != 0) { 574 unsigned short val; 575 if(get_user(val, pusBuffer++)) 576 return -EFAULT; 577 spin_lock_irqsave(&dsp_lock, flags); 578 OutWordDsp(DSP_MsaDataDSISHigh, val); 579 spin_unlock_irqrestore(&dsp_lock, flags); 580 581 PRINTK_3(TRACE_3780I, 582 "3780I::dsp3780I_WriteDStore uCount %x val %x\n", 583 uCount, val); 584 585 PaceMsaAccess(usDspBaseIO); 586 } 587 588 589 PRINTK_1(TRACE_3780I, 590 "3780I::dsp3780D_WriteDStore exit bRC=TRUE\n"); 591 592 return 0; 593 } 594 595 596 int dsp3780I_ReadIStore(unsigned short usDspBaseIO, void __user *pvBuffer, 597 unsigned uCount, unsigned long ulDSPAddr) 598 { 599 unsigned short __user *pusBuffer = pvBuffer; 600 601 PRINTK_5(TRACE_3780I, 602 "3780i::dsp3780I_ReadIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 603 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 604 605 /* 606 * Set the initial MSA address. To convert from an instruction store 607 * address to an MSA address 608 * shift the address two bits to the left and set bit 22 609 */ 610 ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); 611 spin_lock_irqsave(&dsp_lock, flags); 612 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 613 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 614 spin_unlock_irqrestore(&dsp_lock, flags); 615 616 /* Transfer the memory block */ 617 while (uCount-- != 0) { 618 unsigned short val_lo, val_hi; 619 spin_lock_irqsave(&dsp_lock, flags); 620 val_lo = InWordDsp(DSP_MsaDataISLow); 621 val_hi = InWordDsp(DSP_MsaDataDSISHigh); 622 spin_unlock_irqrestore(&dsp_lock, flags); 623 if(put_user(val_lo, pusBuffer++)) 624 return -EFAULT; 625 if(put_user(val_hi, pusBuffer++)) 626 return -EFAULT; 627 628 PRINTK_4(TRACE_3780I, 629 "3780I::dsp3780I_ReadIStore uCount %x val_lo %x val_hi %x\n", 630 uCount, val_lo, val_hi); 631 632 PaceMsaAccess(usDspBaseIO); 633 634 } 635 636 PRINTK_1(TRACE_3780I, 637 "3780I::dsp3780I_ReadIStore exit bRC=TRUE\n"); 638 639 return 0; 640 } 641 642 643 int dsp3780I_WriteIStore(unsigned short usDspBaseIO, void __user *pvBuffer, 644 unsigned uCount, unsigned long ulDSPAddr) 645 { 646 unsigned short __user *pusBuffer = pvBuffer; 647 648 PRINTK_5(TRACE_3780I, 649 "3780i::dsp3780I_WriteIStore entry usDspBaseIO %x, pusBuffer %p, uCount %x, ulDSPAddr %lx\n", 650 usDspBaseIO, pusBuffer, uCount, ulDSPAddr); 651 652 653 /* 654 * Set the initial MSA address. To convert from an instruction store 655 * address to an MSA address 656 * shift the address two bits to the left and set bit 22 657 */ 658 ulDSPAddr = (ulDSPAddr << 2) | (1 << 22); 659 spin_lock_irqsave(&dsp_lock, flags); 660 OutWordDsp(DSP_MsaAddrLow, (unsigned short) ulDSPAddr); 661 OutWordDsp(DSP_MsaAddrHigh, (unsigned short) (ulDSPAddr >> 16)); 662 spin_unlock_irqrestore(&dsp_lock, flags); 663 664 /* Transfer the memory block */ 665 while (uCount-- != 0) { 666 unsigned short val_lo, val_hi; 667 if(get_user(val_lo, pusBuffer++)) 668 return -EFAULT; 669 if(get_user(val_hi, pusBuffer++)) 670 return -EFAULT; 671 spin_lock_irqsave(&dsp_lock, flags); 672 OutWordDsp(DSP_MsaDataISLow, val_lo); 673 OutWordDsp(DSP_MsaDataDSISHigh, val_hi); 674 spin_unlock_irqrestore(&dsp_lock, flags); 675 676 PRINTK_4(TRACE_3780I, 677 "3780I::dsp3780I_WriteIStore uCount %x val_lo %x val_hi %x\n", 678 uCount, val_lo, val_hi); 679 680 PaceMsaAccess(usDspBaseIO); 681 682 } 683 684 PRINTK_1(TRACE_3780I, 685 "3780I::dsp3780I_WriteIStore exit bRC=TRUE\n"); 686 687 return 0; 688 } 689 690 691 int dsp3780I_GetIPCSource(unsigned short usDspBaseIO, 692 unsigned short *pusIPCSource) 693 { 694 DSP_HBRIDGE_CONTROL rHBridgeControl; 695 unsigned short temp; 696 697 698 PRINTK_3(TRACE_3780I, 699 "3780i::dsp3780I_GetIPCSource entry usDspBaseIO %x pusIPCSource %p\n", 700 usDspBaseIO, pusIPCSource); 701 702 /* 703 * Disable DSP to PC interrupts, read the interrupt register, 704 * clear the pending IPC bits, and reenable DSP to PC interrupts 705 */ 706 spin_lock_irqsave(&dsp_lock, flags); 707 MKWORD(rHBridgeControl) = InWordDsp(DSP_HBridgeControl); 708 rHBridgeControl.EnableDspInt = FALSE; 709 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 710 711 *pusIPCSource = InWordDsp(DSP_Interrupt); 712 temp = (unsigned short) ~(*pusIPCSource); 713 714 PRINTK_3(TRACE_3780I, 715 "3780i::dsp3780I_GetIPCSource, usIPCSource %x ~ %x\n", 716 *pusIPCSource, temp); 717 718 OutWordDsp(DSP_Interrupt, (unsigned short) ~(*pusIPCSource)); 719 720 rHBridgeControl.EnableDspInt = TRUE; 721 OutWordDsp(DSP_HBridgeControl, MKWORD(rHBridgeControl)); 722 spin_unlock_irqrestore(&dsp_lock, flags); 723 724 725 PRINTK_2(TRACE_3780I, 726 "3780i::dsp3780I_GetIPCSource exit usIPCSource %x\n", 727 *pusIPCSource); 728 729 return 0; 730 } 731