1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AMD Versal True Random Number Generator driver 4 * Copyright (c) 2024 - 2025 Advanced Micro Devices, Inc. 5 */ 6 7 #include <crypto/sha2.h> 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/firmware/xlnx-zynqmp.h> 12 #include <linux/hw_random.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/platform_device.h> 19 20 /* TRNG Registers Offsets */ 21 #define TRNG_STATUS_OFFSET 0x4U 22 #define TRNG_CTRL_OFFSET 0x8U 23 #define TRNG_EXT_SEED_OFFSET 0x40U 24 #define TRNG_PER_STRNG_OFFSET 0x80U 25 #define TRNG_CORE_OUTPUT_OFFSET 0xC0U 26 #define TRNG_RESET_OFFSET 0xD0U 27 #define TRNG_OSC_EN_OFFSET 0xD4U 28 29 /* Mask values */ 30 #define TRNG_RESET_VAL_MASK BIT(0) 31 #define TRNG_OSC_EN_VAL_MASK BIT(0) 32 #define TRNG_CTRL_PRNGSRST_MASK BIT(0) 33 #define TRNG_CTRL_EUMODE_MASK BIT(8) 34 #define TRNG_CTRL_TRSSEN_MASK BIT(2) 35 #define TRNG_CTRL_PRNGSTART_MASK BIT(5) 36 #define TRNG_CTRL_PRNGXS_MASK BIT(3) 37 #define TRNG_CTRL_PRNGMODE_MASK BIT(7) 38 #define TRNG_STATUS_DONE_MASK BIT(0) 39 #define TRNG_STATUS_QCNT_MASK GENMASK(11, 9) 40 #define TRNG_STATUS_QCNT_16_BYTES 0x800 41 42 /* Sizes in bytes */ 43 #define TRNG_SEED_LEN_BYTES 48U 44 #define TRNG_SEC_STRENGTH_SHIFT 5U 45 #define TRNG_SEC_STRENGTH_BYTES BIT(TRNG_SEC_STRENGTH_SHIFT) 46 #define TRNG_BYTES_PER_REG 4U 47 #define TRNG_RESET_DELAY 10 48 #define TRNG_NUM_INIT_REGS 12U 49 #define TRNG_READ_4_WORD 4 50 #define TRNG_DATA_READ_DELAY 8000 51 52 struct xilinx_rng { 53 void __iomem *rng_base; 54 struct device *dev; 55 struct hwrng trng; 56 }; 57 58 static void xtrng_readwrite32(void __iomem *addr, u32 mask, u8 value) 59 { 60 u32 val; 61 62 val = ioread32(addr); 63 val = (val & (~mask)) | (mask & value); 64 iowrite32(val, addr); 65 } 66 67 static void xtrng_trng_reset(void __iomem *addr) 68 { 69 xtrng_readwrite32(addr + TRNG_RESET_OFFSET, TRNG_RESET_VAL_MASK, TRNG_RESET_VAL_MASK); 70 udelay(TRNG_RESET_DELAY); 71 xtrng_readwrite32(addr + TRNG_RESET_OFFSET, TRNG_RESET_VAL_MASK, 0); 72 } 73 74 static void xtrng_hold_reset(void __iomem *addr) 75 { 76 xtrng_readwrite32(addr + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSRST_MASK, 77 TRNG_CTRL_PRNGSRST_MASK); 78 iowrite32(TRNG_RESET_VAL_MASK, addr + TRNG_RESET_OFFSET); 79 udelay(TRNG_RESET_DELAY); 80 } 81 82 static void xtrng_softreset(struct xilinx_rng *rng) 83 { 84 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSRST_MASK, 85 TRNG_CTRL_PRNGSRST_MASK); 86 udelay(TRNG_RESET_DELAY); 87 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSRST_MASK, 0); 88 } 89 90 /* Return no. of bytes read */ 91 static size_t xtrng_readblock32(void __iomem *rng_base, __be32 *buf, int blocks32, bool wait) 92 { 93 int read = 0, ret; 94 int timeout = 1; 95 int i, idx; 96 u32 val; 97 98 if (wait) 99 timeout = TRNG_DATA_READ_DELAY; 100 101 for (i = 0; i < (blocks32 * 2); i++) { 102 /* TRNG core generate data in 16 bytes. Read twice to complete 32 bytes read */ 103 ret = readl_poll_timeout(rng_base + TRNG_STATUS_OFFSET, val, 104 (val & TRNG_STATUS_QCNT_MASK) == 105 TRNG_STATUS_QCNT_16_BYTES, !!wait, timeout); 106 if (ret) 107 break; 108 109 for (idx = 0; idx < TRNG_READ_4_WORD; idx++) { 110 *(buf + read) = cpu_to_be32(ioread32(rng_base + TRNG_CORE_OUTPUT_OFFSET)); 111 read += 1; 112 } 113 } 114 return read * 4; 115 } 116 117 static int xtrng_collect_random_data(struct xilinx_rng *rng, u8 *rand_gen_buf, 118 int no_of_random_bytes, bool wait) 119 { 120 u8 randbuf[TRNG_SEC_STRENGTH_BYTES]; 121 int byteleft, blocks, count = 0; 122 int ret; 123 124 byteleft = no_of_random_bytes & (TRNG_SEC_STRENGTH_BYTES - 1); 125 blocks = no_of_random_bytes >> TRNG_SEC_STRENGTH_SHIFT; 126 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSTART_MASK, 127 TRNG_CTRL_PRNGSTART_MASK); 128 if (blocks) { 129 ret = xtrng_readblock32(rng->rng_base, (__be32 *)rand_gen_buf, blocks, wait); 130 if (!ret) 131 return 0; 132 count += ret; 133 } 134 135 if (byteleft) { 136 ret = xtrng_readblock32(rng->rng_base, (__be32 *)randbuf, 1, wait); 137 if (!ret) 138 return count; 139 memcpy(rand_gen_buf + (blocks * TRNG_SEC_STRENGTH_BYTES), randbuf, byteleft); 140 count += byteleft; 141 } 142 143 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, 144 TRNG_CTRL_PRNGMODE_MASK | TRNG_CTRL_PRNGSTART_MASK, 0U); 145 146 return count; 147 } 148 149 static void xtrng_write_multiple_registers(void __iomem *base_addr, u32 *values, size_t n) 150 { 151 void __iomem *reg_addr; 152 size_t i; 153 154 /* Write seed value into EXTERNAL_SEED Registers in big endian format */ 155 for (i = 0; i < n; i++) { 156 reg_addr = (base_addr + ((n - 1 - i) * TRNG_BYTES_PER_REG)); 157 iowrite32((u32 __force)(cpu_to_be32(values[i])), reg_addr); 158 } 159 } 160 161 static void xtrng_enable_entropy(struct xilinx_rng *rng) 162 { 163 iowrite32(TRNG_OSC_EN_VAL_MASK, rng->rng_base + TRNG_OSC_EN_OFFSET); 164 xtrng_softreset(rng); 165 iowrite32(TRNG_CTRL_EUMODE_MASK | TRNG_CTRL_TRSSEN_MASK, rng->rng_base + TRNG_CTRL_OFFSET); 166 } 167 168 static int xtrng_reseed_internal(struct xilinx_rng *rng) 169 { 170 static const u8 default_salt[SHA512_DIGEST_SIZE]; 171 u8 entropy[SHA512_DIGEST_SIZE] __aligned(4); 172 u32 val; 173 int ret; 174 175 xtrng_enable_entropy(rng); 176 177 /* Collect some output from the TRNG. */ 178 static_assert(sizeof(entropy) >= TRNG_SEED_LEN_BYTES); 179 ret = xtrng_collect_random_data(rng, entropy, TRNG_SEED_LEN_BYTES, true); 180 if (ret != TRNG_SEED_LEN_BYTES) 181 return -EINVAL; 182 183 /* Extract entropy from the TRNG output using HKDF-SHA512-Extract. */ 184 hmac_sha512_usingrawkey(default_salt, sizeof(default_salt), entropy, 185 TRNG_SEED_LEN_BYTES, entropy); 186 187 /* Write the extracted entropy to the hardware. */ 188 xtrng_write_multiple_registers(rng->rng_base + TRNG_EXT_SEED_OFFSET, 189 (u32 *)entropy, TRNG_NUM_INIT_REGS); 190 191 /* Clear the entropy from the stack. */ 192 memzero_explicit(entropy, sizeof(entropy)); 193 194 /* select reseed operation */ 195 iowrite32(TRNG_CTRL_PRNGXS_MASK, rng->rng_base + TRNG_CTRL_OFFSET); 196 197 /* Start the reseed operation with above configuration and wait for STATUS.Done bit to be 198 * set. Monitor STATUS.CERTF bit, if set indicates SP800-90B entropy health test has failed. 199 */ 200 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSTART_MASK, 201 TRNG_CTRL_PRNGSTART_MASK); 202 203 ret = readl_poll_timeout(rng->rng_base + TRNG_STATUS_OFFSET, val, 204 (val & TRNG_STATUS_DONE_MASK) == TRNG_STATUS_DONE_MASK, 205 1U, 15000U); 206 if (ret) 207 return ret; 208 209 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, TRNG_CTRL_PRNGSTART_MASK, 0U); 210 211 return 0; 212 } 213 214 static int xtrng_random_bytes_generate(struct xilinx_rng *rng, u8 *rand_buf_ptr, 215 u32 rand_buf_size, int wait) 216 { 217 int nbytes; 218 int ret; 219 220 xtrng_readwrite32(rng->rng_base + TRNG_CTRL_OFFSET, 221 TRNG_CTRL_PRNGMODE_MASK | TRNG_CTRL_PRNGXS_MASK, 222 TRNG_CTRL_PRNGMODE_MASK | TRNG_CTRL_PRNGXS_MASK); 223 nbytes = xtrng_collect_random_data(rng, rand_buf_ptr, rand_buf_size, wait); 224 225 ret = xtrng_reseed_internal(rng); 226 if (ret) { 227 dev_err(rng->dev, "Re-seed fail\n"); 228 return ret; 229 } 230 231 return nbytes; 232 } 233 234 static int xtrng_hwrng_trng_read(struct hwrng *hwrng, void *data, size_t max, bool wait) 235 { 236 u8 buf[TRNG_SEC_STRENGTH_BYTES]; 237 struct xilinx_rng *rng; 238 int ret = 0, i = 0; 239 240 rng = container_of(hwrng, struct xilinx_rng, trng); 241 while (i < max) { 242 ret = xtrng_random_bytes_generate(rng, buf, TRNG_SEC_STRENGTH_BYTES, wait); 243 if (ret < 0) { 244 if (i == 0) 245 return ret; 246 break; 247 } 248 249 memcpy(data + i, buf, min_t(int, ret, (max - i))); 250 i += min_t(int, ret, (max - i)); 251 } 252 return i; 253 } 254 255 static int xtrng_hwrng_register(struct hwrng *trng) 256 { 257 int ret; 258 259 trng->name = "Xilinx Versal Crypto Engine TRNG"; 260 trng->read = xtrng_hwrng_trng_read; 261 262 ret = hwrng_register(trng); 263 if (ret) 264 pr_err("Fail to register the TRNG\n"); 265 266 return ret; 267 } 268 269 static void xtrng_hwrng_unregister(struct hwrng *trng) 270 { 271 hwrng_unregister(trng); 272 } 273 274 static int xtrng_probe(struct platform_device *pdev) 275 { 276 struct xilinx_rng *rng; 277 int ret; 278 279 rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL); 280 if (!rng) 281 return -ENOMEM; 282 283 rng->dev = &pdev->dev; 284 rng->rng_base = devm_platform_ioremap_resource(pdev, 0); 285 if (IS_ERR(rng->rng_base)) { 286 dev_err(&pdev->dev, "Failed to map resource %pe\n", rng->rng_base); 287 return PTR_ERR(rng->rng_base); 288 } 289 290 xtrng_trng_reset(rng->rng_base); 291 ret = xtrng_reseed_internal(rng); 292 if (ret) { 293 dev_err(&pdev->dev, "TRNG Seed fail\n"); 294 return ret; 295 } 296 297 ret = xtrng_hwrng_register(&rng->trng); 298 if (ret) { 299 dev_err(&pdev->dev, "HWRNG device registration failed: %d\n", ret); 300 return ret; 301 } 302 platform_set_drvdata(pdev, rng); 303 304 return 0; 305 } 306 307 static void xtrng_remove(struct platform_device *pdev) 308 { 309 struct xilinx_rng *rng; 310 u32 zero[TRNG_NUM_INIT_REGS] = { }; 311 312 rng = platform_get_drvdata(pdev); 313 xtrng_hwrng_unregister(&rng->trng); 314 xtrng_write_multiple_registers(rng->rng_base + TRNG_EXT_SEED_OFFSET, zero, 315 TRNG_NUM_INIT_REGS); 316 xtrng_write_multiple_registers(rng->rng_base + TRNG_PER_STRNG_OFFSET, zero, 317 TRNG_NUM_INIT_REGS); 318 xtrng_hold_reset(rng->rng_base); 319 } 320 321 static const struct of_device_id xtrng_of_match[] = { 322 { .compatible = "xlnx,versal-trng", }, 323 {}, 324 }; 325 326 MODULE_DEVICE_TABLE(of, xtrng_of_match); 327 328 static struct platform_driver xtrng_driver = { 329 .driver = { 330 .name = "xlnx,versal-trng", 331 .of_match_table = xtrng_of_match, 332 }, 333 .probe = xtrng_probe, 334 .remove = xtrng_remove, 335 }; 336 337 module_platform_driver(xtrng_driver); 338 MODULE_LICENSE("GPL"); 339 MODULE_AUTHOR("Harsh Jain <h.jain@amd.com>"); 340 MODULE_AUTHOR("Mounika Botcha <mounika.botcha@amd.com>"); 341 MODULE_DESCRIPTION("True Random Number Generator Driver"); 342