1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2015, Daniel Thompson 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/hw_random.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/slab.h> 19 20 #define RNG_CR 0x00 21 #define RNG_CR_RNGEN BIT(2) 22 #define RNG_CR_CED BIT(5) 23 #define RNG_CR_CONFIG1 GENMASK(11, 8) 24 #define RNG_CR_NISTC BIT(12) 25 #define RNG_CR_CONFIG2 GENMASK(15, 13) 26 #define RNG_CR_CLKDIV_SHIFT 16 27 #define RNG_CR_CLKDIV GENMASK(19, 16) 28 #define RNG_CR_CONFIG3 GENMASK(25, 20) 29 #define RNG_CR_CONDRST BIT(30) 30 #define RNG_CR_CONFLOCK BIT(31) 31 #define RNG_CR_ENTROPY_SRC_MASK (RNG_CR_CONFIG1 | RNG_CR_NISTC | RNG_CR_CONFIG2 | RNG_CR_CONFIG3) 32 #define RNG_CR_CONFIG_MASK (RNG_CR_ENTROPY_SRC_MASK | RNG_CR_CED | RNG_CR_CLKDIV) 33 34 #define RNG_SR 0x04 35 #define RNG_SR_DRDY BIT(0) 36 #define RNG_SR_CECS BIT(1) 37 #define RNG_SR_SECS BIT(2) 38 #define RNG_SR_CEIS BIT(5) 39 #define RNG_SR_SEIS BIT(6) 40 41 #define RNG_DR 0x08 42 43 #define RNG_NSCR 0x0C 44 #define RNG_NSCR_MASK GENMASK(17, 0) 45 46 #define RNG_HTCR 0x10 47 48 #define RNG_NB_RECOVER_TRIES 3 49 50 struct stm32_rng_data { 51 uint max_clock_rate; 52 u32 cr; 53 u32 nscr; 54 u32 htcr; 55 bool has_cond_reset; 56 }; 57 58 /** 59 * struct stm32_rng_config - RNG configuration data 60 * 61 * @cr: RNG configuration. 0 means default hardware RNG configuration 62 * @nscr: Noise sources control configuration. 63 * @htcr: Health tests configuration. 64 */ 65 struct stm32_rng_config { 66 u32 cr; 67 u32 nscr; 68 u32 htcr; 69 }; 70 71 struct stm32_rng_private { 72 struct hwrng rng; 73 void __iomem *base; 74 struct clk *clk; 75 struct reset_control *rst; 76 struct stm32_rng_config pm_conf; 77 const struct stm32_rng_data *data; 78 bool ced; 79 bool lock_conf; 80 }; 81 82 /* 83 * Extracts from the STM32 RNG specification when RNG supports CONDRST. 84 * 85 * When a noise source (or seed) error occurs, the RNG stops generating 86 * random numbers and sets to “1” both SEIS and SECS bits to indicate 87 * that a seed error occurred. (...) 88 * 89 * 1. Software reset by writing CONDRST at 1 and at 0 (see bitfield 90 * description for details). This step is needed only if SECS is set. 91 * Indeed, when SEIS is set and SECS is cleared it means RNG performed 92 * the reset automatically (auto-reset). 93 * 2. If SECS was set in step 1 (no auto-reset) wait for CONDRST 94 * to be cleared in the RNG_CR register, then confirm that SEIS is 95 * cleared in the RNG_SR register. Otherwise just clear SEIS bit in 96 * the RNG_SR register. 97 * 3. If SECS was set in step 1 (no auto-reset) wait for SECS to be 98 * cleared by RNG. The random number generation is now back to normal. 99 */ 100 static int stm32_rng_conceal_seed_error_cond_reset(struct stm32_rng_private *priv) 101 { 102 struct device *dev = (struct device *)priv->rng.priv; 103 u32 sr = readl_relaxed(priv->base + RNG_SR); 104 u32 cr = readl_relaxed(priv->base + RNG_CR); 105 int err; 106 107 if (sr & RNG_SR_SECS) { 108 /* Conceal by resetting the subsystem (step 1.) */ 109 writel_relaxed(cr | RNG_CR_CONDRST, priv->base + RNG_CR); 110 writel_relaxed(cr & ~RNG_CR_CONDRST, priv->base + RNG_CR); 111 } else { 112 /* RNG auto-reset (step 2.) */ 113 writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR); 114 goto end; 115 } 116 117 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, cr, !(cr & RNG_CR_CONDRST), 10, 118 100000); 119 if (err) { 120 dev_err(dev, "%s: timeout %x\n", __func__, sr); 121 return err; 122 } 123 124 /* Check SEIS is cleared (step 2.) */ 125 if (readl_relaxed(priv->base + RNG_SR) & RNG_SR_SEIS) 126 return -EINVAL; 127 128 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_SR, sr, !(sr & RNG_SR_SECS), 10, 129 100000); 130 if (err) { 131 dev_err(dev, "%s: timeout %x\n", __func__, sr); 132 return err; 133 } 134 135 end: 136 return 0; 137 } 138 139 /* 140 * Extracts from the STM32 RNG specification, when CONDRST is not supported 141 * 142 * When a noise source (or seed) error occurs, the RNG stops generating 143 * random numbers and sets to “1” both SEIS and SECS bits to indicate 144 * that a seed error occurred. (...) 145 * 146 * The following sequence shall be used to fully recover from a seed 147 * error after the RNG initialization: 148 * 1. Clear the SEIS bit by writing it to “0”. 149 * 2. Read out 12 words from the RNG_DR register, and discard each of 150 * them in order to clean the pipeline. 151 * 3. Confirm that SEIS is still cleared. Random number generation is 152 * back to normal. 153 */ 154 static int stm32_rng_conceal_seed_error_sw_reset(struct stm32_rng_private *priv) 155 { 156 unsigned int i = 0; 157 u32 sr = readl_relaxed(priv->base + RNG_SR); 158 159 writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR); 160 161 for (i = 12; i != 0; i--) 162 (void)readl_relaxed(priv->base + RNG_DR); 163 164 if (readl_relaxed(priv->base + RNG_SR) & RNG_SR_SEIS) 165 return -EINVAL; 166 167 return 0; 168 } 169 170 static int stm32_rng_conceal_seed_error(struct hwrng *rng) 171 { 172 struct stm32_rng_private *priv = container_of(rng, struct stm32_rng_private, rng); 173 174 dev_dbg((struct device *)priv->rng.priv, "Concealing seed error\n"); 175 176 if (priv->data->has_cond_reset) 177 return stm32_rng_conceal_seed_error_cond_reset(priv); 178 else 179 return stm32_rng_conceal_seed_error_sw_reset(priv); 180 }; 181 182 183 static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait) 184 { 185 struct stm32_rng_private *priv = container_of(rng, struct stm32_rng_private, rng); 186 unsigned int i = 0; 187 int retval = 0, err = 0; 188 u32 sr; 189 190 pm_runtime_get_sync((struct device *) priv->rng.priv); 191 192 if (readl_relaxed(priv->base + RNG_SR) & RNG_SR_SEIS) 193 stm32_rng_conceal_seed_error(rng); 194 195 while (max >= sizeof(u32)) { 196 sr = readl_relaxed(priv->base + RNG_SR); 197 /* 198 * Manage timeout which is based on timer and take 199 * care of initial delay time when enabling the RNG. 200 */ 201 if (!sr && wait) { 202 err = readl_relaxed_poll_timeout_atomic(priv->base 203 + RNG_SR, 204 sr, sr, 205 10, 50000); 206 if (err) { 207 dev_err((struct device *)priv->rng.priv, 208 "%s: timeout %x!\n", __func__, sr); 209 break; 210 } 211 } else if (!sr) { 212 /* The FIFO is being filled up */ 213 break; 214 } 215 216 if (sr != RNG_SR_DRDY) { 217 if (sr & RNG_SR_SEIS) { 218 err = stm32_rng_conceal_seed_error(rng); 219 i++; 220 if (err && i > RNG_NB_RECOVER_TRIES) { 221 dev_err((struct device *)priv->rng.priv, 222 "Couldn't recover from seed error\n"); 223 return -ENOTRECOVERABLE; 224 } 225 226 continue; 227 } 228 229 if (WARN_ONCE((sr & RNG_SR_CEIS), "RNG clock too slow - %x\n", sr)) 230 writel_relaxed(0, priv->base + RNG_SR); 231 } 232 233 /* Late seed error case: DR being 0 is an error status */ 234 *(u32 *)data = readl_relaxed(priv->base + RNG_DR); 235 if (!*(u32 *)data) { 236 err = stm32_rng_conceal_seed_error(rng); 237 i++; 238 if (err && i > RNG_NB_RECOVER_TRIES) { 239 dev_err((struct device *)priv->rng.priv, 240 "Couldn't recover from seed error"); 241 return -ENOTRECOVERABLE; 242 } 243 244 continue; 245 } 246 247 i = 0; 248 retval += sizeof(u32); 249 data += sizeof(u32); 250 max -= sizeof(u32); 251 } 252 253 pm_runtime_mark_last_busy((struct device *) priv->rng.priv); 254 pm_runtime_put_sync_autosuspend((struct device *) priv->rng.priv); 255 256 return retval || !wait ? retval : -EIO; 257 } 258 259 static uint stm32_rng_clock_freq_restrain(struct hwrng *rng) 260 { 261 struct stm32_rng_private *priv = 262 container_of(rng, struct stm32_rng_private, rng); 263 unsigned long clock_rate = 0; 264 uint clock_div = 0; 265 266 clock_rate = clk_get_rate(priv->clk); 267 268 /* 269 * Get the exponent to apply on the CLKDIV field in RNG_CR register 270 * No need to handle the case when clock-div > 0xF as it is physically 271 * impossible 272 */ 273 while ((clock_rate >> clock_div) > priv->data->max_clock_rate) 274 clock_div++; 275 276 pr_debug("RNG clk rate : %lu\n", clk_get_rate(priv->clk) >> clock_div); 277 278 return clock_div; 279 } 280 281 static int stm32_rng_init(struct hwrng *rng) 282 { 283 struct stm32_rng_private *priv = 284 container_of(rng, struct stm32_rng_private, rng); 285 int err; 286 u32 reg; 287 288 err = clk_prepare_enable(priv->clk); 289 if (err) 290 return err; 291 292 /* clear error indicators */ 293 writel_relaxed(0, priv->base + RNG_SR); 294 295 reg = readl_relaxed(priv->base + RNG_CR); 296 297 /* 298 * Keep default RNG configuration if none was specified. 299 * 0 is an invalid value as it disables all entropy sources. 300 */ 301 if (priv->data->has_cond_reset && priv->data->cr) { 302 uint clock_div = stm32_rng_clock_freq_restrain(rng); 303 304 reg &= ~RNG_CR_CONFIG_MASK; 305 reg |= RNG_CR_CONDRST | (priv->data->cr & RNG_CR_ENTROPY_SRC_MASK) | 306 (clock_div << RNG_CR_CLKDIV_SHIFT); 307 if (priv->ced) 308 reg &= ~RNG_CR_CED; 309 else 310 reg |= RNG_CR_CED; 311 writel_relaxed(reg, priv->base + RNG_CR); 312 313 /* Health tests and noise control registers */ 314 writel_relaxed(priv->data->htcr, priv->base + RNG_HTCR); 315 writel_relaxed(priv->data->nscr & RNG_NSCR_MASK, priv->base + RNG_NSCR); 316 317 reg &= ~RNG_CR_CONDRST; 318 reg |= RNG_CR_RNGEN; 319 if (priv->lock_conf) 320 reg |= RNG_CR_CONFLOCK; 321 322 writel_relaxed(reg, priv->base + RNG_CR); 323 324 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, reg, 325 (!(reg & RNG_CR_CONDRST)), 326 10, 50000); 327 if (err) { 328 clk_disable_unprepare(priv->clk); 329 dev_err((struct device *)priv->rng.priv, 330 "%s: timeout %x!\n", __func__, reg); 331 return -EINVAL; 332 } 333 } else { 334 /* Handle all RNG versions by checking if conditional reset should be set */ 335 if (priv->data->has_cond_reset) 336 reg |= RNG_CR_CONDRST; 337 338 if (priv->ced) 339 reg &= ~RNG_CR_CED; 340 else 341 reg |= RNG_CR_CED; 342 343 writel_relaxed(reg, priv->base + RNG_CR); 344 345 if (priv->data->has_cond_reset) 346 reg &= ~RNG_CR_CONDRST; 347 348 reg |= RNG_CR_RNGEN; 349 350 writel_relaxed(reg, priv->base + RNG_CR); 351 } 352 353 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_SR, reg, 354 reg & RNG_SR_DRDY, 355 10, 100000); 356 if (err | (reg & ~RNG_SR_DRDY)) { 357 clk_disable_unprepare(priv->clk); 358 dev_err((struct device *)priv->rng.priv, 359 "%s: timeout:%x SR: %x!\n", __func__, err, reg); 360 return -EINVAL; 361 } 362 363 return 0; 364 } 365 366 static void stm32_rng_remove(struct platform_device *ofdev) 367 { 368 pm_runtime_disable(&ofdev->dev); 369 } 370 371 static int __maybe_unused stm32_rng_runtime_suspend(struct device *dev) 372 { 373 struct stm32_rng_private *priv = dev_get_drvdata(dev); 374 u32 reg; 375 376 reg = readl_relaxed(priv->base + RNG_CR); 377 reg &= ~RNG_CR_RNGEN; 378 writel_relaxed(reg, priv->base + RNG_CR); 379 clk_disable_unprepare(priv->clk); 380 381 return 0; 382 } 383 384 static int __maybe_unused stm32_rng_suspend(struct device *dev) 385 { 386 struct stm32_rng_private *priv = dev_get_drvdata(dev); 387 388 if (priv->data->has_cond_reset) { 389 priv->pm_conf.nscr = readl_relaxed(priv->base + RNG_NSCR); 390 priv->pm_conf.htcr = readl_relaxed(priv->base + RNG_HTCR); 391 } 392 393 /* Do not save that RNG is enabled as it will be handled at resume */ 394 priv->pm_conf.cr = readl_relaxed(priv->base + RNG_CR) & ~RNG_CR_RNGEN; 395 396 writel_relaxed(priv->pm_conf.cr, priv->base + RNG_CR); 397 398 clk_disable_unprepare(priv->clk); 399 400 return 0; 401 } 402 403 static int __maybe_unused stm32_rng_runtime_resume(struct device *dev) 404 { 405 struct stm32_rng_private *priv = dev_get_drvdata(dev); 406 int err; 407 u32 reg; 408 409 err = clk_prepare_enable(priv->clk); 410 if (err) 411 return err; 412 413 /* Clean error indications */ 414 writel_relaxed(0, priv->base + RNG_SR); 415 416 reg = readl_relaxed(priv->base + RNG_CR); 417 reg |= RNG_CR_RNGEN; 418 writel_relaxed(reg, priv->base + RNG_CR); 419 420 return 0; 421 } 422 423 static int __maybe_unused stm32_rng_resume(struct device *dev) 424 { 425 struct stm32_rng_private *priv = dev_get_drvdata(dev); 426 int err; 427 u32 reg; 428 429 err = clk_prepare_enable(priv->clk); 430 if (err) 431 return err; 432 433 /* Clean error indications */ 434 writel_relaxed(0, priv->base + RNG_SR); 435 436 if (priv->data->has_cond_reset) { 437 /* 438 * Correct configuration in bits [29:4] must be set in the same 439 * access that set RNG_CR_CONDRST bit. Else config setting is 440 * not taken into account. CONFIGLOCK bit must also be unset but 441 * it is not handled at the moment. 442 */ 443 writel_relaxed(priv->pm_conf.cr | RNG_CR_CONDRST, priv->base + RNG_CR); 444 445 writel_relaxed(priv->pm_conf.nscr, priv->base + RNG_NSCR); 446 writel_relaxed(priv->pm_conf.htcr, priv->base + RNG_HTCR); 447 448 reg = readl_relaxed(priv->base + RNG_CR); 449 reg |= RNG_CR_RNGEN; 450 reg &= ~RNG_CR_CONDRST; 451 writel_relaxed(reg, priv->base + RNG_CR); 452 453 err = readl_relaxed_poll_timeout_atomic(priv->base + RNG_CR, reg, 454 reg & ~RNG_CR_CONDRST, 10, 100000); 455 456 if (err) { 457 clk_disable_unprepare(priv->clk); 458 dev_err((struct device *)priv->rng.priv, 459 "%s: timeout:%x CR: %x!\n", __func__, err, reg); 460 return -EINVAL; 461 } 462 } else { 463 reg = priv->pm_conf.cr; 464 reg |= RNG_CR_RNGEN; 465 writel_relaxed(reg, priv->base + RNG_CR); 466 } 467 468 return 0; 469 } 470 471 static const struct dev_pm_ops __maybe_unused stm32_rng_pm_ops = { 472 SET_RUNTIME_PM_OPS(stm32_rng_runtime_suspend, 473 stm32_rng_runtime_resume, NULL) 474 SET_SYSTEM_SLEEP_PM_OPS(stm32_rng_suspend, 475 stm32_rng_resume) 476 }; 477 478 static const struct stm32_rng_data stm32mp13_rng_data = { 479 .has_cond_reset = true, 480 .max_clock_rate = 48000000, 481 .cr = 0x00F00D00, 482 .nscr = 0x2B5BB, 483 .htcr = 0x969D, 484 }; 485 486 static const struct stm32_rng_data stm32_rng_data = { 487 .has_cond_reset = false, 488 .max_clock_rate = 3000000, 489 }; 490 491 static const struct of_device_id stm32_rng_match[] = { 492 { 493 .compatible = "st,stm32mp13-rng", 494 .data = &stm32mp13_rng_data, 495 }, 496 { 497 .compatible = "st,stm32-rng", 498 .data = &stm32_rng_data, 499 }, 500 {}, 501 }; 502 MODULE_DEVICE_TABLE(of, stm32_rng_match); 503 504 static int stm32_rng_probe(struct platform_device *ofdev) 505 { 506 struct device *dev = &ofdev->dev; 507 struct device_node *np = ofdev->dev.of_node; 508 struct stm32_rng_private *priv; 509 struct resource *res; 510 511 priv = devm_kzalloc(dev, sizeof(struct stm32_rng_private), GFP_KERNEL); 512 if (!priv) 513 return -ENOMEM; 514 515 priv->base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res); 516 if (IS_ERR(priv->base)) 517 return PTR_ERR(priv->base); 518 519 priv->clk = devm_clk_get(&ofdev->dev, NULL); 520 if (IS_ERR(priv->clk)) 521 return PTR_ERR(priv->clk); 522 523 priv->rst = devm_reset_control_get(&ofdev->dev, NULL); 524 if (!IS_ERR(priv->rst)) { 525 reset_control_assert(priv->rst); 526 udelay(2); 527 reset_control_deassert(priv->rst); 528 } 529 530 priv->ced = of_property_read_bool(np, "clock-error-detect"); 531 priv->lock_conf = of_property_read_bool(np, "st,rng-lock-conf"); 532 533 priv->data = of_device_get_match_data(dev); 534 if (!priv->data) 535 return -ENODEV; 536 537 dev_set_drvdata(dev, priv); 538 539 priv->rng.name = dev_driver_string(dev); 540 priv->rng.init = stm32_rng_init; 541 priv->rng.read = stm32_rng_read; 542 priv->rng.priv = (unsigned long) dev; 543 priv->rng.quality = 900; 544 545 pm_runtime_set_autosuspend_delay(dev, 100); 546 pm_runtime_use_autosuspend(dev); 547 pm_runtime_enable(dev); 548 549 return devm_hwrng_register(dev, &priv->rng); 550 } 551 552 static struct platform_driver stm32_rng_driver = { 553 .driver = { 554 .name = "stm32-rng", 555 .pm = pm_ptr(&stm32_rng_pm_ops), 556 .of_match_table = stm32_rng_match, 557 }, 558 .probe = stm32_rng_probe, 559 .remove_new = stm32_rng_remove, 560 }; 561 562 module_platform_driver(stm32_rng_driver); 563 564 MODULE_LICENSE("GPL"); 565 MODULE_AUTHOR("Daniel Thompson <daniel.thompson@linaro.org>"); 566 MODULE_DESCRIPTION("STMicroelectronics STM32 RNG device driver"); 567