1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * rockchip-rng.c True Random Number Generator driver for Rockchip RK3568 SoC 4 * 5 * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd. 6 * Copyright (c) 2022, Aurelien Jarno 7 * Authors: 8 * Lin Jinhan <troy.lin@rock-chips.com> 9 * Aurelien Jarno <aurelien@aurel32.net> 10 */ 11 #include <linux/clk.h> 12 #include <linux/hw_random.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #define RK_RNG_AUTOSUSPEND_DELAY 100 24 #define RK_RNG_MAX_BYTE 32 25 #define RK_RNG_POLL_PERIOD_US 100 26 #define RK_RNG_POLL_TIMEOUT_US 10000 27 28 /* 29 * TRNG collects osc ring output bit every RK_RNG_SAMPLE_CNT time. The value is 30 * a tradeoff between speed and quality and has been adjusted to get a quality 31 * of ~900 (~87.5% of FIPS 140-2 successes). 32 */ 33 #define RK_RNG_SAMPLE_CNT 1000 34 35 /* TRNG registers from RK3568 TRM-Part2, section 5.4.1 */ 36 #define TRNG_RST_CTL 0x0004 37 #define TRNG_RNG_CTL 0x0400 38 #define TRNG_RNG_CTL_LEN_64_BIT (0x00 << 4) 39 #define TRNG_RNG_CTL_LEN_128_BIT (0x01 << 4) 40 #define TRNG_RNG_CTL_LEN_192_BIT (0x02 << 4) 41 #define TRNG_RNG_CTL_LEN_256_BIT (0x03 << 4) 42 #define TRNG_RNG_CTL_OSC_RING_SPEED_0 (0x00 << 2) 43 #define TRNG_RNG_CTL_OSC_RING_SPEED_1 (0x01 << 2) 44 #define TRNG_RNG_CTL_OSC_RING_SPEED_2 (0x02 << 2) 45 #define TRNG_RNG_CTL_OSC_RING_SPEED_3 (0x03 << 2) 46 #define TRNG_RNG_CTL_MASK GENMASK(15, 0) 47 #define TRNG_RNG_CTL_ENABLE BIT(1) 48 #define TRNG_RNG_CTL_START BIT(0) 49 #define TRNG_RNG_SAMPLE_CNT 0x0404 50 #define TRNG_RNG_DOUT 0x0410 51 52 struct rk_rng { 53 struct hwrng rng; 54 void __iomem *base; 55 struct reset_control *rst; 56 int clk_num; 57 struct clk_bulk_data *clk_bulks; 58 }; 59 60 /* The mask in the upper 16 bits determines the bits that are updated */ 61 static void rk_rng_write_ctl(struct rk_rng *rng, u32 val, u32 mask) 62 { 63 writel((mask << 16) | val, rng->base + TRNG_RNG_CTL); 64 } 65 66 static int rk_rng_init(struct hwrng *rng) 67 { 68 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); 69 int ret; 70 71 /* start clocks */ 72 ret = clk_bulk_prepare_enable(rk_rng->clk_num, rk_rng->clk_bulks); 73 if (ret < 0) { 74 dev_err((struct device *) rk_rng->rng.priv, 75 "Failed to enable clks %d\n", ret); 76 return ret; 77 } 78 79 /* set the sample period */ 80 writel(RK_RNG_SAMPLE_CNT, rk_rng->base + TRNG_RNG_SAMPLE_CNT); 81 82 /* set osc ring speed and enable it */ 83 rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_LEN_256_BIT | 84 TRNG_RNG_CTL_OSC_RING_SPEED_0 | 85 TRNG_RNG_CTL_ENABLE, 86 TRNG_RNG_CTL_MASK); 87 88 return 0; 89 } 90 91 static void rk_rng_cleanup(struct hwrng *rng) 92 { 93 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); 94 95 /* stop TRNG */ 96 rk_rng_write_ctl(rk_rng, 0, TRNG_RNG_CTL_MASK); 97 98 /* stop clocks */ 99 clk_bulk_disable_unprepare(rk_rng->clk_num, rk_rng->clk_bulks); 100 } 101 102 static int rk_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait) 103 { 104 struct rk_rng *rk_rng = container_of(rng, struct rk_rng, rng); 105 size_t to_read = min_t(size_t, max, RK_RNG_MAX_BYTE); 106 u32 reg; 107 int ret = 0; 108 109 ret = pm_runtime_resume_and_get((struct device *) rk_rng->rng.priv); 110 if (ret < 0) 111 return ret; 112 113 /* Start collecting random data */ 114 rk_rng_write_ctl(rk_rng, TRNG_RNG_CTL_START, TRNG_RNG_CTL_START); 115 116 ret = readl_poll_timeout(rk_rng->base + TRNG_RNG_CTL, reg, 117 !(reg & TRNG_RNG_CTL_START), 118 RK_RNG_POLL_PERIOD_US, 119 RK_RNG_POLL_TIMEOUT_US); 120 if (ret < 0) 121 goto out; 122 123 /* Read random data stored in the registers */ 124 memcpy_fromio(buf, rk_rng->base + TRNG_RNG_DOUT, to_read); 125 out: 126 pm_runtime_mark_last_busy((struct device *) rk_rng->rng.priv); 127 pm_runtime_put_sync_autosuspend((struct device *) rk_rng->rng.priv); 128 129 return (ret < 0) ? ret : to_read; 130 } 131 132 static int rk_rng_probe(struct platform_device *pdev) 133 { 134 struct device *dev = &pdev->dev; 135 struct rk_rng *rk_rng; 136 int ret; 137 138 rk_rng = devm_kzalloc(dev, sizeof(*rk_rng), GFP_KERNEL); 139 if (!rk_rng) 140 return -ENOMEM; 141 142 rk_rng->base = devm_platform_ioremap_resource(pdev, 0); 143 if (IS_ERR(rk_rng->base)) 144 return PTR_ERR(rk_rng->base); 145 146 rk_rng->clk_num = devm_clk_bulk_get_all(dev, &rk_rng->clk_bulks); 147 if (rk_rng->clk_num < 0) 148 return dev_err_probe(dev, rk_rng->clk_num, 149 "Failed to get clks property\n"); 150 151 rk_rng->rst = devm_reset_control_array_get_exclusive(&pdev->dev); 152 if (IS_ERR(rk_rng->rst)) 153 return dev_err_probe(dev, PTR_ERR(rk_rng->rst), 154 "Failed to get reset property\n"); 155 156 reset_control_assert(rk_rng->rst); 157 udelay(2); 158 reset_control_deassert(rk_rng->rst); 159 160 platform_set_drvdata(pdev, rk_rng); 161 162 rk_rng->rng.name = dev_driver_string(dev); 163 if (!IS_ENABLED(CONFIG_PM)) { 164 rk_rng->rng.init = rk_rng_init; 165 rk_rng->rng.cleanup = rk_rng_cleanup; 166 } 167 rk_rng->rng.read = rk_rng_read; 168 rk_rng->rng.priv = (unsigned long) dev; 169 rk_rng->rng.quality = 900; 170 171 pm_runtime_set_autosuspend_delay(dev, RK_RNG_AUTOSUSPEND_DELAY); 172 pm_runtime_use_autosuspend(dev); 173 devm_pm_runtime_enable(dev); 174 175 ret = devm_hwrng_register(dev, &rk_rng->rng); 176 if (ret) 177 return dev_err_probe(&pdev->dev, ret, "Failed to register Rockchip hwrng\n"); 178 179 return 0; 180 } 181 182 static int __maybe_unused rk_rng_runtime_suspend(struct device *dev) 183 { 184 struct rk_rng *rk_rng = dev_get_drvdata(dev); 185 186 rk_rng_cleanup(&rk_rng->rng); 187 188 return 0; 189 } 190 191 static int __maybe_unused rk_rng_runtime_resume(struct device *dev) 192 { 193 struct rk_rng *rk_rng = dev_get_drvdata(dev); 194 195 return rk_rng_init(&rk_rng->rng); 196 } 197 198 static const struct dev_pm_ops rk_rng_pm_ops = { 199 SET_RUNTIME_PM_OPS(rk_rng_runtime_suspend, 200 rk_rng_runtime_resume, NULL) 201 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 202 pm_runtime_force_resume) 203 }; 204 205 static const struct of_device_id rk_rng_dt_match[] = { 206 { .compatible = "rockchip,rk3568-rng", }, 207 { /* sentinel */ }, 208 }; 209 210 MODULE_DEVICE_TABLE(of, rk_rng_dt_match); 211 212 static struct platform_driver rk_rng_driver = { 213 .driver = { 214 .name = "rockchip-rng", 215 .pm = &rk_rng_pm_ops, 216 .of_match_table = rk_rng_dt_match, 217 }, 218 .probe = rk_rng_probe, 219 }; 220 221 module_platform_driver(rk_rng_driver); 222 223 MODULE_DESCRIPTION("Rockchip RK3568 True Random Number Generator driver"); 224 MODULE_AUTHOR("Lin Jinhan <troy.lin@rock-chips.com>"); 225 MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>"); 226 MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 227 MODULE_LICENSE("GPL"); 228