1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * RNG driver for Exynos TRNGs 4 * 5 * Author: Łukasz Stelmach <l.stelmach@samsung.com> 6 * 7 * Copyright 2017 (c) Samsung Electronics Software, Inc. 8 * 9 * Based on the Exynos PRNG driver drivers/crypto/exynos-rng by 10 * Krzysztof Kozłowski <krzk@kernel.org> 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/crypto.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/hw_random.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 26 #define EXYNOS_TRNG_CLKDIV 0x0 27 28 #define EXYNOS_TRNG_CTRL 0x20 29 #define EXYNOS_TRNG_CTRL_RNGEN BIT(31) 30 31 #define EXYNOS_TRNG_POST_CTRL 0x30 32 #define EXYNOS_TRNG_ONLINE_CTRL 0x40 33 #define EXYNOS_TRNG_ONLINE_STAT 0x44 34 #define EXYNOS_TRNG_ONLINE_MAXCHI2 0x48 35 #define EXYNOS_TRNG_FIFO_CTRL 0x50 36 #define EXYNOS_TRNG_FIFO_0 0x80 37 #define EXYNOS_TRNG_FIFO_1 0x84 38 #define EXYNOS_TRNG_FIFO_2 0x88 39 #define EXYNOS_TRNG_FIFO_3 0x8c 40 #define EXYNOS_TRNG_FIFO_4 0x90 41 #define EXYNOS_TRNG_FIFO_5 0x94 42 #define EXYNOS_TRNG_FIFO_6 0x98 43 #define EXYNOS_TRNG_FIFO_7 0x9c 44 #define EXYNOS_TRNG_FIFO_LEN 8 45 #define EXYNOS_TRNG_CLOCK_RATE 500000 46 47 struct exynos_trng_dev { 48 struct device *dev; 49 void __iomem *mem; 50 struct clk *clk; /* operating clock */ 51 struct clk *pclk; /* bus clock */ 52 struct hwrng rng; 53 }; 54 55 static int exynos_trng_do_read(struct hwrng *rng, void *data, size_t max, 56 bool wait) 57 { 58 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; 59 int val; 60 61 max = min_t(size_t, max, (EXYNOS_TRNG_FIFO_LEN * 4)); 62 writel_relaxed(max * 8, trng->mem + EXYNOS_TRNG_FIFO_CTRL); 63 val = readl_poll_timeout(trng->mem + EXYNOS_TRNG_FIFO_CTRL, val, 64 val == 0, 200, 1000000); 65 if (val < 0) 66 return val; 67 68 memcpy_fromio(data, trng->mem + EXYNOS_TRNG_FIFO_0, max); 69 70 return max; 71 } 72 73 static int exynos_trng_init(struct hwrng *rng) 74 { 75 struct exynos_trng_dev *trng = (struct exynos_trng_dev *)rng->priv; 76 unsigned long sss_rate; 77 u32 val; 78 79 sss_rate = clk_get_rate(trng->clk); 80 81 /* 82 * For most TRNG circuits the clock frequency of under 500 kHz 83 * is safe. 84 */ 85 val = sss_rate / (EXYNOS_TRNG_CLOCK_RATE * 2); 86 if (val > 0x7fff) { 87 dev_err(trng->dev, "clock divider too large: %d\n", val); 88 return -ERANGE; 89 } 90 val = val << 1; 91 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CLKDIV); 92 93 /* Enable the generator. */ 94 val = EXYNOS_TRNG_CTRL_RNGEN; 95 writel_relaxed(val, trng->mem + EXYNOS_TRNG_CTRL); 96 97 /* 98 * Disable post-processing. /dev/hwrng is supposed to deliver 99 * unprocessed data. 100 */ 101 writel_relaxed(0, trng->mem + EXYNOS_TRNG_POST_CTRL); 102 103 return 0; 104 } 105 106 static int exynos_trng_probe(struct platform_device *pdev) 107 { 108 struct exynos_trng_dev *trng; 109 int ret = -ENOMEM; 110 111 trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL); 112 if (!trng) 113 return ret; 114 115 trng->rng.name = devm_kstrdup(&pdev->dev, dev_name(&pdev->dev), 116 GFP_KERNEL); 117 if (!trng->rng.name) 118 return ret; 119 120 trng->rng.init = exynos_trng_init; 121 trng->rng.read = exynos_trng_do_read; 122 trng->rng.priv = (unsigned long)trng; 123 124 platform_set_drvdata(pdev, trng); 125 trng->dev = &pdev->dev; 126 127 trng->mem = devm_platform_ioremap_resource(pdev, 0); 128 if (IS_ERR(trng->mem)) 129 return PTR_ERR(trng->mem); 130 131 pm_runtime_enable(&pdev->dev); 132 ret = pm_runtime_resume_and_get(&pdev->dev); 133 if (ret < 0) { 134 dev_err(&pdev->dev, "Could not get runtime PM.\n"); 135 goto err_pm_get; 136 } 137 138 trng->clk = devm_clk_get_enabled(&pdev->dev, "secss"); 139 if (IS_ERR(trng->clk)) { 140 ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->clk), 141 "Could not get clock\n"); 142 goto err_clock; 143 } 144 145 trng->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk"); 146 if (IS_ERR(trng->pclk)) { 147 ret = dev_err_probe(&pdev->dev, PTR_ERR(trng->pclk), 148 "Could not get pclk\n"); 149 goto err_clock; 150 } 151 152 ret = devm_hwrng_register(&pdev->dev, &trng->rng); 153 if (ret) { 154 dev_err(&pdev->dev, "Could not register hwrng device.\n"); 155 goto err_clock; 156 } 157 158 dev_info(&pdev->dev, "Exynos True Random Number Generator.\n"); 159 160 return 0; 161 162 err_clock: 163 pm_runtime_put_noidle(&pdev->dev); 164 165 err_pm_get: 166 pm_runtime_disable(&pdev->dev); 167 168 return ret; 169 } 170 171 static void exynos_trng_remove(struct platform_device *pdev) 172 { 173 pm_runtime_put_sync(&pdev->dev); 174 pm_runtime_disable(&pdev->dev); 175 } 176 177 static int exynos_trng_suspend(struct device *dev) 178 { 179 pm_runtime_put_sync(dev); 180 181 return 0; 182 } 183 184 static int exynos_trng_resume(struct device *dev) 185 { 186 int ret; 187 188 ret = pm_runtime_resume_and_get(dev); 189 if (ret < 0) { 190 dev_err(dev, "Could not get runtime PM.\n"); 191 return ret; 192 } 193 194 return 0; 195 } 196 197 static DEFINE_SIMPLE_DEV_PM_OPS(exynos_trng_pm_ops, exynos_trng_suspend, 198 exynos_trng_resume); 199 200 static const struct of_device_id exynos_trng_dt_match[] = { 201 { 202 .compatible = "samsung,exynos5250-trng", 203 }, 204 { }, 205 }; 206 MODULE_DEVICE_TABLE(of, exynos_trng_dt_match); 207 208 static struct platform_driver exynos_trng_driver = { 209 .driver = { 210 .name = "exynos-trng", 211 .pm = pm_sleep_ptr(&exynos_trng_pm_ops), 212 .of_match_table = exynos_trng_dt_match, 213 }, 214 .probe = exynos_trng_probe, 215 .remove_new = exynos_trng_remove, 216 }; 217 218 module_platform_driver(exynos_trng_driver); 219 220 MODULE_AUTHOR("Łukasz Stelmach"); 221 MODULE_DESCRIPTION("H/W TRNG driver for Exynos chips"); 222 MODULE_LICENSE("GPL v2"); 223