1 /* 2 * UniNorth AGPGART routines. 3 */ 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 #include <linux/init.h> 7 #include <linux/pagemap.h> 8 #include <linux/agp_backend.h> 9 #include <linux/delay.h> 10 #include <asm/uninorth.h> 11 #include <asm/pci-bridge.h> 12 #include <asm/prom.h> 13 #include <asm/pmac_feature.h> 14 #include "agp.h" 15 16 /* 17 * NOTES for uninorth3 (G5 AGP) supports : 18 * 19 * There maybe also possibility to have bigger cache line size for 20 * agp (see pmac_pci.c and look for cache line). Need to be investigated 21 * by someone. 22 * 23 * PAGE size are hardcoded but this may change, see asm/page.h. 24 * 25 * Jerome Glisse <j.glisse@gmail.com> 26 */ 27 static int uninorth_rev; 28 static int is_u3; 29 30 31 static int uninorth_fetch_size(void) 32 { 33 int i; 34 u32 temp; 35 struct aper_size_info_32 *values; 36 37 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_BASE, &temp); 38 temp &= ~(0xfffff000); 39 values = A_SIZE_32(agp_bridge->driver->aperture_sizes); 40 41 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 42 if (temp == values[i].size_value) { 43 agp_bridge->previous_size = 44 agp_bridge->current_size = (void *) (values + i); 45 agp_bridge->aperture_size_idx = i; 46 return values[i].size; 47 } 48 } 49 50 agp_bridge->previous_size = 51 agp_bridge->current_size = (void *) (values + 1); 52 agp_bridge->aperture_size_idx = 1; 53 return values[1].size; 54 55 return 0; 56 } 57 58 static void uninorth_tlbflush(struct agp_memory *mem) 59 { 60 u32 ctrl = UNI_N_CFG_GART_ENABLE; 61 62 if (is_u3) 63 ctrl |= U3_N_CFG_GART_PERFRD; 64 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 65 ctrl | UNI_N_CFG_GART_INVAL); 66 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 67 68 if (uninorth_rev <= 0x30) { 69 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 70 ctrl | UNI_N_CFG_GART_2xRESET); 71 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 72 ctrl); 73 } 74 } 75 76 static void uninorth_cleanup(void) 77 { 78 u32 tmp; 79 80 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); 81 if (!(tmp & UNI_N_CFG_GART_ENABLE)) 82 return; 83 tmp |= UNI_N_CFG_GART_INVAL; 84 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); 85 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); 86 87 if (uninorth_rev <= 0x30) { 88 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 89 UNI_N_CFG_GART_2xRESET); 90 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 91 0); 92 } 93 } 94 95 static int uninorth_configure(void) 96 { 97 struct aper_size_info_32 *current_size; 98 99 current_size = A_SIZE_32(agp_bridge->current_size); 100 101 printk(KERN_INFO PFX "configuring for size idx: %d\n", 102 current_size->size_value); 103 104 /* aperture size and gatt addr */ 105 pci_write_config_dword(agp_bridge->dev, 106 UNI_N_CFG_GART_BASE, 107 (agp_bridge->gatt_bus_addr & 0xfffff000) 108 | current_size->size_value); 109 110 /* HACK ALERT 111 * UniNorth seem to be buggy enough not to handle properly when 112 * the AGP aperture isn't mapped at bus physical address 0 113 */ 114 agp_bridge->gart_bus_addr = 0; 115 #ifdef CONFIG_PPC64 116 /* Assume U3 or later on PPC64 systems */ 117 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ 118 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, 119 (agp_bridge->gatt_bus_addr >> 32) & 0xf); 120 #else 121 pci_write_config_dword(agp_bridge->dev, 122 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); 123 #endif 124 125 if (is_u3) { 126 pci_write_config_dword(agp_bridge->dev, 127 UNI_N_CFG_GART_DUMMY_PAGE, 128 agp_bridge->scratch_page_real >> 12); 129 } 130 131 return 0; 132 } 133 134 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, 135 int type) 136 { 137 int i, j, num_entries; 138 void *temp; 139 140 temp = agp_bridge->current_size; 141 num_entries = A_SIZE_32(temp)->num_entries; 142 143 if (type != 0 || mem->type != 0) 144 /* We know nothing of memory types */ 145 return -EINVAL; 146 if ((pg_start + mem->page_count) > num_entries) 147 return -EINVAL; 148 149 j = pg_start; 150 151 while (j < (pg_start + mem->page_count)) { 152 if (agp_bridge->gatt_table[j]) 153 return -EBUSY; 154 j++; 155 } 156 157 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 158 agp_bridge->gatt_table[j] = 159 cpu_to_le32((mem->memory[i] & 0xFFFFF000UL) | 0x1UL); 160 flush_dcache_range((unsigned long)__va(mem->memory[i]), 161 (unsigned long)__va(mem->memory[i])+0x1000); 162 } 163 (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]); 164 mb(); 165 flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start], 166 (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]); 167 168 uninorth_tlbflush(mem); 169 return 0; 170 } 171 172 static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 173 { 174 int i, num_entries; 175 void *temp; 176 u32 *gp; 177 178 temp = agp_bridge->current_size; 179 num_entries = A_SIZE_32(temp)->num_entries; 180 181 if (type != 0 || mem->type != 0) 182 /* We know nothing of memory types */ 183 return -EINVAL; 184 if ((pg_start + mem->page_count) > num_entries) 185 return -EINVAL; 186 187 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 188 for (i = 0; i < mem->page_count; ++i) { 189 if (gp[i]) { 190 printk("u3_insert_memory: entry 0x%x occupied (%x)\n", 191 i, gp[i]); 192 return -EBUSY; 193 } 194 } 195 196 for (i = 0; i < mem->page_count; i++) { 197 gp[i] = (mem->memory[i] >> PAGE_SHIFT) | 0x80000000UL; 198 flush_dcache_range((unsigned long)__va(mem->memory[i]), 199 (unsigned long)__va(mem->memory[i])+0x1000); 200 } 201 mb(); 202 flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); 203 uninorth_tlbflush(mem); 204 205 return 0; 206 } 207 208 int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 209 { 210 size_t i; 211 u32 *gp; 212 213 if (type != 0 || mem->type != 0) 214 /* We know nothing of memory types */ 215 return -EINVAL; 216 217 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 218 for (i = 0; i < mem->page_count; ++i) 219 gp[i] = 0; 220 mb(); 221 flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); 222 uninorth_tlbflush(mem); 223 224 return 0; 225 } 226 227 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) 228 { 229 u32 command, scratch, status; 230 int timeout; 231 232 pci_read_config_dword(bridge->dev, 233 bridge->capndx + PCI_AGP_STATUS, 234 &status); 235 236 command = agp_collect_device_status(bridge, mode, status); 237 command |= PCI_AGP_COMMAND_AGP; 238 239 if (uninorth_rev == 0x21) { 240 /* 241 * Darwin disable AGP 4x on this revision, thus we 242 * may assume it's broken. This is an AGP2 controller. 243 */ 244 command &= ~AGPSTAT2_4X; 245 } 246 247 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { 248 /* 249 * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, 250 * 2.2 and 2.3, Darwin do so. 251 */ 252 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) 253 command = (command & ~AGPSTAT_RQ_DEPTH) 254 | (7 << AGPSTAT_RQ_DEPTH_SHIFT); 255 } 256 257 uninorth_tlbflush(NULL); 258 259 timeout = 0; 260 do { 261 pci_write_config_dword(bridge->dev, 262 bridge->capndx + PCI_AGP_COMMAND, 263 command); 264 pci_read_config_dword(bridge->dev, 265 bridge->capndx + PCI_AGP_COMMAND, 266 &scratch); 267 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); 268 if ((scratch & PCI_AGP_COMMAND_AGP) == 0) 269 printk(KERN_ERR PFX "failed to write UniNorth AGP" 270 " command register\n"); 271 272 if (uninorth_rev >= 0x30) { 273 /* This is an AGP V3 */ 274 agp_device_command(command, (status & AGPSTAT_MODE_3_0)); 275 } else { 276 /* AGP V2 */ 277 agp_device_command(command, 0); 278 } 279 280 uninorth_tlbflush(NULL); 281 } 282 283 #ifdef CONFIG_PM 284 /* 285 * These Power Management routines are _not_ called by the normal PCI PM layer, 286 * but directly by the video driver through function pointers in the device 287 * tree. 288 */ 289 static int agp_uninorth_suspend(struct pci_dev *pdev) 290 { 291 struct agp_bridge_data *bridge; 292 u32 cmd; 293 u8 agp; 294 struct pci_dev *device = NULL; 295 296 bridge = agp_find_bridge(pdev); 297 if (bridge == NULL) 298 return -ENODEV; 299 300 /* Only one suspend supported */ 301 if (bridge->dev_private_data) 302 return 0; 303 304 /* turn off AGP on the video chip, if it was enabled */ 305 for_each_pci_dev(device) { 306 /* Don't touch the bridge yet, device first */ 307 if (device == pdev) 308 continue; 309 /* Only deal with devices on the same bus here, no Mac has a P2P 310 * bridge on the AGP port, and mucking around the entire PCI 311 * tree is source of problems on some machines because of a bug 312 * in some versions of pci_find_capability() when hitting a dead 313 * device 314 */ 315 if (device->bus != pdev->bus) 316 continue; 317 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 318 if (!agp) 319 continue; 320 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); 321 if (!(cmd & PCI_AGP_COMMAND_AGP)) 322 continue; 323 printk("uninorth-agp: disabling AGP on device %s\n", 324 pci_name(device)); 325 cmd &= ~PCI_AGP_COMMAND_AGP; 326 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); 327 } 328 329 /* turn off AGP on the bridge */ 330 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); 331 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); 332 bridge->dev_private_data = (void *)cmd; 333 if (cmd & PCI_AGP_COMMAND_AGP) { 334 printk("uninorth-agp: disabling AGP on bridge %s\n", 335 pci_name(pdev)); 336 cmd &= ~PCI_AGP_COMMAND_AGP; 337 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); 338 } 339 /* turn off the GART */ 340 uninorth_cleanup(); 341 342 return 0; 343 } 344 345 static int agp_uninorth_resume(struct pci_dev *pdev) 346 { 347 struct agp_bridge_data *bridge; 348 u32 command; 349 350 bridge = agp_find_bridge(pdev); 351 if (bridge == NULL) 352 return -ENODEV; 353 354 command = (u32)bridge->dev_private_data; 355 bridge->dev_private_data = NULL; 356 if (!(command & PCI_AGP_COMMAND_AGP)) 357 return 0; 358 359 uninorth_agp_enable(bridge, command); 360 361 return 0; 362 } 363 #endif /* CONFIG_PM */ 364 365 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) 366 { 367 char *table; 368 char *table_end; 369 int size; 370 int page_order; 371 int num_entries; 372 int i; 373 void *temp; 374 struct page *page; 375 376 /* We can't handle 2 level gatt's */ 377 if (bridge->driver->size_type == LVL2_APER_SIZE) 378 return -EINVAL; 379 380 table = NULL; 381 i = bridge->aperture_size_idx; 382 temp = bridge->current_size; 383 size = page_order = num_entries = 0; 384 385 do { 386 size = A_SIZE_32(temp)->size; 387 page_order = A_SIZE_32(temp)->page_order; 388 num_entries = A_SIZE_32(temp)->num_entries; 389 390 table = (char *) __get_free_pages(GFP_KERNEL, page_order); 391 392 if (table == NULL) { 393 i++; 394 bridge->current_size = A_IDX32(bridge); 395 } else { 396 bridge->aperture_size_idx = i; 397 } 398 } while (!table && (i < bridge->driver->num_aperture_sizes)); 399 400 if (table == NULL) 401 return -ENOMEM; 402 403 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 404 405 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 406 SetPageReserved(page); 407 408 bridge->gatt_table_real = (u32 *) table; 409 bridge->gatt_table = (u32 *)table; 410 bridge->gatt_bus_addr = virt_to_gart(table); 411 412 for (i = 0; i < num_entries; i++) 413 bridge->gatt_table[i] = 0; 414 415 flush_dcache_range((unsigned long)table, (unsigned long)table_end); 416 417 return 0; 418 } 419 420 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) 421 { 422 int page_order; 423 char *table, *table_end; 424 void *temp; 425 struct page *page; 426 427 temp = bridge->current_size; 428 page_order = A_SIZE_32(temp)->page_order; 429 430 /* Do not worry about freeing memory, because if this is 431 * called, then all agp memory is deallocated and removed 432 * from the table. 433 */ 434 435 table = (char *) bridge->gatt_table_real; 436 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 437 438 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 439 ClearPageReserved(page); 440 441 free_pages((unsigned long) bridge->gatt_table_real, page_order); 442 443 return 0; 444 } 445 446 void null_cache_flush(void) 447 { 448 mb(); 449 } 450 451 /* Setup function */ 452 453 static struct aper_size_info_32 uninorth_sizes[7] = 454 { 455 #if 0 /* Not sure uninorth supports that high aperture sizes */ 456 {256, 65536, 6, 64}, 457 {128, 32768, 5, 32}, 458 {64, 16384, 4, 16}, 459 #endif 460 {32, 8192, 3, 8}, 461 {16, 4096, 2, 4}, 462 {8, 2048, 1, 2}, 463 {4, 1024, 0, 1} 464 }; 465 466 /* 467 * Not sure that u3 supports that high aperture sizes but it 468 * would strange if it did not :) 469 */ 470 static struct aper_size_info_32 u3_sizes[8] = 471 { 472 {512, 131072, 7, 128}, 473 {256, 65536, 6, 64}, 474 {128, 32768, 5, 32}, 475 {64, 16384, 4, 16}, 476 {32, 8192, 3, 8}, 477 {16, 4096, 2, 4}, 478 {8, 2048, 1, 2}, 479 {4, 1024, 0, 1} 480 }; 481 482 struct agp_bridge_driver uninorth_agp_driver = { 483 .owner = THIS_MODULE, 484 .aperture_sizes = (void *)uninorth_sizes, 485 .size_type = U32_APER_SIZE, 486 .num_aperture_sizes = 4, 487 .configure = uninorth_configure, 488 .fetch_size = uninorth_fetch_size, 489 .cleanup = uninorth_cleanup, 490 .tlb_flush = uninorth_tlbflush, 491 .mask_memory = agp_generic_mask_memory, 492 .masks = NULL, 493 .cache_flush = null_cache_flush, 494 .agp_enable = uninorth_agp_enable, 495 .create_gatt_table = uninorth_create_gatt_table, 496 .free_gatt_table = uninorth_free_gatt_table, 497 .insert_memory = uninorth_insert_memory, 498 .remove_memory = agp_generic_remove_memory, 499 .alloc_by_type = agp_generic_alloc_by_type, 500 .free_by_type = agp_generic_free_by_type, 501 .agp_alloc_page = agp_generic_alloc_page, 502 .agp_destroy_page = agp_generic_destroy_page, 503 .cant_use_aperture = 1, 504 }; 505 506 struct agp_bridge_driver u3_agp_driver = { 507 .owner = THIS_MODULE, 508 .aperture_sizes = (void *)u3_sizes, 509 .size_type = U32_APER_SIZE, 510 .num_aperture_sizes = 8, 511 .configure = uninorth_configure, 512 .fetch_size = uninorth_fetch_size, 513 .cleanup = uninorth_cleanup, 514 .tlb_flush = uninorth_tlbflush, 515 .mask_memory = agp_generic_mask_memory, 516 .masks = NULL, 517 .cache_flush = null_cache_flush, 518 .agp_enable = uninorth_agp_enable, 519 .create_gatt_table = uninorth_create_gatt_table, 520 .free_gatt_table = uninorth_free_gatt_table, 521 .insert_memory = u3_insert_memory, 522 .remove_memory = u3_remove_memory, 523 .alloc_by_type = agp_generic_alloc_by_type, 524 .free_by_type = agp_generic_free_by_type, 525 .agp_alloc_page = agp_generic_alloc_page, 526 .agp_destroy_page = agp_generic_destroy_page, 527 .cant_use_aperture = 1, 528 .needs_scratch_page = 1, 529 }; 530 531 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { 532 { 533 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, 534 .chipset_name = "UniNorth", 535 }, 536 { 537 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, 538 .chipset_name = "UniNorth/Pangea", 539 }, 540 { 541 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, 542 .chipset_name = "UniNorth 1.5", 543 }, 544 { 545 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, 546 .chipset_name = "UniNorth 2", 547 }, 548 { 549 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, 550 .chipset_name = "U3", 551 }, 552 { 553 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, 554 .chipset_name = "U3L", 555 }, 556 { 557 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, 558 .chipset_name = "U3H", 559 }, 560 }; 561 562 static int __devinit agp_uninorth_probe(struct pci_dev *pdev, 563 const struct pci_device_id *ent) 564 { 565 struct agp_device_ids *devs = uninorth_agp_device_ids; 566 struct agp_bridge_data *bridge; 567 struct device_node *uninorth_node; 568 u8 cap_ptr; 569 int j; 570 571 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 572 if (cap_ptr == 0) 573 return -ENODEV; 574 575 /* probe for known chipsets */ 576 for (j = 0; devs[j].chipset_name != NULL; ++j) { 577 if (pdev->device == devs[j].device_id) { 578 printk(KERN_INFO PFX "Detected Apple %s chipset\n", 579 devs[j].chipset_name); 580 goto found; 581 } 582 } 583 584 printk(KERN_ERR PFX "Unsupported Apple chipset (device id: %04x).\n", 585 pdev->device); 586 return -ENODEV; 587 588 found: 589 /* Set revision to 0 if we could not read it. */ 590 uninorth_rev = 0; 591 is_u3 = 0; 592 /* Locate core99 Uni-N */ 593 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 594 /* Locate G5 u3 */ 595 if (uninorth_node == NULL) { 596 is_u3 = 1; 597 uninorth_node = of_find_node_by_name(NULL, "u3"); 598 } 599 if (uninorth_node) { 600 int *revprop = (int *) 601 get_property(uninorth_node, "device-rev", NULL); 602 if (revprop != NULL) 603 uninorth_rev = *revprop & 0x3f; 604 of_node_put(uninorth_node); 605 } 606 607 #ifdef CONFIG_PM 608 /* Inform platform of our suspend/resume caps */ 609 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); 610 #endif 611 612 /* Allocate & setup our driver */ 613 bridge = agp_alloc_bridge(); 614 if (!bridge) 615 return -ENOMEM; 616 617 if (is_u3) 618 bridge->driver = &u3_agp_driver; 619 else 620 bridge->driver = &uninorth_agp_driver; 621 622 bridge->dev = pdev; 623 bridge->capndx = cap_ptr; 624 bridge->flags = AGP_ERRATA_FASTWRITES; 625 626 /* Fill in the mode register */ 627 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); 628 629 pci_set_drvdata(pdev, bridge); 630 return agp_add_bridge(bridge); 631 } 632 633 static void __devexit agp_uninorth_remove(struct pci_dev *pdev) 634 { 635 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 636 637 #ifdef CONFIG_PM 638 /* Inform platform of our suspend/resume caps */ 639 pmac_register_agp_pm(pdev, NULL, NULL); 640 #endif 641 642 agp_remove_bridge(bridge); 643 agp_put_bridge(bridge); 644 } 645 646 static struct pci_device_id agp_uninorth_pci_table[] = { 647 { 648 .class = (PCI_CLASS_BRIDGE_HOST << 8), 649 .class_mask = ~0, 650 .vendor = PCI_VENDOR_ID_APPLE, 651 .device = PCI_ANY_ID, 652 .subvendor = PCI_ANY_ID, 653 .subdevice = PCI_ANY_ID, 654 }, 655 { } 656 }; 657 658 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); 659 660 static struct pci_driver agp_uninorth_pci_driver = { 661 .name = "agpgart-uninorth", 662 .id_table = agp_uninorth_pci_table, 663 .probe = agp_uninorth_probe, 664 .remove = agp_uninorth_remove, 665 }; 666 667 static int __init agp_uninorth_init(void) 668 { 669 if (agp_off) 670 return -EINVAL; 671 return pci_register_driver(&agp_uninorth_pci_driver); 672 } 673 674 static void __exit agp_uninorth_cleanup(void) 675 { 676 pci_unregister_driver(&agp_uninorth_pci_driver); 677 } 678 679 module_init(agp_uninorth_init); 680 module_exit(agp_uninorth_cleanup); 681 682 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); 683 MODULE_LICENSE("GPL"); 684