1 /* 2 * Serverworks AGPGART routines. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/init.h> 8 #include <linux/string.h> 9 #include <linux/slab.h> 10 #include <linux/jiffies.h> 11 #include <linux/agp_backend.h> 12 #include <asm/set_memory.h> 13 #include "agp.h" 14 15 #define SVWRKS_COMMAND 0x04 16 #define SVWRKS_APSIZE 0x10 17 #define SVWRKS_MMBASE 0x14 18 #define SVWRKS_CACHING 0x4b 19 #define SVWRKS_AGP_ENABLE 0x60 20 #define SVWRKS_FEATURE 0x68 21 22 #define SVWRKS_SIZE_MASK 0xfe000000 23 24 /* Memory mapped registers */ 25 #define SVWRKS_GART_CACHE 0x02 26 #define SVWRKS_GATTBASE 0x04 27 #define SVWRKS_TLBFLUSH 0x10 28 #define SVWRKS_POSTFLUSH 0x14 29 #define SVWRKS_DIRFLUSH 0x0c 30 31 32 struct serverworks_page_map { 33 unsigned long *real; 34 unsigned long __iomem *remapped; 35 }; 36 37 static struct _serverworks_private { 38 struct pci_dev *svrwrks_dev; /* device one */ 39 volatile u8 __iomem *registers; 40 struct serverworks_page_map **gatt_pages; 41 int num_tables; 42 struct serverworks_page_map scratch_dir; 43 44 int gart_addr_ofs; 45 int mm_addr_ofs; 46 } serverworks_private; 47 48 static int serverworks_create_page_map(struct serverworks_page_map *page_map) 49 { 50 int i; 51 52 page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL); 53 if (page_map->real == NULL) { 54 return -ENOMEM; 55 } 56 57 set_memory_uc((unsigned long)page_map->real, 1); 58 page_map->remapped = page_map->real; 59 60 for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) 61 writel(agp_bridge->scratch_page, page_map->remapped+i); 62 /* Red Pen: Everyone else does pci posting flush here */ 63 64 return 0; 65 } 66 67 static void serverworks_free_page_map(struct serverworks_page_map *page_map) 68 { 69 set_memory_wb((unsigned long)page_map->real, 1); 70 free_page((unsigned long) page_map->real); 71 } 72 73 static void serverworks_free_gatt_pages(void) 74 { 75 int i; 76 struct serverworks_page_map **tables; 77 struct serverworks_page_map *entry; 78 79 tables = serverworks_private.gatt_pages; 80 for (i = 0; i < serverworks_private.num_tables; i++) { 81 entry = tables[i]; 82 if (entry != NULL) { 83 if (entry->real != NULL) { 84 serverworks_free_page_map(entry); 85 } 86 kfree(entry); 87 } 88 } 89 kfree(tables); 90 } 91 92 static int serverworks_create_gatt_pages(int nr_tables) 93 { 94 struct serverworks_page_map **tables; 95 struct serverworks_page_map *entry; 96 int retval = 0; 97 int i; 98 99 tables = kzalloc_objs(struct serverworks_page_map *, nr_tables + 1); 100 if (tables == NULL) 101 return -ENOMEM; 102 103 for (i = 0; i < nr_tables; i++) { 104 entry = kzalloc_obj(struct serverworks_page_map); 105 if (entry == NULL) { 106 retval = -ENOMEM; 107 break; 108 } 109 tables[i] = entry; 110 retval = serverworks_create_page_map(entry); 111 if (retval != 0) break; 112 } 113 serverworks_private.num_tables = nr_tables; 114 serverworks_private.gatt_pages = tables; 115 116 if (retval != 0) serverworks_free_gatt_pages(); 117 118 return retval; 119 } 120 121 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\ 122 GET_PAGE_DIR_IDX(addr)]->remapped) 123 124 #ifndef GET_PAGE_DIR_OFF 125 #define GET_PAGE_DIR_OFF(addr) (addr >> 22) 126 #endif 127 128 #ifndef GET_PAGE_DIR_IDX 129 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ 130 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) 131 #endif 132 133 #ifndef GET_GATT_OFF 134 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) 135 #endif 136 137 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge) 138 { 139 struct aper_size_info_lvl2 *value; 140 struct serverworks_page_map page_dir; 141 int retval; 142 u32 temp; 143 int i; 144 145 value = A_SIZE_LVL2(agp_bridge->current_size); 146 retval = serverworks_create_page_map(&page_dir); 147 if (retval != 0) { 148 return retval; 149 } 150 retval = serverworks_create_page_map(&serverworks_private.scratch_dir); 151 if (retval != 0) { 152 serverworks_free_page_map(&page_dir); 153 return retval; 154 } 155 /* Create a fake scratch directory */ 156 for (i = 0; i < 1024; i++) { 157 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i); 158 writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i); 159 } 160 161 retval = serverworks_create_gatt_pages(value->num_entries / 1024); 162 if (retval != 0) { 163 serverworks_free_page_map(&page_dir); 164 serverworks_free_page_map(&serverworks_private.scratch_dir); 165 return retval; 166 } 167 168 agp_bridge->gatt_table_real = (u32 *)page_dir.real; 169 agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped; 170 agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real); 171 172 /* Get the address for the gart region. 173 * This is a bus address even on the alpha, b/c its 174 * used to program the agp master not the cpu 175 */ 176 177 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp); 178 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 179 180 /* Calculate the agp offset */ 181 for (i = 0; i < value->num_entries / 1024; i++) 182 writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i); 183 184 return 0; 185 } 186 187 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge) 188 { 189 struct serverworks_page_map page_dir; 190 191 page_dir.real = (unsigned long *)agp_bridge->gatt_table_real; 192 page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table; 193 194 serverworks_free_gatt_pages(); 195 serverworks_free_page_map(&page_dir); 196 serverworks_free_page_map(&serverworks_private.scratch_dir); 197 return 0; 198 } 199 200 static int serverworks_fetch_size(void) 201 { 202 int i; 203 u32 temp; 204 u32 temp2; 205 struct aper_size_info_lvl2 *values; 206 207 values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); 208 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp); 209 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs, 210 SVWRKS_SIZE_MASK); 211 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2); 212 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp); 213 temp2 &= SVWRKS_SIZE_MASK; 214 215 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 216 if (temp2 == values[i].size_value) { 217 agp_bridge->previous_size = 218 agp_bridge->current_size = (void *) (values + i); 219 220 agp_bridge->aperture_size_idx = i; 221 return values[i].size; 222 } 223 } 224 225 return 0; 226 } 227 228 /* 229 * This routine could be implemented by taking the addresses 230 * written to the GATT, and flushing them individually. However 231 * currently it just flushes the whole table. Which is probably 232 * more efficient, since agp_memory blocks can be a large number of 233 * entries. 234 */ 235 static void serverworks_tlbflush(struct agp_memory *temp) 236 { 237 unsigned long timeout; 238 239 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); 240 timeout = jiffies + 3*HZ; 241 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { 242 cpu_relax(); 243 if (time_after(jiffies, timeout)) { 244 dev_err(&serverworks_private.svrwrks_dev->dev, 245 "TLB post flush took more than 3 seconds\n"); 246 break; 247 } 248 } 249 250 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); 251 timeout = jiffies + 3*HZ; 252 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { 253 cpu_relax(); 254 if (time_after(jiffies, timeout)) { 255 dev_err(&serverworks_private.svrwrks_dev->dev, 256 "TLB Dir flush took more than 3 seconds\n"); 257 break; 258 } 259 } 260 } 261 262 static int serverworks_configure(void) 263 { 264 u32 temp; 265 u8 enable_reg; 266 u16 cap_reg; 267 268 /* Get the memory mapped registers */ 269 pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp); 270 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK); 271 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); 272 if (!serverworks_private.registers) { 273 dev_err(&agp_bridge->dev->dev, "can't ioremap(%#x)\n", temp); 274 return -ENOMEM; 275 } 276 277 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); 278 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ 279 280 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); 281 readl(serverworks_private.registers+SVWRKS_GATTBASE); /* PCI Posting. */ 282 283 cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND); 284 cap_reg &= ~0x0007; 285 cap_reg |= 0x4; 286 writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND); 287 readw(serverworks_private.registers+SVWRKS_COMMAND); 288 289 pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg); 290 enable_reg |= 0x1; /* Agp Enable bit */ 291 pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg); 292 serverworks_tlbflush(NULL); 293 294 agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP); 295 296 /* Fill in the mode register */ 297 pci_read_config_dword(serverworks_private.svrwrks_dev, 298 agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode); 299 300 pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg); 301 enable_reg &= ~0x3; 302 pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg); 303 304 pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg); 305 enable_reg |= (1<<6); 306 pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg); 307 308 return 0; 309 } 310 311 static void serverworks_cleanup(void) 312 { 313 iounmap((void __iomem *) serverworks_private.registers); 314 } 315 316 static int serverworks_insert_memory(struct agp_memory *mem, 317 off_t pg_start, int type) 318 { 319 int i, j, num_entries; 320 unsigned long __iomem *cur_gatt; 321 unsigned long addr; 322 323 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; 324 325 if (type != 0 || mem->type != 0) { 326 return -EINVAL; 327 } 328 if ((pg_start + mem->page_count) > num_entries) { 329 return -EINVAL; 330 } 331 332 j = pg_start; 333 while (j < (pg_start + mem->page_count)) { 334 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; 335 cur_gatt = SVRWRKS_GET_GATT(addr); 336 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr)))) 337 return -EBUSY; 338 j++; 339 } 340 341 if (!mem->is_flushed) { 342 global_cache_flush(); 343 mem->is_flushed = true; 344 } 345 346 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 347 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr; 348 cur_gatt = SVRWRKS_GET_GATT(addr); 349 writel(agp_bridge->driver->mask_memory(agp_bridge, 350 page_to_phys(mem->pages[i]), mem->type), 351 cur_gatt+GET_GATT_OFF(addr)); 352 } 353 serverworks_tlbflush(mem); 354 return 0; 355 } 356 357 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start, 358 int type) 359 { 360 int i; 361 unsigned long __iomem *cur_gatt; 362 unsigned long addr; 363 364 if (type != 0 || mem->type != 0) { 365 return -EINVAL; 366 } 367 368 global_cache_flush(); 369 serverworks_tlbflush(mem); 370 371 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 372 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr; 373 cur_gatt = SVRWRKS_GET_GATT(addr); 374 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr)); 375 } 376 377 serverworks_tlbflush(mem); 378 return 0; 379 } 380 381 static const struct gatt_mask serverworks_masks[] = 382 { 383 {.mask = 1, .type = 0} 384 }; 385 386 static const struct aper_size_info_lvl2 serverworks_sizes[7] = 387 { 388 {2048, 524288, 0x80000000}, 389 {1024, 262144, 0xc0000000}, 390 {512, 131072, 0xe0000000}, 391 {256, 65536, 0xf0000000}, 392 {128, 32768, 0xf8000000}, 393 {64, 16384, 0xfc000000}, 394 {32, 8192, 0xfe000000} 395 }; 396 397 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode) 398 { 399 u32 command; 400 401 pci_read_config_dword(serverworks_private.svrwrks_dev, 402 bridge->capndx + PCI_AGP_STATUS, 403 &command); 404 405 command = agp_collect_device_status(bridge, mode, command); 406 407 command &= ~0x10; /* disable FW */ 408 command &= ~0x08; 409 410 command |= 0x100; 411 412 pci_write_config_dword(serverworks_private.svrwrks_dev, 413 bridge->capndx + PCI_AGP_COMMAND, 414 command); 415 416 agp_device_command(command, false); 417 } 418 419 static const struct agp_bridge_driver sworks_driver = { 420 .owner = THIS_MODULE, 421 .aperture_sizes = serverworks_sizes, 422 .size_type = LVL2_APER_SIZE, 423 .num_aperture_sizes = 7, 424 .configure = serverworks_configure, 425 .fetch_size = serverworks_fetch_size, 426 .cleanup = serverworks_cleanup, 427 .tlb_flush = serverworks_tlbflush, 428 .mask_memory = agp_generic_mask_memory, 429 .masks = serverworks_masks, 430 .agp_enable = serverworks_agp_enable, 431 .cache_flush = global_cache_flush, 432 .create_gatt_table = serverworks_create_gatt_table, 433 .free_gatt_table = serverworks_free_gatt_table, 434 .insert_memory = serverworks_insert_memory, 435 .remove_memory = serverworks_remove_memory, 436 .alloc_by_type = agp_generic_alloc_by_type, 437 .free_by_type = agp_generic_free_by_type, 438 .agp_alloc_page = agp_generic_alloc_page, 439 .agp_alloc_pages = agp_generic_alloc_pages, 440 .agp_destroy_page = agp_generic_destroy_page, 441 .agp_destroy_pages = agp_generic_destroy_pages, 442 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 443 }; 444 445 static int agp_serverworks_probe(struct pci_dev *pdev, 446 const struct pci_device_id *ent) 447 { 448 struct agp_bridge_data *bridge; 449 struct pci_dev *bridge_dev; 450 u32 temp, temp2; 451 u8 cap_ptr = 0; 452 453 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 454 455 switch (pdev->device) { 456 case 0x0006: 457 dev_err(&pdev->dev, "ServerWorks CNB20HE is unsupported due to lack of documentation\n"); 458 return -ENODEV; 459 460 case PCI_DEVICE_ID_SERVERWORKS_HE: 461 case PCI_DEVICE_ID_SERVERWORKS_LE: 462 case 0x0007: 463 break; 464 465 default: 466 if (cap_ptr) 467 dev_err(&pdev->dev, "unsupported Serverworks chipset " 468 "[%04x/%04x]\n", pdev->vendor, pdev->device); 469 return -ENODEV; 470 } 471 472 /* Everything is on func 1 here so we are hardcoding function one */ 473 bridge_dev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 474 (unsigned int)pdev->bus->number, 475 PCI_DEVFN(0, 1)); 476 if (!bridge_dev) { 477 dev_info(&pdev->dev, "can't find secondary device\n"); 478 return -ENODEV; 479 } 480 481 serverworks_private.svrwrks_dev = bridge_dev; 482 serverworks_private.gart_addr_ofs = 0x10; 483 484 pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp); 485 if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { 486 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2); 487 if (temp2 != 0) { 488 dev_info(&pdev->dev, "64 bit aperture address, " 489 "but top bits are not zero; disabling AGP\n"); 490 return -ENODEV; 491 } 492 serverworks_private.mm_addr_ofs = 0x18; 493 } else 494 serverworks_private.mm_addr_ofs = 0x14; 495 496 pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp); 497 if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) { 498 pci_read_config_dword(pdev, 499 serverworks_private.mm_addr_ofs + 4, &temp2); 500 if (temp2 != 0) { 501 dev_info(&pdev->dev, "64 bit MMIO address, but top " 502 "bits are not zero; disabling AGP\n"); 503 return -ENODEV; 504 } 505 } 506 507 bridge = agp_alloc_bridge(); 508 if (!bridge) 509 return -ENOMEM; 510 511 bridge->driver = &sworks_driver; 512 bridge->dev_private_data = &serverworks_private; 513 bridge->dev = pci_dev_get(pdev); 514 515 pci_set_drvdata(pdev, bridge); 516 return agp_add_bridge(bridge); 517 } 518 519 static void agp_serverworks_remove(struct pci_dev *pdev) 520 { 521 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 522 523 pci_dev_put(bridge->dev); 524 agp_remove_bridge(bridge); 525 agp_put_bridge(bridge); 526 pci_dev_put(serverworks_private.svrwrks_dev); 527 serverworks_private.svrwrks_dev = NULL; 528 } 529 530 static struct pci_device_id agp_serverworks_pci_table[] = { 531 { 532 .class = (PCI_CLASS_BRIDGE_HOST << 8), 533 .class_mask = ~0, 534 .vendor = PCI_VENDOR_ID_SERVERWORKS, 535 .device = PCI_ANY_ID, 536 .subvendor = PCI_ANY_ID, 537 .subdevice = PCI_ANY_ID, 538 }, 539 { } 540 }; 541 542 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table); 543 544 static struct pci_driver agp_serverworks_pci_driver = { 545 .name = "agpgart-serverworks", 546 .id_table = agp_serverworks_pci_table, 547 .probe = agp_serverworks_probe, 548 .remove = agp_serverworks_remove, 549 }; 550 551 static int __init agp_serverworks_init(void) 552 { 553 if (agp_off) 554 return -EINVAL; 555 return pci_register_driver(&agp_serverworks_pci_driver); 556 } 557 558 static void __exit agp_serverworks_cleanup(void) 559 { 560 pci_unregister_driver(&agp_serverworks_pci_driver); 561 } 562 563 module_init(agp_serverworks_init); 564 module_exit(agp_serverworks_cleanup); 565 566 MODULE_DESCRIPTION("Serverworks AGPGART routines"); 567 MODULE_LICENSE("GPL and additional rights"); 568 569