xref: /linux/drivers/char/agp/sworks-agp.c (revision b889fcf63cb62e7fdb7816565e28f44dbe4a76a5)
1 /*
2  * Serverworks AGPGART routines.
3  */
4 
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/string.h>
9 #include <linux/slab.h>
10 #include <linux/jiffies.h>
11 #include <linux/agp_backend.h>
12 #include "agp.h"
13 
14 #define SVWRKS_COMMAND		0x04
15 #define SVWRKS_APSIZE		0x10
16 #define SVWRKS_MMBASE		0x14
17 #define SVWRKS_CACHING		0x4b
18 #define SVWRKS_AGP_ENABLE	0x60
19 #define SVWRKS_FEATURE		0x68
20 
21 #define SVWRKS_SIZE_MASK	0xfe000000
22 
23 /* Memory mapped registers */
24 #define SVWRKS_GART_CACHE	0x02
25 #define SVWRKS_GATTBASE		0x04
26 #define SVWRKS_TLBFLUSH		0x10
27 #define SVWRKS_POSTFLUSH	0x14
28 #define SVWRKS_DIRFLUSH		0x0c
29 
30 
31 struct serverworks_page_map {
32 	unsigned long *real;
33 	unsigned long __iomem *remapped;
34 };
35 
36 static struct _serverworks_private {
37 	struct pci_dev *svrwrks_dev;	/* device one */
38 	volatile u8 __iomem *registers;
39 	struct serverworks_page_map **gatt_pages;
40 	int num_tables;
41 	struct serverworks_page_map scratch_dir;
42 
43 	int gart_addr_ofs;
44 	int mm_addr_ofs;
45 } serverworks_private;
46 
47 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
48 {
49 	int i;
50 
51 	page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
52 	if (page_map->real == NULL) {
53 		return -ENOMEM;
54 	}
55 
56 	set_memory_uc((unsigned long)page_map->real, 1);
57 	page_map->remapped = page_map->real;
58 
59 	for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
60 		writel(agp_bridge->scratch_page, page_map->remapped+i);
61 		/* Red Pen: Everyone else does pci posting flush here */
62 
63 	return 0;
64 }
65 
66 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
67 {
68 	set_memory_wb((unsigned long)page_map->real, 1);
69 	free_page((unsigned long) page_map->real);
70 }
71 
72 static void serverworks_free_gatt_pages(void)
73 {
74 	int i;
75 	struct serverworks_page_map **tables;
76 	struct serverworks_page_map *entry;
77 
78 	tables = serverworks_private.gatt_pages;
79 	for (i = 0; i < serverworks_private.num_tables; i++) {
80 		entry = tables[i];
81 		if (entry != NULL) {
82 			if (entry->real != NULL) {
83 				serverworks_free_page_map(entry);
84 			}
85 			kfree(entry);
86 		}
87 	}
88 	kfree(tables);
89 }
90 
91 static int serverworks_create_gatt_pages(int nr_tables)
92 {
93 	struct serverworks_page_map **tables;
94 	struct serverworks_page_map *entry;
95 	int retval = 0;
96 	int i;
97 
98 	tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
99 			 GFP_KERNEL);
100 	if (tables == NULL)
101 		return -ENOMEM;
102 
103 	for (i = 0; i < nr_tables; i++) {
104 		entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
105 		if (entry == NULL) {
106 			retval = -ENOMEM;
107 			break;
108 		}
109 		tables[i] = entry;
110 		retval = serverworks_create_page_map(entry);
111 		if (retval != 0) break;
112 	}
113 	serverworks_private.num_tables = nr_tables;
114 	serverworks_private.gatt_pages = tables;
115 
116 	if (retval != 0) serverworks_free_gatt_pages();
117 
118 	return retval;
119 }
120 
121 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
122 	GET_PAGE_DIR_IDX(addr)]->remapped)
123 
124 #ifndef GET_PAGE_DIR_OFF
125 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
126 #endif
127 
128 #ifndef GET_PAGE_DIR_IDX
129 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
130 	GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
131 #endif
132 
133 #ifndef GET_GATT_OFF
134 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
135 #endif
136 
137 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
138 {
139 	struct aper_size_info_lvl2 *value;
140 	struct serverworks_page_map page_dir;
141 	int retval;
142 	u32 temp;
143 	int i;
144 
145 	value = A_SIZE_LVL2(agp_bridge->current_size);
146 	retval = serverworks_create_page_map(&page_dir);
147 	if (retval != 0) {
148 		return retval;
149 	}
150 	retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
151 	if (retval != 0) {
152 		serverworks_free_page_map(&page_dir);
153 		return retval;
154 	}
155 	/* Create a fake scratch directory */
156 	for (i = 0; i < 1024; i++) {
157 		writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
158 		writel(virt_to_phys(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
159 	}
160 
161 	retval = serverworks_create_gatt_pages(value->num_entries / 1024);
162 	if (retval != 0) {
163 		serverworks_free_page_map(&page_dir);
164 		serverworks_free_page_map(&serverworks_private.scratch_dir);
165 		return retval;
166 	}
167 
168 	agp_bridge->gatt_table_real = (u32 *)page_dir.real;
169 	agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
170 	agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
171 
172 	/* Get the address for the gart region.
173 	 * This is a bus address even on the alpha, b/c its
174 	 * used to program the agp master not the cpu
175 	 */
176 
177 	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
178 	agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
179 
180 	/* Calculate the agp offset */
181 	for (i = 0; i < value->num_entries / 1024; i++)
182 		writel(virt_to_phys(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
183 
184 	return 0;
185 }
186 
187 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
188 {
189 	struct serverworks_page_map page_dir;
190 
191 	page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
192 	page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
193 
194 	serverworks_free_gatt_pages();
195 	serverworks_free_page_map(&page_dir);
196 	serverworks_free_page_map(&serverworks_private.scratch_dir);
197 	return 0;
198 }
199 
200 static int serverworks_fetch_size(void)
201 {
202 	int i;
203 	u32 temp;
204 	u32 temp2;
205 	struct aper_size_info_lvl2 *values;
206 
207 	values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
208 	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
209 	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
210 					SVWRKS_SIZE_MASK);
211 	pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
212 	pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
213 	temp2 &= SVWRKS_SIZE_MASK;
214 
215 	for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
216 		if (temp2 == values[i].size_value) {
217 			agp_bridge->previous_size =
218 			    agp_bridge->current_size = (void *) (values + i);
219 
220 			agp_bridge->aperture_size_idx = i;
221 			return values[i].size;
222 		}
223 	}
224 
225 	return 0;
226 }
227 
228 /*
229  * This routine could be implemented by taking the addresses
230  * written to the GATT, and flushing them individually.  However
231  * currently it just flushes the whole table.  Which is probably
232  * more efficient, since agp_memory blocks can be a large number of
233  * entries.
234  */
235 static void serverworks_tlbflush(struct agp_memory *temp)
236 {
237 	unsigned long timeout;
238 
239 	writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
240 	timeout = jiffies + 3*HZ;
241 	while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
242 		cpu_relax();
243 		if (time_after(jiffies, timeout)) {
244 			dev_err(&serverworks_private.svrwrks_dev->dev,
245 				"TLB post flush took more than 3 seconds\n");
246 			break;
247 		}
248 	}
249 
250 	writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
251 	timeout = jiffies + 3*HZ;
252 	while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
253 		cpu_relax();
254 		if (time_after(jiffies, timeout)) {
255 			dev_err(&serverworks_private.svrwrks_dev->dev,
256 				"TLB Dir flush took more than 3 seconds\n");
257 			break;
258 		}
259 	}
260 }
261 
262 static int serverworks_configure(void)
263 {
264 	struct aper_size_info_lvl2 *current_size;
265 	u32 temp;
266 	u8 enable_reg;
267 	u16 cap_reg;
268 
269 	current_size = A_SIZE_LVL2(agp_bridge->current_size);
270 
271 	/* Get the memory mapped registers */
272 	pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
273 	temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
274 	serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
275 	if (!serverworks_private.registers) {
276 		dev_err(&agp_bridge->dev->dev, "can't ioremap(%#x)\n", temp);
277 		return -ENOMEM;
278 	}
279 
280 	writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
281 	readb(serverworks_private.registers+SVWRKS_GART_CACHE);	/* PCI Posting. */
282 
283 	writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
284 	readl(serverworks_private.registers+SVWRKS_GATTBASE);	/* PCI Posting. */
285 
286 	cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
287 	cap_reg &= ~0x0007;
288 	cap_reg |= 0x4;
289 	writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
290 	readw(serverworks_private.registers+SVWRKS_COMMAND);
291 
292 	pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
293 	enable_reg |= 0x1; /* Agp Enable bit */
294 	pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
295 	serverworks_tlbflush(NULL);
296 
297 	agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
298 
299 	/* Fill in the mode register */
300 	pci_read_config_dword(serverworks_private.svrwrks_dev,
301 			      agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
302 
303 	pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
304 	enable_reg &= ~0x3;
305 	pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
306 
307 	pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
308 	enable_reg |= (1<<6);
309 	pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
310 
311 	return 0;
312 }
313 
314 static void serverworks_cleanup(void)
315 {
316 	iounmap((void __iomem *) serverworks_private.registers);
317 }
318 
319 static int serverworks_insert_memory(struct agp_memory *mem,
320 			     off_t pg_start, int type)
321 {
322 	int i, j, num_entries;
323 	unsigned long __iomem *cur_gatt;
324 	unsigned long addr;
325 
326 	num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
327 
328 	if (type != 0 || mem->type != 0) {
329 		return -EINVAL;
330 	}
331 	if ((pg_start + mem->page_count) > num_entries) {
332 		return -EINVAL;
333 	}
334 
335 	j = pg_start;
336 	while (j < (pg_start + mem->page_count)) {
337 		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
338 		cur_gatt = SVRWRKS_GET_GATT(addr);
339 		if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
340 			return -EBUSY;
341 		j++;
342 	}
343 
344 	if (!mem->is_flushed) {
345 		global_cache_flush();
346 		mem->is_flushed = true;
347 	}
348 
349 	for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
350 		addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
351 		cur_gatt = SVRWRKS_GET_GATT(addr);
352 		writel(agp_bridge->driver->mask_memory(agp_bridge,
353 				page_to_phys(mem->pages[i]), mem->type),
354 		       cur_gatt+GET_GATT_OFF(addr));
355 	}
356 	serverworks_tlbflush(mem);
357 	return 0;
358 }
359 
360 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
361 			     int type)
362 {
363 	int i;
364 	unsigned long __iomem *cur_gatt;
365 	unsigned long addr;
366 
367 	if (type != 0 || mem->type != 0) {
368 		return -EINVAL;
369 	}
370 
371 	global_cache_flush();
372 	serverworks_tlbflush(mem);
373 
374 	for (i = pg_start; i < (mem->page_count + pg_start); i++) {
375 		addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
376 		cur_gatt = SVRWRKS_GET_GATT(addr);
377 		writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
378 	}
379 
380 	serverworks_tlbflush(mem);
381 	return 0;
382 }
383 
384 static const struct gatt_mask serverworks_masks[] =
385 {
386 	{.mask = 1, .type = 0}
387 };
388 
389 static const struct aper_size_info_lvl2 serverworks_sizes[7] =
390 {
391 	{2048, 524288, 0x80000000},
392 	{1024, 262144, 0xc0000000},
393 	{512, 131072, 0xe0000000},
394 	{256, 65536, 0xf0000000},
395 	{128, 32768, 0xf8000000},
396 	{64, 16384, 0xfc000000},
397 	{32, 8192, 0xfe000000}
398 };
399 
400 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
401 {
402 	u32 command;
403 
404 	pci_read_config_dword(serverworks_private.svrwrks_dev,
405 			      bridge->capndx + PCI_AGP_STATUS,
406 			      &command);
407 
408 	command = agp_collect_device_status(bridge, mode, command);
409 
410 	command &= ~0x10;	/* disable FW */
411 	command &= ~0x08;
412 
413 	command |= 0x100;
414 
415 	pci_write_config_dword(serverworks_private.svrwrks_dev,
416 			       bridge->capndx + PCI_AGP_COMMAND,
417 			       command);
418 
419 	agp_device_command(command, false);
420 }
421 
422 static const struct agp_bridge_driver sworks_driver = {
423 	.owner			= THIS_MODULE,
424 	.aperture_sizes		= serverworks_sizes,
425 	.size_type		= LVL2_APER_SIZE,
426 	.num_aperture_sizes	= 7,
427 	.configure		= serverworks_configure,
428 	.fetch_size		= serverworks_fetch_size,
429 	.cleanup		= serverworks_cleanup,
430 	.tlb_flush		= serverworks_tlbflush,
431 	.mask_memory		= agp_generic_mask_memory,
432 	.masks			= serverworks_masks,
433 	.agp_enable		= serverworks_agp_enable,
434 	.cache_flush		= global_cache_flush,
435 	.create_gatt_table	= serverworks_create_gatt_table,
436 	.free_gatt_table	= serverworks_free_gatt_table,
437 	.insert_memory		= serverworks_insert_memory,
438 	.remove_memory		= serverworks_remove_memory,
439 	.alloc_by_type		= agp_generic_alloc_by_type,
440 	.free_by_type		= agp_generic_free_by_type,
441 	.agp_alloc_page		= agp_generic_alloc_page,
442 	.agp_alloc_pages	= agp_generic_alloc_pages,
443 	.agp_destroy_page	= agp_generic_destroy_page,
444 	.agp_destroy_pages	= agp_generic_destroy_pages,
445 	.agp_type_to_mask_type  = agp_generic_type_to_mask_type,
446 };
447 
448 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
449 					   const struct pci_device_id *ent)
450 {
451 	struct agp_bridge_data *bridge;
452 	struct pci_dev *bridge_dev;
453 	u32 temp, temp2;
454 	u8 cap_ptr = 0;
455 
456 	cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
457 
458 	switch (pdev->device) {
459 	case 0x0006:
460 		dev_err(&pdev->dev, "ServerWorks CNB20HE is unsupported due to lack of documentation\n");
461 		return -ENODEV;
462 
463 	case PCI_DEVICE_ID_SERVERWORKS_HE:
464 	case PCI_DEVICE_ID_SERVERWORKS_LE:
465 	case 0x0007:
466 		break;
467 
468 	default:
469 		if (cap_ptr)
470 			dev_err(&pdev->dev, "unsupported Serverworks chipset "
471 				"[%04x/%04x]\n", pdev->vendor, pdev->device);
472 		return -ENODEV;
473 	}
474 
475 	/* Everything is on func 1 here so we are hardcoding function one */
476 	bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
477 			PCI_DEVFN(0, 1));
478 	if (!bridge_dev) {
479 		dev_info(&pdev->dev, "can't find secondary device\n");
480 		return -ENODEV;
481 	}
482 
483 	serverworks_private.svrwrks_dev = bridge_dev;
484 	serverworks_private.gart_addr_ofs = 0x10;
485 
486 	pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
487 	if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
488 		pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
489 		if (temp2 != 0) {
490 			dev_info(&pdev->dev, "64 bit aperture address, "
491 				 "but top bits are not zero; disabling AGP\n");
492 			return -ENODEV;
493 		}
494 		serverworks_private.mm_addr_ofs = 0x18;
495 	} else
496 		serverworks_private.mm_addr_ofs = 0x14;
497 
498 	pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
499 	if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
500 		pci_read_config_dword(pdev,
501 				serverworks_private.mm_addr_ofs + 4, &temp2);
502 		if (temp2 != 0) {
503 			dev_info(&pdev->dev, "64 bit MMIO address, but top "
504 				 "bits are not zero; disabling AGP\n");
505 			return -ENODEV;
506 		}
507 	}
508 
509 	bridge = agp_alloc_bridge();
510 	if (!bridge)
511 		return -ENOMEM;
512 
513 	bridge->driver = &sworks_driver;
514 	bridge->dev_private_data = &serverworks_private,
515 	bridge->dev = pci_dev_get(pdev);
516 
517 	pci_set_drvdata(pdev, bridge);
518 	return agp_add_bridge(bridge);
519 }
520 
521 static void agp_serverworks_remove(struct pci_dev *pdev)
522 {
523 	struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
524 
525 	pci_dev_put(bridge->dev);
526 	agp_remove_bridge(bridge);
527 	agp_put_bridge(bridge);
528 	pci_dev_put(serverworks_private.svrwrks_dev);
529 	serverworks_private.svrwrks_dev = NULL;
530 }
531 
532 static struct pci_device_id agp_serverworks_pci_table[] = {
533 	{
534 	.class		= (PCI_CLASS_BRIDGE_HOST << 8),
535 	.class_mask	= ~0,
536 	.vendor		= PCI_VENDOR_ID_SERVERWORKS,
537 	.device		= PCI_ANY_ID,
538 	.subvendor	= PCI_ANY_ID,
539 	.subdevice	= PCI_ANY_ID,
540 	},
541 	{ }
542 };
543 
544 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
545 
546 static struct pci_driver agp_serverworks_pci_driver = {
547 	.name		= "agpgart-serverworks",
548 	.id_table	= agp_serverworks_pci_table,
549 	.probe		= agp_serverworks_probe,
550 	.remove		= agp_serverworks_remove,
551 };
552 
553 static int __init agp_serverworks_init(void)
554 {
555 	if (agp_off)
556 		return -EINVAL;
557 	return pci_register_driver(&agp_serverworks_pci_driver);
558 }
559 
560 static void __exit agp_serverworks_cleanup(void)
561 {
562 	pci_unregister_driver(&agp_serverworks_pci_driver);
563 }
564 
565 module_init(agp_serverworks_init);
566 module_exit(agp_serverworks_cleanup);
567 
568 MODULE_LICENSE("GPL and additional rights");
569 
570