1 /* 2 * Intel GTT (Graphics Translation Table) routines 3 * 4 * Caveat: This driver implements the linux agp interface, but this is far from 5 * a agp driver! GTT support ended up here for purely historical reasons: The 6 * old userspace intel graphics drivers needed an interface to map memory into 7 * the GTT. And the drm provides a default interface for graphic devices sitting 8 * on an agp port. So it made sense to fake the GTT support as an agp port to 9 * avoid having to create a new api. 10 * 11 * With gem this does not make much sense anymore, just needlessly complicates 12 * the code. But as long as the old graphics stack is still support, it's stuck 13 * here. 14 * 15 * /fairy-tale-mode off 16 */ 17 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/pagemap.h> 23 #include <linux/agp_backend.h> 24 #include <linux/delay.h> 25 #include <asm/smp.h> 26 #include "agp.h" 27 #include "intel-agp.h" 28 #include <drm/intel-gtt.h> 29 30 /* 31 * If we have Intel graphics, we're not going to have anything other than 32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). 34 * Only newer chipsets need to bother with this, of course. 35 */ 36 #ifdef CONFIG_INTEL_IOMMU 37 #define USE_PCI_DMA_API 1 38 #else 39 #define USE_PCI_DMA_API 0 40 #endif 41 42 struct intel_gtt_driver { 43 unsigned int gen : 8; 44 unsigned int is_g33 : 1; 45 unsigned int is_pineview : 1; 46 unsigned int is_ironlake : 1; 47 unsigned int has_pgtbl_enable : 1; 48 unsigned int dma_mask_size : 8; 49 /* Chipset specific GTT setup */ 50 int (*setup)(void); 51 /* This should undo anything done in ->setup() save the unmapping 52 * of the mmio register file, that's done in the generic code. */ 53 void (*cleanup)(void); 54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 55 /* Flags is a more or less chipset specific opaque value. 56 * For chipsets that need to support old ums (non-gem) code, this 57 * needs to be identical to the various supported agp memory types! */ 58 bool (*check_flags)(unsigned int flags); 59 void (*chipset_flush)(void); 60 }; 61 62 static struct _intel_private { 63 struct intel_gtt base; 64 const struct intel_gtt_driver *driver; 65 struct pci_dev *pcidev; /* device one */ 66 struct pci_dev *bridge_dev; 67 u8 __iomem *registers; 68 phys_addr_t gtt_bus_addr; 69 phys_addr_t gma_bus_addr; 70 u32 PGETBL_save; 71 u32 __iomem *gtt; /* I915G */ 72 bool clear_fake_agp; /* on first access via agp, fill with scratch */ 73 int num_dcache_entries; 74 void __iomem *i9xx_flush_page; 75 char *i81x_gtt_table; 76 struct resource ifp_resource; 77 int resource_valid; 78 struct page *scratch_page; 79 dma_addr_t scratch_page_dma; 80 } intel_private; 81 82 #define INTEL_GTT_GEN intel_private.driver->gen 83 #define IS_G33 intel_private.driver->is_g33 84 #define IS_PINEVIEW intel_private.driver->is_pineview 85 #define IS_IRONLAKE intel_private.driver->is_ironlake 86 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 87 88 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, 89 struct scatterlist **sg_list, int *num_sg) 90 { 91 struct sg_table st; 92 struct scatterlist *sg; 93 int i; 94 95 if (*sg_list) 96 return 0; /* already mapped (for e.g. resume */ 97 98 DBG("try mapping %lu pages\n", (unsigned long)num_entries); 99 100 if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) 101 goto err; 102 103 *sg_list = sg = st.sgl; 104 105 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) 106 sg_set_page(sg, pages[i], PAGE_SIZE, 0); 107 108 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, 109 num_entries, PCI_DMA_BIDIRECTIONAL); 110 if (unlikely(!*num_sg)) 111 goto err; 112 113 return 0; 114 115 err: 116 sg_free_table(&st); 117 return -ENOMEM; 118 } 119 EXPORT_SYMBOL(intel_gtt_map_memory); 120 121 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 122 { 123 struct sg_table st; 124 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 125 126 pci_unmap_sg(intel_private.pcidev, sg_list, 127 num_sg, PCI_DMA_BIDIRECTIONAL); 128 129 st.sgl = sg_list; 130 st.orig_nents = st.nents = num_sg; 131 132 sg_free_table(&st); 133 } 134 EXPORT_SYMBOL(intel_gtt_unmap_memory); 135 136 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 137 { 138 return; 139 } 140 141 /* Exists to support ARGB cursors */ 142 static struct page *i8xx_alloc_pages(void) 143 { 144 struct page *page; 145 146 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 147 if (page == NULL) 148 return NULL; 149 150 if (set_pages_uc(page, 4) < 0) { 151 set_pages_wb(page, 4); 152 __free_pages(page, 2); 153 return NULL; 154 } 155 get_page(page); 156 atomic_inc(&agp_bridge->current_memory_agp); 157 return page; 158 } 159 160 static void i8xx_destroy_pages(struct page *page) 161 { 162 if (page == NULL) 163 return; 164 165 set_pages_wb(page, 4); 166 put_page(page); 167 __free_pages(page, 2); 168 atomic_dec(&agp_bridge->current_memory_agp); 169 } 170 171 #define I810_GTT_ORDER 4 172 static int i810_setup(void) 173 { 174 u32 reg_addr; 175 char *gtt_table; 176 177 /* i81x does not preallocate the gtt. It's always 64kb in size. */ 178 gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 179 if (gtt_table == NULL) 180 return -ENOMEM; 181 intel_private.i81x_gtt_table = gtt_table; 182 183 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 184 reg_addr &= 0xfff80000; 185 186 intel_private.registers = ioremap(reg_addr, KB(64)); 187 if (!intel_private.registers) 188 return -ENOMEM; 189 190 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 191 intel_private.registers+I810_PGETBL_CTL); 192 193 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 194 195 if ((readl(intel_private.registers+I810_DRAM_CTL) 196 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 197 dev_info(&intel_private.pcidev->dev, 198 "detected 4MB dedicated video ram\n"); 199 intel_private.num_dcache_entries = 1024; 200 } 201 202 return 0; 203 } 204 205 static void i810_cleanup(void) 206 { 207 writel(0, intel_private.registers+I810_PGETBL_CTL); 208 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 209 } 210 211 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 212 int type) 213 { 214 int i; 215 216 if ((pg_start + mem->page_count) 217 > intel_private.num_dcache_entries) 218 return -EINVAL; 219 220 if (!mem->is_flushed) 221 global_cache_flush(); 222 223 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 224 dma_addr_t addr = i << PAGE_SHIFT; 225 intel_private.driver->write_entry(addr, 226 i, type); 227 } 228 readl(intel_private.gtt+i-1); 229 230 return 0; 231 } 232 233 /* 234 * The i810/i830 requires a physical address to program its mouse 235 * pointer into hardware. 236 * However the Xserver still writes to it through the agp aperture. 237 */ 238 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 239 { 240 struct agp_memory *new; 241 struct page *page; 242 243 switch (pg_count) { 244 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 245 break; 246 case 4: 247 /* kludge to get 4 physical pages for ARGB cursor */ 248 page = i8xx_alloc_pages(); 249 break; 250 default: 251 return NULL; 252 } 253 254 if (page == NULL) 255 return NULL; 256 257 new = agp_create_memory(pg_count); 258 if (new == NULL) 259 return NULL; 260 261 new->pages[0] = page; 262 if (pg_count == 4) { 263 /* kludge to get 4 physical pages for ARGB cursor */ 264 new->pages[1] = new->pages[0] + 1; 265 new->pages[2] = new->pages[1] + 1; 266 new->pages[3] = new->pages[2] + 1; 267 } 268 new->page_count = pg_count; 269 new->num_scratch_pages = pg_count; 270 new->type = AGP_PHYS_MEMORY; 271 new->physical = page_to_phys(new->pages[0]); 272 return new; 273 } 274 275 static void intel_i810_free_by_type(struct agp_memory *curr) 276 { 277 agp_free_key(curr->key); 278 if (curr->type == AGP_PHYS_MEMORY) { 279 if (curr->page_count == 4) 280 i8xx_destroy_pages(curr->pages[0]); 281 else { 282 agp_bridge->driver->agp_destroy_page(curr->pages[0], 283 AGP_PAGE_DESTROY_UNMAP); 284 agp_bridge->driver->agp_destroy_page(curr->pages[0], 285 AGP_PAGE_DESTROY_FREE); 286 } 287 agp_free_page_array(curr); 288 } 289 kfree(curr); 290 } 291 292 static int intel_gtt_setup_scratch_page(void) 293 { 294 struct page *page; 295 dma_addr_t dma_addr; 296 297 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 298 if (page == NULL) 299 return -ENOMEM; 300 get_page(page); 301 set_pages_uc(page, 1); 302 303 if (intel_private.base.needs_dmar) { 304 dma_addr = pci_map_page(intel_private.pcidev, page, 0, 305 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 306 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 307 return -EINVAL; 308 309 intel_private.scratch_page_dma = dma_addr; 310 } else 311 intel_private.scratch_page_dma = page_to_phys(page); 312 313 intel_private.scratch_page = page; 314 315 return 0; 316 } 317 318 static void i810_write_entry(dma_addr_t addr, unsigned int entry, 319 unsigned int flags) 320 { 321 u32 pte_flags = I810_PTE_VALID; 322 323 switch (flags) { 324 case AGP_DCACHE_MEMORY: 325 pte_flags |= I810_PTE_LOCAL; 326 break; 327 case AGP_USER_CACHED_MEMORY: 328 pte_flags |= I830_PTE_SYSTEM_CACHED; 329 break; 330 } 331 332 writel(addr | pte_flags, intel_private.gtt + entry); 333 } 334 335 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 336 {32, 8192, 3}, 337 {64, 16384, 4}, 338 {128, 32768, 5}, 339 {256, 65536, 6}, 340 {512, 131072, 7}, 341 }; 342 343 static unsigned int intel_gtt_stolen_size(void) 344 { 345 u16 gmch_ctrl; 346 u8 rdct; 347 int local = 0; 348 static const int ddt[4] = { 0, 16, 32, 64 }; 349 unsigned int stolen_size = 0; 350 351 if (INTEL_GTT_GEN == 1) 352 return 0; /* no stolen mem on i81x */ 353 354 pci_read_config_word(intel_private.bridge_dev, 355 I830_GMCH_CTRL, &gmch_ctrl); 356 357 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 358 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 359 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 360 case I830_GMCH_GMS_STOLEN_512: 361 stolen_size = KB(512); 362 break; 363 case I830_GMCH_GMS_STOLEN_1024: 364 stolen_size = MB(1); 365 break; 366 case I830_GMCH_GMS_STOLEN_8192: 367 stolen_size = MB(8); 368 break; 369 case I830_GMCH_GMS_LOCAL: 370 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 371 stolen_size = (I830_RDRAM_ND(rdct) + 1) * 372 MB(ddt[I830_RDRAM_DDT(rdct)]); 373 local = 1; 374 break; 375 default: 376 stolen_size = 0; 377 break; 378 } 379 } else if (INTEL_GTT_GEN == 6) { 380 /* 381 * SandyBridge has new memory control reg at 0x50.w 382 */ 383 u16 snb_gmch_ctl; 384 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 385 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 386 case SNB_GMCH_GMS_STOLEN_32M: 387 stolen_size = MB(32); 388 break; 389 case SNB_GMCH_GMS_STOLEN_64M: 390 stolen_size = MB(64); 391 break; 392 case SNB_GMCH_GMS_STOLEN_96M: 393 stolen_size = MB(96); 394 break; 395 case SNB_GMCH_GMS_STOLEN_128M: 396 stolen_size = MB(128); 397 break; 398 case SNB_GMCH_GMS_STOLEN_160M: 399 stolen_size = MB(160); 400 break; 401 case SNB_GMCH_GMS_STOLEN_192M: 402 stolen_size = MB(192); 403 break; 404 case SNB_GMCH_GMS_STOLEN_224M: 405 stolen_size = MB(224); 406 break; 407 case SNB_GMCH_GMS_STOLEN_256M: 408 stolen_size = MB(256); 409 break; 410 case SNB_GMCH_GMS_STOLEN_288M: 411 stolen_size = MB(288); 412 break; 413 case SNB_GMCH_GMS_STOLEN_320M: 414 stolen_size = MB(320); 415 break; 416 case SNB_GMCH_GMS_STOLEN_352M: 417 stolen_size = MB(352); 418 break; 419 case SNB_GMCH_GMS_STOLEN_384M: 420 stolen_size = MB(384); 421 break; 422 case SNB_GMCH_GMS_STOLEN_416M: 423 stolen_size = MB(416); 424 break; 425 case SNB_GMCH_GMS_STOLEN_448M: 426 stolen_size = MB(448); 427 break; 428 case SNB_GMCH_GMS_STOLEN_480M: 429 stolen_size = MB(480); 430 break; 431 case SNB_GMCH_GMS_STOLEN_512M: 432 stolen_size = MB(512); 433 break; 434 } 435 } else { 436 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 437 case I855_GMCH_GMS_STOLEN_1M: 438 stolen_size = MB(1); 439 break; 440 case I855_GMCH_GMS_STOLEN_4M: 441 stolen_size = MB(4); 442 break; 443 case I855_GMCH_GMS_STOLEN_8M: 444 stolen_size = MB(8); 445 break; 446 case I855_GMCH_GMS_STOLEN_16M: 447 stolen_size = MB(16); 448 break; 449 case I855_GMCH_GMS_STOLEN_32M: 450 stolen_size = MB(32); 451 break; 452 case I915_GMCH_GMS_STOLEN_48M: 453 stolen_size = MB(48); 454 break; 455 case I915_GMCH_GMS_STOLEN_64M: 456 stolen_size = MB(64); 457 break; 458 case G33_GMCH_GMS_STOLEN_128M: 459 stolen_size = MB(128); 460 break; 461 case G33_GMCH_GMS_STOLEN_256M: 462 stolen_size = MB(256); 463 break; 464 case INTEL_GMCH_GMS_STOLEN_96M: 465 stolen_size = MB(96); 466 break; 467 case INTEL_GMCH_GMS_STOLEN_160M: 468 stolen_size = MB(160); 469 break; 470 case INTEL_GMCH_GMS_STOLEN_224M: 471 stolen_size = MB(224); 472 break; 473 case INTEL_GMCH_GMS_STOLEN_352M: 474 stolen_size = MB(352); 475 break; 476 default: 477 stolen_size = 0; 478 break; 479 } 480 } 481 482 if (stolen_size > 0) { 483 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 484 stolen_size / KB(1), local ? "local" : "stolen"); 485 } else { 486 dev_info(&intel_private.bridge_dev->dev, 487 "no pre-allocated video memory detected\n"); 488 stolen_size = 0; 489 } 490 491 return stolen_size; 492 } 493 494 static void i965_adjust_pgetbl_size(unsigned int size_flag) 495 { 496 u32 pgetbl_ctl, pgetbl_ctl2; 497 498 /* ensure that ppgtt is disabled */ 499 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 500 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 501 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 502 503 /* write the new ggtt size */ 504 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 505 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 506 pgetbl_ctl |= size_flag; 507 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 508 } 509 510 static unsigned int i965_gtt_total_entries(void) 511 { 512 int size; 513 u32 pgetbl_ctl; 514 u16 gmch_ctl; 515 516 pci_read_config_word(intel_private.bridge_dev, 517 I830_GMCH_CTRL, &gmch_ctl); 518 519 if (INTEL_GTT_GEN == 5) { 520 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 521 case G4x_GMCH_SIZE_1M: 522 case G4x_GMCH_SIZE_VT_1M: 523 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 524 break; 525 case G4x_GMCH_SIZE_VT_1_5M: 526 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 527 break; 528 case G4x_GMCH_SIZE_2M: 529 case G4x_GMCH_SIZE_VT_2M: 530 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 531 break; 532 } 533 } 534 535 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 536 537 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 538 case I965_PGETBL_SIZE_128KB: 539 size = KB(128); 540 break; 541 case I965_PGETBL_SIZE_256KB: 542 size = KB(256); 543 break; 544 case I965_PGETBL_SIZE_512KB: 545 size = KB(512); 546 break; 547 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 548 case I965_PGETBL_SIZE_1MB: 549 size = KB(1024); 550 break; 551 case I965_PGETBL_SIZE_2MB: 552 size = KB(2048); 553 break; 554 case I965_PGETBL_SIZE_1_5MB: 555 size = KB(1024 + 512); 556 break; 557 default: 558 dev_info(&intel_private.pcidev->dev, 559 "unknown page table size, assuming 512KB\n"); 560 size = KB(512); 561 } 562 563 return size/4; 564 } 565 566 static unsigned int intel_gtt_total_entries(void) 567 { 568 int size; 569 570 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 571 return i965_gtt_total_entries(); 572 else if (INTEL_GTT_GEN == 6) { 573 u16 snb_gmch_ctl; 574 575 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 576 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 577 default: 578 case SNB_GTT_SIZE_0M: 579 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 580 size = MB(0); 581 break; 582 case SNB_GTT_SIZE_1M: 583 size = MB(1); 584 break; 585 case SNB_GTT_SIZE_2M: 586 size = MB(2); 587 break; 588 } 589 return size/4; 590 } else { 591 /* On previous hardware, the GTT size was just what was 592 * required to map the aperture. 593 */ 594 return intel_private.base.gtt_mappable_entries; 595 } 596 } 597 598 static unsigned int intel_gtt_mappable_entries(void) 599 { 600 unsigned int aperture_size; 601 602 if (INTEL_GTT_GEN == 1) { 603 u32 smram_miscc; 604 605 pci_read_config_dword(intel_private.bridge_dev, 606 I810_SMRAM_MISCC, &smram_miscc); 607 608 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 609 == I810_GFX_MEM_WIN_32M) 610 aperture_size = MB(32); 611 else 612 aperture_size = MB(64); 613 } else if (INTEL_GTT_GEN == 2) { 614 u16 gmch_ctrl; 615 616 pci_read_config_word(intel_private.bridge_dev, 617 I830_GMCH_CTRL, &gmch_ctrl); 618 619 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 620 aperture_size = MB(64); 621 else 622 aperture_size = MB(128); 623 } else { 624 /* 9xx supports large sizes, just look at the length */ 625 aperture_size = pci_resource_len(intel_private.pcidev, 2); 626 } 627 628 return aperture_size >> PAGE_SHIFT; 629 } 630 631 static void intel_gtt_teardown_scratch_page(void) 632 { 633 set_pages_wb(intel_private.scratch_page, 1); 634 pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, 635 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 636 put_page(intel_private.scratch_page); 637 __free_page(intel_private.scratch_page); 638 } 639 640 static void intel_gtt_cleanup(void) 641 { 642 intel_private.driver->cleanup(); 643 644 iounmap(intel_private.gtt); 645 iounmap(intel_private.registers); 646 647 intel_gtt_teardown_scratch_page(); 648 } 649 650 static int intel_gtt_init(void) 651 { 652 u32 gtt_map_size; 653 int ret; 654 655 ret = intel_private.driver->setup(); 656 if (ret != 0) 657 return ret; 658 659 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 660 intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 661 662 /* save the PGETBL reg for resume */ 663 intel_private.PGETBL_save = 664 readl(intel_private.registers+I810_PGETBL_CTL) 665 & ~I810_PGETBL_ENABLED; 666 /* we only ever restore the register when enabling the PGTBL... */ 667 if (HAS_PGTBL_EN) 668 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 669 670 dev_info(&intel_private.bridge_dev->dev, 671 "detected gtt size: %dK total, %dK mappable\n", 672 intel_private.base.gtt_total_entries * 4, 673 intel_private.base.gtt_mappable_entries * 4); 674 675 gtt_map_size = intel_private.base.gtt_total_entries * 4; 676 677 intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 678 gtt_map_size); 679 if (!intel_private.gtt) { 680 intel_private.driver->cleanup(); 681 iounmap(intel_private.registers); 682 return -ENOMEM; 683 } 684 685 global_cache_flush(); /* FIXME: ? */ 686 687 intel_private.base.stolen_size = intel_gtt_stolen_size(); 688 689 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 690 691 ret = intel_gtt_setup_scratch_page(); 692 if (ret != 0) { 693 intel_gtt_cleanup(); 694 return ret; 695 } 696 697 return 0; 698 } 699 700 static int intel_fake_agp_fetch_size(void) 701 { 702 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 703 unsigned int aper_size; 704 int i; 705 706 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 707 / MB(1); 708 709 for (i = 0; i < num_sizes; i++) { 710 if (aper_size == intel_fake_agp_sizes[i].size) { 711 agp_bridge->current_size = 712 (void *) (intel_fake_agp_sizes + i); 713 return aper_size; 714 } 715 } 716 717 return 0; 718 } 719 720 static void i830_cleanup(void) 721 { 722 } 723 724 /* The chipset_flush interface needs to get data that has already been 725 * flushed out of the CPU all the way out to main memory, because the GPU 726 * doesn't snoop those buffers. 727 * 728 * The 8xx series doesn't have the same lovely interface for flushing the 729 * chipset write buffers that the later chips do. According to the 865 730 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 731 * that buffer out, we just fill 1KB and clflush it out, on the assumption 732 * that it'll push whatever was in there out. It appears to work. 733 */ 734 static void i830_chipset_flush(void) 735 { 736 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 737 738 /* Forcibly evict everything from the CPU write buffers. 739 * clflush appears to be insufficient. 740 */ 741 wbinvd_on_all_cpus(); 742 743 /* Now we've only seen documents for this magic bit on 855GM, 744 * we hope it exists for the other gen2 chipsets... 745 * 746 * Also works as advertised on my 845G. 747 */ 748 writel(readl(intel_private.registers+I830_HIC) | (1<<31), 749 intel_private.registers+I830_HIC); 750 751 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 752 if (time_after(jiffies, timeout)) 753 break; 754 755 udelay(50); 756 } 757 } 758 759 static void i830_write_entry(dma_addr_t addr, unsigned int entry, 760 unsigned int flags) 761 { 762 u32 pte_flags = I810_PTE_VALID; 763 764 if (flags == AGP_USER_CACHED_MEMORY) 765 pte_flags |= I830_PTE_SYSTEM_CACHED; 766 767 writel(addr | pte_flags, intel_private.gtt + entry); 768 } 769 770 static bool intel_enable_gtt(void) 771 { 772 u32 gma_addr; 773 u8 __iomem *reg; 774 775 if (INTEL_GTT_GEN <= 2) 776 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 777 &gma_addr); 778 else 779 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 780 &gma_addr); 781 782 intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 783 784 if (INTEL_GTT_GEN >= 6) 785 return true; 786 787 if (INTEL_GTT_GEN == 2) { 788 u16 gmch_ctrl; 789 790 pci_read_config_word(intel_private.bridge_dev, 791 I830_GMCH_CTRL, &gmch_ctrl); 792 gmch_ctrl |= I830_GMCH_ENABLED; 793 pci_write_config_word(intel_private.bridge_dev, 794 I830_GMCH_CTRL, gmch_ctrl); 795 796 pci_read_config_word(intel_private.bridge_dev, 797 I830_GMCH_CTRL, &gmch_ctrl); 798 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 799 dev_err(&intel_private.pcidev->dev, 800 "failed to enable the GTT: GMCH_CTRL=%x\n", 801 gmch_ctrl); 802 return false; 803 } 804 } 805 806 /* On the resume path we may be adjusting the PGTBL value, so 807 * be paranoid and flush all chipset write buffers... 808 */ 809 if (INTEL_GTT_GEN >= 3) 810 writel(0, intel_private.registers+GFX_FLSH_CNTL); 811 812 reg = intel_private.registers+I810_PGETBL_CTL; 813 writel(intel_private.PGETBL_save, reg); 814 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 815 dev_err(&intel_private.pcidev->dev, 816 "failed to enable the GTT: PGETBL=%x [expected %x]\n", 817 readl(reg), intel_private.PGETBL_save); 818 return false; 819 } 820 821 if (INTEL_GTT_GEN >= 3) 822 writel(0, intel_private.registers+GFX_FLSH_CNTL); 823 824 return true; 825 } 826 827 static int i830_setup(void) 828 { 829 u32 reg_addr; 830 831 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 832 reg_addr &= 0xfff80000; 833 834 intel_private.registers = ioremap(reg_addr, KB(64)); 835 if (!intel_private.registers) 836 return -ENOMEM; 837 838 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 839 840 return 0; 841 } 842 843 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 844 { 845 agp_bridge->gatt_table_real = NULL; 846 agp_bridge->gatt_table = NULL; 847 agp_bridge->gatt_bus_addr = 0; 848 849 return 0; 850 } 851 852 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 853 { 854 return 0; 855 } 856 857 static int intel_fake_agp_configure(void) 858 { 859 if (!intel_enable_gtt()) 860 return -EIO; 861 862 intel_private.clear_fake_agp = true; 863 agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; 864 865 return 0; 866 } 867 868 static bool i830_check_flags(unsigned int flags) 869 { 870 switch (flags) { 871 case 0: 872 case AGP_PHYS_MEMORY: 873 case AGP_USER_CACHED_MEMORY: 874 case AGP_USER_MEMORY: 875 return true; 876 } 877 878 return false; 879 } 880 881 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, 882 unsigned int sg_len, 883 unsigned int pg_start, 884 unsigned int flags) 885 { 886 struct scatterlist *sg; 887 unsigned int len, m; 888 int i, j; 889 890 j = pg_start; 891 892 /* sg may merge pages, but we have to separate 893 * per-page addr for GTT */ 894 for_each_sg(sg_list, sg, sg_len, i) { 895 len = sg_dma_len(sg) >> PAGE_SHIFT; 896 for (m = 0; m < len; m++) { 897 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 898 intel_private.driver->write_entry(addr, 899 j, flags); 900 j++; 901 } 902 } 903 readl(intel_private.gtt+j-1); 904 } 905 EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 906 907 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, 908 struct page **pages, unsigned int flags) 909 { 910 int i, j; 911 912 for (i = 0, j = first_entry; i < num_entries; i++, j++) { 913 dma_addr_t addr = page_to_phys(pages[i]); 914 intel_private.driver->write_entry(addr, 915 j, flags); 916 } 917 readl(intel_private.gtt+j-1); 918 } 919 EXPORT_SYMBOL(intel_gtt_insert_pages); 920 921 static int intel_fake_agp_insert_entries(struct agp_memory *mem, 922 off_t pg_start, int type) 923 { 924 int ret = -EINVAL; 925 926 if (intel_private.base.do_idle_maps) 927 return -ENODEV; 928 929 if (intel_private.clear_fake_agp) { 930 int start = intel_private.base.stolen_size / PAGE_SIZE; 931 int end = intel_private.base.gtt_mappable_entries; 932 intel_gtt_clear_range(start, end - start); 933 intel_private.clear_fake_agp = false; 934 } 935 936 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 937 return i810_insert_dcache_entries(mem, pg_start, type); 938 939 if (mem->page_count == 0) 940 goto out; 941 942 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) 943 goto out_err; 944 945 if (type != mem->type) 946 goto out_err; 947 948 if (!intel_private.driver->check_flags(type)) 949 goto out_err; 950 951 if (!mem->is_flushed) 952 global_cache_flush(); 953 954 if (intel_private.base.needs_dmar) { 955 ret = intel_gtt_map_memory(mem->pages, mem->page_count, 956 &mem->sg_list, &mem->num_sg); 957 if (ret != 0) 958 return ret; 959 960 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, 961 pg_start, type); 962 } else 963 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 964 type); 965 966 out: 967 ret = 0; 968 out_err: 969 mem->is_flushed = true; 970 return ret; 971 } 972 973 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 974 { 975 unsigned int i; 976 977 for (i = first_entry; i < (first_entry + num_entries); i++) { 978 intel_private.driver->write_entry(intel_private.scratch_page_dma, 979 i, 0); 980 } 981 readl(intel_private.gtt+i-1); 982 } 983 EXPORT_SYMBOL(intel_gtt_clear_range); 984 985 static int intel_fake_agp_remove_entries(struct agp_memory *mem, 986 off_t pg_start, int type) 987 { 988 if (mem->page_count == 0) 989 return 0; 990 991 if (intel_private.base.do_idle_maps) 992 return -ENODEV; 993 994 intel_gtt_clear_range(pg_start, mem->page_count); 995 996 if (intel_private.base.needs_dmar) { 997 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 998 mem->sg_list = NULL; 999 mem->num_sg = 0; 1000 } 1001 1002 return 0; 1003 } 1004 1005 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1006 int type) 1007 { 1008 struct agp_memory *new; 1009 1010 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 1011 if (pg_count != intel_private.num_dcache_entries) 1012 return NULL; 1013 1014 new = agp_create_memory(1); 1015 if (new == NULL) 1016 return NULL; 1017 1018 new->type = AGP_DCACHE_MEMORY; 1019 new->page_count = pg_count; 1020 new->num_scratch_pages = 0; 1021 agp_free_page_array(new); 1022 return new; 1023 } 1024 if (type == AGP_PHYS_MEMORY) 1025 return alloc_agpphysmem_i8xx(pg_count, type); 1026 /* always return NULL for other allocation types for now */ 1027 return NULL; 1028 } 1029 1030 static int intel_alloc_chipset_flush_resource(void) 1031 { 1032 int ret; 1033 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1034 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1035 pcibios_align_resource, intel_private.bridge_dev); 1036 1037 return ret; 1038 } 1039 1040 static void intel_i915_setup_chipset_flush(void) 1041 { 1042 int ret; 1043 u32 temp; 1044 1045 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1046 if (!(temp & 0x1)) { 1047 intel_alloc_chipset_flush_resource(); 1048 intel_private.resource_valid = 1; 1049 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1050 } else { 1051 temp &= ~1; 1052 1053 intel_private.resource_valid = 1; 1054 intel_private.ifp_resource.start = temp; 1055 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1056 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1057 /* some BIOSes reserve this area in a pnp some don't */ 1058 if (ret) 1059 intel_private.resource_valid = 0; 1060 } 1061 } 1062 1063 static void intel_i965_g33_setup_chipset_flush(void) 1064 { 1065 u32 temp_hi, temp_lo; 1066 int ret; 1067 1068 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1069 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1070 1071 if (!(temp_lo & 0x1)) { 1072 1073 intel_alloc_chipset_flush_resource(); 1074 1075 intel_private.resource_valid = 1; 1076 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1077 upper_32_bits(intel_private.ifp_resource.start)); 1078 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1079 } else { 1080 u64 l64; 1081 1082 temp_lo &= ~0x1; 1083 l64 = ((u64)temp_hi << 32) | temp_lo; 1084 1085 intel_private.resource_valid = 1; 1086 intel_private.ifp_resource.start = l64; 1087 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1088 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1089 /* some BIOSes reserve this area in a pnp some don't */ 1090 if (ret) 1091 intel_private.resource_valid = 0; 1092 } 1093 } 1094 1095 static void intel_i9xx_setup_flush(void) 1096 { 1097 /* return if already configured */ 1098 if (intel_private.ifp_resource.start) 1099 return; 1100 1101 if (INTEL_GTT_GEN == 6) 1102 return; 1103 1104 /* setup a resource for this object */ 1105 intel_private.ifp_resource.name = "Intel Flush Page"; 1106 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1107 1108 /* Setup chipset flush for 915 */ 1109 if (IS_G33 || INTEL_GTT_GEN >= 4) { 1110 intel_i965_g33_setup_chipset_flush(); 1111 } else { 1112 intel_i915_setup_chipset_flush(); 1113 } 1114 1115 if (intel_private.ifp_resource.start) 1116 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1117 if (!intel_private.i9xx_flush_page) 1118 dev_err(&intel_private.pcidev->dev, 1119 "can't ioremap flush page - no chipset flushing\n"); 1120 } 1121 1122 static void i9xx_cleanup(void) 1123 { 1124 if (intel_private.i9xx_flush_page) 1125 iounmap(intel_private.i9xx_flush_page); 1126 if (intel_private.resource_valid) 1127 release_resource(&intel_private.ifp_resource); 1128 intel_private.ifp_resource.start = 0; 1129 intel_private.resource_valid = 0; 1130 } 1131 1132 static void i9xx_chipset_flush(void) 1133 { 1134 if (intel_private.i9xx_flush_page) 1135 writel(1, intel_private.i9xx_flush_page); 1136 } 1137 1138 static void i965_write_entry(dma_addr_t addr, 1139 unsigned int entry, 1140 unsigned int flags) 1141 { 1142 u32 pte_flags; 1143 1144 pte_flags = I810_PTE_VALID; 1145 if (flags == AGP_USER_CACHED_MEMORY) 1146 pte_flags |= I830_PTE_SYSTEM_CACHED; 1147 1148 /* Shift high bits down */ 1149 addr |= (addr >> 28) & 0xf0; 1150 writel(addr | pte_flags, intel_private.gtt + entry); 1151 } 1152 1153 static bool gen6_check_flags(unsigned int flags) 1154 { 1155 return true; 1156 } 1157 1158 static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 1159 unsigned int flags) 1160 { 1161 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; 1162 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; 1163 u32 pte_flags; 1164 1165 if (type_mask == AGP_USER_MEMORY) 1166 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; 1167 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { 1168 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; 1169 if (gfdt) 1170 pte_flags |= GEN6_PTE_GFDT; 1171 } else { /* set 'normal'/'cached' to LLC by default */ 1172 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; 1173 if (gfdt) 1174 pte_flags |= GEN6_PTE_GFDT; 1175 } 1176 1177 /* gen6 has bit11-4 for physical addr bit39-32 */ 1178 addr |= (addr >> 28) & 0xff0; 1179 writel(addr | pte_flags, intel_private.gtt + entry); 1180 } 1181 1182 static void gen6_cleanup(void) 1183 { 1184 } 1185 1186 /* Certain Gen5 chipsets require require idling the GPU before 1187 * unmapping anything from the GTT when VT-d is enabled. 1188 */ 1189 static inline int needs_idle_maps(void) 1190 { 1191 #ifdef CONFIG_INTEL_IOMMU 1192 const unsigned short gpu_devid = intel_private.pcidev->device; 1193 extern int intel_iommu_gfx_mapped; 1194 1195 /* Query intel_iommu to see if we need the workaround. Presumably that 1196 * was loaded first. 1197 */ 1198 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || 1199 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && 1200 intel_iommu_gfx_mapped) 1201 return 1; 1202 #endif 1203 return 0; 1204 } 1205 1206 static int i9xx_setup(void) 1207 { 1208 u32 reg_addr; 1209 1210 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 1211 1212 reg_addr &= 0xfff80000; 1213 1214 intel_private.registers = ioremap(reg_addr, 128 * 4096); 1215 if (!intel_private.registers) 1216 return -ENOMEM; 1217 1218 if (INTEL_GTT_GEN == 3) { 1219 u32 gtt_addr; 1220 1221 pci_read_config_dword(intel_private.pcidev, 1222 I915_PTEADDR, >t_addr); 1223 intel_private.gtt_bus_addr = gtt_addr; 1224 } else { 1225 u32 gtt_offset; 1226 1227 switch (INTEL_GTT_GEN) { 1228 case 5: 1229 case 6: 1230 gtt_offset = MB(2); 1231 break; 1232 case 4: 1233 default: 1234 gtt_offset = KB(512); 1235 break; 1236 } 1237 intel_private.gtt_bus_addr = reg_addr + gtt_offset; 1238 } 1239 1240 if (needs_idle_maps()) 1241 intel_private.base.do_idle_maps = 1; 1242 1243 intel_i9xx_setup_flush(); 1244 1245 return 0; 1246 } 1247 1248 static const struct agp_bridge_driver intel_fake_agp_driver = { 1249 .owner = THIS_MODULE, 1250 .size_type = FIXED_APER_SIZE, 1251 .aperture_sizes = intel_fake_agp_sizes, 1252 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1253 .configure = intel_fake_agp_configure, 1254 .fetch_size = intel_fake_agp_fetch_size, 1255 .cleanup = intel_gtt_cleanup, 1256 .agp_enable = intel_fake_agp_enable, 1257 .cache_flush = global_cache_flush, 1258 .create_gatt_table = intel_fake_agp_create_gatt_table, 1259 .free_gatt_table = intel_fake_agp_free_gatt_table, 1260 .insert_memory = intel_fake_agp_insert_entries, 1261 .remove_memory = intel_fake_agp_remove_entries, 1262 .alloc_by_type = intel_fake_agp_alloc_by_type, 1263 .free_by_type = intel_i810_free_by_type, 1264 .agp_alloc_page = agp_generic_alloc_page, 1265 .agp_alloc_pages = agp_generic_alloc_pages, 1266 .agp_destroy_page = agp_generic_destroy_page, 1267 .agp_destroy_pages = agp_generic_destroy_pages, 1268 }; 1269 1270 static const struct intel_gtt_driver i81x_gtt_driver = { 1271 .gen = 1, 1272 .has_pgtbl_enable = 1, 1273 .dma_mask_size = 32, 1274 .setup = i810_setup, 1275 .cleanup = i810_cleanup, 1276 .check_flags = i830_check_flags, 1277 .write_entry = i810_write_entry, 1278 }; 1279 static const struct intel_gtt_driver i8xx_gtt_driver = { 1280 .gen = 2, 1281 .has_pgtbl_enable = 1, 1282 .setup = i830_setup, 1283 .cleanup = i830_cleanup, 1284 .write_entry = i830_write_entry, 1285 .dma_mask_size = 32, 1286 .check_flags = i830_check_flags, 1287 .chipset_flush = i830_chipset_flush, 1288 }; 1289 static const struct intel_gtt_driver i915_gtt_driver = { 1290 .gen = 3, 1291 .has_pgtbl_enable = 1, 1292 .setup = i9xx_setup, 1293 .cleanup = i9xx_cleanup, 1294 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1295 .write_entry = i830_write_entry, 1296 .dma_mask_size = 32, 1297 .check_flags = i830_check_flags, 1298 .chipset_flush = i9xx_chipset_flush, 1299 }; 1300 static const struct intel_gtt_driver g33_gtt_driver = { 1301 .gen = 3, 1302 .is_g33 = 1, 1303 .setup = i9xx_setup, 1304 .cleanup = i9xx_cleanup, 1305 .write_entry = i965_write_entry, 1306 .dma_mask_size = 36, 1307 .check_flags = i830_check_flags, 1308 .chipset_flush = i9xx_chipset_flush, 1309 }; 1310 static const struct intel_gtt_driver pineview_gtt_driver = { 1311 .gen = 3, 1312 .is_pineview = 1, .is_g33 = 1, 1313 .setup = i9xx_setup, 1314 .cleanup = i9xx_cleanup, 1315 .write_entry = i965_write_entry, 1316 .dma_mask_size = 36, 1317 .check_flags = i830_check_flags, 1318 .chipset_flush = i9xx_chipset_flush, 1319 }; 1320 static const struct intel_gtt_driver i965_gtt_driver = { 1321 .gen = 4, 1322 .has_pgtbl_enable = 1, 1323 .setup = i9xx_setup, 1324 .cleanup = i9xx_cleanup, 1325 .write_entry = i965_write_entry, 1326 .dma_mask_size = 36, 1327 .check_flags = i830_check_flags, 1328 .chipset_flush = i9xx_chipset_flush, 1329 }; 1330 static const struct intel_gtt_driver g4x_gtt_driver = { 1331 .gen = 5, 1332 .setup = i9xx_setup, 1333 .cleanup = i9xx_cleanup, 1334 .write_entry = i965_write_entry, 1335 .dma_mask_size = 36, 1336 .check_flags = i830_check_flags, 1337 .chipset_flush = i9xx_chipset_flush, 1338 }; 1339 static const struct intel_gtt_driver ironlake_gtt_driver = { 1340 .gen = 5, 1341 .is_ironlake = 1, 1342 .setup = i9xx_setup, 1343 .cleanup = i9xx_cleanup, 1344 .write_entry = i965_write_entry, 1345 .dma_mask_size = 36, 1346 .check_flags = i830_check_flags, 1347 .chipset_flush = i9xx_chipset_flush, 1348 }; 1349 static const struct intel_gtt_driver sandybridge_gtt_driver = { 1350 .gen = 6, 1351 .setup = i9xx_setup, 1352 .cleanup = gen6_cleanup, 1353 .write_entry = gen6_write_entry, 1354 .dma_mask_size = 40, 1355 .check_flags = gen6_check_flags, 1356 .chipset_flush = i9xx_chipset_flush, 1357 }; 1358 1359 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1360 * driver and gmch_driver must be non-null, and find_gmch will determine 1361 * which one should be used if a gmch_chip_id is present. 1362 */ 1363 static const struct intel_gtt_driver_description { 1364 unsigned int gmch_chip_id; 1365 char *name; 1366 const struct intel_gtt_driver *gtt_driver; 1367 } intel_gtt_chipsets[] = { 1368 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1369 &i81x_gtt_driver}, 1370 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1371 &i81x_gtt_driver}, 1372 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1373 &i81x_gtt_driver}, 1374 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1375 &i81x_gtt_driver}, 1376 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1377 &i8xx_gtt_driver}, 1378 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1379 &i8xx_gtt_driver}, 1380 { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1381 &i8xx_gtt_driver}, 1382 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1383 &i8xx_gtt_driver}, 1384 { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1385 &i8xx_gtt_driver}, 1386 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1387 &i915_gtt_driver }, 1388 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1389 &i915_gtt_driver }, 1390 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1391 &i915_gtt_driver }, 1392 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1393 &i915_gtt_driver }, 1394 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1395 &i915_gtt_driver }, 1396 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1397 &i915_gtt_driver }, 1398 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1399 &i965_gtt_driver }, 1400 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1401 &i965_gtt_driver }, 1402 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1403 &i965_gtt_driver }, 1404 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1405 &i965_gtt_driver }, 1406 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1407 &i965_gtt_driver }, 1408 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1409 &i965_gtt_driver }, 1410 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1411 &g33_gtt_driver }, 1412 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1413 &g33_gtt_driver }, 1414 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1415 &g33_gtt_driver }, 1416 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1417 &pineview_gtt_driver }, 1418 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1419 &pineview_gtt_driver }, 1420 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1421 &g4x_gtt_driver }, 1422 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1423 &g4x_gtt_driver }, 1424 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1425 &g4x_gtt_driver }, 1426 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1427 &g4x_gtt_driver }, 1428 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1429 &g4x_gtt_driver }, 1430 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1431 &g4x_gtt_driver }, 1432 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1433 &g4x_gtt_driver }, 1434 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1435 "HD Graphics", &ironlake_gtt_driver }, 1436 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1437 "HD Graphics", &ironlake_gtt_driver }, 1438 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 1439 "Sandybridge", &sandybridge_gtt_driver }, 1440 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 1441 "Sandybridge", &sandybridge_gtt_driver }, 1442 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 1443 "Sandybridge", &sandybridge_gtt_driver }, 1444 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 1445 "Sandybridge", &sandybridge_gtt_driver }, 1446 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 1447 "Sandybridge", &sandybridge_gtt_driver }, 1448 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 1449 "Sandybridge", &sandybridge_gtt_driver }, 1450 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 1451 "Sandybridge", &sandybridge_gtt_driver }, 1452 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, 1453 "Ivybridge", &sandybridge_gtt_driver }, 1454 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, 1455 "Ivybridge", &sandybridge_gtt_driver }, 1456 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, 1457 "Ivybridge", &sandybridge_gtt_driver }, 1458 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, 1459 "Ivybridge", &sandybridge_gtt_driver }, 1460 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, 1461 "Ivybridge", &sandybridge_gtt_driver }, 1462 { 0, NULL, NULL } 1463 }; 1464 1465 static int find_gmch(u16 device) 1466 { 1467 struct pci_dev *gmch_device; 1468 1469 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1470 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1471 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1472 device, gmch_device); 1473 } 1474 1475 if (!gmch_device) 1476 return 0; 1477 1478 intel_private.pcidev = gmch_device; 1479 return 1; 1480 } 1481 1482 int intel_gmch_probe(struct pci_dev *pdev, 1483 struct agp_bridge_data *bridge) 1484 { 1485 int i, mask; 1486 intel_private.driver = NULL; 1487 1488 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 1489 if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 1490 intel_private.driver = 1491 intel_gtt_chipsets[i].gtt_driver; 1492 break; 1493 } 1494 } 1495 1496 if (!intel_private.driver) 1497 return 0; 1498 1499 bridge->driver = &intel_fake_agp_driver; 1500 bridge->dev_private_data = &intel_private; 1501 bridge->dev = pdev; 1502 1503 intel_private.bridge_dev = pci_dev_get(pdev); 1504 1505 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 1506 1507 mask = intel_private.driver->dma_mask_size; 1508 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 1509 dev_err(&intel_private.pcidev->dev, 1510 "set gfx device dma mask %d-bit failed!\n", mask); 1511 else 1512 pci_set_consistent_dma_mask(intel_private.pcidev, 1513 DMA_BIT_MASK(mask)); 1514 1515 /*if (bridge->driver == &intel_810_driver) 1516 return 1;*/ 1517 1518 if (intel_gtt_init() != 0) 1519 return 0; 1520 1521 return 1; 1522 } 1523 EXPORT_SYMBOL(intel_gmch_probe); 1524 1525 const struct intel_gtt *intel_gtt_get(void) 1526 { 1527 return &intel_private.base; 1528 } 1529 EXPORT_SYMBOL(intel_gtt_get); 1530 1531 void intel_gtt_chipset_flush(void) 1532 { 1533 if (intel_private.driver->chipset_flush) 1534 intel_private.driver->chipset_flush(); 1535 } 1536 EXPORT_SYMBOL(intel_gtt_chipset_flush); 1537 1538 void intel_gmch_remove(struct pci_dev *pdev) 1539 { 1540 if (intel_private.pcidev) 1541 pci_dev_put(intel_private.pcidev); 1542 if (intel_private.bridge_dev) 1543 pci_dev_put(intel_private.bridge_dev); 1544 } 1545 EXPORT_SYMBOL(intel_gmch_remove); 1546 1547 MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1548 MODULE_LICENSE("GPL and additional rights"); 1549