1 /* 2 * Intel GTT (Graphics Translation Table) routines 3 * 4 * Caveat: This driver implements the linux agp interface, but this is far from 5 * a agp driver! GTT support ended up here for purely historical reasons: The 6 * old userspace intel graphics drivers needed an interface to map memory into 7 * the GTT. And the drm provides a default interface for graphic devices sitting 8 * on an agp port. So it made sense to fake the GTT support as an agp port to 9 * avoid having to create a new api. 10 * 11 * With gem this does not make much sense anymore, just needlessly complicates 12 * the code. But as long as the old graphics stack is still support, it's stuck 13 * here. 14 * 15 * /fairy-tale-mode off 16 */ 17 18 #include <linux/module.h> 19 #include <linux/pci.h> 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/pagemap.h> 23 #include <linux/agp_backend.h> 24 #include <linux/delay.h> 25 #include <asm/smp.h> 26 #include "agp.h" 27 #include "intel-agp.h" 28 #include <drm/intel-gtt.h> 29 30 /* 31 * If we have Intel graphics, we're not going to have anything other than 32 * an Intel IOMMU. So make the correct use of the PCI DMA API contingent 33 * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). 34 * Only newer chipsets need to bother with this, of course. 35 */ 36 #ifdef CONFIG_INTEL_IOMMU 37 #define USE_PCI_DMA_API 1 38 #else 39 #define USE_PCI_DMA_API 0 40 #endif 41 42 struct intel_gtt_driver { 43 unsigned int gen : 8; 44 unsigned int is_g33 : 1; 45 unsigned int is_pineview : 1; 46 unsigned int is_ironlake : 1; 47 unsigned int has_pgtbl_enable : 1; 48 unsigned int dma_mask_size : 8; 49 /* Chipset specific GTT setup */ 50 int (*setup)(void); 51 /* This should undo anything done in ->setup() save the unmapping 52 * of the mmio register file, that's done in the generic code. */ 53 void (*cleanup)(void); 54 void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); 55 /* Flags is a more or less chipset specific opaque value. 56 * For chipsets that need to support old ums (non-gem) code, this 57 * needs to be identical to the various supported agp memory types! */ 58 bool (*check_flags)(unsigned int flags); 59 void (*chipset_flush)(void); 60 }; 61 62 static struct _intel_private { 63 struct intel_gtt base; 64 const struct intel_gtt_driver *driver; 65 struct pci_dev *pcidev; /* device one */ 66 struct pci_dev *bridge_dev; 67 u8 __iomem *registers; 68 phys_addr_t gtt_bus_addr; 69 u32 PGETBL_save; 70 u32 __iomem *gtt; /* I915G */ 71 bool clear_fake_agp; /* on first access via agp, fill with scratch */ 72 int num_dcache_entries; 73 void __iomem *i9xx_flush_page; 74 char *i81x_gtt_table; 75 struct resource ifp_resource; 76 int resource_valid; 77 struct page *scratch_page; 78 int refcount; 79 } intel_private; 80 81 #define INTEL_GTT_GEN intel_private.driver->gen 82 #define IS_G33 intel_private.driver->is_g33 83 #define IS_PINEVIEW intel_private.driver->is_pineview 84 #define IS_IRONLAKE intel_private.driver->is_ironlake 85 #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 86 87 int intel_gtt_map_memory(struct page **pages, unsigned int num_entries, 88 struct scatterlist **sg_list, int *num_sg) 89 { 90 struct sg_table st; 91 struct scatterlist *sg; 92 int i; 93 94 if (*sg_list) 95 return 0; /* already mapped (for e.g. resume */ 96 97 DBG("try mapping %lu pages\n", (unsigned long)num_entries); 98 99 if (sg_alloc_table(&st, num_entries, GFP_KERNEL)) 100 goto err; 101 102 *sg_list = sg = st.sgl; 103 104 for (i = 0 ; i < num_entries; i++, sg = sg_next(sg)) 105 sg_set_page(sg, pages[i], PAGE_SIZE, 0); 106 107 *num_sg = pci_map_sg(intel_private.pcidev, *sg_list, 108 num_entries, PCI_DMA_BIDIRECTIONAL); 109 if (unlikely(!*num_sg)) 110 goto err; 111 112 return 0; 113 114 err: 115 sg_free_table(&st); 116 return -ENOMEM; 117 } 118 EXPORT_SYMBOL(intel_gtt_map_memory); 119 120 void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) 121 { 122 struct sg_table st; 123 DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); 124 125 pci_unmap_sg(intel_private.pcidev, sg_list, 126 num_sg, PCI_DMA_BIDIRECTIONAL); 127 128 st.sgl = sg_list; 129 st.orig_nents = st.nents = num_sg; 130 131 sg_free_table(&st); 132 } 133 EXPORT_SYMBOL(intel_gtt_unmap_memory); 134 135 static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) 136 { 137 return; 138 } 139 140 /* Exists to support ARGB cursors */ 141 static struct page *i8xx_alloc_pages(void) 142 { 143 struct page *page; 144 145 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 146 if (page == NULL) 147 return NULL; 148 149 if (set_pages_uc(page, 4) < 0) { 150 set_pages_wb(page, 4); 151 __free_pages(page, 2); 152 return NULL; 153 } 154 get_page(page); 155 atomic_inc(&agp_bridge->current_memory_agp); 156 return page; 157 } 158 159 static void i8xx_destroy_pages(struct page *page) 160 { 161 if (page == NULL) 162 return; 163 164 set_pages_wb(page, 4); 165 put_page(page); 166 __free_pages(page, 2); 167 atomic_dec(&agp_bridge->current_memory_agp); 168 } 169 170 #define I810_GTT_ORDER 4 171 static int i810_setup(void) 172 { 173 u32 reg_addr; 174 char *gtt_table; 175 176 /* i81x does not preallocate the gtt. It's always 64kb in size. */ 177 gtt_table = alloc_gatt_pages(I810_GTT_ORDER); 178 if (gtt_table == NULL) 179 return -ENOMEM; 180 intel_private.i81x_gtt_table = gtt_table; 181 182 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 183 reg_addr &= 0xfff80000; 184 185 intel_private.registers = ioremap(reg_addr, KB(64)); 186 if (!intel_private.registers) 187 return -ENOMEM; 188 189 writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, 190 intel_private.registers+I810_PGETBL_CTL); 191 192 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 193 194 if ((readl(intel_private.registers+I810_DRAM_CTL) 195 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 196 dev_info(&intel_private.pcidev->dev, 197 "detected 4MB dedicated video ram\n"); 198 intel_private.num_dcache_entries = 1024; 199 } 200 201 return 0; 202 } 203 204 static void i810_cleanup(void) 205 { 206 writel(0, intel_private.registers+I810_PGETBL_CTL); 207 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 208 } 209 210 static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 211 int type) 212 { 213 int i; 214 215 if ((pg_start + mem->page_count) 216 > intel_private.num_dcache_entries) 217 return -EINVAL; 218 219 if (!mem->is_flushed) 220 global_cache_flush(); 221 222 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 223 dma_addr_t addr = i << PAGE_SHIFT; 224 intel_private.driver->write_entry(addr, 225 i, type); 226 } 227 readl(intel_private.gtt+i-1); 228 229 return 0; 230 } 231 232 /* 233 * The i810/i830 requires a physical address to program its mouse 234 * pointer into hardware. 235 * However the Xserver still writes to it through the agp aperture. 236 */ 237 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 238 { 239 struct agp_memory *new; 240 struct page *page; 241 242 switch (pg_count) { 243 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); 244 break; 245 case 4: 246 /* kludge to get 4 physical pages for ARGB cursor */ 247 page = i8xx_alloc_pages(); 248 break; 249 default: 250 return NULL; 251 } 252 253 if (page == NULL) 254 return NULL; 255 256 new = agp_create_memory(pg_count); 257 if (new == NULL) 258 return NULL; 259 260 new->pages[0] = page; 261 if (pg_count == 4) { 262 /* kludge to get 4 physical pages for ARGB cursor */ 263 new->pages[1] = new->pages[0] + 1; 264 new->pages[2] = new->pages[1] + 1; 265 new->pages[3] = new->pages[2] + 1; 266 } 267 new->page_count = pg_count; 268 new->num_scratch_pages = pg_count; 269 new->type = AGP_PHYS_MEMORY; 270 new->physical = page_to_phys(new->pages[0]); 271 return new; 272 } 273 274 static void intel_i810_free_by_type(struct agp_memory *curr) 275 { 276 agp_free_key(curr->key); 277 if (curr->type == AGP_PHYS_MEMORY) { 278 if (curr->page_count == 4) 279 i8xx_destroy_pages(curr->pages[0]); 280 else { 281 agp_bridge->driver->agp_destroy_page(curr->pages[0], 282 AGP_PAGE_DESTROY_UNMAP); 283 agp_bridge->driver->agp_destroy_page(curr->pages[0], 284 AGP_PAGE_DESTROY_FREE); 285 } 286 agp_free_page_array(curr); 287 } 288 kfree(curr); 289 } 290 291 static int intel_gtt_setup_scratch_page(void) 292 { 293 struct page *page; 294 dma_addr_t dma_addr; 295 296 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 297 if (page == NULL) 298 return -ENOMEM; 299 get_page(page); 300 set_pages_uc(page, 1); 301 302 if (intel_private.base.needs_dmar) { 303 dma_addr = pci_map_page(intel_private.pcidev, page, 0, 304 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 305 if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) 306 return -EINVAL; 307 308 intel_private.base.scratch_page_dma = dma_addr; 309 } else 310 intel_private.base.scratch_page_dma = page_to_phys(page); 311 312 intel_private.scratch_page = page; 313 314 return 0; 315 } 316 317 static void i810_write_entry(dma_addr_t addr, unsigned int entry, 318 unsigned int flags) 319 { 320 u32 pte_flags = I810_PTE_VALID; 321 322 switch (flags) { 323 case AGP_DCACHE_MEMORY: 324 pte_flags |= I810_PTE_LOCAL; 325 break; 326 case AGP_USER_CACHED_MEMORY: 327 pte_flags |= I830_PTE_SYSTEM_CACHED; 328 break; 329 } 330 331 writel(addr | pte_flags, intel_private.gtt + entry); 332 } 333 334 static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { 335 {32, 8192, 3}, 336 {64, 16384, 4}, 337 {128, 32768, 5}, 338 {256, 65536, 6}, 339 {512, 131072, 7}, 340 }; 341 342 static unsigned int intel_gtt_stolen_size(void) 343 { 344 u16 gmch_ctrl; 345 u8 rdct; 346 int local = 0; 347 static const int ddt[4] = { 0, 16, 32, 64 }; 348 unsigned int stolen_size = 0; 349 350 if (INTEL_GTT_GEN == 1) 351 return 0; /* no stolen mem on i81x */ 352 353 pci_read_config_word(intel_private.bridge_dev, 354 I830_GMCH_CTRL, &gmch_ctrl); 355 356 if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 357 intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 358 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 359 case I830_GMCH_GMS_STOLEN_512: 360 stolen_size = KB(512); 361 break; 362 case I830_GMCH_GMS_STOLEN_1024: 363 stolen_size = MB(1); 364 break; 365 case I830_GMCH_GMS_STOLEN_8192: 366 stolen_size = MB(8); 367 break; 368 case I830_GMCH_GMS_LOCAL: 369 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); 370 stolen_size = (I830_RDRAM_ND(rdct) + 1) * 371 MB(ddt[I830_RDRAM_DDT(rdct)]); 372 local = 1; 373 break; 374 default: 375 stolen_size = 0; 376 break; 377 } 378 } else if (INTEL_GTT_GEN == 6) { 379 /* 380 * SandyBridge has new memory control reg at 0x50.w 381 */ 382 u16 snb_gmch_ctl; 383 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 384 switch (snb_gmch_ctl & SNB_GMCH_GMS_STOLEN_MASK) { 385 case SNB_GMCH_GMS_STOLEN_32M: 386 stolen_size = MB(32); 387 break; 388 case SNB_GMCH_GMS_STOLEN_64M: 389 stolen_size = MB(64); 390 break; 391 case SNB_GMCH_GMS_STOLEN_96M: 392 stolen_size = MB(96); 393 break; 394 case SNB_GMCH_GMS_STOLEN_128M: 395 stolen_size = MB(128); 396 break; 397 case SNB_GMCH_GMS_STOLEN_160M: 398 stolen_size = MB(160); 399 break; 400 case SNB_GMCH_GMS_STOLEN_192M: 401 stolen_size = MB(192); 402 break; 403 case SNB_GMCH_GMS_STOLEN_224M: 404 stolen_size = MB(224); 405 break; 406 case SNB_GMCH_GMS_STOLEN_256M: 407 stolen_size = MB(256); 408 break; 409 case SNB_GMCH_GMS_STOLEN_288M: 410 stolen_size = MB(288); 411 break; 412 case SNB_GMCH_GMS_STOLEN_320M: 413 stolen_size = MB(320); 414 break; 415 case SNB_GMCH_GMS_STOLEN_352M: 416 stolen_size = MB(352); 417 break; 418 case SNB_GMCH_GMS_STOLEN_384M: 419 stolen_size = MB(384); 420 break; 421 case SNB_GMCH_GMS_STOLEN_416M: 422 stolen_size = MB(416); 423 break; 424 case SNB_GMCH_GMS_STOLEN_448M: 425 stolen_size = MB(448); 426 break; 427 case SNB_GMCH_GMS_STOLEN_480M: 428 stolen_size = MB(480); 429 break; 430 case SNB_GMCH_GMS_STOLEN_512M: 431 stolen_size = MB(512); 432 break; 433 } 434 } else { 435 switch (gmch_ctrl & I855_GMCH_GMS_MASK) { 436 case I855_GMCH_GMS_STOLEN_1M: 437 stolen_size = MB(1); 438 break; 439 case I855_GMCH_GMS_STOLEN_4M: 440 stolen_size = MB(4); 441 break; 442 case I855_GMCH_GMS_STOLEN_8M: 443 stolen_size = MB(8); 444 break; 445 case I855_GMCH_GMS_STOLEN_16M: 446 stolen_size = MB(16); 447 break; 448 case I855_GMCH_GMS_STOLEN_32M: 449 stolen_size = MB(32); 450 break; 451 case I915_GMCH_GMS_STOLEN_48M: 452 stolen_size = MB(48); 453 break; 454 case I915_GMCH_GMS_STOLEN_64M: 455 stolen_size = MB(64); 456 break; 457 case G33_GMCH_GMS_STOLEN_128M: 458 stolen_size = MB(128); 459 break; 460 case G33_GMCH_GMS_STOLEN_256M: 461 stolen_size = MB(256); 462 break; 463 case INTEL_GMCH_GMS_STOLEN_96M: 464 stolen_size = MB(96); 465 break; 466 case INTEL_GMCH_GMS_STOLEN_160M: 467 stolen_size = MB(160); 468 break; 469 case INTEL_GMCH_GMS_STOLEN_224M: 470 stolen_size = MB(224); 471 break; 472 case INTEL_GMCH_GMS_STOLEN_352M: 473 stolen_size = MB(352); 474 break; 475 default: 476 stolen_size = 0; 477 break; 478 } 479 } 480 481 if (stolen_size > 0) { 482 dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", 483 stolen_size / KB(1), local ? "local" : "stolen"); 484 } else { 485 dev_info(&intel_private.bridge_dev->dev, 486 "no pre-allocated video memory detected\n"); 487 stolen_size = 0; 488 } 489 490 return stolen_size; 491 } 492 493 static void i965_adjust_pgetbl_size(unsigned int size_flag) 494 { 495 u32 pgetbl_ctl, pgetbl_ctl2; 496 497 /* ensure that ppgtt is disabled */ 498 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); 499 pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; 500 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); 501 502 /* write the new ggtt size */ 503 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 504 pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; 505 pgetbl_ctl |= size_flag; 506 writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); 507 } 508 509 static unsigned int i965_gtt_total_entries(void) 510 { 511 int size; 512 u32 pgetbl_ctl; 513 u16 gmch_ctl; 514 515 pci_read_config_word(intel_private.bridge_dev, 516 I830_GMCH_CTRL, &gmch_ctl); 517 518 if (INTEL_GTT_GEN == 5) { 519 switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { 520 case G4x_GMCH_SIZE_1M: 521 case G4x_GMCH_SIZE_VT_1M: 522 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); 523 break; 524 case G4x_GMCH_SIZE_VT_1_5M: 525 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); 526 break; 527 case G4x_GMCH_SIZE_2M: 528 case G4x_GMCH_SIZE_VT_2M: 529 i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); 530 break; 531 } 532 } 533 534 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); 535 536 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 537 case I965_PGETBL_SIZE_128KB: 538 size = KB(128); 539 break; 540 case I965_PGETBL_SIZE_256KB: 541 size = KB(256); 542 break; 543 case I965_PGETBL_SIZE_512KB: 544 size = KB(512); 545 break; 546 /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ 547 case I965_PGETBL_SIZE_1MB: 548 size = KB(1024); 549 break; 550 case I965_PGETBL_SIZE_2MB: 551 size = KB(2048); 552 break; 553 case I965_PGETBL_SIZE_1_5MB: 554 size = KB(1024 + 512); 555 break; 556 default: 557 dev_info(&intel_private.pcidev->dev, 558 "unknown page table size, assuming 512KB\n"); 559 size = KB(512); 560 } 561 562 return size/4; 563 } 564 565 static unsigned int intel_gtt_total_entries(void) 566 { 567 int size; 568 569 if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) 570 return i965_gtt_total_entries(); 571 else if (INTEL_GTT_GEN == 6) { 572 u16 snb_gmch_ctl; 573 574 pci_read_config_word(intel_private.pcidev, SNB_GMCH_CTRL, &snb_gmch_ctl); 575 switch (snb_gmch_ctl & SNB_GTT_SIZE_MASK) { 576 default: 577 case SNB_GTT_SIZE_0M: 578 printk(KERN_ERR "Bad GTT size mask: 0x%04x.\n", snb_gmch_ctl); 579 size = MB(0); 580 break; 581 case SNB_GTT_SIZE_1M: 582 size = MB(1); 583 break; 584 case SNB_GTT_SIZE_2M: 585 size = MB(2); 586 break; 587 } 588 return size/4; 589 } else { 590 /* On previous hardware, the GTT size was just what was 591 * required to map the aperture. 592 */ 593 return intel_private.base.gtt_mappable_entries; 594 } 595 } 596 597 static unsigned int intel_gtt_mappable_entries(void) 598 { 599 unsigned int aperture_size; 600 601 if (INTEL_GTT_GEN == 1) { 602 u32 smram_miscc; 603 604 pci_read_config_dword(intel_private.bridge_dev, 605 I810_SMRAM_MISCC, &smram_miscc); 606 607 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) 608 == I810_GFX_MEM_WIN_32M) 609 aperture_size = MB(32); 610 else 611 aperture_size = MB(64); 612 } else if (INTEL_GTT_GEN == 2) { 613 u16 gmch_ctrl; 614 615 pci_read_config_word(intel_private.bridge_dev, 616 I830_GMCH_CTRL, &gmch_ctrl); 617 618 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) 619 aperture_size = MB(64); 620 else 621 aperture_size = MB(128); 622 } else { 623 /* 9xx supports large sizes, just look at the length */ 624 aperture_size = pci_resource_len(intel_private.pcidev, 2); 625 } 626 627 return aperture_size >> PAGE_SHIFT; 628 } 629 630 static void intel_gtt_teardown_scratch_page(void) 631 { 632 set_pages_wb(intel_private.scratch_page, 1); 633 pci_unmap_page(intel_private.pcidev, intel_private.base.scratch_page_dma, 634 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 635 put_page(intel_private.scratch_page); 636 __free_page(intel_private.scratch_page); 637 } 638 639 static void intel_gtt_cleanup(void) 640 { 641 intel_private.driver->cleanup(); 642 643 iounmap(intel_private.gtt); 644 iounmap(intel_private.registers); 645 646 intel_gtt_teardown_scratch_page(); 647 } 648 649 static int intel_gtt_init(void) 650 { 651 u32 gma_addr; 652 u32 gtt_map_size; 653 int ret; 654 655 ret = intel_private.driver->setup(); 656 if (ret != 0) 657 return ret; 658 659 intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); 660 intel_private.base.gtt_total_entries = intel_gtt_total_entries(); 661 662 /* save the PGETBL reg for resume */ 663 intel_private.PGETBL_save = 664 readl(intel_private.registers+I810_PGETBL_CTL) 665 & ~I810_PGETBL_ENABLED; 666 /* we only ever restore the register when enabling the PGTBL... */ 667 if (HAS_PGTBL_EN) 668 intel_private.PGETBL_save |= I810_PGETBL_ENABLED; 669 670 dev_info(&intel_private.bridge_dev->dev, 671 "detected gtt size: %dK total, %dK mappable\n", 672 intel_private.base.gtt_total_entries * 4, 673 intel_private.base.gtt_mappable_entries * 4); 674 675 gtt_map_size = intel_private.base.gtt_total_entries * 4; 676 677 intel_private.gtt = ioremap(intel_private.gtt_bus_addr, 678 gtt_map_size); 679 if (!intel_private.gtt) { 680 intel_private.driver->cleanup(); 681 iounmap(intel_private.registers); 682 return -ENOMEM; 683 } 684 intel_private.base.gtt = intel_private.gtt; 685 686 global_cache_flush(); /* FIXME: ? */ 687 688 intel_private.base.stolen_size = intel_gtt_stolen_size(); 689 690 intel_private.base.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; 691 692 ret = intel_gtt_setup_scratch_page(); 693 if (ret != 0) { 694 intel_gtt_cleanup(); 695 return ret; 696 } 697 698 if (INTEL_GTT_GEN <= 2) 699 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, 700 &gma_addr); 701 else 702 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, 703 &gma_addr); 704 705 intel_private.base.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); 706 707 return 0; 708 } 709 710 static int intel_fake_agp_fetch_size(void) 711 { 712 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 713 unsigned int aper_size; 714 int i; 715 716 aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) 717 / MB(1); 718 719 for (i = 0; i < num_sizes; i++) { 720 if (aper_size == intel_fake_agp_sizes[i].size) { 721 agp_bridge->current_size = 722 (void *) (intel_fake_agp_sizes + i); 723 return aper_size; 724 } 725 } 726 727 return 0; 728 } 729 730 static void i830_cleanup(void) 731 { 732 } 733 734 /* The chipset_flush interface needs to get data that has already been 735 * flushed out of the CPU all the way out to main memory, because the GPU 736 * doesn't snoop those buffers. 737 * 738 * The 8xx series doesn't have the same lovely interface for flushing the 739 * chipset write buffers that the later chips do. According to the 865 740 * specs, it's 64 octwords, or 1KB. So, to get those previous things in 741 * that buffer out, we just fill 1KB and clflush it out, on the assumption 742 * that it'll push whatever was in there out. It appears to work. 743 */ 744 static void i830_chipset_flush(void) 745 { 746 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 747 748 /* Forcibly evict everything from the CPU write buffers. 749 * clflush appears to be insufficient. 750 */ 751 wbinvd_on_all_cpus(); 752 753 /* Now we've only seen documents for this magic bit on 855GM, 754 * we hope it exists for the other gen2 chipsets... 755 * 756 * Also works as advertised on my 845G. 757 */ 758 writel(readl(intel_private.registers+I830_HIC) | (1<<31), 759 intel_private.registers+I830_HIC); 760 761 while (readl(intel_private.registers+I830_HIC) & (1<<31)) { 762 if (time_after(jiffies, timeout)) 763 break; 764 765 udelay(50); 766 } 767 } 768 769 static void i830_write_entry(dma_addr_t addr, unsigned int entry, 770 unsigned int flags) 771 { 772 u32 pte_flags = I810_PTE_VALID; 773 774 if (flags == AGP_USER_CACHED_MEMORY) 775 pte_flags |= I830_PTE_SYSTEM_CACHED; 776 777 writel(addr | pte_flags, intel_private.gtt + entry); 778 } 779 780 bool intel_enable_gtt(void) 781 { 782 u8 __iomem *reg; 783 784 if (INTEL_GTT_GEN >= 6) 785 return true; 786 787 if (INTEL_GTT_GEN == 2) { 788 u16 gmch_ctrl; 789 790 pci_read_config_word(intel_private.bridge_dev, 791 I830_GMCH_CTRL, &gmch_ctrl); 792 gmch_ctrl |= I830_GMCH_ENABLED; 793 pci_write_config_word(intel_private.bridge_dev, 794 I830_GMCH_CTRL, gmch_ctrl); 795 796 pci_read_config_word(intel_private.bridge_dev, 797 I830_GMCH_CTRL, &gmch_ctrl); 798 if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { 799 dev_err(&intel_private.pcidev->dev, 800 "failed to enable the GTT: GMCH_CTRL=%x\n", 801 gmch_ctrl); 802 return false; 803 } 804 } 805 806 /* On the resume path we may be adjusting the PGTBL value, so 807 * be paranoid and flush all chipset write buffers... 808 */ 809 if (INTEL_GTT_GEN >= 3) 810 writel(0, intel_private.registers+GFX_FLSH_CNTL); 811 812 reg = intel_private.registers+I810_PGETBL_CTL; 813 writel(intel_private.PGETBL_save, reg); 814 if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { 815 dev_err(&intel_private.pcidev->dev, 816 "failed to enable the GTT: PGETBL=%x [expected %x]\n", 817 readl(reg), intel_private.PGETBL_save); 818 return false; 819 } 820 821 if (INTEL_GTT_GEN >= 3) 822 writel(0, intel_private.registers+GFX_FLSH_CNTL); 823 824 return true; 825 } 826 EXPORT_SYMBOL(intel_enable_gtt); 827 828 static int i830_setup(void) 829 { 830 u32 reg_addr; 831 832 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); 833 reg_addr &= 0xfff80000; 834 835 intel_private.registers = ioremap(reg_addr, KB(64)); 836 if (!intel_private.registers) 837 return -ENOMEM; 838 839 intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; 840 841 return 0; 842 } 843 844 static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 845 { 846 agp_bridge->gatt_table_real = NULL; 847 agp_bridge->gatt_table = NULL; 848 agp_bridge->gatt_bus_addr = 0; 849 850 return 0; 851 } 852 853 static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) 854 { 855 return 0; 856 } 857 858 static int intel_fake_agp_configure(void) 859 { 860 if (!intel_enable_gtt()) 861 return -EIO; 862 863 intel_private.clear_fake_agp = true; 864 agp_bridge->gart_bus_addr = intel_private.base.gma_bus_addr; 865 866 return 0; 867 } 868 869 static bool i830_check_flags(unsigned int flags) 870 { 871 switch (flags) { 872 case 0: 873 case AGP_PHYS_MEMORY: 874 case AGP_USER_CACHED_MEMORY: 875 case AGP_USER_MEMORY: 876 return true; 877 } 878 879 return false; 880 } 881 882 void intel_gtt_insert_sg_entries(struct scatterlist *sg_list, 883 unsigned int sg_len, 884 unsigned int pg_start, 885 unsigned int flags) 886 { 887 struct scatterlist *sg; 888 unsigned int len, m; 889 int i, j; 890 891 j = pg_start; 892 893 /* sg may merge pages, but we have to separate 894 * per-page addr for GTT */ 895 for_each_sg(sg_list, sg, sg_len, i) { 896 len = sg_dma_len(sg) >> PAGE_SHIFT; 897 for (m = 0; m < len; m++) { 898 dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); 899 intel_private.driver->write_entry(addr, 900 j, flags); 901 j++; 902 } 903 } 904 readl(intel_private.gtt+j-1); 905 } 906 EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 907 908 void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, 909 struct page **pages, unsigned int flags) 910 { 911 int i, j; 912 913 for (i = 0, j = first_entry; i < num_entries; i++, j++) { 914 dma_addr_t addr = page_to_phys(pages[i]); 915 intel_private.driver->write_entry(addr, 916 j, flags); 917 } 918 readl(intel_private.gtt+j-1); 919 } 920 EXPORT_SYMBOL(intel_gtt_insert_pages); 921 922 static int intel_fake_agp_insert_entries(struct agp_memory *mem, 923 off_t pg_start, int type) 924 { 925 int ret = -EINVAL; 926 927 if (intel_private.base.do_idle_maps) 928 return -ENODEV; 929 930 if (intel_private.clear_fake_agp) { 931 int start = intel_private.base.stolen_size / PAGE_SIZE; 932 int end = intel_private.base.gtt_mappable_entries; 933 intel_gtt_clear_range(start, end - start); 934 intel_private.clear_fake_agp = false; 935 } 936 937 if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) 938 return i810_insert_dcache_entries(mem, pg_start, type); 939 940 if (mem->page_count == 0) 941 goto out; 942 943 if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) 944 goto out_err; 945 946 if (type != mem->type) 947 goto out_err; 948 949 if (!intel_private.driver->check_flags(type)) 950 goto out_err; 951 952 if (!mem->is_flushed) 953 global_cache_flush(); 954 955 if (intel_private.base.needs_dmar) { 956 ret = intel_gtt_map_memory(mem->pages, mem->page_count, 957 &mem->sg_list, &mem->num_sg); 958 if (ret != 0) 959 return ret; 960 961 intel_gtt_insert_sg_entries(mem->sg_list, mem->num_sg, 962 pg_start, type); 963 } else 964 intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, 965 type); 966 967 out: 968 ret = 0; 969 out_err: 970 mem->is_flushed = true; 971 return ret; 972 } 973 974 void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 975 { 976 unsigned int i; 977 978 for (i = first_entry; i < (first_entry + num_entries); i++) { 979 intel_private.driver->write_entry(intel_private.base.scratch_page_dma, 980 i, 0); 981 } 982 readl(intel_private.gtt+i-1); 983 } 984 EXPORT_SYMBOL(intel_gtt_clear_range); 985 986 static int intel_fake_agp_remove_entries(struct agp_memory *mem, 987 off_t pg_start, int type) 988 { 989 if (mem->page_count == 0) 990 return 0; 991 992 if (intel_private.base.do_idle_maps) 993 return -ENODEV; 994 995 intel_gtt_clear_range(pg_start, mem->page_count); 996 997 if (intel_private.base.needs_dmar) { 998 intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); 999 mem->sg_list = NULL; 1000 mem->num_sg = 0; 1001 } 1002 1003 return 0; 1004 } 1005 1006 static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, 1007 int type) 1008 { 1009 struct agp_memory *new; 1010 1011 if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { 1012 if (pg_count != intel_private.num_dcache_entries) 1013 return NULL; 1014 1015 new = agp_create_memory(1); 1016 if (new == NULL) 1017 return NULL; 1018 1019 new->type = AGP_DCACHE_MEMORY; 1020 new->page_count = pg_count; 1021 new->num_scratch_pages = 0; 1022 agp_free_page_array(new); 1023 return new; 1024 } 1025 if (type == AGP_PHYS_MEMORY) 1026 return alloc_agpphysmem_i8xx(pg_count, type); 1027 /* always return NULL for other allocation types for now */ 1028 return NULL; 1029 } 1030 1031 static int intel_alloc_chipset_flush_resource(void) 1032 { 1033 int ret; 1034 ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, 1035 PAGE_SIZE, PCIBIOS_MIN_MEM, 0, 1036 pcibios_align_resource, intel_private.bridge_dev); 1037 1038 return ret; 1039 } 1040 1041 static void intel_i915_setup_chipset_flush(void) 1042 { 1043 int ret; 1044 u32 temp; 1045 1046 pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); 1047 if (!(temp & 0x1)) { 1048 intel_alloc_chipset_flush_resource(); 1049 intel_private.resource_valid = 1; 1050 pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1051 } else { 1052 temp &= ~1; 1053 1054 intel_private.resource_valid = 1; 1055 intel_private.ifp_resource.start = temp; 1056 intel_private.ifp_resource.end = temp + PAGE_SIZE; 1057 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1058 /* some BIOSes reserve this area in a pnp some don't */ 1059 if (ret) 1060 intel_private.resource_valid = 0; 1061 } 1062 } 1063 1064 static void intel_i965_g33_setup_chipset_flush(void) 1065 { 1066 u32 temp_hi, temp_lo; 1067 int ret; 1068 1069 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); 1070 pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); 1071 1072 if (!(temp_lo & 0x1)) { 1073 1074 intel_alloc_chipset_flush_resource(); 1075 1076 intel_private.resource_valid = 1; 1077 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, 1078 upper_32_bits(intel_private.ifp_resource.start)); 1079 pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); 1080 } else { 1081 u64 l64; 1082 1083 temp_lo &= ~0x1; 1084 l64 = ((u64)temp_hi << 32) | temp_lo; 1085 1086 intel_private.resource_valid = 1; 1087 intel_private.ifp_resource.start = l64; 1088 intel_private.ifp_resource.end = l64 + PAGE_SIZE; 1089 ret = request_resource(&iomem_resource, &intel_private.ifp_resource); 1090 /* some BIOSes reserve this area in a pnp some don't */ 1091 if (ret) 1092 intel_private.resource_valid = 0; 1093 } 1094 } 1095 1096 static void intel_i9xx_setup_flush(void) 1097 { 1098 /* return if already configured */ 1099 if (intel_private.ifp_resource.start) 1100 return; 1101 1102 if (INTEL_GTT_GEN == 6) 1103 return; 1104 1105 /* setup a resource for this object */ 1106 intel_private.ifp_resource.name = "Intel Flush Page"; 1107 intel_private.ifp_resource.flags = IORESOURCE_MEM; 1108 1109 /* Setup chipset flush for 915 */ 1110 if (IS_G33 || INTEL_GTT_GEN >= 4) { 1111 intel_i965_g33_setup_chipset_flush(); 1112 } else { 1113 intel_i915_setup_chipset_flush(); 1114 } 1115 1116 if (intel_private.ifp_resource.start) 1117 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); 1118 if (!intel_private.i9xx_flush_page) 1119 dev_err(&intel_private.pcidev->dev, 1120 "can't ioremap flush page - no chipset flushing\n"); 1121 } 1122 1123 static void i9xx_cleanup(void) 1124 { 1125 if (intel_private.i9xx_flush_page) 1126 iounmap(intel_private.i9xx_flush_page); 1127 if (intel_private.resource_valid) 1128 release_resource(&intel_private.ifp_resource); 1129 intel_private.ifp_resource.start = 0; 1130 intel_private.resource_valid = 0; 1131 } 1132 1133 static void i9xx_chipset_flush(void) 1134 { 1135 if (intel_private.i9xx_flush_page) 1136 writel(1, intel_private.i9xx_flush_page); 1137 } 1138 1139 static void i965_write_entry(dma_addr_t addr, 1140 unsigned int entry, 1141 unsigned int flags) 1142 { 1143 u32 pte_flags; 1144 1145 pte_flags = I810_PTE_VALID; 1146 if (flags == AGP_USER_CACHED_MEMORY) 1147 pte_flags |= I830_PTE_SYSTEM_CACHED; 1148 1149 /* Shift high bits down */ 1150 addr |= (addr >> 28) & 0xf0; 1151 writel(addr | pte_flags, intel_private.gtt + entry); 1152 } 1153 1154 static bool gen6_check_flags(unsigned int flags) 1155 { 1156 return true; 1157 } 1158 1159 static void haswell_write_entry(dma_addr_t addr, unsigned int entry, 1160 unsigned int flags) 1161 { 1162 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; 1163 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; 1164 u32 pte_flags; 1165 1166 if (type_mask == AGP_USER_MEMORY) 1167 pte_flags = HSW_PTE_UNCACHED | I810_PTE_VALID; 1168 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { 1169 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; 1170 if (gfdt) 1171 pte_flags |= GEN6_PTE_GFDT; 1172 } else { /* set 'normal'/'cached' to LLC by default */ 1173 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; 1174 if (gfdt) 1175 pte_flags |= GEN6_PTE_GFDT; 1176 } 1177 1178 /* gen6 has bit11-4 for physical addr bit39-32 */ 1179 addr |= (addr >> 28) & 0xff0; 1180 writel(addr | pte_flags, intel_private.gtt + entry); 1181 } 1182 1183 static void gen6_write_entry(dma_addr_t addr, unsigned int entry, 1184 unsigned int flags) 1185 { 1186 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; 1187 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; 1188 u32 pte_flags; 1189 1190 if (type_mask == AGP_USER_MEMORY) 1191 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; 1192 else if (type_mask == AGP_USER_CACHED_MEMORY_LLC_MLC) { 1193 pte_flags = GEN6_PTE_LLC_MLC | I810_PTE_VALID; 1194 if (gfdt) 1195 pte_flags |= GEN6_PTE_GFDT; 1196 } else { /* set 'normal'/'cached' to LLC by default */ 1197 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; 1198 if (gfdt) 1199 pte_flags |= GEN6_PTE_GFDT; 1200 } 1201 1202 /* gen6 has bit11-4 for physical addr bit39-32 */ 1203 addr |= (addr >> 28) & 0xff0; 1204 writel(addr | pte_flags, intel_private.gtt + entry); 1205 } 1206 1207 static void valleyview_write_entry(dma_addr_t addr, unsigned int entry, 1208 unsigned int flags) 1209 { 1210 unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT; 1211 unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT; 1212 u32 pte_flags; 1213 1214 if (type_mask == AGP_USER_MEMORY) 1215 pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID; 1216 else { 1217 pte_flags = GEN6_PTE_LLC | I810_PTE_VALID; 1218 if (gfdt) 1219 pte_flags |= GEN6_PTE_GFDT; 1220 } 1221 1222 /* gen6 has bit11-4 for physical addr bit39-32 */ 1223 addr |= (addr >> 28) & 0xff0; 1224 writel(addr | pte_flags, intel_private.gtt + entry); 1225 1226 writel(1, intel_private.registers + GFX_FLSH_CNTL_VLV); 1227 } 1228 1229 static void gen6_cleanup(void) 1230 { 1231 } 1232 1233 /* Certain Gen5 chipsets require require idling the GPU before 1234 * unmapping anything from the GTT when VT-d is enabled. 1235 */ 1236 static inline int needs_idle_maps(void) 1237 { 1238 #ifdef CONFIG_INTEL_IOMMU 1239 const unsigned short gpu_devid = intel_private.pcidev->device; 1240 1241 /* Query intel_iommu to see if we need the workaround. Presumably that 1242 * was loaded first. 1243 */ 1244 if ((gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB || 1245 gpu_devid == PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG) && 1246 intel_iommu_gfx_mapped) 1247 return 1; 1248 #endif 1249 return 0; 1250 } 1251 1252 static int i9xx_setup(void) 1253 { 1254 u32 reg_addr; 1255 int size = KB(512); 1256 1257 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); 1258 1259 reg_addr &= 0xfff80000; 1260 1261 if (INTEL_GTT_GEN >= 7) 1262 size = MB(2); 1263 1264 intel_private.registers = ioremap(reg_addr, size); 1265 if (!intel_private.registers) 1266 return -ENOMEM; 1267 1268 if (INTEL_GTT_GEN == 3) { 1269 u32 gtt_addr; 1270 1271 pci_read_config_dword(intel_private.pcidev, 1272 I915_PTEADDR, >t_addr); 1273 intel_private.gtt_bus_addr = gtt_addr; 1274 } else { 1275 u32 gtt_offset; 1276 1277 switch (INTEL_GTT_GEN) { 1278 case 5: 1279 case 6: 1280 case 7: 1281 gtt_offset = MB(2); 1282 break; 1283 case 4: 1284 default: 1285 gtt_offset = KB(512); 1286 break; 1287 } 1288 intel_private.gtt_bus_addr = reg_addr + gtt_offset; 1289 } 1290 1291 if (needs_idle_maps()) 1292 intel_private.base.do_idle_maps = 1; 1293 1294 intel_i9xx_setup_flush(); 1295 1296 return 0; 1297 } 1298 1299 static const struct agp_bridge_driver intel_fake_agp_driver = { 1300 .owner = THIS_MODULE, 1301 .size_type = FIXED_APER_SIZE, 1302 .aperture_sizes = intel_fake_agp_sizes, 1303 .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), 1304 .configure = intel_fake_agp_configure, 1305 .fetch_size = intel_fake_agp_fetch_size, 1306 .cleanup = intel_gtt_cleanup, 1307 .agp_enable = intel_fake_agp_enable, 1308 .cache_flush = global_cache_flush, 1309 .create_gatt_table = intel_fake_agp_create_gatt_table, 1310 .free_gatt_table = intel_fake_agp_free_gatt_table, 1311 .insert_memory = intel_fake_agp_insert_entries, 1312 .remove_memory = intel_fake_agp_remove_entries, 1313 .alloc_by_type = intel_fake_agp_alloc_by_type, 1314 .free_by_type = intel_i810_free_by_type, 1315 .agp_alloc_page = agp_generic_alloc_page, 1316 .agp_alloc_pages = agp_generic_alloc_pages, 1317 .agp_destroy_page = agp_generic_destroy_page, 1318 .agp_destroy_pages = agp_generic_destroy_pages, 1319 }; 1320 1321 static const struct intel_gtt_driver i81x_gtt_driver = { 1322 .gen = 1, 1323 .has_pgtbl_enable = 1, 1324 .dma_mask_size = 32, 1325 .setup = i810_setup, 1326 .cleanup = i810_cleanup, 1327 .check_flags = i830_check_flags, 1328 .write_entry = i810_write_entry, 1329 }; 1330 static const struct intel_gtt_driver i8xx_gtt_driver = { 1331 .gen = 2, 1332 .has_pgtbl_enable = 1, 1333 .setup = i830_setup, 1334 .cleanup = i830_cleanup, 1335 .write_entry = i830_write_entry, 1336 .dma_mask_size = 32, 1337 .check_flags = i830_check_flags, 1338 .chipset_flush = i830_chipset_flush, 1339 }; 1340 static const struct intel_gtt_driver i915_gtt_driver = { 1341 .gen = 3, 1342 .has_pgtbl_enable = 1, 1343 .setup = i9xx_setup, 1344 .cleanup = i9xx_cleanup, 1345 /* i945 is the last gpu to need phys mem (for overlay and cursors). */ 1346 .write_entry = i830_write_entry, 1347 .dma_mask_size = 32, 1348 .check_flags = i830_check_flags, 1349 .chipset_flush = i9xx_chipset_flush, 1350 }; 1351 static const struct intel_gtt_driver g33_gtt_driver = { 1352 .gen = 3, 1353 .is_g33 = 1, 1354 .setup = i9xx_setup, 1355 .cleanup = i9xx_cleanup, 1356 .write_entry = i965_write_entry, 1357 .dma_mask_size = 36, 1358 .check_flags = i830_check_flags, 1359 .chipset_flush = i9xx_chipset_flush, 1360 }; 1361 static const struct intel_gtt_driver pineview_gtt_driver = { 1362 .gen = 3, 1363 .is_pineview = 1, .is_g33 = 1, 1364 .setup = i9xx_setup, 1365 .cleanup = i9xx_cleanup, 1366 .write_entry = i965_write_entry, 1367 .dma_mask_size = 36, 1368 .check_flags = i830_check_flags, 1369 .chipset_flush = i9xx_chipset_flush, 1370 }; 1371 static const struct intel_gtt_driver i965_gtt_driver = { 1372 .gen = 4, 1373 .has_pgtbl_enable = 1, 1374 .setup = i9xx_setup, 1375 .cleanup = i9xx_cleanup, 1376 .write_entry = i965_write_entry, 1377 .dma_mask_size = 36, 1378 .check_flags = i830_check_flags, 1379 .chipset_flush = i9xx_chipset_flush, 1380 }; 1381 static const struct intel_gtt_driver g4x_gtt_driver = { 1382 .gen = 5, 1383 .setup = i9xx_setup, 1384 .cleanup = i9xx_cleanup, 1385 .write_entry = i965_write_entry, 1386 .dma_mask_size = 36, 1387 .check_flags = i830_check_flags, 1388 .chipset_flush = i9xx_chipset_flush, 1389 }; 1390 static const struct intel_gtt_driver ironlake_gtt_driver = { 1391 .gen = 5, 1392 .is_ironlake = 1, 1393 .setup = i9xx_setup, 1394 .cleanup = i9xx_cleanup, 1395 .write_entry = i965_write_entry, 1396 .dma_mask_size = 36, 1397 .check_flags = i830_check_flags, 1398 .chipset_flush = i9xx_chipset_flush, 1399 }; 1400 static const struct intel_gtt_driver sandybridge_gtt_driver = { 1401 .gen = 6, 1402 .setup = i9xx_setup, 1403 .cleanup = gen6_cleanup, 1404 .write_entry = gen6_write_entry, 1405 .dma_mask_size = 40, 1406 .check_flags = gen6_check_flags, 1407 .chipset_flush = i9xx_chipset_flush, 1408 }; 1409 static const struct intel_gtt_driver haswell_gtt_driver = { 1410 .gen = 6, 1411 .setup = i9xx_setup, 1412 .cleanup = gen6_cleanup, 1413 .write_entry = haswell_write_entry, 1414 .dma_mask_size = 40, 1415 .check_flags = gen6_check_flags, 1416 .chipset_flush = i9xx_chipset_flush, 1417 }; 1418 static const struct intel_gtt_driver valleyview_gtt_driver = { 1419 .gen = 7, 1420 .setup = i9xx_setup, 1421 .cleanup = gen6_cleanup, 1422 .write_entry = valleyview_write_entry, 1423 .dma_mask_size = 40, 1424 .check_flags = gen6_check_flags, 1425 }; 1426 1427 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of 1428 * driver and gmch_driver must be non-null, and find_gmch will determine 1429 * which one should be used if a gmch_chip_id is present. 1430 */ 1431 static const struct intel_gtt_driver_description { 1432 unsigned int gmch_chip_id; 1433 char *name; 1434 const struct intel_gtt_driver *gtt_driver; 1435 } intel_gtt_chipsets[] = { 1436 { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", 1437 &i81x_gtt_driver}, 1438 { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", 1439 &i81x_gtt_driver}, 1440 { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", 1441 &i81x_gtt_driver}, 1442 { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", 1443 &i81x_gtt_driver}, 1444 { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", 1445 &i8xx_gtt_driver}, 1446 { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", 1447 &i8xx_gtt_driver}, 1448 { PCI_DEVICE_ID_INTEL_82854_IG, "854", 1449 &i8xx_gtt_driver}, 1450 { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", 1451 &i8xx_gtt_driver}, 1452 { PCI_DEVICE_ID_INTEL_82865_IG, "865", 1453 &i8xx_gtt_driver}, 1454 { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", 1455 &i915_gtt_driver }, 1456 { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", 1457 &i915_gtt_driver }, 1458 { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", 1459 &i915_gtt_driver }, 1460 { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", 1461 &i915_gtt_driver }, 1462 { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", 1463 &i915_gtt_driver }, 1464 { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", 1465 &i915_gtt_driver }, 1466 { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", 1467 &i965_gtt_driver }, 1468 { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", 1469 &i965_gtt_driver }, 1470 { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", 1471 &i965_gtt_driver }, 1472 { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", 1473 &i965_gtt_driver }, 1474 { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", 1475 &i965_gtt_driver }, 1476 { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", 1477 &i965_gtt_driver }, 1478 { PCI_DEVICE_ID_INTEL_G33_IG, "G33", 1479 &g33_gtt_driver }, 1480 { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", 1481 &g33_gtt_driver }, 1482 { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", 1483 &g33_gtt_driver }, 1484 { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", 1485 &pineview_gtt_driver }, 1486 { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", 1487 &pineview_gtt_driver }, 1488 { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", 1489 &g4x_gtt_driver }, 1490 { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", 1491 &g4x_gtt_driver }, 1492 { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", 1493 &g4x_gtt_driver }, 1494 { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", 1495 &g4x_gtt_driver }, 1496 { PCI_DEVICE_ID_INTEL_B43_IG, "B43", 1497 &g4x_gtt_driver }, 1498 { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", 1499 &g4x_gtt_driver }, 1500 { PCI_DEVICE_ID_INTEL_G41_IG, "G41", 1501 &g4x_gtt_driver }, 1502 { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, 1503 "HD Graphics", &ironlake_gtt_driver }, 1504 { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, 1505 "HD Graphics", &ironlake_gtt_driver }, 1506 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG, 1507 "Sandybridge", &sandybridge_gtt_driver }, 1508 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG, 1509 "Sandybridge", &sandybridge_gtt_driver }, 1510 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG, 1511 "Sandybridge", &sandybridge_gtt_driver }, 1512 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG, 1513 "Sandybridge", &sandybridge_gtt_driver }, 1514 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG, 1515 "Sandybridge", &sandybridge_gtt_driver }, 1516 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG, 1517 "Sandybridge", &sandybridge_gtt_driver }, 1518 { PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG, 1519 "Sandybridge", &sandybridge_gtt_driver }, 1520 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG, 1521 "Ivybridge", &sandybridge_gtt_driver }, 1522 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG, 1523 "Ivybridge", &sandybridge_gtt_driver }, 1524 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG, 1525 "Ivybridge", &sandybridge_gtt_driver }, 1526 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG, 1527 "Ivybridge", &sandybridge_gtt_driver }, 1528 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG, 1529 "Ivybridge", &sandybridge_gtt_driver }, 1530 { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG, 1531 "Ivybridge", &sandybridge_gtt_driver }, 1532 { PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG, 1533 "ValleyView", &valleyview_gtt_driver }, 1534 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG, 1535 "Haswell", &haswell_gtt_driver }, 1536 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG, 1537 "Haswell", &haswell_gtt_driver }, 1538 { PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG, 1539 "Haswell", &haswell_gtt_driver }, 1540 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG, 1541 "Haswell", &haswell_gtt_driver }, 1542 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG, 1543 "Haswell", &haswell_gtt_driver }, 1544 { PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG, 1545 "Haswell", &haswell_gtt_driver }, 1546 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG, 1547 "Haswell", &haswell_gtt_driver }, 1548 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG, 1549 "Haswell", &haswell_gtt_driver }, 1550 { PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_PLUS_IG, 1551 "Haswell", &haswell_gtt_driver }, 1552 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT1_IG, 1553 "Haswell", &haswell_gtt_driver }, 1554 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_IG, 1555 "Haswell", &haswell_gtt_driver }, 1556 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_D_GT2_PLUS_IG, 1557 "Haswell", &haswell_gtt_driver }, 1558 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT1_IG, 1559 "Haswell", &haswell_gtt_driver }, 1560 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_IG, 1561 "Haswell", &haswell_gtt_driver }, 1562 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_M_GT2_PLUS_IG, 1563 "Haswell", &haswell_gtt_driver }, 1564 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT1_IG, 1565 "Haswell", &haswell_gtt_driver }, 1566 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_IG, 1567 "Haswell", &haswell_gtt_driver }, 1568 { PCI_DEVICE_ID_INTEL_HASWELL_SDV_S_GT2_PLUS_IG, 1569 "Haswell", &haswell_gtt_driver }, 1570 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT1_IG, 1571 "Haswell", &haswell_gtt_driver }, 1572 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_IG, 1573 "Haswell", &haswell_gtt_driver }, 1574 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_D_GT2_PLUS_IG, 1575 "Haswell", &haswell_gtt_driver }, 1576 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT1_IG, 1577 "Haswell", &haswell_gtt_driver }, 1578 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_IG, 1579 "Haswell", &haswell_gtt_driver }, 1580 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_M_GT2_PLUS_IG, 1581 "Haswell", &haswell_gtt_driver }, 1582 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT1_IG, 1583 "Haswell", &haswell_gtt_driver }, 1584 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_IG, 1585 "Haswell", &haswell_gtt_driver }, 1586 { PCI_DEVICE_ID_INTEL_HASWELL_ULT_S_GT2_PLUS_IG, 1587 "Haswell", &haswell_gtt_driver }, 1588 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT1_IG, 1589 "Haswell", &haswell_gtt_driver }, 1590 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_IG, 1591 "Haswell", &haswell_gtt_driver }, 1592 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_D_GT2_PLUS_IG, 1593 "Haswell", &haswell_gtt_driver }, 1594 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT1_IG, 1595 "Haswell", &haswell_gtt_driver }, 1596 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_IG, 1597 "Haswell", &haswell_gtt_driver }, 1598 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_M_GT2_PLUS_IG, 1599 "Haswell", &haswell_gtt_driver }, 1600 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT1_IG, 1601 "Haswell", &haswell_gtt_driver }, 1602 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_IG, 1603 "Haswell", &haswell_gtt_driver }, 1604 { PCI_DEVICE_ID_INTEL_HASWELL_CRW_S_GT2_PLUS_IG, 1605 "Haswell", &haswell_gtt_driver }, 1606 { 0, NULL, NULL } 1607 }; 1608 1609 static int find_gmch(u16 device) 1610 { 1611 struct pci_dev *gmch_device; 1612 1613 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1614 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { 1615 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, 1616 device, gmch_device); 1617 } 1618 1619 if (!gmch_device) 1620 return 0; 1621 1622 intel_private.pcidev = gmch_device; 1623 return 1; 1624 } 1625 1626 int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, 1627 struct agp_bridge_data *bridge) 1628 { 1629 int i, mask; 1630 1631 /* 1632 * Can be called from the fake agp driver but also directly from 1633 * drm/i915.ko. Hence we need to check whether everything is set up 1634 * already. 1635 */ 1636 if (intel_private.driver) { 1637 intel_private.refcount++; 1638 return 1; 1639 } 1640 1641 for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { 1642 if (gpu_pdev) { 1643 if (gpu_pdev->device == 1644 intel_gtt_chipsets[i].gmch_chip_id) { 1645 intel_private.pcidev = pci_dev_get(gpu_pdev); 1646 intel_private.driver = 1647 intel_gtt_chipsets[i].gtt_driver; 1648 1649 break; 1650 } 1651 } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { 1652 intel_private.driver = 1653 intel_gtt_chipsets[i].gtt_driver; 1654 break; 1655 } 1656 } 1657 1658 if (!intel_private.driver) 1659 return 0; 1660 1661 intel_private.refcount++; 1662 1663 if (bridge) { 1664 bridge->driver = &intel_fake_agp_driver; 1665 bridge->dev_private_data = &intel_private; 1666 bridge->dev = bridge_pdev; 1667 } 1668 1669 intel_private.bridge_dev = pci_dev_get(bridge_pdev); 1670 1671 dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); 1672 1673 mask = intel_private.driver->dma_mask_size; 1674 if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) 1675 dev_err(&intel_private.pcidev->dev, 1676 "set gfx device dma mask %d-bit failed!\n", mask); 1677 else 1678 pci_set_consistent_dma_mask(intel_private.pcidev, 1679 DMA_BIT_MASK(mask)); 1680 1681 if (intel_gtt_init() != 0) { 1682 intel_gmch_remove(); 1683 1684 return 0; 1685 } 1686 1687 return 1; 1688 } 1689 EXPORT_SYMBOL(intel_gmch_probe); 1690 1691 const struct intel_gtt *intel_gtt_get(void) 1692 { 1693 return &intel_private.base; 1694 } 1695 EXPORT_SYMBOL(intel_gtt_get); 1696 1697 void intel_gtt_chipset_flush(void) 1698 { 1699 if (intel_private.driver->chipset_flush) 1700 intel_private.driver->chipset_flush(); 1701 } 1702 EXPORT_SYMBOL(intel_gtt_chipset_flush); 1703 1704 void intel_gmch_remove(void) 1705 { 1706 if (--intel_private.refcount) 1707 return; 1708 1709 if (intel_private.pcidev) 1710 pci_dev_put(intel_private.pcidev); 1711 if (intel_private.bridge_dev) 1712 pci_dev_put(intel_private.bridge_dev); 1713 intel_private.driver = NULL; 1714 } 1715 EXPORT_SYMBOL(intel_gmch_remove); 1716 1717 MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); 1718 MODULE_LICENSE("GPL and additional rights"); 1719