1 /* 2 * Intel AGPGART routines. 3 */ 4 5 /* 6 * Intel(R) 855GM/852GM and 865G support added by David Dawes 7 * <dawes@tungstengraphics.com>. 8 * 9 * Intel(R) 915G/915GM support added by Alan Hourihane 10 * <alanh@tungstengraphics.com>. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/init.h> 16 #include <linux/pagemap.h> 17 #include <linux/agp_backend.h> 18 #include "agp.h" 19 20 /* Intel 815 register */ 21 #define INTEL_815_APCONT 0x51 22 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 23 24 /* Intel i820 registers */ 25 #define INTEL_I820_RDCR 0x51 26 #define INTEL_I820_ERRSTS 0xc8 27 28 /* Intel i840 registers */ 29 #define INTEL_I840_MCHCFG 0x50 30 #define INTEL_I840_ERRSTS 0xc8 31 32 /* Intel i850 registers */ 33 #define INTEL_I850_MCHCFG 0x50 34 #define INTEL_I850_ERRSTS 0xc8 35 36 /* intel 915G registers */ 37 #define I915_GMADDR 0x18 38 #define I915_MMADDR 0x10 39 #define I915_PTEADDR 0x1C 40 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 41 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 42 43 44 /* Intel 7505 registers */ 45 #define INTEL_I7505_APSIZE 0x74 46 #define INTEL_I7505_NCAPID 0x60 47 #define INTEL_I7505_NISTAT 0x6c 48 #define INTEL_I7505_ATTBASE 0x78 49 #define INTEL_I7505_ERRSTS 0x42 50 #define INTEL_I7505_AGPCTRL 0x70 51 #define INTEL_I7505_MCHCFG 0x50 52 53 static struct aper_size_info_fixed intel_i810_sizes[] = 54 { 55 {64, 16384, 4}, 56 /* The 32M mode still requires a 64k gatt */ 57 {32, 8192, 4} 58 }; 59 60 #define AGP_DCACHE_MEMORY 1 61 #define AGP_PHYS_MEMORY 2 62 63 static struct gatt_mask intel_i810_masks[] = 64 { 65 {.mask = I810_PTE_VALID, .type = 0}, 66 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 67 {.mask = I810_PTE_VALID, .type = 0} 68 }; 69 70 static struct _intel_i810_private { 71 struct pci_dev *i810_dev; /* device one */ 72 volatile u8 __iomem *registers; 73 int num_dcache_entries; 74 } intel_i810_private; 75 76 static int intel_i810_fetch_size(void) 77 { 78 u32 smram_miscc; 79 struct aper_size_info_fixed *values; 80 81 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 82 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 83 84 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 85 printk(KERN_WARNING PFX "i810 is disabled\n"); 86 return 0; 87 } 88 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 89 agp_bridge->previous_size = 90 agp_bridge->current_size = (void *) (values + 1); 91 agp_bridge->aperture_size_idx = 1; 92 return values[1].size; 93 } else { 94 agp_bridge->previous_size = 95 agp_bridge->current_size = (void *) (values); 96 agp_bridge->aperture_size_idx = 0; 97 return values[0].size; 98 } 99 100 return 0; 101 } 102 103 static int intel_i810_configure(void) 104 { 105 struct aper_size_info_fixed *current_size; 106 u32 temp; 107 int i; 108 109 current_size = A_SIZE_FIX(agp_bridge->current_size); 110 111 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); 112 temp &= 0xfff80000; 113 114 intel_i810_private.registers = ioremap(temp, 128 * 4096); 115 if (!intel_i810_private.registers) { 116 printk(KERN_ERR PFX "Unable to remap memory.\n"); 117 return -ENOMEM; 118 } 119 120 if ((readl(intel_i810_private.registers+I810_DRAM_CTL) 121 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 122 /* This will need to be dynamically assigned */ 123 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); 124 intel_i810_private.num_dcache_entries = 1024; 125 } 126 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); 127 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 128 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL); 129 readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 130 131 if (agp_bridge->driver->needs_scratch_page) { 132 for (i = 0; i < current_size->num_entries; i++) { 133 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 134 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 135 } 136 } 137 global_cache_flush(); 138 return 0; 139 } 140 141 static void intel_i810_cleanup(void) 142 { 143 writel(0, intel_i810_private.registers+I810_PGETBL_CTL); 144 readl(intel_i810_private.registers); /* PCI Posting. */ 145 iounmap(intel_i810_private.registers); 146 } 147 148 static void intel_i810_tlbflush(struct agp_memory *mem) 149 { 150 return; 151 } 152 153 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 154 { 155 return; 156 } 157 158 /* Exists to support ARGB cursors */ 159 static void *i8xx_alloc_pages(void) 160 { 161 struct page * page; 162 163 page = alloc_pages(GFP_KERNEL, 2); 164 if (page == NULL) 165 return NULL; 166 167 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { 168 global_flush_tlb(); 169 __free_page(page); 170 return NULL; 171 } 172 global_flush_tlb(); 173 get_page(page); 174 SetPageLocked(page); 175 atomic_inc(&agp_bridge->current_memory_agp); 176 return page_address(page); 177 } 178 179 static void i8xx_destroy_pages(void *addr) 180 { 181 struct page *page; 182 183 if (addr == NULL) 184 return; 185 186 page = virt_to_page(addr); 187 change_page_attr(page, 4, PAGE_KERNEL); 188 global_flush_tlb(); 189 put_page(page); 190 unlock_page(page); 191 free_pages((unsigned long)addr, 2); 192 atomic_dec(&agp_bridge->current_memory_agp); 193 } 194 195 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 196 int type) 197 { 198 int i, j, num_entries; 199 void *temp; 200 201 temp = agp_bridge->current_size; 202 num_entries = A_SIZE_FIX(temp)->num_entries; 203 204 if ((pg_start + mem->page_count) > num_entries) 205 return -EINVAL; 206 207 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 208 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) 209 return -EBUSY; 210 } 211 212 if (type != 0 || mem->type != 0) { 213 if ((type == AGP_DCACHE_MEMORY) && (mem->type == AGP_DCACHE_MEMORY)) { 214 /* special insert */ 215 global_cache_flush(); 216 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 217 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 218 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 219 } 220 global_cache_flush(); 221 agp_bridge->driver->tlb_flush(mem); 222 return 0; 223 } 224 if ((type == AGP_PHYS_MEMORY) && (mem->type == AGP_PHYS_MEMORY)) 225 goto insert; 226 return -EINVAL; 227 } 228 229 insert: 230 global_cache_flush(); 231 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 232 writel(agp_bridge->driver->mask_memory(agp_bridge, 233 mem->memory[i], mem->type), 234 intel_i810_private.registers+I810_PTE_BASE+(j*4)); 235 readl(intel_i810_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */ 236 } 237 global_cache_flush(); 238 239 agp_bridge->driver->tlb_flush(mem); 240 return 0; 241 } 242 243 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 244 int type) 245 { 246 int i; 247 248 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 249 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 250 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 251 } 252 253 global_cache_flush(); 254 agp_bridge->driver->tlb_flush(mem); 255 return 0; 256 } 257 258 /* 259 * The i810/i830 requires a physical address to program its mouse 260 * pointer into hardware. 261 * However the Xserver still writes to it through the agp aperture. 262 */ 263 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 264 { 265 struct agp_memory *new; 266 void *addr; 267 268 if (pg_count != 1 && pg_count != 4) 269 return NULL; 270 271 switch (pg_count) { 272 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 273 global_flush_tlb(); 274 break; 275 case 4: 276 /* kludge to get 4 physical pages for ARGB cursor */ 277 addr = i8xx_alloc_pages(); 278 break; 279 default: 280 return NULL; 281 } 282 283 if (addr == NULL) 284 return NULL; 285 286 new = agp_create_memory(pg_count); 287 if (new == NULL) 288 return NULL; 289 290 new->memory[0] = virt_to_gart(addr); 291 if (pg_count == 4) { 292 /* kludge to get 4 physical pages for ARGB cursor */ 293 new->memory[1] = new->memory[0] + PAGE_SIZE; 294 new->memory[2] = new->memory[1] + PAGE_SIZE; 295 new->memory[3] = new->memory[2] + PAGE_SIZE; 296 } 297 new->page_count = pg_count; 298 new->num_scratch_pages = pg_count; 299 new->type = AGP_PHYS_MEMORY; 300 new->physical = new->memory[0]; 301 return new; 302 } 303 304 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 305 { 306 struct agp_memory *new; 307 308 if (type == AGP_DCACHE_MEMORY) { 309 if (pg_count != intel_i810_private.num_dcache_entries) 310 return NULL; 311 312 new = agp_create_memory(1); 313 if (new == NULL) 314 return NULL; 315 316 new->type = AGP_DCACHE_MEMORY; 317 new->page_count = pg_count; 318 new->num_scratch_pages = 0; 319 vfree(new->memory); 320 return new; 321 } 322 if (type == AGP_PHYS_MEMORY) 323 return alloc_agpphysmem_i8xx(pg_count, type); 324 325 return NULL; 326 } 327 328 static void intel_i810_free_by_type(struct agp_memory *curr) 329 { 330 agp_free_key(curr->key); 331 if (curr->type == AGP_PHYS_MEMORY) { 332 if (curr->page_count == 4) 333 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 334 else { 335 agp_bridge->driver->agp_destroy_page( 336 gart_to_virt(curr->memory[0])); 337 global_flush_tlb(); 338 } 339 vfree(curr->memory); 340 } 341 kfree(curr); 342 } 343 344 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 345 unsigned long addr, int type) 346 { 347 /* Type checking must be done elsewhere */ 348 return addr | bridge->driver->masks[type].mask; 349 } 350 351 static struct aper_size_info_fixed intel_i830_sizes[] = 352 { 353 {128, 32768, 5}, 354 /* The 64M mode still requires a 128k gatt */ 355 {64, 16384, 5}, 356 {256, 65536, 6}, 357 }; 358 359 static struct _intel_i830_private { 360 struct pci_dev *i830_dev; /* device one */ 361 volatile u8 __iomem *registers; 362 volatile u32 __iomem *gtt; /* I915G */ 363 int gtt_entries; 364 } intel_i830_private; 365 366 static void intel_i830_init_gtt_entries(void) 367 { 368 u16 gmch_ctrl; 369 int gtt_entries; 370 u8 rdct; 371 int local = 0; 372 static const int ddt[4] = { 0, 16, 32, 64 }; 373 int size; 374 375 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 376 377 /* We obtain the size of the GTT, which is also stored (for some 378 * reason) at the top of stolen memory. Then we add 4KB to that 379 * for the video BIOS popup, which is also stored in there. */ 380 size = agp_bridge->driver->fetch_size() + 4; 381 382 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 383 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 384 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 385 case I830_GMCH_GMS_STOLEN_512: 386 gtt_entries = KB(512) - KB(size); 387 break; 388 case I830_GMCH_GMS_STOLEN_1024: 389 gtt_entries = MB(1) - KB(size); 390 break; 391 case I830_GMCH_GMS_STOLEN_8192: 392 gtt_entries = MB(8) - KB(size); 393 break; 394 case I830_GMCH_GMS_LOCAL: 395 rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE); 396 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 397 MB(ddt[I830_RDRAM_DDT(rdct)]); 398 local = 1; 399 break; 400 default: 401 gtt_entries = 0; 402 break; 403 } 404 } else { 405 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 406 case I855_GMCH_GMS_STOLEN_1M: 407 gtt_entries = MB(1) - KB(size); 408 break; 409 case I855_GMCH_GMS_STOLEN_4M: 410 gtt_entries = MB(4) - KB(size); 411 break; 412 case I855_GMCH_GMS_STOLEN_8M: 413 gtt_entries = MB(8) - KB(size); 414 break; 415 case I855_GMCH_GMS_STOLEN_16M: 416 gtt_entries = MB(16) - KB(size); 417 break; 418 case I855_GMCH_GMS_STOLEN_32M: 419 gtt_entries = MB(32) - KB(size); 420 break; 421 case I915_GMCH_GMS_STOLEN_48M: 422 /* Check it's really I915G */ 423 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 424 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 425 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 426 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB) 427 gtt_entries = MB(48) - KB(size); 428 else 429 gtt_entries = 0; 430 break; 431 case I915_GMCH_GMS_STOLEN_64M: 432 /* Check it's really I915G */ 433 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 434 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 435 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 436 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB) 437 gtt_entries = MB(64) - KB(size); 438 else 439 gtt_entries = 0; 440 default: 441 gtt_entries = 0; 442 break; 443 } 444 } 445 if (gtt_entries > 0) 446 printk(KERN_INFO PFX "Detected %dK %s memory.\n", 447 gtt_entries / KB(1), local ? "local" : "stolen"); 448 else 449 printk(KERN_INFO PFX 450 "No pre-allocated video memory detected.\n"); 451 gtt_entries /= KB(4); 452 453 intel_i830_private.gtt_entries = gtt_entries; 454 } 455 456 /* The intel i830 automatically initializes the agp aperture during POST. 457 * Use the memory already set aside for in the GTT. 458 */ 459 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 460 { 461 int page_order; 462 struct aper_size_info_fixed *size; 463 int num_entries; 464 u32 temp; 465 466 size = agp_bridge->current_size; 467 page_order = size->page_order; 468 num_entries = size->num_entries; 469 agp_bridge->gatt_table_real = NULL; 470 471 pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); 472 temp &= 0xfff80000; 473 474 intel_i830_private.registers = ioremap(temp,128 * 4096); 475 if (!intel_i830_private.registers) 476 return -ENOMEM; 477 478 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 479 global_cache_flush(); /* FIXME: ?? */ 480 481 /* we have to call this as early as possible after the MMIO base address is known */ 482 intel_i830_init_gtt_entries(); 483 484 agp_bridge->gatt_table = NULL; 485 486 agp_bridge->gatt_bus_addr = temp; 487 488 return 0; 489 } 490 491 /* Return the gatt table to a sane state. Use the top of stolen 492 * memory for the GTT. 493 */ 494 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 495 { 496 return 0; 497 } 498 499 static int intel_i830_fetch_size(void) 500 { 501 u16 gmch_ctrl; 502 struct aper_size_info_fixed *values; 503 504 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 505 506 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 507 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 508 /* 855GM/852GM/865G has 128MB aperture size */ 509 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 510 agp_bridge->aperture_size_idx = 0; 511 return values[0].size; 512 } 513 514 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 515 516 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 517 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 518 agp_bridge->aperture_size_idx = 0; 519 return values[0].size; 520 } else { 521 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 522 agp_bridge->aperture_size_idx = 1; 523 return values[1].size; 524 } 525 526 return 0; 527 } 528 529 static int intel_i830_configure(void) 530 { 531 struct aper_size_info_fixed *current_size; 532 u32 temp; 533 u16 gmch_ctrl; 534 int i; 535 536 current_size = A_SIZE_FIX(agp_bridge->current_size); 537 538 pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); 539 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 540 541 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 542 gmch_ctrl |= I830_GMCH_ENABLED; 543 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 544 545 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 546 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 547 548 if (agp_bridge->driver->needs_scratch_page) { 549 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 550 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 551 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 552 } 553 } 554 555 global_cache_flush(); 556 return 0; 557 } 558 559 static void intel_i830_cleanup(void) 560 { 561 iounmap(intel_i830_private.registers); 562 } 563 564 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) 565 { 566 int i,j,num_entries; 567 void *temp; 568 569 temp = agp_bridge->current_size; 570 num_entries = A_SIZE_FIX(temp)->num_entries; 571 572 if (pg_start < intel_i830_private.gtt_entries) { 573 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 574 pg_start,intel_i830_private.gtt_entries); 575 576 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 577 return -EINVAL; 578 } 579 580 if ((pg_start + mem->page_count) > num_entries) 581 return -EINVAL; 582 583 /* The i830 can't check the GTT for entries since its read only, 584 * depend on the caller to make the correct offset decisions. 585 */ 586 587 if ((type != 0 && type != AGP_PHYS_MEMORY) || 588 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) 589 return -EINVAL; 590 591 global_cache_flush(); /* FIXME: Necessary ?*/ 592 593 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 594 writel(agp_bridge->driver->mask_memory(agp_bridge, 595 mem->memory[i], mem->type), 596 intel_i830_private.registers+I810_PTE_BASE+(j*4)); 597 readl(intel_i830_private.registers+I810_PTE_BASE+(j*4)); /* PCI Posting. */ 598 } 599 600 global_cache_flush(); 601 agp_bridge->driver->tlb_flush(mem); 602 return 0; 603 } 604 605 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, 606 int type) 607 { 608 int i; 609 610 global_cache_flush(); 611 612 if (pg_start < intel_i830_private.gtt_entries) { 613 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 614 return -EINVAL; 615 } 616 617 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 618 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 619 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 620 } 621 622 global_cache_flush(); 623 agp_bridge->driver->tlb_flush(mem); 624 return 0; 625 } 626 627 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) 628 { 629 if (type == AGP_PHYS_MEMORY) 630 return alloc_agpphysmem_i8xx(pg_count, type); 631 632 /* always return NULL for other allocation types for now */ 633 return NULL; 634 } 635 636 static int intel_i915_configure(void) 637 { 638 struct aper_size_info_fixed *current_size; 639 u32 temp; 640 u16 gmch_ctrl; 641 int i; 642 643 current_size = A_SIZE_FIX(agp_bridge->current_size); 644 645 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 646 647 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 648 649 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 650 gmch_ctrl |= I830_GMCH_ENABLED; 651 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 652 653 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 654 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 655 656 if (agp_bridge->driver->needs_scratch_page) { 657 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 658 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 659 readl(intel_i830_private.gtt+i); /* PCI Posting. */ 660 } 661 } 662 663 global_cache_flush(); 664 return 0; 665 } 666 667 static void intel_i915_cleanup(void) 668 { 669 iounmap(intel_i830_private.gtt); 670 iounmap(intel_i830_private.registers); 671 } 672 673 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, 674 int type) 675 { 676 int i,j,num_entries; 677 void *temp; 678 679 temp = agp_bridge->current_size; 680 num_entries = A_SIZE_FIX(temp)->num_entries; 681 682 if (pg_start < intel_i830_private.gtt_entries) { 683 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 684 pg_start,intel_i830_private.gtt_entries); 685 686 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 687 return -EINVAL; 688 } 689 690 if ((pg_start + mem->page_count) > num_entries) 691 return -EINVAL; 692 693 /* The i830 can't check the GTT for entries since its read only, 694 * depend on the caller to make the correct offset decisions. 695 */ 696 697 if ((type != 0 && type != AGP_PHYS_MEMORY) || 698 (mem->type != 0 && mem->type != AGP_PHYS_MEMORY)) 699 return -EINVAL; 700 701 global_cache_flush(); 702 703 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 704 writel(agp_bridge->driver->mask_memory(agp_bridge, 705 mem->memory[i], mem->type), intel_i830_private.gtt+j); 706 readl(intel_i830_private.gtt+j); /* PCI Posting. */ 707 } 708 709 global_cache_flush(); 710 agp_bridge->driver->tlb_flush(mem); 711 return 0; 712 } 713 714 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, 715 int type) 716 { 717 int i; 718 719 global_cache_flush(); 720 721 if (pg_start < intel_i830_private.gtt_entries) { 722 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 723 return -EINVAL; 724 } 725 726 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 727 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 728 readl(intel_i830_private.gtt+i); 729 } 730 731 global_cache_flush(); 732 agp_bridge->driver->tlb_flush(mem); 733 return 0; 734 } 735 736 static int intel_i915_fetch_size(void) 737 { 738 struct aper_size_info_fixed *values; 739 u32 temp, offset; 740 741 #define I915_256MB_ADDRESS_MASK (1<<27) 742 743 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 744 745 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 746 if (temp & I915_256MB_ADDRESS_MASK) 747 offset = 0; /* 128MB aperture */ 748 else 749 offset = 2; /* 256MB aperture */ 750 agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset); 751 return values[offset].size; 752 } 753 754 /* The intel i915 automatically initializes the agp aperture during POST. 755 * Use the memory already set aside for in the GTT. 756 */ 757 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 758 { 759 int page_order; 760 struct aper_size_info_fixed *size; 761 int num_entries; 762 u32 temp, temp2; 763 764 size = agp_bridge->current_size; 765 page_order = size->page_order; 766 num_entries = size->num_entries; 767 agp_bridge->gatt_table_real = NULL; 768 769 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); 770 pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2); 771 772 intel_i830_private.gtt = ioremap(temp2, 256 * 1024); 773 if (!intel_i830_private.gtt) 774 return -ENOMEM; 775 776 temp &= 0xfff80000; 777 778 intel_i830_private.registers = ioremap(temp,128 * 4096); 779 if (!intel_i830_private.registers) 780 return -ENOMEM; 781 782 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 783 global_cache_flush(); /* FIXME: ? */ 784 785 /* we have to call this as early as possible after the MMIO base address is known */ 786 intel_i830_init_gtt_entries(); 787 788 agp_bridge->gatt_table = NULL; 789 790 agp_bridge->gatt_bus_addr = temp; 791 792 return 0; 793 } 794 795 static int intel_fetch_size(void) 796 { 797 int i; 798 u16 temp; 799 struct aper_size_info_16 *values; 800 801 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 802 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 803 804 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 805 if (temp == values[i].size_value) { 806 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 807 agp_bridge->aperture_size_idx = i; 808 return values[i].size; 809 } 810 } 811 812 return 0; 813 } 814 815 static int __intel_8xx_fetch_size(u8 temp) 816 { 817 int i; 818 struct aper_size_info_8 *values; 819 820 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 821 822 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 823 if (temp == values[i].size_value) { 824 agp_bridge->previous_size = 825 agp_bridge->current_size = (void *) (values + i); 826 agp_bridge->aperture_size_idx = i; 827 return values[i].size; 828 } 829 } 830 return 0; 831 } 832 833 static int intel_8xx_fetch_size(void) 834 { 835 u8 temp; 836 837 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 838 return __intel_8xx_fetch_size(temp); 839 } 840 841 static int intel_815_fetch_size(void) 842 { 843 u8 temp; 844 845 /* Intel 815 chipsets have a _weird_ APSIZE register with only 846 * one non-reserved bit, so mask the others out ... */ 847 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 848 temp &= (1 << 3); 849 850 return __intel_8xx_fetch_size(temp); 851 } 852 853 static void intel_tlbflush(struct agp_memory *mem) 854 { 855 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 856 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 857 } 858 859 860 static void intel_8xx_tlbflush(struct agp_memory *mem) 861 { 862 u32 temp; 863 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 864 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 865 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 866 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 867 } 868 869 870 static void intel_cleanup(void) 871 { 872 u16 temp; 873 struct aper_size_info_16 *previous_size; 874 875 previous_size = A_SIZE_16(agp_bridge->previous_size); 876 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 877 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 878 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 879 } 880 881 882 static void intel_8xx_cleanup(void) 883 { 884 u16 temp; 885 struct aper_size_info_8 *previous_size; 886 887 previous_size = A_SIZE_8(agp_bridge->previous_size); 888 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 889 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 890 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 891 } 892 893 894 static int intel_configure(void) 895 { 896 u32 temp; 897 u16 temp2; 898 struct aper_size_info_16 *current_size; 899 900 current_size = A_SIZE_16(agp_bridge->current_size); 901 902 /* aperture size */ 903 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 904 905 /* address to map to */ 906 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 907 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 908 909 /* attbase - aperture base */ 910 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 911 912 /* agpctrl */ 913 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 914 915 /* paccfg/nbxcfg */ 916 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 917 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 918 (temp2 & ~(1 << 10)) | (1 << 9)); 919 /* clear any possible error conditions */ 920 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 921 return 0; 922 } 923 924 static int intel_815_configure(void) 925 { 926 u32 temp, addr; 927 u8 temp2; 928 struct aper_size_info_8 *current_size; 929 930 /* attbase - aperture base */ 931 /* the Intel 815 chipset spec. says that bits 29-31 in the 932 * ATTBASE register are reserved -> try not to write them */ 933 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 934 printk (KERN_EMERG PFX "gatt bus addr too high"); 935 return -EINVAL; 936 } 937 938 current_size = A_SIZE_8(agp_bridge->current_size); 939 940 /* aperture size */ 941 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 942 current_size->size_value); 943 944 /* address to map to */ 945 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 946 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 947 948 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 949 addr &= INTEL_815_ATTBASE_MASK; 950 addr |= agp_bridge->gatt_bus_addr; 951 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 952 953 /* agpctrl */ 954 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 955 956 /* apcont */ 957 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 958 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 959 960 /* clear any possible error conditions */ 961 /* Oddness : this chipset seems to have no ERRSTS register ! */ 962 return 0; 963 } 964 965 static void intel_820_tlbflush(struct agp_memory *mem) 966 { 967 return; 968 } 969 970 static void intel_820_cleanup(void) 971 { 972 u8 temp; 973 struct aper_size_info_8 *previous_size; 974 975 previous_size = A_SIZE_8(agp_bridge->previous_size); 976 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 977 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 978 temp & ~(1 << 1)); 979 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 980 previous_size->size_value); 981 } 982 983 984 static int intel_820_configure(void) 985 { 986 u32 temp; 987 u8 temp2; 988 struct aper_size_info_8 *current_size; 989 990 current_size = A_SIZE_8(agp_bridge->current_size); 991 992 /* aperture size */ 993 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 994 995 /* address to map to */ 996 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 997 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 998 999 /* attbase - aperture base */ 1000 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1001 1002 /* agpctrl */ 1003 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1004 1005 /* global enable aperture access */ 1006 /* This flag is not accessed through MCHCFG register as in */ 1007 /* i850 chipset. */ 1008 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1009 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1010 /* clear any possible AGP-related error conditions */ 1011 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1012 return 0; 1013 } 1014 1015 static int intel_840_configure(void) 1016 { 1017 u32 temp; 1018 u16 temp2; 1019 struct aper_size_info_8 *current_size; 1020 1021 current_size = A_SIZE_8(agp_bridge->current_size); 1022 1023 /* aperture size */ 1024 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1025 1026 /* address to map to */ 1027 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1028 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1029 1030 /* attbase - aperture base */ 1031 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1032 1033 /* agpctrl */ 1034 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1035 1036 /* mcgcfg */ 1037 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1038 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1039 /* clear any possible error conditions */ 1040 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1041 return 0; 1042 } 1043 1044 static int intel_845_configure(void) 1045 { 1046 u32 temp; 1047 u8 temp2; 1048 struct aper_size_info_8 *current_size; 1049 1050 current_size = A_SIZE_8(agp_bridge->current_size); 1051 1052 /* aperture size */ 1053 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1054 1055 if (agp_bridge->apbase_config != 0) { 1056 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1057 agp_bridge->apbase_config); 1058 } else { 1059 /* address to map to */ 1060 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1061 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1062 agp_bridge->apbase_config = temp; 1063 } 1064 1065 /* attbase - aperture base */ 1066 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1067 1068 /* agpctrl */ 1069 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1070 1071 /* agpm */ 1072 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1073 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1074 /* clear any possible error conditions */ 1075 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1076 return 0; 1077 } 1078 1079 static int intel_850_configure(void) 1080 { 1081 u32 temp; 1082 u16 temp2; 1083 struct aper_size_info_8 *current_size; 1084 1085 current_size = A_SIZE_8(agp_bridge->current_size); 1086 1087 /* aperture size */ 1088 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1089 1090 /* address to map to */ 1091 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1092 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1093 1094 /* attbase - aperture base */ 1095 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1096 1097 /* agpctrl */ 1098 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1099 1100 /* mcgcfg */ 1101 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1102 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1103 /* clear any possible AGP-related error conditions */ 1104 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1105 return 0; 1106 } 1107 1108 static int intel_860_configure(void) 1109 { 1110 u32 temp; 1111 u16 temp2; 1112 struct aper_size_info_8 *current_size; 1113 1114 current_size = A_SIZE_8(agp_bridge->current_size); 1115 1116 /* aperture size */ 1117 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1118 1119 /* address to map to */ 1120 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1121 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1122 1123 /* attbase - aperture base */ 1124 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1125 1126 /* agpctrl */ 1127 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1128 1129 /* mcgcfg */ 1130 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1131 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1132 /* clear any possible AGP-related error conditions */ 1133 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1134 return 0; 1135 } 1136 1137 static int intel_830mp_configure(void) 1138 { 1139 u32 temp; 1140 u16 temp2; 1141 struct aper_size_info_8 *current_size; 1142 1143 current_size = A_SIZE_8(agp_bridge->current_size); 1144 1145 /* aperture size */ 1146 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1147 1148 /* address to map to */ 1149 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1150 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1151 1152 /* attbase - aperture base */ 1153 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1154 1155 /* agpctrl */ 1156 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1157 1158 /* gmch */ 1159 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1160 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1161 /* clear any possible AGP-related error conditions */ 1162 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1163 return 0; 1164 } 1165 1166 static int intel_7505_configure(void) 1167 { 1168 u32 temp; 1169 u16 temp2; 1170 struct aper_size_info_8 *current_size; 1171 1172 current_size = A_SIZE_8(agp_bridge->current_size); 1173 1174 /* aperture size */ 1175 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1176 1177 /* address to map to */ 1178 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1179 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1180 1181 /* attbase - aperture base */ 1182 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1183 1184 /* agpctrl */ 1185 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1186 1187 /* mchcfg */ 1188 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1189 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1190 1191 return 0; 1192 } 1193 1194 /* Setup function */ 1195 static struct gatt_mask intel_generic_masks[] = 1196 { 1197 {.mask = 0x00000017, .type = 0} 1198 }; 1199 1200 static struct aper_size_info_8 intel_815_sizes[2] = 1201 { 1202 {64, 16384, 4, 0}, 1203 {32, 8192, 3, 8}, 1204 }; 1205 1206 static struct aper_size_info_8 intel_8xx_sizes[7] = 1207 { 1208 {256, 65536, 6, 0}, 1209 {128, 32768, 5, 32}, 1210 {64, 16384, 4, 48}, 1211 {32, 8192, 3, 56}, 1212 {16, 4096, 2, 60}, 1213 {8, 2048, 1, 62}, 1214 {4, 1024, 0, 63} 1215 }; 1216 1217 static struct aper_size_info_16 intel_generic_sizes[7] = 1218 { 1219 {256, 65536, 6, 0}, 1220 {128, 32768, 5, 32}, 1221 {64, 16384, 4, 48}, 1222 {32, 8192, 3, 56}, 1223 {16, 4096, 2, 60}, 1224 {8, 2048, 1, 62}, 1225 {4, 1024, 0, 63} 1226 }; 1227 1228 static struct aper_size_info_8 intel_830mp_sizes[4] = 1229 { 1230 {256, 65536, 6, 0}, 1231 {128, 32768, 5, 32}, 1232 {64, 16384, 4, 48}, 1233 {32, 8192, 3, 56} 1234 }; 1235 1236 static struct agp_bridge_driver intel_generic_driver = { 1237 .owner = THIS_MODULE, 1238 .aperture_sizes = intel_generic_sizes, 1239 .size_type = U16_APER_SIZE, 1240 .num_aperture_sizes = 7, 1241 .configure = intel_configure, 1242 .fetch_size = intel_fetch_size, 1243 .cleanup = intel_cleanup, 1244 .tlb_flush = intel_tlbflush, 1245 .mask_memory = agp_generic_mask_memory, 1246 .masks = intel_generic_masks, 1247 .agp_enable = agp_generic_enable, 1248 .cache_flush = global_cache_flush, 1249 .create_gatt_table = agp_generic_create_gatt_table, 1250 .free_gatt_table = agp_generic_free_gatt_table, 1251 .insert_memory = agp_generic_insert_memory, 1252 .remove_memory = agp_generic_remove_memory, 1253 .alloc_by_type = agp_generic_alloc_by_type, 1254 .free_by_type = agp_generic_free_by_type, 1255 .agp_alloc_page = agp_generic_alloc_page, 1256 .agp_destroy_page = agp_generic_destroy_page, 1257 }; 1258 1259 static struct agp_bridge_driver intel_810_driver = { 1260 .owner = THIS_MODULE, 1261 .aperture_sizes = intel_i810_sizes, 1262 .size_type = FIXED_APER_SIZE, 1263 .num_aperture_sizes = 2, 1264 .needs_scratch_page = TRUE, 1265 .configure = intel_i810_configure, 1266 .fetch_size = intel_i810_fetch_size, 1267 .cleanup = intel_i810_cleanup, 1268 .tlb_flush = intel_i810_tlbflush, 1269 .mask_memory = intel_i810_mask_memory, 1270 .masks = intel_i810_masks, 1271 .agp_enable = intel_i810_agp_enable, 1272 .cache_flush = global_cache_flush, 1273 .create_gatt_table = agp_generic_create_gatt_table, 1274 .free_gatt_table = agp_generic_free_gatt_table, 1275 .insert_memory = intel_i810_insert_entries, 1276 .remove_memory = intel_i810_remove_entries, 1277 .alloc_by_type = intel_i810_alloc_by_type, 1278 .free_by_type = intel_i810_free_by_type, 1279 .agp_alloc_page = agp_generic_alloc_page, 1280 .agp_destroy_page = agp_generic_destroy_page, 1281 }; 1282 1283 static struct agp_bridge_driver intel_815_driver = { 1284 .owner = THIS_MODULE, 1285 .aperture_sizes = intel_815_sizes, 1286 .size_type = U8_APER_SIZE, 1287 .num_aperture_sizes = 2, 1288 .configure = intel_815_configure, 1289 .fetch_size = intel_815_fetch_size, 1290 .cleanup = intel_8xx_cleanup, 1291 .tlb_flush = intel_8xx_tlbflush, 1292 .mask_memory = agp_generic_mask_memory, 1293 .masks = intel_generic_masks, 1294 .agp_enable = agp_generic_enable, 1295 .cache_flush = global_cache_flush, 1296 .create_gatt_table = agp_generic_create_gatt_table, 1297 .free_gatt_table = agp_generic_free_gatt_table, 1298 .insert_memory = agp_generic_insert_memory, 1299 .remove_memory = agp_generic_remove_memory, 1300 .alloc_by_type = agp_generic_alloc_by_type, 1301 .free_by_type = agp_generic_free_by_type, 1302 .agp_alloc_page = agp_generic_alloc_page, 1303 .agp_destroy_page = agp_generic_destroy_page, 1304 }; 1305 1306 static struct agp_bridge_driver intel_830_driver = { 1307 .owner = THIS_MODULE, 1308 .aperture_sizes = intel_i830_sizes, 1309 .size_type = FIXED_APER_SIZE, 1310 .num_aperture_sizes = 3, 1311 .needs_scratch_page = TRUE, 1312 .configure = intel_i830_configure, 1313 .fetch_size = intel_i830_fetch_size, 1314 .cleanup = intel_i830_cleanup, 1315 .tlb_flush = intel_i810_tlbflush, 1316 .mask_memory = intel_i810_mask_memory, 1317 .masks = intel_i810_masks, 1318 .agp_enable = intel_i810_agp_enable, 1319 .cache_flush = global_cache_flush, 1320 .create_gatt_table = intel_i830_create_gatt_table, 1321 .free_gatt_table = intel_i830_free_gatt_table, 1322 .insert_memory = intel_i830_insert_entries, 1323 .remove_memory = intel_i830_remove_entries, 1324 .alloc_by_type = intel_i830_alloc_by_type, 1325 .free_by_type = intel_i810_free_by_type, 1326 .agp_alloc_page = agp_generic_alloc_page, 1327 .agp_destroy_page = agp_generic_destroy_page, 1328 }; 1329 1330 static struct agp_bridge_driver intel_820_driver = { 1331 .owner = THIS_MODULE, 1332 .aperture_sizes = intel_8xx_sizes, 1333 .size_type = U8_APER_SIZE, 1334 .num_aperture_sizes = 7, 1335 .configure = intel_820_configure, 1336 .fetch_size = intel_8xx_fetch_size, 1337 .cleanup = intel_820_cleanup, 1338 .tlb_flush = intel_820_tlbflush, 1339 .mask_memory = agp_generic_mask_memory, 1340 .masks = intel_generic_masks, 1341 .agp_enable = agp_generic_enable, 1342 .cache_flush = global_cache_flush, 1343 .create_gatt_table = agp_generic_create_gatt_table, 1344 .free_gatt_table = agp_generic_free_gatt_table, 1345 .insert_memory = agp_generic_insert_memory, 1346 .remove_memory = agp_generic_remove_memory, 1347 .alloc_by_type = agp_generic_alloc_by_type, 1348 .free_by_type = agp_generic_free_by_type, 1349 .agp_alloc_page = agp_generic_alloc_page, 1350 .agp_destroy_page = agp_generic_destroy_page, 1351 }; 1352 1353 static struct agp_bridge_driver intel_830mp_driver = { 1354 .owner = THIS_MODULE, 1355 .aperture_sizes = intel_830mp_sizes, 1356 .size_type = U8_APER_SIZE, 1357 .num_aperture_sizes = 4, 1358 .configure = intel_830mp_configure, 1359 .fetch_size = intel_8xx_fetch_size, 1360 .cleanup = intel_8xx_cleanup, 1361 .tlb_flush = intel_8xx_tlbflush, 1362 .mask_memory = agp_generic_mask_memory, 1363 .masks = intel_generic_masks, 1364 .agp_enable = agp_generic_enable, 1365 .cache_flush = global_cache_flush, 1366 .create_gatt_table = agp_generic_create_gatt_table, 1367 .free_gatt_table = agp_generic_free_gatt_table, 1368 .insert_memory = agp_generic_insert_memory, 1369 .remove_memory = agp_generic_remove_memory, 1370 .alloc_by_type = agp_generic_alloc_by_type, 1371 .free_by_type = agp_generic_free_by_type, 1372 .agp_alloc_page = agp_generic_alloc_page, 1373 .agp_destroy_page = agp_generic_destroy_page, 1374 }; 1375 1376 static struct agp_bridge_driver intel_840_driver = { 1377 .owner = THIS_MODULE, 1378 .aperture_sizes = intel_8xx_sizes, 1379 .size_type = U8_APER_SIZE, 1380 .num_aperture_sizes = 7, 1381 .configure = intel_840_configure, 1382 .fetch_size = intel_8xx_fetch_size, 1383 .cleanup = intel_8xx_cleanup, 1384 .tlb_flush = intel_8xx_tlbflush, 1385 .mask_memory = agp_generic_mask_memory, 1386 .masks = intel_generic_masks, 1387 .agp_enable = agp_generic_enable, 1388 .cache_flush = global_cache_flush, 1389 .create_gatt_table = agp_generic_create_gatt_table, 1390 .free_gatt_table = agp_generic_free_gatt_table, 1391 .insert_memory = agp_generic_insert_memory, 1392 .remove_memory = agp_generic_remove_memory, 1393 .alloc_by_type = agp_generic_alloc_by_type, 1394 .free_by_type = agp_generic_free_by_type, 1395 .agp_alloc_page = agp_generic_alloc_page, 1396 .agp_destroy_page = agp_generic_destroy_page, 1397 }; 1398 1399 static struct agp_bridge_driver intel_845_driver = { 1400 .owner = THIS_MODULE, 1401 .aperture_sizes = intel_8xx_sizes, 1402 .size_type = U8_APER_SIZE, 1403 .num_aperture_sizes = 7, 1404 .configure = intel_845_configure, 1405 .fetch_size = intel_8xx_fetch_size, 1406 .cleanup = intel_8xx_cleanup, 1407 .tlb_flush = intel_8xx_tlbflush, 1408 .mask_memory = agp_generic_mask_memory, 1409 .masks = intel_generic_masks, 1410 .agp_enable = agp_generic_enable, 1411 .cache_flush = global_cache_flush, 1412 .create_gatt_table = agp_generic_create_gatt_table, 1413 .free_gatt_table = agp_generic_free_gatt_table, 1414 .insert_memory = agp_generic_insert_memory, 1415 .remove_memory = agp_generic_remove_memory, 1416 .alloc_by_type = agp_generic_alloc_by_type, 1417 .free_by_type = agp_generic_free_by_type, 1418 .agp_alloc_page = agp_generic_alloc_page, 1419 .agp_destroy_page = agp_generic_destroy_page, 1420 }; 1421 1422 static struct agp_bridge_driver intel_850_driver = { 1423 .owner = THIS_MODULE, 1424 .aperture_sizes = intel_8xx_sizes, 1425 .size_type = U8_APER_SIZE, 1426 .num_aperture_sizes = 7, 1427 .configure = intel_850_configure, 1428 .fetch_size = intel_8xx_fetch_size, 1429 .cleanup = intel_8xx_cleanup, 1430 .tlb_flush = intel_8xx_tlbflush, 1431 .mask_memory = agp_generic_mask_memory, 1432 .masks = intel_generic_masks, 1433 .agp_enable = agp_generic_enable, 1434 .cache_flush = global_cache_flush, 1435 .create_gatt_table = agp_generic_create_gatt_table, 1436 .free_gatt_table = agp_generic_free_gatt_table, 1437 .insert_memory = agp_generic_insert_memory, 1438 .remove_memory = agp_generic_remove_memory, 1439 .alloc_by_type = agp_generic_alloc_by_type, 1440 .free_by_type = agp_generic_free_by_type, 1441 .agp_alloc_page = agp_generic_alloc_page, 1442 .agp_destroy_page = agp_generic_destroy_page, 1443 }; 1444 1445 static struct agp_bridge_driver intel_860_driver = { 1446 .owner = THIS_MODULE, 1447 .aperture_sizes = intel_8xx_sizes, 1448 .size_type = U8_APER_SIZE, 1449 .num_aperture_sizes = 7, 1450 .configure = intel_860_configure, 1451 .fetch_size = intel_8xx_fetch_size, 1452 .cleanup = intel_8xx_cleanup, 1453 .tlb_flush = intel_8xx_tlbflush, 1454 .mask_memory = agp_generic_mask_memory, 1455 .masks = intel_generic_masks, 1456 .agp_enable = agp_generic_enable, 1457 .cache_flush = global_cache_flush, 1458 .create_gatt_table = agp_generic_create_gatt_table, 1459 .free_gatt_table = agp_generic_free_gatt_table, 1460 .insert_memory = agp_generic_insert_memory, 1461 .remove_memory = agp_generic_remove_memory, 1462 .alloc_by_type = agp_generic_alloc_by_type, 1463 .free_by_type = agp_generic_free_by_type, 1464 .agp_alloc_page = agp_generic_alloc_page, 1465 .agp_destroy_page = agp_generic_destroy_page, 1466 }; 1467 1468 static struct agp_bridge_driver intel_915_driver = { 1469 .owner = THIS_MODULE, 1470 .aperture_sizes = intel_i830_sizes, 1471 .size_type = FIXED_APER_SIZE, 1472 .num_aperture_sizes = 3, 1473 .needs_scratch_page = TRUE, 1474 .configure = intel_i915_configure, 1475 .fetch_size = intel_i915_fetch_size, 1476 .cleanup = intel_i915_cleanup, 1477 .tlb_flush = intel_i810_tlbflush, 1478 .mask_memory = intel_i810_mask_memory, 1479 .masks = intel_i810_masks, 1480 .agp_enable = intel_i810_agp_enable, 1481 .cache_flush = global_cache_flush, 1482 .create_gatt_table = intel_i915_create_gatt_table, 1483 .free_gatt_table = intel_i830_free_gatt_table, 1484 .insert_memory = intel_i915_insert_entries, 1485 .remove_memory = intel_i915_remove_entries, 1486 .alloc_by_type = intel_i830_alloc_by_type, 1487 .free_by_type = intel_i810_free_by_type, 1488 .agp_alloc_page = agp_generic_alloc_page, 1489 .agp_destroy_page = agp_generic_destroy_page, 1490 }; 1491 1492 1493 static struct agp_bridge_driver intel_7505_driver = { 1494 .owner = THIS_MODULE, 1495 .aperture_sizes = intel_8xx_sizes, 1496 .size_type = U8_APER_SIZE, 1497 .num_aperture_sizes = 7, 1498 .configure = intel_7505_configure, 1499 .fetch_size = intel_8xx_fetch_size, 1500 .cleanup = intel_8xx_cleanup, 1501 .tlb_flush = intel_8xx_tlbflush, 1502 .mask_memory = agp_generic_mask_memory, 1503 .masks = intel_generic_masks, 1504 .agp_enable = agp_generic_enable, 1505 .cache_flush = global_cache_flush, 1506 .create_gatt_table = agp_generic_create_gatt_table, 1507 .free_gatt_table = agp_generic_free_gatt_table, 1508 .insert_memory = agp_generic_insert_memory, 1509 .remove_memory = agp_generic_remove_memory, 1510 .alloc_by_type = agp_generic_alloc_by_type, 1511 .free_by_type = agp_generic_free_by_type, 1512 .agp_alloc_page = agp_generic_alloc_page, 1513 .agp_destroy_page = agp_generic_destroy_page, 1514 }; 1515 1516 static int find_i810(u16 device) 1517 { 1518 struct pci_dev *i810_dev; 1519 1520 i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1521 if (!i810_dev) 1522 return 0; 1523 intel_i810_private.i810_dev = i810_dev; 1524 return 1; 1525 } 1526 1527 static int find_i830(u16 device) 1528 { 1529 struct pci_dev *i830_dev; 1530 1531 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1532 if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) { 1533 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 1534 device, i830_dev); 1535 } 1536 1537 if (!i830_dev) 1538 return 0; 1539 1540 intel_i830_private.i830_dev = i830_dev; 1541 return 1; 1542 } 1543 1544 static int __devinit agp_intel_probe(struct pci_dev *pdev, 1545 const struct pci_device_id *ent) 1546 { 1547 struct agp_bridge_data *bridge; 1548 char *name = "(unknown)"; 1549 u8 cap_ptr = 0; 1550 struct resource *r; 1551 1552 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 1553 1554 bridge = agp_alloc_bridge(); 1555 if (!bridge) 1556 return -ENOMEM; 1557 1558 switch (pdev->device) { 1559 case PCI_DEVICE_ID_INTEL_82443LX_0: 1560 bridge->driver = &intel_generic_driver; 1561 name = "440LX"; 1562 break; 1563 case PCI_DEVICE_ID_INTEL_82443BX_0: 1564 bridge->driver = &intel_generic_driver; 1565 name = "440BX"; 1566 break; 1567 case PCI_DEVICE_ID_INTEL_82443GX_0: 1568 bridge->driver = &intel_generic_driver; 1569 name = "440GX"; 1570 break; 1571 case PCI_DEVICE_ID_INTEL_82810_MC1: 1572 name = "i810"; 1573 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1)) 1574 goto fail; 1575 bridge->driver = &intel_810_driver; 1576 break; 1577 case PCI_DEVICE_ID_INTEL_82810_MC3: 1578 name = "i810 DC100"; 1579 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3)) 1580 goto fail; 1581 bridge->driver = &intel_810_driver; 1582 break; 1583 case PCI_DEVICE_ID_INTEL_82810E_MC: 1584 name = "i810 E"; 1585 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG)) 1586 goto fail; 1587 bridge->driver = &intel_810_driver; 1588 break; 1589 case PCI_DEVICE_ID_INTEL_82815_MC: 1590 /* 1591 * The i815 can operate either as an i810 style 1592 * integrated device, or as an AGP4X motherboard. 1593 */ 1594 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC)) 1595 bridge->driver = &intel_810_driver; 1596 else 1597 bridge->driver = &intel_815_driver; 1598 name = "i815"; 1599 break; 1600 case PCI_DEVICE_ID_INTEL_82820_HB: 1601 case PCI_DEVICE_ID_INTEL_82820_UP_HB: 1602 bridge->driver = &intel_820_driver; 1603 name = "i820"; 1604 break; 1605 case PCI_DEVICE_ID_INTEL_82830_HB: 1606 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) 1607 bridge->driver = &intel_830_driver; 1608 else 1609 bridge->driver = &intel_830mp_driver; 1610 name = "830M"; 1611 break; 1612 case PCI_DEVICE_ID_INTEL_82840_HB: 1613 bridge->driver = &intel_840_driver; 1614 name = "i840"; 1615 break; 1616 case PCI_DEVICE_ID_INTEL_82845_HB: 1617 bridge->driver = &intel_845_driver; 1618 name = "i845"; 1619 break; 1620 case PCI_DEVICE_ID_INTEL_82845G_HB: 1621 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) 1622 bridge->driver = &intel_830_driver; 1623 else 1624 bridge->driver = &intel_845_driver; 1625 name = "845G"; 1626 break; 1627 case PCI_DEVICE_ID_INTEL_82850_HB: 1628 bridge->driver = &intel_850_driver; 1629 name = "i850"; 1630 break; 1631 case PCI_DEVICE_ID_INTEL_82855PM_HB: 1632 bridge->driver = &intel_845_driver; 1633 name = "855PM"; 1634 break; 1635 case PCI_DEVICE_ID_INTEL_82855GM_HB: 1636 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) { 1637 bridge->driver = &intel_830_driver; 1638 name = "855"; 1639 } else { 1640 bridge->driver = &intel_845_driver; 1641 name = "855GM"; 1642 } 1643 break; 1644 case PCI_DEVICE_ID_INTEL_82860_HB: 1645 bridge->driver = &intel_860_driver; 1646 name = "i860"; 1647 break; 1648 case PCI_DEVICE_ID_INTEL_82865_HB: 1649 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) 1650 bridge->driver = &intel_830_driver; 1651 else 1652 bridge->driver = &intel_845_driver; 1653 name = "865"; 1654 break; 1655 case PCI_DEVICE_ID_INTEL_82875_HB: 1656 bridge->driver = &intel_845_driver; 1657 name = "i875"; 1658 break; 1659 case PCI_DEVICE_ID_INTEL_82915G_HB: 1660 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) 1661 bridge->driver = &intel_915_driver; 1662 else 1663 bridge->driver = &intel_845_driver; 1664 name = "915G"; 1665 break; 1666 case PCI_DEVICE_ID_INTEL_82915GM_HB: 1667 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) 1668 bridge->driver = &intel_915_driver; 1669 else 1670 bridge->driver = &intel_845_driver; 1671 name = "915GM"; 1672 break; 1673 case PCI_DEVICE_ID_INTEL_82945G_HB: 1674 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG)) 1675 bridge->driver = &intel_915_driver; 1676 else 1677 bridge->driver = &intel_845_driver; 1678 name = "945G"; 1679 break; 1680 case PCI_DEVICE_ID_INTEL_82945GM_HB: 1681 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG)) 1682 bridge->driver = &intel_915_driver; 1683 else 1684 bridge->driver = &intel_845_driver; 1685 name = "945GM"; 1686 break; 1687 case PCI_DEVICE_ID_INTEL_7505_0: 1688 bridge->driver = &intel_7505_driver; 1689 name = "E7505"; 1690 break; 1691 case PCI_DEVICE_ID_INTEL_7205_0: 1692 bridge->driver = &intel_7505_driver; 1693 name = "E7205"; 1694 break; 1695 default: 1696 if (cap_ptr) 1697 printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n", 1698 pdev->device); 1699 agp_put_bridge(bridge); 1700 return -ENODEV; 1701 }; 1702 1703 bridge->dev = pdev; 1704 bridge->capndx = cap_ptr; 1705 1706 if (bridge->driver == &intel_810_driver) 1707 bridge->dev_private_data = &intel_i810_private; 1708 else if (bridge->driver == &intel_830_driver) 1709 bridge->dev_private_data = &intel_i830_private; 1710 1711 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); 1712 1713 /* 1714 * The following fixes the case where the BIOS has "forgotten" to 1715 * provide an address range for the GART. 1716 * 20030610 - hamish@zot.org 1717 */ 1718 r = &pdev->resource[0]; 1719 if (!r->start && r->end) { 1720 if (pci_assign_resource(pdev, 0)) { 1721 printk(KERN_ERR PFX "could not assign resource 0\n"); 1722 agp_put_bridge(bridge); 1723 return -ENODEV; 1724 } 1725 } 1726 1727 /* 1728 * If the device has not been properly setup, the following will catch 1729 * the problem and should stop the system from crashing. 1730 * 20030610 - hamish@zot.org 1731 */ 1732 if (pci_enable_device(pdev)) { 1733 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 1734 agp_put_bridge(bridge); 1735 return -ENODEV; 1736 } 1737 1738 /* Fill in the mode register */ 1739 if (cap_ptr) { 1740 pci_read_config_dword(pdev, 1741 bridge->capndx+PCI_AGP_STATUS, 1742 &bridge->mode); 1743 } 1744 1745 pci_set_drvdata(pdev, bridge); 1746 return agp_add_bridge(bridge); 1747 1748 fail: 1749 printk(KERN_ERR PFX "Detected an Intel %s chipset, " 1750 "but could not find the secondary device.\n", name); 1751 agp_put_bridge(bridge); 1752 return -ENODEV; 1753 } 1754 1755 static void __devexit agp_intel_remove(struct pci_dev *pdev) 1756 { 1757 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1758 1759 agp_remove_bridge(bridge); 1760 1761 if (intel_i810_private.i810_dev) 1762 pci_dev_put(intel_i810_private.i810_dev); 1763 if (intel_i830_private.i830_dev) 1764 pci_dev_put(intel_i830_private.i830_dev); 1765 1766 agp_put_bridge(bridge); 1767 } 1768 1769 static int agp_intel_resume(struct pci_dev *pdev) 1770 { 1771 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1772 1773 pci_restore_state(pdev); 1774 1775 if (bridge->driver == &intel_generic_driver) 1776 intel_configure(); 1777 else if (bridge->driver == &intel_850_driver) 1778 intel_850_configure(); 1779 else if (bridge->driver == &intel_845_driver) 1780 intel_845_configure(); 1781 else if (bridge->driver == &intel_830mp_driver) 1782 intel_830mp_configure(); 1783 else if (bridge->driver == &intel_915_driver) 1784 intel_i915_configure(); 1785 else if (bridge->driver == &intel_830_driver) 1786 intel_i830_configure(); 1787 else if (bridge->driver == &intel_810_driver) 1788 intel_i810_configure(); 1789 1790 return 0; 1791 } 1792 1793 static struct pci_device_id agp_intel_pci_table[] = { 1794 #define ID(x) \ 1795 { \ 1796 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 1797 .class_mask = ~0, \ 1798 .vendor = PCI_VENDOR_ID_INTEL, \ 1799 .device = x, \ 1800 .subvendor = PCI_ANY_ID, \ 1801 .subdevice = PCI_ANY_ID, \ 1802 } 1803 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 1804 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 1805 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 1806 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 1807 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 1808 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 1809 ID(PCI_DEVICE_ID_INTEL_82815_MC), 1810 ID(PCI_DEVICE_ID_INTEL_82820_HB), 1811 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 1812 ID(PCI_DEVICE_ID_INTEL_82830_HB), 1813 ID(PCI_DEVICE_ID_INTEL_82840_HB), 1814 ID(PCI_DEVICE_ID_INTEL_82845_HB), 1815 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 1816 ID(PCI_DEVICE_ID_INTEL_82850_HB), 1817 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 1818 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 1819 ID(PCI_DEVICE_ID_INTEL_82860_HB), 1820 ID(PCI_DEVICE_ID_INTEL_82865_HB), 1821 ID(PCI_DEVICE_ID_INTEL_82875_HB), 1822 ID(PCI_DEVICE_ID_INTEL_7505_0), 1823 ID(PCI_DEVICE_ID_INTEL_7205_0), 1824 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 1825 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 1826 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 1827 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 1828 { } 1829 }; 1830 1831 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 1832 1833 static struct pci_driver agp_intel_pci_driver = { 1834 .name = "agpgart-intel", 1835 .id_table = agp_intel_pci_table, 1836 .probe = agp_intel_probe, 1837 .remove = __devexit_p(agp_intel_remove), 1838 .resume = agp_intel_resume, 1839 }; 1840 1841 static int __init agp_intel_init(void) 1842 { 1843 if (agp_off) 1844 return -EINVAL; 1845 return pci_register_driver(&agp_intel_pci_driver); 1846 } 1847 1848 static void __exit agp_intel_cleanup(void) 1849 { 1850 pci_unregister_driver(&agp_intel_pci_driver); 1851 } 1852 1853 module_init(agp_intel_init); 1854 module_exit(agp_intel_cleanup); 1855 1856 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 1857 MODULE_LICENSE("GPL and additional rights"); 1858