1 /* 2 * Intel AGPGART routines. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/init.h> 8 #include <linux/kernel.h> 9 #include <linux/pagemap.h> 10 #include <linux/agp_backend.h> 11 #include "agp.h" 12 13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970 14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972 15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB 0x2980 16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG 0x2982 17 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990 18 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992 19 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0 20 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2 21 22 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \ 23 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \ 24 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \ 25 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB) 26 27 28 extern int agp_memory_reserved; 29 30 31 /* Intel 815 register */ 32 #define INTEL_815_APCONT 0x51 33 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF 34 35 /* Intel i820 registers */ 36 #define INTEL_I820_RDCR 0x51 37 #define INTEL_I820_ERRSTS 0xc8 38 39 /* Intel i840 registers */ 40 #define INTEL_I840_MCHCFG 0x50 41 #define INTEL_I840_ERRSTS 0xc8 42 43 /* Intel i850 registers */ 44 #define INTEL_I850_MCHCFG 0x50 45 #define INTEL_I850_ERRSTS 0xc8 46 47 /* intel 915G registers */ 48 #define I915_GMADDR 0x18 49 #define I915_MMADDR 0x10 50 #define I915_PTEADDR 0x1C 51 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) 52 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) 53 54 /* Intel 965G registers */ 55 #define I965_MSAC 0x62 56 57 /* Intel 7505 registers */ 58 #define INTEL_I7505_APSIZE 0x74 59 #define INTEL_I7505_NCAPID 0x60 60 #define INTEL_I7505_NISTAT 0x6c 61 #define INTEL_I7505_ATTBASE 0x78 62 #define INTEL_I7505_ERRSTS 0x42 63 #define INTEL_I7505_AGPCTRL 0x70 64 #define INTEL_I7505_MCHCFG 0x50 65 66 static const struct aper_size_info_fixed intel_i810_sizes[] = 67 { 68 {64, 16384, 4}, 69 /* The 32M mode still requires a 64k gatt */ 70 {32, 8192, 4} 71 }; 72 73 #define AGP_DCACHE_MEMORY 1 74 #define AGP_PHYS_MEMORY 2 75 #define INTEL_AGP_CACHED_MEMORY 3 76 77 static struct gatt_mask intel_i810_masks[] = 78 { 79 {.mask = I810_PTE_VALID, .type = 0}, 80 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY}, 81 {.mask = I810_PTE_VALID, .type = 0}, 82 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED, 83 .type = INTEL_AGP_CACHED_MEMORY} 84 }; 85 86 static struct _intel_i810_private { 87 struct pci_dev *i810_dev; /* device one */ 88 volatile u8 __iomem *registers; 89 int num_dcache_entries; 90 } intel_i810_private; 91 92 static int intel_i810_fetch_size(void) 93 { 94 u32 smram_miscc; 95 struct aper_size_info_fixed *values; 96 97 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc); 98 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 99 100 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) { 101 printk(KERN_WARNING PFX "i810 is disabled\n"); 102 return 0; 103 } 104 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) { 105 agp_bridge->previous_size = 106 agp_bridge->current_size = (void *) (values + 1); 107 agp_bridge->aperture_size_idx = 1; 108 return values[1].size; 109 } else { 110 agp_bridge->previous_size = 111 agp_bridge->current_size = (void *) (values); 112 agp_bridge->aperture_size_idx = 0; 113 return values[0].size; 114 } 115 116 return 0; 117 } 118 119 static int intel_i810_configure(void) 120 { 121 struct aper_size_info_fixed *current_size; 122 u32 temp; 123 int i; 124 125 current_size = A_SIZE_FIX(agp_bridge->current_size); 126 127 if (!intel_i810_private.registers) { 128 pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp); 129 temp &= 0xfff80000; 130 131 intel_i810_private.registers = ioremap(temp, 128 * 4096); 132 if (!intel_i810_private.registers) { 133 printk(KERN_ERR PFX "Unable to remap memory.\n"); 134 return -ENOMEM; 135 } 136 } 137 138 if ((readl(intel_i810_private.registers+I810_DRAM_CTL) 139 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { 140 /* This will need to be dynamically assigned */ 141 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n"); 142 intel_i810_private.num_dcache_entries = 1024; 143 } 144 pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp); 145 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 146 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL); 147 readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 148 149 if (agp_bridge->driver->needs_scratch_page) { 150 for (i = 0; i < current_size->num_entries; i++) { 151 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 152 readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */ 153 } 154 } 155 global_cache_flush(); 156 return 0; 157 } 158 159 static void intel_i810_cleanup(void) 160 { 161 writel(0, intel_i810_private.registers+I810_PGETBL_CTL); 162 readl(intel_i810_private.registers); /* PCI Posting. */ 163 iounmap(intel_i810_private.registers); 164 } 165 166 static void intel_i810_tlbflush(struct agp_memory *mem) 167 { 168 return; 169 } 170 171 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode) 172 { 173 return; 174 } 175 176 /* Exists to support ARGB cursors */ 177 static void *i8xx_alloc_pages(void) 178 { 179 struct page * page; 180 181 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); 182 if (page == NULL) 183 return NULL; 184 185 if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) { 186 global_flush_tlb(); 187 __free_page(page); 188 return NULL; 189 } 190 global_flush_tlb(); 191 get_page(page); 192 SetPageLocked(page); 193 atomic_inc(&agp_bridge->current_memory_agp); 194 return page_address(page); 195 } 196 197 static void i8xx_destroy_pages(void *addr) 198 { 199 struct page *page; 200 201 if (addr == NULL) 202 return; 203 204 page = virt_to_page(addr); 205 change_page_attr(page, 4, PAGE_KERNEL); 206 global_flush_tlb(); 207 put_page(page); 208 unlock_page(page); 209 free_pages((unsigned long)addr, 2); 210 atomic_dec(&agp_bridge->current_memory_agp); 211 } 212 213 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge, 214 int type) 215 { 216 if (type < AGP_USER_TYPES) 217 return type; 218 else if (type == AGP_USER_CACHED_MEMORY) 219 return INTEL_AGP_CACHED_MEMORY; 220 else 221 return 0; 222 } 223 224 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start, 225 int type) 226 { 227 int i, j, num_entries; 228 void *temp; 229 int ret = -EINVAL; 230 int mask_type; 231 232 if (mem->page_count == 0) 233 goto out; 234 235 temp = agp_bridge->current_size; 236 num_entries = A_SIZE_FIX(temp)->num_entries; 237 238 if ((pg_start + mem->page_count) > num_entries) 239 goto out_err; 240 241 242 for (j = pg_start; j < (pg_start + mem->page_count); j++) { 243 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) { 244 ret = -EBUSY; 245 goto out_err; 246 } 247 } 248 249 if (type != mem->type) 250 goto out_err; 251 252 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 253 254 switch (mask_type) { 255 case AGP_DCACHE_MEMORY: 256 if (!mem->is_flushed) 257 global_cache_flush(); 258 for (i = pg_start; i < (pg_start + mem->page_count); i++) { 259 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID, 260 intel_i810_private.registers+I810_PTE_BASE+(i*4)); 261 } 262 readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4)); 263 break; 264 case AGP_PHYS_MEMORY: 265 case AGP_NORMAL_MEMORY: 266 if (!mem->is_flushed) 267 global_cache_flush(); 268 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 269 writel(agp_bridge->driver->mask_memory(agp_bridge, 270 mem->memory[i], 271 mask_type), 272 intel_i810_private.registers+I810_PTE_BASE+(j*4)); 273 } 274 readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4)); 275 break; 276 default: 277 goto out_err; 278 } 279 280 agp_bridge->driver->tlb_flush(mem); 281 out: 282 ret = 0; 283 out_err: 284 mem->is_flushed = 1; 285 return ret; 286 } 287 288 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start, 289 int type) 290 { 291 int i; 292 293 if (mem->page_count == 0) 294 return 0; 295 296 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 297 writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4)); 298 } 299 readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4)); 300 301 agp_bridge->driver->tlb_flush(mem); 302 return 0; 303 } 304 305 /* 306 * The i810/i830 requires a physical address to program its mouse 307 * pointer into hardware. 308 * However the Xserver still writes to it through the agp aperture. 309 */ 310 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) 311 { 312 struct agp_memory *new; 313 void *addr; 314 315 if (pg_count != 1 && pg_count != 4) 316 return NULL; 317 318 switch (pg_count) { 319 case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge); 320 global_flush_tlb(); 321 break; 322 case 4: 323 /* kludge to get 4 physical pages for ARGB cursor */ 324 addr = i8xx_alloc_pages(); 325 break; 326 default: 327 return NULL; 328 } 329 330 if (addr == NULL) 331 return NULL; 332 333 new = agp_create_memory(pg_count); 334 if (new == NULL) 335 return NULL; 336 337 new->memory[0] = virt_to_gart(addr); 338 if (pg_count == 4) { 339 /* kludge to get 4 physical pages for ARGB cursor */ 340 new->memory[1] = new->memory[0] + PAGE_SIZE; 341 new->memory[2] = new->memory[1] + PAGE_SIZE; 342 new->memory[3] = new->memory[2] + PAGE_SIZE; 343 } 344 new->page_count = pg_count; 345 new->num_scratch_pages = pg_count; 346 new->type = AGP_PHYS_MEMORY; 347 new->physical = new->memory[0]; 348 return new; 349 } 350 351 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type) 352 { 353 struct agp_memory *new; 354 355 if (type == AGP_DCACHE_MEMORY) { 356 if (pg_count != intel_i810_private.num_dcache_entries) 357 return NULL; 358 359 new = agp_create_memory(1); 360 if (new == NULL) 361 return NULL; 362 363 new->type = AGP_DCACHE_MEMORY; 364 new->page_count = pg_count; 365 new->num_scratch_pages = 0; 366 agp_free_page_array(new); 367 return new; 368 } 369 if (type == AGP_PHYS_MEMORY) 370 return alloc_agpphysmem_i8xx(pg_count, type); 371 return NULL; 372 } 373 374 static void intel_i810_free_by_type(struct agp_memory *curr) 375 { 376 agp_free_key(curr->key); 377 if (curr->type == AGP_PHYS_MEMORY) { 378 if (curr->page_count == 4) 379 i8xx_destroy_pages(gart_to_virt(curr->memory[0])); 380 else { 381 agp_bridge->driver->agp_destroy_page( 382 gart_to_virt(curr->memory[0])); 383 global_flush_tlb(); 384 } 385 agp_free_page_array(curr); 386 } 387 kfree(curr); 388 } 389 390 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge, 391 unsigned long addr, int type) 392 { 393 /* Type checking must be done elsewhere */ 394 return addr | bridge->driver->masks[type].mask; 395 } 396 397 static struct aper_size_info_fixed intel_i830_sizes[] = 398 { 399 {128, 32768, 5}, 400 /* The 64M mode still requires a 128k gatt */ 401 {64, 16384, 5}, 402 {256, 65536, 6}, 403 {512, 131072, 7}, 404 }; 405 406 static struct _intel_i830_private { 407 struct pci_dev *i830_dev; /* device one */ 408 volatile u8 __iomem *registers; 409 volatile u32 __iomem *gtt; /* I915G */ 410 /* gtt_entries is the number of gtt entries that are already mapped 411 * to stolen memory. Stolen memory is larger than the memory mapped 412 * through gtt_entries, as it includes some reserved space for the BIOS 413 * popup and for the GTT. 414 */ 415 int gtt_entries; 416 } intel_i830_private; 417 418 static void intel_i830_init_gtt_entries(void) 419 { 420 u16 gmch_ctrl; 421 int gtt_entries; 422 u8 rdct; 423 int local = 0; 424 static const int ddt[4] = { 0, 16, 32, 64 }; 425 int size; /* reserved space (in kb) at the top of stolen memory */ 426 427 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 428 429 if (IS_I965) { 430 u32 pgetbl_ctl; 431 432 pci_read_config_dword(agp_bridge->dev, I810_PGETBL_CTL, 433 &pgetbl_ctl); 434 /* The 965 has a field telling us the size of the GTT, 435 * which may be larger than what is necessary to map the 436 * aperture. 437 */ 438 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { 439 case I965_PGETBL_SIZE_128KB: 440 size = 128; 441 break; 442 case I965_PGETBL_SIZE_256KB: 443 size = 256; 444 break; 445 case I965_PGETBL_SIZE_512KB: 446 size = 512; 447 break; 448 default: 449 printk(KERN_INFO PFX "Unknown page table size, " 450 "assuming 512KB\n"); 451 size = 512; 452 } 453 size += 4; /* add in BIOS popup space */ 454 } else { 455 /* On previous hardware, the GTT size was just what was 456 * required to map the aperture. 457 */ 458 size = agp_bridge->driver->fetch_size() + 4; 459 } 460 461 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB || 462 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { 463 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 464 case I830_GMCH_GMS_STOLEN_512: 465 gtt_entries = KB(512) - KB(size); 466 break; 467 case I830_GMCH_GMS_STOLEN_1024: 468 gtt_entries = MB(1) - KB(size); 469 break; 470 case I830_GMCH_GMS_STOLEN_8192: 471 gtt_entries = MB(8) - KB(size); 472 break; 473 case I830_GMCH_GMS_LOCAL: 474 rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE); 475 gtt_entries = (I830_RDRAM_ND(rdct) + 1) * 476 MB(ddt[I830_RDRAM_DDT(rdct)]); 477 local = 1; 478 break; 479 default: 480 gtt_entries = 0; 481 break; 482 } 483 } else { 484 switch (gmch_ctrl & I830_GMCH_GMS_MASK) { 485 case I855_GMCH_GMS_STOLEN_1M: 486 gtt_entries = MB(1) - KB(size); 487 break; 488 case I855_GMCH_GMS_STOLEN_4M: 489 gtt_entries = MB(4) - KB(size); 490 break; 491 case I855_GMCH_GMS_STOLEN_8M: 492 gtt_entries = MB(8) - KB(size); 493 break; 494 case I855_GMCH_GMS_STOLEN_16M: 495 gtt_entries = MB(16) - KB(size); 496 break; 497 case I855_GMCH_GMS_STOLEN_32M: 498 gtt_entries = MB(32) - KB(size); 499 break; 500 case I915_GMCH_GMS_STOLEN_48M: 501 /* Check it's really I915G */ 502 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 503 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 504 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 505 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965 ) 506 gtt_entries = MB(48) - KB(size); 507 else 508 gtt_entries = 0; 509 break; 510 case I915_GMCH_GMS_STOLEN_64M: 511 /* Check it's really I915G */ 512 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || 513 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || 514 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || 515 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || IS_I965) 516 gtt_entries = MB(64) - KB(size); 517 else 518 gtt_entries = 0; 519 default: 520 gtt_entries = 0; 521 break; 522 } 523 } 524 if (gtt_entries > 0) 525 printk(KERN_INFO PFX "Detected %dK %s memory.\n", 526 gtt_entries / KB(1), local ? "local" : "stolen"); 527 else 528 printk(KERN_INFO PFX 529 "No pre-allocated video memory detected.\n"); 530 gtt_entries /= KB(4); 531 532 intel_i830_private.gtt_entries = gtt_entries; 533 } 534 535 /* The intel i830 automatically initializes the agp aperture during POST. 536 * Use the memory already set aside for in the GTT. 537 */ 538 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge) 539 { 540 int page_order; 541 struct aper_size_info_fixed *size; 542 int num_entries; 543 u32 temp; 544 545 size = agp_bridge->current_size; 546 page_order = size->page_order; 547 num_entries = size->num_entries; 548 agp_bridge->gatt_table_real = NULL; 549 550 pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp); 551 temp &= 0xfff80000; 552 553 intel_i830_private.registers = ioremap(temp,128 * 4096); 554 if (!intel_i830_private.registers) 555 return -ENOMEM; 556 557 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 558 global_cache_flush(); /* FIXME: ?? */ 559 560 /* we have to call this as early as possible after the MMIO base address is known */ 561 intel_i830_init_gtt_entries(); 562 563 agp_bridge->gatt_table = NULL; 564 565 agp_bridge->gatt_bus_addr = temp; 566 567 return 0; 568 } 569 570 /* Return the gatt table to a sane state. Use the top of stolen 571 * memory for the GTT. 572 */ 573 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge) 574 { 575 return 0; 576 } 577 578 static int intel_i830_fetch_size(void) 579 { 580 u16 gmch_ctrl; 581 struct aper_size_info_fixed *values; 582 583 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes); 584 585 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB && 586 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) { 587 /* 855GM/852GM/865G has 128MB aperture size */ 588 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 589 agp_bridge->aperture_size_idx = 0; 590 return values[0].size; 591 } 592 593 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 594 595 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) { 596 agp_bridge->previous_size = agp_bridge->current_size = (void *) values; 597 agp_bridge->aperture_size_idx = 0; 598 return values[0].size; 599 } else { 600 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1); 601 agp_bridge->aperture_size_idx = 1; 602 return values[1].size; 603 } 604 605 return 0; 606 } 607 608 static int intel_i830_configure(void) 609 { 610 struct aper_size_info_fixed *current_size; 611 u32 temp; 612 u16 gmch_ctrl; 613 int i; 614 615 current_size = A_SIZE_FIX(agp_bridge->current_size); 616 617 pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp); 618 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 619 620 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 621 gmch_ctrl |= I830_GMCH_ENABLED; 622 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 623 624 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 625 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 626 627 if (agp_bridge->driver->needs_scratch_page) { 628 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 629 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 630 readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */ 631 } 632 } 633 634 global_cache_flush(); 635 return 0; 636 } 637 638 static void intel_i830_cleanup(void) 639 { 640 iounmap(intel_i830_private.registers); 641 } 642 643 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type) 644 { 645 int i,j,num_entries; 646 void *temp; 647 int ret = -EINVAL; 648 int mask_type; 649 650 if (mem->page_count == 0) 651 goto out; 652 653 temp = agp_bridge->current_size; 654 num_entries = A_SIZE_FIX(temp)->num_entries; 655 656 if (pg_start < intel_i830_private.gtt_entries) { 657 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 658 pg_start,intel_i830_private.gtt_entries); 659 660 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 661 goto out_err; 662 } 663 664 if ((pg_start + mem->page_count) > num_entries) 665 goto out_err; 666 667 /* The i830 can't check the GTT for entries since its read only, 668 * depend on the caller to make the correct offset decisions. 669 */ 670 671 if (type != mem->type) 672 goto out_err; 673 674 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 675 676 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 677 mask_type != INTEL_AGP_CACHED_MEMORY) 678 goto out_err; 679 680 if (!mem->is_flushed) 681 global_cache_flush(); 682 683 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 684 writel(agp_bridge->driver->mask_memory(agp_bridge, 685 mem->memory[i], mask_type), 686 intel_i830_private.registers+I810_PTE_BASE+(j*4)); 687 } 688 readl(intel_i830_private.registers+I810_PTE_BASE+((j-1)*4)); 689 agp_bridge->driver->tlb_flush(mem); 690 691 out: 692 ret = 0; 693 out_err: 694 mem->is_flushed = 1; 695 return ret; 696 } 697 698 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start, 699 int type) 700 { 701 int i; 702 703 if (mem->page_count == 0) 704 return 0; 705 706 if (pg_start < intel_i830_private.gtt_entries) { 707 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 708 return -EINVAL; 709 } 710 711 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 712 writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4)); 713 } 714 readl(intel_i830_private.registers+I810_PTE_BASE+((i-1)*4)); 715 716 agp_bridge->driver->tlb_flush(mem); 717 return 0; 718 } 719 720 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type) 721 { 722 if (type == AGP_PHYS_MEMORY) 723 return alloc_agpphysmem_i8xx(pg_count, type); 724 /* always return NULL for other allocation types for now */ 725 return NULL; 726 } 727 728 static int intel_i915_configure(void) 729 { 730 struct aper_size_info_fixed *current_size; 731 u32 temp; 732 u16 gmch_ctrl; 733 int i; 734 735 current_size = A_SIZE_FIX(agp_bridge->current_size); 736 737 pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp); 738 739 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 740 741 pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl); 742 gmch_ctrl |= I830_GMCH_ENABLED; 743 pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl); 744 745 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL); 746 readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */ 747 748 if (agp_bridge->driver->needs_scratch_page) { 749 for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) { 750 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 751 readl(intel_i830_private.gtt+i); /* PCI Posting. */ 752 } 753 } 754 755 global_cache_flush(); 756 return 0; 757 } 758 759 static void intel_i915_cleanup(void) 760 { 761 iounmap(intel_i830_private.gtt); 762 iounmap(intel_i830_private.registers); 763 } 764 765 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start, 766 int type) 767 { 768 int i,j,num_entries; 769 void *temp; 770 int ret = -EINVAL; 771 int mask_type; 772 773 if (mem->page_count == 0) 774 goto out; 775 776 temp = agp_bridge->current_size; 777 num_entries = A_SIZE_FIX(temp)->num_entries; 778 779 if (pg_start < intel_i830_private.gtt_entries) { 780 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n", 781 pg_start,intel_i830_private.gtt_entries); 782 783 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n"); 784 goto out_err; 785 } 786 787 if ((pg_start + mem->page_count) > num_entries) 788 goto out_err; 789 790 /* The i915 can't check the GTT for entries since its read only, 791 * depend on the caller to make the correct offset decisions. 792 */ 793 794 if (type != mem->type) 795 goto out_err; 796 797 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 798 799 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY && 800 mask_type != INTEL_AGP_CACHED_MEMORY) 801 goto out_err; 802 803 if (!mem->is_flushed) 804 global_cache_flush(); 805 806 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 807 writel(agp_bridge->driver->mask_memory(agp_bridge, 808 mem->memory[i], mask_type), intel_i830_private.gtt+j); 809 } 810 811 readl(intel_i830_private.gtt+j-1); 812 agp_bridge->driver->tlb_flush(mem); 813 814 out: 815 ret = 0; 816 out_err: 817 mem->is_flushed = 1; 818 return ret; 819 } 820 821 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start, 822 int type) 823 { 824 int i; 825 826 if (mem->page_count == 0) 827 return 0; 828 829 if (pg_start < intel_i830_private.gtt_entries) { 830 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n"); 831 return -EINVAL; 832 } 833 834 for (i = pg_start; i < (mem->page_count + pg_start); i++) { 835 writel(agp_bridge->scratch_page, intel_i830_private.gtt+i); 836 } 837 readl(intel_i830_private.gtt+i-1); 838 839 agp_bridge->driver->tlb_flush(mem); 840 return 0; 841 } 842 843 /* Return the aperture size by just checking the resource length. The effect 844 * described in the spec of the MSAC registers is just changing of the 845 * resource size. 846 */ 847 static int intel_i9xx_fetch_size(void) 848 { 849 int num_sizes = ARRAY_SIZE(intel_i830_sizes); 850 int aper_size; /* size in megabytes */ 851 int i; 852 853 aper_size = pci_resource_len(intel_i830_private.i830_dev, 2) / MB(1); 854 855 for (i = 0; i < num_sizes; i++) { 856 if (aper_size == intel_i830_sizes[i].size) { 857 agp_bridge->current_size = intel_i830_sizes + i; 858 agp_bridge->previous_size = agp_bridge->current_size; 859 return aper_size; 860 } 861 } 862 863 return 0; 864 } 865 866 /* The intel i915 automatically initializes the agp aperture during POST. 867 * Use the memory already set aside for in the GTT. 868 */ 869 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge) 870 { 871 int page_order; 872 struct aper_size_info_fixed *size; 873 int num_entries; 874 u32 temp, temp2; 875 876 size = agp_bridge->current_size; 877 page_order = size->page_order; 878 num_entries = size->num_entries; 879 agp_bridge->gatt_table_real = NULL; 880 881 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); 882 pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2); 883 884 intel_i830_private.gtt = ioremap(temp2, 256 * 1024); 885 if (!intel_i830_private.gtt) 886 return -ENOMEM; 887 888 temp &= 0xfff80000; 889 890 intel_i830_private.registers = ioremap(temp,128 * 4096); 891 if (!intel_i830_private.registers) 892 return -ENOMEM; 893 894 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 895 global_cache_flush(); /* FIXME: ? */ 896 897 /* we have to call this as early as possible after the MMIO base address is known */ 898 intel_i830_init_gtt_entries(); 899 900 agp_bridge->gatt_table = NULL; 901 902 agp_bridge->gatt_bus_addr = temp; 903 904 return 0; 905 } 906 907 /* 908 * The i965 supports 36-bit physical addresses, but to keep 909 * the format of the GTT the same, the bits that don't fit 910 * in a 32-bit word are shifted down to bits 4..7. 911 * 912 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0" 913 * is always zero on 32-bit architectures, so no need to make 914 * this conditional. 915 */ 916 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge, 917 unsigned long addr, int type) 918 { 919 /* Shift high bits down */ 920 addr |= (addr >> 28) & 0xf0; 921 922 /* Type checking must be done elsewhere */ 923 return addr | bridge->driver->masks[type].mask; 924 } 925 926 /* The intel i965 automatically initializes the agp aperture during POST. 927 * Use the memory already set aside for in the GTT. 928 */ 929 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge) 930 { 931 int page_order; 932 struct aper_size_info_fixed *size; 933 int num_entries; 934 u32 temp; 935 936 size = agp_bridge->current_size; 937 page_order = size->page_order; 938 num_entries = size->num_entries; 939 agp_bridge->gatt_table_real = NULL; 940 941 pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp); 942 943 temp &= 0xfff00000; 944 intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024); 945 946 if (!intel_i830_private.gtt) 947 return -ENOMEM; 948 949 950 intel_i830_private.registers = ioremap(temp,128 * 4096); 951 if (!intel_i830_private.registers) 952 return -ENOMEM; 953 954 temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000; 955 global_cache_flush(); /* FIXME: ? */ 956 957 /* we have to call this as early as possible after the MMIO base address is known */ 958 intel_i830_init_gtt_entries(); 959 960 agp_bridge->gatt_table = NULL; 961 962 agp_bridge->gatt_bus_addr = temp; 963 964 return 0; 965 } 966 967 968 static int intel_fetch_size(void) 969 { 970 int i; 971 u16 temp; 972 struct aper_size_info_16 *values; 973 974 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 975 values = A_SIZE_16(agp_bridge->driver->aperture_sizes); 976 977 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 978 if (temp == values[i].size_value) { 979 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i); 980 agp_bridge->aperture_size_idx = i; 981 return values[i].size; 982 } 983 } 984 985 return 0; 986 } 987 988 static int __intel_8xx_fetch_size(u8 temp) 989 { 990 int i; 991 struct aper_size_info_8 *values; 992 993 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 994 995 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 996 if (temp == values[i].size_value) { 997 agp_bridge->previous_size = 998 agp_bridge->current_size = (void *) (values + i); 999 agp_bridge->aperture_size_idx = i; 1000 return values[i].size; 1001 } 1002 } 1003 return 0; 1004 } 1005 1006 static int intel_8xx_fetch_size(void) 1007 { 1008 u8 temp; 1009 1010 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1011 return __intel_8xx_fetch_size(temp); 1012 } 1013 1014 static int intel_815_fetch_size(void) 1015 { 1016 u8 temp; 1017 1018 /* Intel 815 chipsets have a _weird_ APSIZE register with only 1019 * one non-reserved bit, so mask the others out ... */ 1020 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp); 1021 temp &= (1 << 3); 1022 1023 return __intel_8xx_fetch_size(temp); 1024 } 1025 1026 static void intel_tlbflush(struct agp_memory *mem) 1027 { 1028 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 1029 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1030 } 1031 1032 1033 static void intel_8xx_tlbflush(struct agp_memory *mem) 1034 { 1035 u32 temp; 1036 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1037 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7)); 1038 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp); 1039 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7)); 1040 } 1041 1042 1043 static void intel_cleanup(void) 1044 { 1045 u16 temp; 1046 struct aper_size_info_16 *previous_size; 1047 1048 previous_size = A_SIZE_16(agp_bridge->previous_size); 1049 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1050 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1051 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1052 } 1053 1054 1055 static void intel_8xx_cleanup(void) 1056 { 1057 u16 temp; 1058 struct aper_size_info_8 *previous_size; 1059 1060 previous_size = A_SIZE_8(agp_bridge->previous_size); 1061 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 1062 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 1063 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value); 1064 } 1065 1066 1067 static int intel_configure(void) 1068 { 1069 u32 temp; 1070 u16 temp2; 1071 struct aper_size_info_16 *current_size; 1072 1073 current_size = A_SIZE_16(agp_bridge->current_size); 1074 1075 /* aperture size */ 1076 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1077 1078 /* address to map to */ 1079 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1080 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1081 1082 /* attbase - aperture base */ 1083 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1084 1085 /* agpctrl */ 1086 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 1087 1088 /* paccfg/nbxcfg */ 1089 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1090 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 1091 (temp2 & ~(1 << 10)) | (1 << 9)); 1092 /* clear any possible error conditions */ 1093 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 1094 return 0; 1095 } 1096 1097 static int intel_815_configure(void) 1098 { 1099 u32 temp, addr; 1100 u8 temp2; 1101 struct aper_size_info_8 *current_size; 1102 1103 /* attbase - aperture base */ 1104 /* the Intel 815 chipset spec. says that bits 29-31 in the 1105 * ATTBASE register are reserved -> try not to write them */ 1106 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) { 1107 printk (KERN_EMERG PFX "gatt bus addr too high"); 1108 return -EINVAL; 1109 } 1110 1111 current_size = A_SIZE_8(agp_bridge->current_size); 1112 1113 /* aperture size */ 1114 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1115 current_size->size_value); 1116 1117 /* address to map to */ 1118 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1119 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1120 1121 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr); 1122 addr &= INTEL_815_ATTBASE_MASK; 1123 addr |= agp_bridge->gatt_bus_addr; 1124 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr); 1125 1126 /* agpctrl */ 1127 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1128 1129 /* apcont */ 1130 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2); 1131 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1)); 1132 1133 /* clear any possible error conditions */ 1134 /* Oddness : this chipset seems to have no ERRSTS register ! */ 1135 return 0; 1136 } 1137 1138 static void intel_820_tlbflush(struct agp_memory *mem) 1139 { 1140 return; 1141 } 1142 1143 static void intel_820_cleanup(void) 1144 { 1145 u8 temp; 1146 struct aper_size_info_8 *previous_size; 1147 1148 previous_size = A_SIZE_8(agp_bridge->previous_size); 1149 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp); 1150 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, 1151 temp & ~(1 << 1)); 1152 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, 1153 previous_size->size_value); 1154 } 1155 1156 1157 static int intel_820_configure(void) 1158 { 1159 u32 temp; 1160 u8 temp2; 1161 struct aper_size_info_8 *current_size; 1162 1163 current_size = A_SIZE_8(agp_bridge->current_size); 1164 1165 /* aperture size */ 1166 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1167 1168 /* address to map to */ 1169 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1170 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1171 1172 /* attbase - aperture base */ 1173 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1174 1175 /* agpctrl */ 1176 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1177 1178 /* global enable aperture access */ 1179 /* This flag is not accessed through MCHCFG register as in */ 1180 /* i850 chipset. */ 1181 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2); 1182 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1)); 1183 /* clear any possible AGP-related error conditions */ 1184 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c); 1185 return 0; 1186 } 1187 1188 static int intel_840_configure(void) 1189 { 1190 u32 temp; 1191 u16 temp2; 1192 struct aper_size_info_8 *current_size; 1193 1194 current_size = A_SIZE_8(agp_bridge->current_size); 1195 1196 /* aperture size */ 1197 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1198 1199 /* address to map to */ 1200 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1201 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1202 1203 /* attbase - aperture base */ 1204 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1205 1206 /* agpctrl */ 1207 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1208 1209 /* mcgcfg */ 1210 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2); 1211 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9)); 1212 /* clear any possible error conditions */ 1213 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000); 1214 return 0; 1215 } 1216 1217 static int intel_845_configure(void) 1218 { 1219 u32 temp; 1220 u8 temp2; 1221 struct aper_size_info_8 *current_size; 1222 1223 current_size = A_SIZE_8(agp_bridge->current_size); 1224 1225 /* aperture size */ 1226 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1227 1228 if (agp_bridge->apbase_config != 0) { 1229 pci_write_config_dword(agp_bridge->dev, AGP_APBASE, 1230 agp_bridge->apbase_config); 1231 } else { 1232 /* address to map to */ 1233 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1234 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1235 agp_bridge->apbase_config = temp; 1236 } 1237 1238 /* attbase - aperture base */ 1239 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1240 1241 /* agpctrl */ 1242 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1243 1244 /* agpm */ 1245 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2); 1246 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1)); 1247 /* clear any possible error conditions */ 1248 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c); 1249 return 0; 1250 } 1251 1252 static int intel_850_configure(void) 1253 { 1254 u32 temp; 1255 u16 temp2; 1256 struct aper_size_info_8 *current_size; 1257 1258 current_size = A_SIZE_8(agp_bridge->current_size); 1259 1260 /* aperture size */ 1261 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1262 1263 /* address to map to */ 1264 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1265 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1266 1267 /* attbase - aperture base */ 1268 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1269 1270 /* agpctrl */ 1271 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1272 1273 /* mcgcfg */ 1274 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2); 1275 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9)); 1276 /* clear any possible AGP-related error conditions */ 1277 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c); 1278 return 0; 1279 } 1280 1281 static int intel_860_configure(void) 1282 { 1283 u32 temp; 1284 u16 temp2; 1285 struct aper_size_info_8 *current_size; 1286 1287 current_size = A_SIZE_8(agp_bridge->current_size); 1288 1289 /* aperture size */ 1290 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1291 1292 /* address to map to */ 1293 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1294 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1295 1296 /* attbase - aperture base */ 1297 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1298 1299 /* agpctrl */ 1300 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1301 1302 /* mcgcfg */ 1303 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2); 1304 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9)); 1305 /* clear any possible AGP-related error conditions */ 1306 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700); 1307 return 0; 1308 } 1309 1310 static int intel_830mp_configure(void) 1311 { 1312 u32 temp; 1313 u16 temp2; 1314 struct aper_size_info_8 *current_size; 1315 1316 current_size = A_SIZE_8(agp_bridge->current_size); 1317 1318 /* aperture size */ 1319 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1320 1321 /* address to map to */ 1322 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1323 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1324 1325 /* attbase - aperture base */ 1326 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1327 1328 /* agpctrl */ 1329 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1330 1331 /* gmch */ 1332 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 1333 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9)); 1334 /* clear any possible AGP-related error conditions */ 1335 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c); 1336 return 0; 1337 } 1338 1339 static int intel_7505_configure(void) 1340 { 1341 u32 temp; 1342 u16 temp2; 1343 struct aper_size_info_8 *current_size; 1344 1345 current_size = A_SIZE_8(agp_bridge->current_size); 1346 1347 /* aperture size */ 1348 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value); 1349 1350 /* address to map to */ 1351 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 1352 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 1353 1354 /* attbase - aperture base */ 1355 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr); 1356 1357 /* agpctrl */ 1358 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000); 1359 1360 /* mchcfg */ 1361 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2); 1362 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9)); 1363 1364 return 0; 1365 } 1366 1367 /* Setup function */ 1368 static const struct gatt_mask intel_generic_masks[] = 1369 { 1370 {.mask = 0x00000017, .type = 0} 1371 }; 1372 1373 static const struct aper_size_info_8 intel_815_sizes[2] = 1374 { 1375 {64, 16384, 4, 0}, 1376 {32, 8192, 3, 8}, 1377 }; 1378 1379 static const struct aper_size_info_8 intel_8xx_sizes[7] = 1380 { 1381 {256, 65536, 6, 0}, 1382 {128, 32768, 5, 32}, 1383 {64, 16384, 4, 48}, 1384 {32, 8192, 3, 56}, 1385 {16, 4096, 2, 60}, 1386 {8, 2048, 1, 62}, 1387 {4, 1024, 0, 63} 1388 }; 1389 1390 static const struct aper_size_info_16 intel_generic_sizes[7] = 1391 { 1392 {256, 65536, 6, 0}, 1393 {128, 32768, 5, 32}, 1394 {64, 16384, 4, 48}, 1395 {32, 8192, 3, 56}, 1396 {16, 4096, 2, 60}, 1397 {8, 2048, 1, 62}, 1398 {4, 1024, 0, 63} 1399 }; 1400 1401 static const struct aper_size_info_8 intel_830mp_sizes[4] = 1402 { 1403 {256, 65536, 6, 0}, 1404 {128, 32768, 5, 32}, 1405 {64, 16384, 4, 48}, 1406 {32, 8192, 3, 56} 1407 }; 1408 1409 static const struct agp_bridge_driver intel_generic_driver = { 1410 .owner = THIS_MODULE, 1411 .aperture_sizes = intel_generic_sizes, 1412 .size_type = U16_APER_SIZE, 1413 .num_aperture_sizes = 7, 1414 .configure = intel_configure, 1415 .fetch_size = intel_fetch_size, 1416 .cleanup = intel_cleanup, 1417 .tlb_flush = intel_tlbflush, 1418 .mask_memory = agp_generic_mask_memory, 1419 .masks = intel_generic_masks, 1420 .agp_enable = agp_generic_enable, 1421 .cache_flush = global_cache_flush, 1422 .create_gatt_table = agp_generic_create_gatt_table, 1423 .free_gatt_table = agp_generic_free_gatt_table, 1424 .insert_memory = agp_generic_insert_memory, 1425 .remove_memory = agp_generic_remove_memory, 1426 .alloc_by_type = agp_generic_alloc_by_type, 1427 .free_by_type = agp_generic_free_by_type, 1428 .agp_alloc_page = agp_generic_alloc_page, 1429 .agp_destroy_page = agp_generic_destroy_page, 1430 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1431 }; 1432 1433 static const struct agp_bridge_driver intel_810_driver = { 1434 .owner = THIS_MODULE, 1435 .aperture_sizes = intel_i810_sizes, 1436 .size_type = FIXED_APER_SIZE, 1437 .num_aperture_sizes = 2, 1438 .needs_scratch_page = TRUE, 1439 .configure = intel_i810_configure, 1440 .fetch_size = intel_i810_fetch_size, 1441 .cleanup = intel_i810_cleanup, 1442 .tlb_flush = intel_i810_tlbflush, 1443 .mask_memory = intel_i810_mask_memory, 1444 .masks = intel_i810_masks, 1445 .agp_enable = intel_i810_agp_enable, 1446 .cache_flush = global_cache_flush, 1447 .create_gatt_table = agp_generic_create_gatt_table, 1448 .free_gatt_table = agp_generic_free_gatt_table, 1449 .insert_memory = intel_i810_insert_entries, 1450 .remove_memory = intel_i810_remove_entries, 1451 .alloc_by_type = intel_i810_alloc_by_type, 1452 .free_by_type = intel_i810_free_by_type, 1453 .agp_alloc_page = agp_generic_alloc_page, 1454 .agp_destroy_page = agp_generic_destroy_page, 1455 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1456 }; 1457 1458 static const struct agp_bridge_driver intel_815_driver = { 1459 .owner = THIS_MODULE, 1460 .aperture_sizes = intel_815_sizes, 1461 .size_type = U8_APER_SIZE, 1462 .num_aperture_sizes = 2, 1463 .configure = intel_815_configure, 1464 .fetch_size = intel_815_fetch_size, 1465 .cleanup = intel_8xx_cleanup, 1466 .tlb_flush = intel_8xx_tlbflush, 1467 .mask_memory = agp_generic_mask_memory, 1468 .masks = intel_generic_masks, 1469 .agp_enable = agp_generic_enable, 1470 .cache_flush = global_cache_flush, 1471 .create_gatt_table = agp_generic_create_gatt_table, 1472 .free_gatt_table = agp_generic_free_gatt_table, 1473 .insert_memory = agp_generic_insert_memory, 1474 .remove_memory = agp_generic_remove_memory, 1475 .alloc_by_type = agp_generic_alloc_by_type, 1476 .free_by_type = agp_generic_free_by_type, 1477 .agp_alloc_page = agp_generic_alloc_page, 1478 .agp_destroy_page = agp_generic_destroy_page, 1479 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1480 }; 1481 1482 static const struct agp_bridge_driver intel_830_driver = { 1483 .owner = THIS_MODULE, 1484 .aperture_sizes = intel_i830_sizes, 1485 .size_type = FIXED_APER_SIZE, 1486 .num_aperture_sizes = 4, 1487 .needs_scratch_page = TRUE, 1488 .configure = intel_i830_configure, 1489 .fetch_size = intel_i830_fetch_size, 1490 .cleanup = intel_i830_cleanup, 1491 .tlb_flush = intel_i810_tlbflush, 1492 .mask_memory = intel_i810_mask_memory, 1493 .masks = intel_i810_masks, 1494 .agp_enable = intel_i810_agp_enable, 1495 .cache_flush = global_cache_flush, 1496 .create_gatt_table = intel_i830_create_gatt_table, 1497 .free_gatt_table = intel_i830_free_gatt_table, 1498 .insert_memory = intel_i830_insert_entries, 1499 .remove_memory = intel_i830_remove_entries, 1500 .alloc_by_type = intel_i830_alloc_by_type, 1501 .free_by_type = intel_i810_free_by_type, 1502 .agp_alloc_page = agp_generic_alloc_page, 1503 .agp_destroy_page = agp_generic_destroy_page, 1504 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1505 }; 1506 1507 static const struct agp_bridge_driver intel_820_driver = { 1508 .owner = THIS_MODULE, 1509 .aperture_sizes = intel_8xx_sizes, 1510 .size_type = U8_APER_SIZE, 1511 .num_aperture_sizes = 7, 1512 .configure = intel_820_configure, 1513 .fetch_size = intel_8xx_fetch_size, 1514 .cleanup = intel_820_cleanup, 1515 .tlb_flush = intel_820_tlbflush, 1516 .mask_memory = agp_generic_mask_memory, 1517 .masks = intel_generic_masks, 1518 .agp_enable = agp_generic_enable, 1519 .cache_flush = global_cache_flush, 1520 .create_gatt_table = agp_generic_create_gatt_table, 1521 .free_gatt_table = agp_generic_free_gatt_table, 1522 .insert_memory = agp_generic_insert_memory, 1523 .remove_memory = agp_generic_remove_memory, 1524 .alloc_by_type = agp_generic_alloc_by_type, 1525 .free_by_type = agp_generic_free_by_type, 1526 .agp_alloc_page = agp_generic_alloc_page, 1527 .agp_destroy_page = agp_generic_destroy_page, 1528 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1529 }; 1530 1531 static const struct agp_bridge_driver intel_830mp_driver = { 1532 .owner = THIS_MODULE, 1533 .aperture_sizes = intel_830mp_sizes, 1534 .size_type = U8_APER_SIZE, 1535 .num_aperture_sizes = 4, 1536 .configure = intel_830mp_configure, 1537 .fetch_size = intel_8xx_fetch_size, 1538 .cleanup = intel_8xx_cleanup, 1539 .tlb_flush = intel_8xx_tlbflush, 1540 .mask_memory = agp_generic_mask_memory, 1541 .masks = intel_generic_masks, 1542 .agp_enable = agp_generic_enable, 1543 .cache_flush = global_cache_flush, 1544 .create_gatt_table = agp_generic_create_gatt_table, 1545 .free_gatt_table = agp_generic_free_gatt_table, 1546 .insert_memory = agp_generic_insert_memory, 1547 .remove_memory = agp_generic_remove_memory, 1548 .alloc_by_type = agp_generic_alloc_by_type, 1549 .free_by_type = agp_generic_free_by_type, 1550 .agp_alloc_page = agp_generic_alloc_page, 1551 .agp_destroy_page = agp_generic_destroy_page, 1552 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1553 }; 1554 1555 static const struct agp_bridge_driver intel_840_driver = { 1556 .owner = THIS_MODULE, 1557 .aperture_sizes = intel_8xx_sizes, 1558 .size_type = U8_APER_SIZE, 1559 .num_aperture_sizes = 7, 1560 .configure = intel_840_configure, 1561 .fetch_size = intel_8xx_fetch_size, 1562 .cleanup = intel_8xx_cleanup, 1563 .tlb_flush = intel_8xx_tlbflush, 1564 .mask_memory = agp_generic_mask_memory, 1565 .masks = intel_generic_masks, 1566 .agp_enable = agp_generic_enable, 1567 .cache_flush = global_cache_flush, 1568 .create_gatt_table = agp_generic_create_gatt_table, 1569 .free_gatt_table = agp_generic_free_gatt_table, 1570 .insert_memory = agp_generic_insert_memory, 1571 .remove_memory = agp_generic_remove_memory, 1572 .alloc_by_type = agp_generic_alloc_by_type, 1573 .free_by_type = agp_generic_free_by_type, 1574 .agp_alloc_page = agp_generic_alloc_page, 1575 .agp_destroy_page = agp_generic_destroy_page, 1576 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1577 }; 1578 1579 static const struct agp_bridge_driver intel_845_driver = { 1580 .owner = THIS_MODULE, 1581 .aperture_sizes = intel_8xx_sizes, 1582 .size_type = U8_APER_SIZE, 1583 .num_aperture_sizes = 7, 1584 .configure = intel_845_configure, 1585 .fetch_size = intel_8xx_fetch_size, 1586 .cleanup = intel_8xx_cleanup, 1587 .tlb_flush = intel_8xx_tlbflush, 1588 .mask_memory = agp_generic_mask_memory, 1589 .masks = intel_generic_masks, 1590 .agp_enable = agp_generic_enable, 1591 .cache_flush = global_cache_flush, 1592 .create_gatt_table = agp_generic_create_gatt_table, 1593 .free_gatt_table = agp_generic_free_gatt_table, 1594 .insert_memory = agp_generic_insert_memory, 1595 .remove_memory = agp_generic_remove_memory, 1596 .alloc_by_type = agp_generic_alloc_by_type, 1597 .free_by_type = agp_generic_free_by_type, 1598 .agp_alloc_page = agp_generic_alloc_page, 1599 .agp_destroy_page = agp_generic_destroy_page, 1600 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1601 }; 1602 1603 static const struct agp_bridge_driver intel_850_driver = { 1604 .owner = THIS_MODULE, 1605 .aperture_sizes = intel_8xx_sizes, 1606 .size_type = U8_APER_SIZE, 1607 .num_aperture_sizes = 7, 1608 .configure = intel_850_configure, 1609 .fetch_size = intel_8xx_fetch_size, 1610 .cleanup = intel_8xx_cleanup, 1611 .tlb_flush = intel_8xx_tlbflush, 1612 .mask_memory = agp_generic_mask_memory, 1613 .masks = intel_generic_masks, 1614 .agp_enable = agp_generic_enable, 1615 .cache_flush = global_cache_flush, 1616 .create_gatt_table = agp_generic_create_gatt_table, 1617 .free_gatt_table = agp_generic_free_gatt_table, 1618 .insert_memory = agp_generic_insert_memory, 1619 .remove_memory = agp_generic_remove_memory, 1620 .alloc_by_type = agp_generic_alloc_by_type, 1621 .free_by_type = agp_generic_free_by_type, 1622 .agp_alloc_page = agp_generic_alloc_page, 1623 .agp_destroy_page = agp_generic_destroy_page, 1624 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1625 }; 1626 1627 static const struct agp_bridge_driver intel_860_driver = { 1628 .owner = THIS_MODULE, 1629 .aperture_sizes = intel_8xx_sizes, 1630 .size_type = U8_APER_SIZE, 1631 .num_aperture_sizes = 7, 1632 .configure = intel_860_configure, 1633 .fetch_size = intel_8xx_fetch_size, 1634 .cleanup = intel_8xx_cleanup, 1635 .tlb_flush = intel_8xx_tlbflush, 1636 .mask_memory = agp_generic_mask_memory, 1637 .masks = intel_generic_masks, 1638 .agp_enable = agp_generic_enable, 1639 .cache_flush = global_cache_flush, 1640 .create_gatt_table = agp_generic_create_gatt_table, 1641 .free_gatt_table = agp_generic_free_gatt_table, 1642 .insert_memory = agp_generic_insert_memory, 1643 .remove_memory = agp_generic_remove_memory, 1644 .alloc_by_type = agp_generic_alloc_by_type, 1645 .free_by_type = agp_generic_free_by_type, 1646 .agp_alloc_page = agp_generic_alloc_page, 1647 .agp_destroy_page = agp_generic_destroy_page, 1648 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1649 }; 1650 1651 static const struct agp_bridge_driver intel_915_driver = { 1652 .owner = THIS_MODULE, 1653 .aperture_sizes = intel_i830_sizes, 1654 .size_type = FIXED_APER_SIZE, 1655 .num_aperture_sizes = 4, 1656 .needs_scratch_page = TRUE, 1657 .configure = intel_i915_configure, 1658 .fetch_size = intel_i9xx_fetch_size, 1659 .cleanup = intel_i915_cleanup, 1660 .tlb_flush = intel_i810_tlbflush, 1661 .mask_memory = intel_i810_mask_memory, 1662 .masks = intel_i810_masks, 1663 .agp_enable = intel_i810_agp_enable, 1664 .cache_flush = global_cache_flush, 1665 .create_gatt_table = intel_i915_create_gatt_table, 1666 .free_gatt_table = intel_i830_free_gatt_table, 1667 .insert_memory = intel_i915_insert_entries, 1668 .remove_memory = intel_i915_remove_entries, 1669 .alloc_by_type = intel_i830_alloc_by_type, 1670 .free_by_type = intel_i810_free_by_type, 1671 .agp_alloc_page = agp_generic_alloc_page, 1672 .agp_destroy_page = agp_generic_destroy_page, 1673 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1674 }; 1675 1676 static const struct agp_bridge_driver intel_i965_driver = { 1677 .owner = THIS_MODULE, 1678 .aperture_sizes = intel_i830_sizes, 1679 .size_type = FIXED_APER_SIZE, 1680 .num_aperture_sizes = 4, 1681 .needs_scratch_page = TRUE, 1682 .configure = intel_i915_configure, 1683 .fetch_size = intel_i9xx_fetch_size, 1684 .cleanup = intel_i915_cleanup, 1685 .tlb_flush = intel_i810_tlbflush, 1686 .mask_memory = intel_i965_mask_memory, 1687 .masks = intel_i810_masks, 1688 .agp_enable = intel_i810_agp_enable, 1689 .cache_flush = global_cache_flush, 1690 .create_gatt_table = intel_i965_create_gatt_table, 1691 .free_gatt_table = intel_i830_free_gatt_table, 1692 .insert_memory = intel_i915_insert_entries, 1693 .remove_memory = intel_i915_remove_entries, 1694 .alloc_by_type = intel_i830_alloc_by_type, 1695 .free_by_type = intel_i810_free_by_type, 1696 .agp_alloc_page = agp_generic_alloc_page, 1697 .agp_destroy_page = agp_generic_destroy_page, 1698 .agp_type_to_mask_type = intel_i830_type_to_mask_type, 1699 }; 1700 1701 static const struct agp_bridge_driver intel_7505_driver = { 1702 .owner = THIS_MODULE, 1703 .aperture_sizes = intel_8xx_sizes, 1704 .size_type = U8_APER_SIZE, 1705 .num_aperture_sizes = 7, 1706 .configure = intel_7505_configure, 1707 .fetch_size = intel_8xx_fetch_size, 1708 .cleanup = intel_8xx_cleanup, 1709 .tlb_flush = intel_8xx_tlbflush, 1710 .mask_memory = agp_generic_mask_memory, 1711 .masks = intel_generic_masks, 1712 .agp_enable = agp_generic_enable, 1713 .cache_flush = global_cache_flush, 1714 .create_gatt_table = agp_generic_create_gatt_table, 1715 .free_gatt_table = agp_generic_free_gatt_table, 1716 .insert_memory = agp_generic_insert_memory, 1717 .remove_memory = agp_generic_remove_memory, 1718 .alloc_by_type = agp_generic_alloc_by_type, 1719 .free_by_type = agp_generic_free_by_type, 1720 .agp_alloc_page = agp_generic_alloc_page, 1721 .agp_destroy_page = agp_generic_destroy_page, 1722 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 1723 }; 1724 1725 static int find_i810(u16 device) 1726 { 1727 struct pci_dev *i810_dev; 1728 1729 i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1730 if (!i810_dev) 1731 return 0; 1732 intel_i810_private.i810_dev = i810_dev; 1733 return 1; 1734 } 1735 1736 static int find_i830(u16 device) 1737 { 1738 struct pci_dev *i830_dev; 1739 1740 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); 1741 if (i830_dev && PCI_FUNC(i830_dev->devfn) != 0) { 1742 i830_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 1743 device, i830_dev); 1744 } 1745 1746 if (!i830_dev) 1747 return 0; 1748 1749 intel_i830_private.i830_dev = i830_dev; 1750 return 1; 1751 } 1752 1753 static int __devinit agp_intel_probe(struct pci_dev *pdev, 1754 const struct pci_device_id *ent) 1755 { 1756 struct agp_bridge_data *bridge; 1757 char *name = "(unknown)"; 1758 u8 cap_ptr = 0; 1759 struct resource *r; 1760 1761 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 1762 1763 bridge = agp_alloc_bridge(); 1764 if (!bridge) 1765 return -ENOMEM; 1766 1767 switch (pdev->device) { 1768 case PCI_DEVICE_ID_INTEL_82443LX_0: 1769 bridge->driver = &intel_generic_driver; 1770 name = "440LX"; 1771 break; 1772 case PCI_DEVICE_ID_INTEL_82443BX_0: 1773 bridge->driver = &intel_generic_driver; 1774 name = "440BX"; 1775 break; 1776 case PCI_DEVICE_ID_INTEL_82443GX_0: 1777 bridge->driver = &intel_generic_driver; 1778 name = "440GX"; 1779 break; 1780 case PCI_DEVICE_ID_INTEL_82810_MC1: 1781 name = "i810"; 1782 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG1)) 1783 goto fail; 1784 bridge->driver = &intel_810_driver; 1785 break; 1786 case PCI_DEVICE_ID_INTEL_82810_MC3: 1787 name = "i810 DC100"; 1788 if (!find_i810(PCI_DEVICE_ID_INTEL_82810_IG3)) 1789 goto fail; 1790 bridge->driver = &intel_810_driver; 1791 break; 1792 case PCI_DEVICE_ID_INTEL_82810E_MC: 1793 name = "i810 E"; 1794 if (!find_i810(PCI_DEVICE_ID_INTEL_82810E_IG)) 1795 goto fail; 1796 bridge->driver = &intel_810_driver; 1797 break; 1798 case PCI_DEVICE_ID_INTEL_82815_MC: 1799 /* 1800 * The i815 can operate either as an i810 style 1801 * integrated device, or as an AGP4X motherboard. 1802 */ 1803 if (find_i810(PCI_DEVICE_ID_INTEL_82815_CGC)) 1804 bridge->driver = &intel_810_driver; 1805 else 1806 bridge->driver = &intel_815_driver; 1807 name = "i815"; 1808 break; 1809 case PCI_DEVICE_ID_INTEL_82820_HB: 1810 case PCI_DEVICE_ID_INTEL_82820_UP_HB: 1811 bridge->driver = &intel_820_driver; 1812 name = "i820"; 1813 break; 1814 case PCI_DEVICE_ID_INTEL_82830_HB: 1815 if (find_i830(PCI_DEVICE_ID_INTEL_82830_CGC)) 1816 bridge->driver = &intel_830_driver; 1817 else 1818 bridge->driver = &intel_830mp_driver; 1819 name = "830M"; 1820 break; 1821 case PCI_DEVICE_ID_INTEL_82840_HB: 1822 bridge->driver = &intel_840_driver; 1823 name = "i840"; 1824 break; 1825 case PCI_DEVICE_ID_INTEL_82845_HB: 1826 bridge->driver = &intel_845_driver; 1827 name = "i845"; 1828 break; 1829 case PCI_DEVICE_ID_INTEL_82845G_HB: 1830 if (find_i830(PCI_DEVICE_ID_INTEL_82845G_IG)) 1831 bridge->driver = &intel_830_driver; 1832 else 1833 bridge->driver = &intel_845_driver; 1834 name = "845G"; 1835 break; 1836 case PCI_DEVICE_ID_INTEL_82850_HB: 1837 bridge->driver = &intel_850_driver; 1838 name = "i850"; 1839 break; 1840 case PCI_DEVICE_ID_INTEL_82855PM_HB: 1841 bridge->driver = &intel_845_driver; 1842 name = "855PM"; 1843 break; 1844 case PCI_DEVICE_ID_INTEL_82855GM_HB: 1845 if (find_i830(PCI_DEVICE_ID_INTEL_82855GM_IG)) { 1846 bridge->driver = &intel_830_driver; 1847 name = "855"; 1848 } else { 1849 bridge->driver = &intel_845_driver; 1850 name = "855GM"; 1851 } 1852 break; 1853 case PCI_DEVICE_ID_INTEL_82860_HB: 1854 bridge->driver = &intel_860_driver; 1855 name = "i860"; 1856 break; 1857 case PCI_DEVICE_ID_INTEL_82865_HB: 1858 if (find_i830(PCI_DEVICE_ID_INTEL_82865_IG)) 1859 bridge->driver = &intel_830_driver; 1860 else 1861 bridge->driver = &intel_845_driver; 1862 name = "865"; 1863 break; 1864 case PCI_DEVICE_ID_INTEL_82875_HB: 1865 bridge->driver = &intel_845_driver; 1866 name = "i875"; 1867 break; 1868 case PCI_DEVICE_ID_INTEL_82915G_HB: 1869 if (find_i830(PCI_DEVICE_ID_INTEL_82915G_IG)) 1870 bridge->driver = &intel_915_driver; 1871 else 1872 bridge->driver = &intel_845_driver; 1873 name = "915G"; 1874 break; 1875 case PCI_DEVICE_ID_INTEL_82915GM_HB: 1876 if (find_i830(PCI_DEVICE_ID_INTEL_82915GM_IG)) 1877 bridge->driver = &intel_915_driver; 1878 else 1879 bridge->driver = &intel_845_driver; 1880 name = "915GM"; 1881 break; 1882 case PCI_DEVICE_ID_INTEL_82945G_HB: 1883 if (find_i830(PCI_DEVICE_ID_INTEL_82945G_IG)) 1884 bridge->driver = &intel_915_driver; 1885 else 1886 bridge->driver = &intel_845_driver; 1887 name = "945G"; 1888 break; 1889 case PCI_DEVICE_ID_INTEL_82945GM_HB: 1890 if (find_i830(PCI_DEVICE_ID_INTEL_82945GM_IG)) 1891 bridge->driver = &intel_915_driver; 1892 else 1893 bridge->driver = &intel_845_driver; 1894 name = "945GM"; 1895 break; 1896 case PCI_DEVICE_ID_INTEL_82946GZ_HB: 1897 if (find_i830(PCI_DEVICE_ID_INTEL_82946GZ_IG)) 1898 bridge->driver = &intel_i965_driver; 1899 else 1900 bridge->driver = &intel_845_driver; 1901 name = "946GZ"; 1902 break; 1903 case PCI_DEVICE_ID_INTEL_82965G_1_HB: 1904 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_1_IG)) 1905 bridge->driver = &intel_i965_driver; 1906 else 1907 bridge->driver = &intel_845_driver; 1908 name = "965G"; 1909 break; 1910 case PCI_DEVICE_ID_INTEL_82965Q_HB: 1911 if (find_i830(PCI_DEVICE_ID_INTEL_82965Q_IG)) 1912 bridge->driver = &intel_i965_driver; 1913 else 1914 bridge->driver = &intel_845_driver; 1915 name = "965Q"; 1916 break; 1917 case PCI_DEVICE_ID_INTEL_82965G_HB: 1918 if (find_i830(PCI_DEVICE_ID_INTEL_82965G_IG)) 1919 bridge->driver = &intel_i965_driver; 1920 else 1921 bridge->driver = &intel_845_driver; 1922 name = "965G"; 1923 break; 1924 1925 case PCI_DEVICE_ID_INTEL_7505_0: 1926 bridge->driver = &intel_7505_driver; 1927 name = "E7505"; 1928 break; 1929 case PCI_DEVICE_ID_INTEL_7205_0: 1930 bridge->driver = &intel_7505_driver; 1931 name = "E7205"; 1932 break; 1933 default: 1934 if (cap_ptr) 1935 printk(KERN_WARNING PFX "Unsupported Intel chipset (device id: %04x)\n", 1936 pdev->device); 1937 agp_put_bridge(bridge); 1938 return -ENODEV; 1939 }; 1940 1941 bridge->dev = pdev; 1942 bridge->capndx = cap_ptr; 1943 1944 if (bridge->driver == &intel_810_driver) 1945 bridge->dev_private_data = &intel_i810_private; 1946 else if (bridge->driver == &intel_830_driver) 1947 bridge->dev_private_data = &intel_i830_private; 1948 1949 printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name); 1950 1951 /* 1952 * The following fixes the case where the BIOS has "forgotten" to 1953 * provide an address range for the GART. 1954 * 20030610 - hamish@zot.org 1955 */ 1956 r = &pdev->resource[0]; 1957 if (!r->start && r->end) { 1958 if (pci_assign_resource(pdev, 0)) { 1959 printk(KERN_ERR PFX "could not assign resource 0\n"); 1960 agp_put_bridge(bridge); 1961 return -ENODEV; 1962 } 1963 } 1964 1965 /* 1966 * If the device has not been properly setup, the following will catch 1967 * the problem and should stop the system from crashing. 1968 * 20030610 - hamish@zot.org 1969 */ 1970 if (pci_enable_device(pdev)) { 1971 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 1972 agp_put_bridge(bridge); 1973 return -ENODEV; 1974 } 1975 1976 /* Fill in the mode register */ 1977 if (cap_ptr) { 1978 pci_read_config_dword(pdev, 1979 bridge->capndx+PCI_AGP_STATUS, 1980 &bridge->mode); 1981 } 1982 1983 pci_set_drvdata(pdev, bridge); 1984 return agp_add_bridge(bridge); 1985 1986 fail: 1987 printk(KERN_ERR PFX "Detected an Intel %s chipset, " 1988 "but could not find the secondary device.\n", name); 1989 agp_put_bridge(bridge); 1990 return -ENODEV; 1991 } 1992 1993 static void __devexit agp_intel_remove(struct pci_dev *pdev) 1994 { 1995 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 1996 1997 agp_remove_bridge(bridge); 1998 1999 if (intel_i810_private.i810_dev) 2000 pci_dev_put(intel_i810_private.i810_dev); 2001 if (intel_i830_private.i830_dev) 2002 pci_dev_put(intel_i830_private.i830_dev); 2003 2004 agp_put_bridge(bridge); 2005 } 2006 2007 #ifdef CONFIG_PM 2008 static int agp_intel_resume(struct pci_dev *pdev) 2009 { 2010 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 2011 2012 pci_restore_state(pdev); 2013 2014 /* We should restore our graphics device's config space, 2015 * as host bridge (00:00) resumes before graphics device (02:00), 2016 * then our access to its pci space can work right. 2017 */ 2018 if (intel_i810_private.i810_dev) 2019 pci_restore_state(intel_i810_private.i810_dev); 2020 if (intel_i830_private.i830_dev) 2021 pci_restore_state(intel_i830_private.i830_dev); 2022 2023 if (bridge->driver == &intel_generic_driver) 2024 intel_configure(); 2025 else if (bridge->driver == &intel_850_driver) 2026 intel_850_configure(); 2027 else if (bridge->driver == &intel_845_driver) 2028 intel_845_configure(); 2029 else if (bridge->driver == &intel_830mp_driver) 2030 intel_830mp_configure(); 2031 else if (bridge->driver == &intel_915_driver) 2032 intel_i915_configure(); 2033 else if (bridge->driver == &intel_830_driver) 2034 intel_i830_configure(); 2035 else if (bridge->driver == &intel_810_driver) 2036 intel_i810_configure(); 2037 else if (bridge->driver == &intel_i965_driver) 2038 intel_i915_configure(); 2039 2040 return 0; 2041 } 2042 #endif 2043 2044 static struct pci_device_id agp_intel_pci_table[] = { 2045 #define ID(x) \ 2046 { \ 2047 .class = (PCI_CLASS_BRIDGE_HOST << 8), \ 2048 .class_mask = ~0, \ 2049 .vendor = PCI_VENDOR_ID_INTEL, \ 2050 .device = x, \ 2051 .subvendor = PCI_ANY_ID, \ 2052 .subdevice = PCI_ANY_ID, \ 2053 } 2054 ID(PCI_DEVICE_ID_INTEL_82443LX_0), 2055 ID(PCI_DEVICE_ID_INTEL_82443BX_0), 2056 ID(PCI_DEVICE_ID_INTEL_82443GX_0), 2057 ID(PCI_DEVICE_ID_INTEL_82810_MC1), 2058 ID(PCI_DEVICE_ID_INTEL_82810_MC3), 2059 ID(PCI_DEVICE_ID_INTEL_82810E_MC), 2060 ID(PCI_DEVICE_ID_INTEL_82815_MC), 2061 ID(PCI_DEVICE_ID_INTEL_82820_HB), 2062 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB), 2063 ID(PCI_DEVICE_ID_INTEL_82830_HB), 2064 ID(PCI_DEVICE_ID_INTEL_82840_HB), 2065 ID(PCI_DEVICE_ID_INTEL_82845_HB), 2066 ID(PCI_DEVICE_ID_INTEL_82845G_HB), 2067 ID(PCI_DEVICE_ID_INTEL_82850_HB), 2068 ID(PCI_DEVICE_ID_INTEL_82855PM_HB), 2069 ID(PCI_DEVICE_ID_INTEL_82855GM_HB), 2070 ID(PCI_DEVICE_ID_INTEL_82860_HB), 2071 ID(PCI_DEVICE_ID_INTEL_82865_HB), 2072 ID(PCI_DEVICE_ID_INTEL_82875_HB), 2073 ID(PCI_DEVICE_ID_INTEL_7505_0), 2074 ID(PCI_DEVICE_ID_INTEL_7205_0), 2075 ID(PCI_DEVICE_ID_INTEL_82915G_HB), 2076 ID(PCI_DEVICE_ID_INTEL_82915GM_HB), 2077 ID(PCI_DEVICE_ID_INTEL_82945G_HB), 2078 ID(PCI_DEVICE_ID_INTEL_82945GM_HB), 2079 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB), 2080 ID(PCI_DEVICE_ID_INTEL_82965G_1_HB), 2081 ID(PCI_DEVICE_ID_INTEL_82965Q_HB), 2082 ID(PCI_DEVICE_ID_INTEL_82965G_HB), 2083 { } 2084 }; 2085 2086 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table); 2087 2088 static struct pci_driver agp_intel_pci_driver = { 2089 .name = "agpgart-intel", 2090 .id_table = agp_intel_pci_table, 2091 .probe = agp_intel_probe, 2092 .remove = __devexit_p(agp_intel_remove), 2093 #ifdef CONFIG_PM 2094 .resume = agp_intel_resume, 2095 #endif 2096 }; 2097 2098 static int __init agp_intel_init(void) 2099 { 2100 if (agp_off) 2101 return -EINVAL; 2102 return pci_register_driver(&agp_intel_pci_driver); 2103 } 2104 2105 static void __exit agp_intel_cleanup(void) 2106 { 2107 pci_unregister_driver(&agp_intel_pci_driver); 2108 } 2109 2110 module_init(agp_intel_init); 2111 module_exit(agp_intel_cleanup); 2112 2113 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>"); 2114 MODULE_LICENSE("GPL and additional rights"); 2115