1 /* 2 * Transmeta's Efficeon AGPGART driver. 3 * 4 * Based upon a diff by Linus around November '02. 5 * 6 * Ported to the 2.6 kernel by Carlos Puchol <cpglinux@puchol.com> 7 * and H. Peter Anvin <hpa@transmeta.com>. 8 */ 9 10 /* 11 * NOTE-cpg-040217: 12 * 13 * - when compiled as a module, after loading the module, 14 * it will refuse to unload, indicating it is in use, 15 * when it is not. 16 * - no s3 (suspend to ram) testing. 17 * - tested on the efficeon integrated nothbridge for tens 18 * of iterations of starting x and glxgears. 19 * - tested with radeon 9000 and radeon mobility m9 cards 20 * - tested with c3/c4 enabled (with the mobility m9 card) 21 */ 22 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/init.h> 26 #include <linux/agp_backend.h> 27 #include <linux/gfp.h> 28 #include <linux/page-flags.h> 29 #include <linux/mm.h> 30 #include <asm/cpuid/api.h> 31 #include "agp.h" 32 #include "intel-agp.h" 33 34 /* 35 * The real differences to the generic AGP code is 36 * in the GART mappings - a two-level setup with the 37 * first level being an on-chip 64-entry table. 38 * 39 * The page array is filled through the ATTPAGE register 40 * (Aperture Translation Table Page Register) at 0xB8. Bits: 41 * 31:20: physical page address 42 * 11:9: Page Attribute Table Index (PATI) 43 * must match the PAT index for the 44 * mapped pages (the 2nd level page table pages 45 * themselves should be just regular WB-cacheable, 46 * so this is normally zero.) 47 * 8: Present 48 * 7:6: reserved, write as zero 49 * 5:0: GATT directory index: which 1st-level entry 50 * 51 * The Efficeon AGP spec requires pages to be WB-cacheable 52 * but to be explicitly CLFLUSH'd after any changes. 53 */ 54 #define EFFICEON_ATTPAGE 0xb8 55 #define EFFICEON_L1_SIZE 64 /* Number of PDE pages */ 56 57 #define EFFICEON_PATI (0 << 9) 58 #define EFFICEON_PRESENT (1 << 8) 59 60 static struct _efficeon_private { 61 unsigned long l1_table[EFFICEON_L1_SIZE]; 62 } efficeon_private; 63 64 static const struct gatt_mask efficeon_generic_masks[] = 65 { 66 {.mask = 0x00000001, .type = 0} 67 }; 68 69 /* This function does the same thing as mask_memory() for this chipset... */ 70 static inline unsigned long efficeon_mask_memory(struct page *page) 71 { 72 unsigned long addr = page_to_phys(page); 73 return addr | 0x00000001; 74 } 75 76 static const struct aper_size_info_lvl2 efficeon_generic_sizes[4] = 77 { 78 {256, 65536, 0}, 79 {128, 32768, 32}, 80 {64, 16384, 48}, 81 {32, 8192, 56} 82 }; 83 84 /* 85 * Control interfaces are largely identical to 86 * the legacy Intel 440BX.. 87 */ 88 89 static int efficeon_fetch_size(void) 90 { 91 int i; 92 u16 temp; 93 struct aper_size_info_lvl2 *values; 94 95 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp); 96 values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes); 97 98 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 99 if (temp == values[i].size_value) { 100 agp_bridge->previous_size = 101 agp_bridge->current_size = (void *) (values + i); 102 agp_bridge->aperture_size_idx = i; 103 return values[i].size; 104 } 105 } 106 107 return 0; 108 } 109 110 static void efficeon_tlbflush(struct agp_memory * mem) 111 { 112 printk(KERN_DEBUG PFX "efficeon_tlbflush()\n"); 113 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200); 114 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 115 } 116 117 static void efficeon_cleanup(void) 118 { 119 u16 temp; 120 struct aper_size_info_lvl2 *previous_size; 121 122 printk(KERN_DEBUG PFX "efficeon_cleanup()\n"); 123 previous_size = A_SIZE_LVL2(agp_bridge->previous_size); 124 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp); 125 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9)); 126 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, 127 previous_size->size_value); 128 } 129 130 static int efficeon_configure(void) 131 { 132 u16 temp2; 133 struct aper_size_info_lvl2 *current_size; 134 135 printk(KERN_DEBUG PFX "efficeon_configure()\n"); 136 137 current_size = A_SIZE_LVL2(agp_bridge->current_size); 138 139 /* aperture size */ 140 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, 141 current_size->size_value); 142 143 /* address to map to */ 144 agp_bridge->gart_bus_addr = pci_bus_address(agp_bridge->dev, 145 AGP_APERTURE_BAR); 146 147 /* agpctrl */ 148 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280); 149 150 /* paccfg/nbxcfg */ 151 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2); 152 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, 153 (temp2 & ~(1 << 10)) | (1 << 9) | (1 << 11)); 154 /* clear any possible error conditions */ 155 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7); 156 return 0; 157 } 158 159 static int efficeon_free_gatt_table(struct agp_bridge_data *bridge) 160 { 161 int index, freed = 0; 162 163 for (index = 0; index < EFFICEON_L1_SIZE; index++) { 164 unsigned long page = efficeon_private.l1_table[index]; 165 if (page) { 166 efficeon_private.l1_table[index] = 0; 167 free_page(page); 168 freed++; 169 } 170 printk(KERN_DEBUG PFX "efficeon_free_gatt_table(%p, %02x, %08x)\n", 171 agp_bridge->dev, EFFICEON_ATTPAGE, index); 172 pci_write_config_dword(agp_bridge->dev, 173 EFFICEON_ATTPAGE, index); 174 } 175 printk(KERN_DEBUG PFX "efficeon_free_gatt_table() freed %d pages\n", freed); 176 return 0; 177 } 178 179 180 /* 181 * Since we don't need contiguous memory we just try 182 * to get the gatt table once 183 */ 184 185 #define GET_PAGE_DIR_OFF(addr) (addr >> 22) 186 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \ 187 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr)) 188 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12) 189 #undef GET_GATT 190 #define GET_GATT(addr) (efficeon_private.gatt_pages[\ 191 GET_PAGE_DIR_IDX(addr)]->remapped) 192 193 static int efficeon_create_gatt_table(struct agp_bridge_data *bridge) 194 { 195 int index; 196 const int pati = EFFICEON_PATI; 197 const int present = EFFICEON_PRESENT; 198 const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3; 199 int num_entries, l1_pages; 200 201 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; 202 203 printk(KERN_DEBUG PFX "efficeon_create_gatt_table(%d)\n", num_entries); 204 205 /* There are 2^10 PTE pages per PDE page */ 206 BUG_ON(num_entries & 0x3ff); 207 l1_pages = num_entries >> 10; 208 209 for (index = 0 ; index < l1_pages ; index++) { 210 int offset; 211 unsigned long page; 212 unsigned long value; 213 214 page = efficeon_private.l1_table[index]; 215 BUG_ON(page); 216 217 page = get_zeroed_page(GFP_KERNEL); 218 if (!page) { 219 efficeon_free_gatt_table(agp_bridge); 220 return -ENOMEM; 221 } 222 223 for (offset = 0; offset < PAGE_SIZE; offset += clflush_chunk) 224 clflush((char *)page+offset); 225 226 efficeon_private.l1_table[index] = page; 227 228 value = virt_to_phys((unsigned long *)page) | pati | present | index; 229 230 pci_write_config_dword(agp_bridge->dev, 231 EFFICEON_ATTPAGE, value); 232 } 233 234 return 0; 235 } 236 237 static int efficeon_insert_memory(struct agp_memory * mem, off_t pg_start, int type) 238 { 239 int i, count = mem->page_count, num_entries; 240 unsigned int *page, *last_page; 241 const int clflush_chunk = ((cpuid_ebx(1) >> 8) & 0xff) << 3; 242 const unsigned long clflush_mask = ~(clflush_chunk-1); 243 244 printk(KERN_DEBUG PFX "efficeon_insert_memory(%lx, %d)\n", pg_start, count); 245 246 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; 247 if ((pg_start + mem->page_count) > num_entries) 248 return -EINVAL; 249 if (type != 0 || mem->type != 0) 250 return -EINVAL; 251 252 if (!mem->is_flushed) { 253 global_cache_flush(); 254 mem->is_flushed = true; 255 } 256 257 last_page = NULL; 258 for (i = 0; i < count; i++) { 259 int index = pg_start + i; 260 unsigned long insert = efficeon_mask_memory(mem->pages[i]); 261 262 page = (unsigned int *) efficeon_private.l1_table[index >> 10]; 263 264 if (!page) 265 continue; 266 267 page += (index & 0x3ff); 268 *page = insert; 269 270 /* clflush is slow, so don't clflush until we have to */ 271 if (last_page && 272 (((unsigned long)page^(unsigned long)last_page) & 273 clflush_mask)) 274 clflush(last_page); 275 276 last_page = page; 277 } 278 279 if ( last_page ) 280 clflush(last_page); 281 282 agp_bridge->driver->tlb_flush(mem); 283 return 0; 284 } 285 286 static int efficeon_remove_memory(struct agp_memory * mem, off_t pg_start, int type) 287 { 288 int i, count = mem->page_count, num_entries; 289 290 printk(KERN_DEBUG PFX "efficeon_remove_memory(%lx, %d)\n", pg_start, count); 291 292 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries; 293 294 if ((pg_start + mem->page_count) > num_entries) 295 return -EINVAL; 296 if (type != 0 || mem->type != 0) 297 return -EINVAL; 298 299 for (i = 0; i < count; i++) { 300 int index = pg_start + i; 301 unsigned int *page = (unsigned int *) efficeon_private.l1_table[index >> 10]; 302 303 if (!page) 304 continue; 305 page += (index & 0x3ff); 306 *page = 0; 307 } 308 agp_bridge->driver->tlb_flush(mem); 309 return 0; 310 } 311 312 313 static const struct agp_bridge_driver efficeon_driver = { 314 .owner = THIS_MODULE, 315 .aperture_sizes = efficeon_generic_sizes, 316 .size_type = LVL2_APER_SIZE, 317 .num_aperture_sizes = 4, 318 .configure = efficeon_configure, 319 .fetch_size = efficeon_fetch_size, 320 .cleanup = efficeon_cleanup, 321 .tlb_flush = efficeon_tlbflush, 322 .mask_memory = agp_generic_mask_memory, 323 .masks = efficeon_generic_masks, 324 .agp_enable = agp_generic_enable, 325 .cache_flush = global_cache_flush, 326 327 // Efficeon-specific GATT table setup / populate / teardown 328 .create_gatt_table = efficeon_create_gatt_table, 329 .free_gatt_table = efficeon_free_gatt_table, 330 .insert_memory = efficeon_insert_memory, 331 .remove_memory = efficeon_remove_memory, 332 .cant_use_aperture = false, // true might be faster? 333 334 // Generic 335 .alloc_by_type = agp_generic_alloc_by_type, 336 .free_by_type = agp_generic_free_by_type, 337 .agp_alloc_page = agp_generic_alloc_page, 338 .agp_alloc_pages = agp_generic_alloc_pages, 339 .agp_destroy_page = agp_generic_destroy_page, 340 .agp_destroy_pages = agp_generic_destroy_pages, 341 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 342 }; 343 344 static int agp_efficeon_probe(struct pci_dev *pdev, 345 const struct pci_device_id *ent) 346 { 347 struct agp_bridge_data *bridge; 348 u8 cap_ptr; 349 struct resource *r; 350 351 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 352 if (!cap_ptr) 353 return -ENODEV; 354 355 /* Probe for Efficeon controller */ 356 if (pdev->device != PCI_DEVICE_ID_EFFICEON) { 357 printk(KERN_ERR PFX "Unsupported Efficeon chipset (device id: %04x)\n", 358 pdev->device); 359 return -ENODEV; 360 } 361 362 printk(KERN_INFO PFX "Detected Transmeta Efficeon TM8000 series chipset\n"); 363 364 bridge = agp_alloc_bridge(); 365 if (!bridge) 366 return -ENOMEM; 367 368 bridge->driver = &efficeon_driver; 369 bridge->dev = pdev; 370 bridge->capndx = cap_ptr; 371 372 /* 373 * If the device has not been properly setup, the following will catch 374 * the problem and should stop the system from crashing. 375 * 20030610 - hamish@zot.org 376 */ 377 if (pci_enable_device(pdev)) { 378 printk(KERN_ERR PFX "Unable to Enable PCI device\n"); 379 agp_put_bridge(bridge); 380 return -ENODEV; 381 } 382 383 /* 384 * The following fixes the case where the BIOS has "forgotten" to 385 * provide an address range for the GART. 386 * 20030610 - hamish@zot.org 387 */ 388 r = &pdev->resource[0]; 389 if (!r->start && r->end) { 390 if (pci_assign_resource(pdev, 0)) { 391 printk(KERN_ERR PFX "could not assign resource 0\n"); 392 agp_put_bridge(bridge); 393 return -ENODEV; 394 } 395 } 396 397 /* Fill in the mode register */ 398 if (cap_ptr) { 399 pci_read_config_dword(pdev, 400 bridge->capndx+PCI_AGP_STATUS, 401 &bridge->mode); 402 } 403 404 pci_set_drvdata(pdev, bridge); 405 return agp_add_bridge(bridge); 406 } 407 408 static void agp_efficeon_remove(struct pci_dev *pdev) 409 { 410 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 411 412 agp_remove_bridge(bridge); 413 agp_put_bridge(bridge); 414 } 415 416 static int agp_efficeon_resume(struct device *dev) 417 { 418 printk(KERN_DEBUG PFX "agp_efficeon_resume()\n"); 419 return efficeon_configure(); 420 } 421 422 static const struct pci_device_id agp_efficeon_pci_table[] = { 423 { 424 .class = (PCI_CLASS_BRIDGE_HOST << 8), 425 .class_mask = ~0, 426 .vendor = PCI_VENDOR_ID_TRANSMETA, 427 .device = PCI_ANY_ID, 428 .subvendor = PCI_ANY_ID, 429 .subdevice = PCI_ANY_ID, 430 }, 431 { } 432 }; 433 434 static DEFINE_SIMPLE_DEV_PM_OPS(agp_efficeon_pm_ops, NULL, agp_efficeon_resume); 435 436 MODULE_DEVICE_TABLE(pci, agp_efficeon_pci_table); 437 438 static struct pci_driver agp_efficeon_pci_driver = { 439 .name = "agpgart-efficeon", 440 .id_table = agp_efficeon_pci_table, 441 .probe = agp_efficeon_probe, 442 .remove = agp_efficeon_remove, 443 .driver.pm = &agp_efficeon_pm_ops, 444 }; 445 446 static int __init agp_efficeon_init(void) 447 { 448 static int agp_initialised=0; 449 450 if (agp_off) 451 return -EINVAL; 452 453 if (agp_initialised == 1) 454 return 0; 455 agp_initialised=1; 456 457 return pci_register_driver(&agp_efficeon_pci_driver); 458 } 459 460 static void __exit agp_efficeon_cleanup(void) 461 { 462 pci_unregister_driver(&agp_efficeon_pci_driver); 463 } 464 465 module_init(agp_efficeon_init); 466 module_exit(agp_efficeon_cleanup); 467 468 MODULE_AUTHOR("Carlos Puchol <cpglinux@puchol.com>"); 469 MODULE_DESCRIPTION("Transmeta's Efficeon AGPGART driver"); 470 MODULE_LICENSE("GPL and additional rights"); 471