1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Driver for AMD network controllers and boards 4 * 5 * Copyright (C) 2021, Xilinx, Inc. 6 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc. 7 */ 8 9 #ifndef MC_CDX_PCOL_H 10 #define MC_CDX_PCOL_H 11 12 /* The current version of the MCDI protocol. */ 13 #define MCDI_PCOL_VERSION 2 14 15 /* 16 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit 17 * structure, filled in by the client. 18 * 19 * 0 7 8 16 20 22 23 24 31 20 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 21 * | | | 22 * | | \--- Response 23 * | \------- Error 24 * \------------------------------ Resync (always set) 25 * 26 * The client writes its request into MC shared memory, and rings the 27 * doorbell. Each request is completed either by the MC writing 28 * back into shared memory, or by writing out an event. 29 * 30 * All MCDI commands support completion by shared memory response. Each 31 * request may also contain additional data (accounted for by HEADER.LEN), 32 * and some responses may also contain additional data (again, accounted 33 * for by HEADER.LEN). 34 * 35 * Some MCDI commands support completion by event, in which any associated 36 * response data is included in the event. 37 * 38 * The protocol requires one response to be delivered for every request; a 39 * request should not be sent unless the response for the previous request 40 * has been received (either by polling shared memory, or by receiving 41 * an event). 42 */ 43 44 /** Request/Response structure */ 45 #define MCDI_HEADER_OFST 0 46 #define MCDI_HEADER_CODE_LBN 0 47 #define MCDI_HEADER_CODE_WIDTH 7 48 #define MCDI_HEADER_RESYNC_LBN 7 49 #define MCDI_HEADER_RESYNC_WIDTH 1 50 #define MCDI_HEADER_DATALEN_LBN 8 51 #define MCDI_HEADER_DATALEN_WIDTH 8 52 #define MCDI_HEADER_SEQ_LBN 16 53 #define MCDI_HEADER_SEQ_WIDTH 4 54 #define MCDI_HEADER_RSVD_LBN 20 55 #define MCDI_HEADER_RSVD_WIDTH 1 56 #define MCDI_HEADER_NOT_EPOCH_LBN 21 57 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 58 #define MCDI_HEADER_ERROR_LBN 22 59 #define MCDI_HEADER_ERROR_WIDTH 1 60 #define MCDI_HEADER_RESPONSE_LBN 23 61 #define MCDI_HEADER_RESPONSE_WIDTH 1 62 #define MCDI_HEADER_XFLAGS_LBN 24 63 #define MCDI_HEADER_XFLAGS_WIDTH 8 64 /* Request response using event */ 65 #define MCDI_HEADER_XFLAGS_EVREQ 0x01 66 /* Request (and signal) early doorbell return */ 67 #define MCDI_HEADER_XFLAGS_DBRET 0x02 68 69 /* Maximum number of payload bytes */ 70 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 71 72 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 73 74 /* 75 * The MC can generate events for two reasons: 76 * - To advance a shared memory request if XFLAGS_EVREQ was set 77 * - As a notification (link state, i2c event), controlled 78 * via MC_CMD_LOG_CTRL 79 * 80 * Both events share a common structure: 81 * 82 * 0 32 33 36 44 52 60 83 * | Data | Cont | Level | Src | Code | Rsvd | 84 * | 85 * \ There is another event pending in this notification 86 * 87 * If Code==CMDDONE, then the fields are further interpreted as: 88 * 89 * - LEVEL==INFO Command succeeded 90 * - LEVEL==ERR Command failed 91 * 92 * 0 8 16 24 32 93 * | Seq | Datalen | Errno | Rsvd | 94 * 95 * These fields are taken directly out of the standard MCDI header, i.e., 96 * LEVEL==ERR, Datalen == 0 => Reboot 97 * 98 * Events can be squirted out of the UART (using LOG_CTRL) without a 99 * MCDI header. An event can be distinguished from a MCDI response by 100 * examining the first byte which is 0xc0. This corresponds to the 101 * non-existent MCDI command MC_CMD_DEBUG_LOG. 102 * 103 * 0 7 8 104 * | command | Resync | = 0xc0 105 * 106 * Since the event is written in big-endian byte order, this works 107 * providing bits 56-63 of the event are 0xc0. 108 * 109 * 56 60 63 110 * | Rsvd | Code | = 0xc0 111 * 112 * Which means for convenience the event code is 0xc for all MC 113 * generated events. 114 */ 115 116 /* 117 * the errno value may be followed by the (0-based) number of the 118 * first argument that could not be processed. 119 */ 120 #define MC_CMD_ERR_ARG_OFST 4 121 122 /* MC_CMD_ERR MCDI error codes. */ 123 /* Operation not permitted. */ 124 #define MC_CMD_ERR_EPERM 0x1 125 /* Non-existent command target */ 126 #define MC_CMD_ERR_ENOENT 0x2 127 /* assert() has killed the MC */ 128 #define MC_CMD_ERR_EINTR 0x4 129 /* I/O failure */ 130 #define MC_CMD_ERR_EIO 0x5 131 /* Already exists */ 132 #define MC_CMD_ERR_EEXIST 0x6 133 /* Try again */ 134 #define MC_CMD_ERR_EAGAIN 0xb 135 /* Out of memory */ 136 #define MC_CMD_ERR_ENOMEM 0xc 137 /* Caller does not hold required locks */ 138 #define MC_CMD_ERR_EACCES 0xd 139 /* Resource is currently unavailable (e.g. lock contention) */ 140 #define MC_CMD_ERR_EBUSY 0x10 141 /* No such device */ 142 #define MC_CMD_ERR_ENODEV 0x13 143 /* Invalid argument to target */ 144 #define MC_CMD_ERR_EINVAL 0x16 145 /* No space */ 146 #define MC_CMD_ERR_ENOSPC 0x1c 147 /* Read-only */ 148 #define MC_CMD_ERR_EROFS 0x1e 149 /* Broken pipe */ 150 #define MC_CMD_ERR_EPIPE 0x20 151 /* Out of range */ 152 #define MC_CMD_ERR_ERANGE 0x22 153 /* Non-recursive resource is already acquired */ 154 #define MC_CMD_ERR_EDEADLK 0x23 155 /* Operation not implemented */ 156 #define MC_CMD_ERR_ENOSYS 0x26 157 /* Operation timed out */ 158 #define MC_CMD_ERR_ETIME 0x3e 159 /* Link has been severed */ 160 #define MC_CMD_ERR_ENOLINK 0x43 161 /* Protocol error */ 162 #define MC_CMD_ERR_EPROTO 0x47 163 /* Bad message */ 164 #define MC_CMD_ERR_EBADMSG 0x4a 165 /* Operation not supported */ 166 #define MC_CMD_ERR_ENOTSUP 0x5f 167 /* Address not available */ 168 #define MC_CMD_ERR_EADDRNOTAVAIL 0x63 169 /* Not connected */ 170 #define MC_CMD_ERR_ENOTCONN 0x6b 171 /* Operation already in progress */ 172 #define MC_CMD_ERR_EALREADY 0x72 173 /* Stale handle. The handle references resource that no longer exists */ 174 #define MC_CMD_ERR_ESTALE 0x74 175 /* Resource allocation failed. */ 176 #define MC_CMD_ERR_ALLOC_FAIL 0x1000 177 /* V-adaptor not found. */ 178 #define MC_CMD_ERR_NO_VADAPTOR 0x1001 179 /* EVB port not found. */ 180 #define MC_CMD_ERR_NO_EVB_PORT 0x1002 181 /* V-switch not found. */ 182 #define MC_CMD_ERR_NO_VSWITCH 0x1003 183 /* Too many VLAN tags. */ 184 #define MC_CMD_ERR_VLAN_LIMIT 0x1004 185 /* Bad PCI function number. */ 186 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 187 /* Invalid VLAN mode. */ 188 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 189 /* Invalid v-switch type. */ 190 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 191 /* Invalid v-port type. */ 192 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 193 /* MAC address exists. */ 194 #define MC_CMD_ERR_MAC_EXIST 0x1009 195 /* Slave core not present */ 196 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a 197 /* The datapath is disabled. */ 198 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b 199 /* The requesting client is not a function */ 200 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c 201 /* 202 * The requested operation might require the command to be passed between 203 * MCs, and the transport doesn't support that. Should only ever been seen over 204 * the UART. 205 */ 206 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013 207 /* 208 * Workaround 26807 could not be turned on/off because some functions 209 * have already installed filters. See the comment at 210 * MC_CMD_WORKAROUND_BUG26807. May also returned for other operations such as 211 * sub-variant switching. 212 */ 213 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014 214 /* The clock whose frequency you've attempted to set doesn't exist */ 215 #define MC_CMD_ERR_NO_CLOCK 0x1015 216 /* 217 * Returned by MC_CMD_TESTASSERT if the action that should have caused an 218 * assertion failed to do so. 219 */ 220 #define MC_CMD_ERR_UNREACHABLE 0x1016 221 /* 222 * This command needs to be processed in the background but there were no 223 * resources to do so. Send it again after a command has completed. 224 */ 225 #define MC_CMD_ERR_QUEUE_FULL 0x1017 226 /* 227 * The operation could not be completed because the PCIe link has gone 228 * away. This error code is never expected to be returned over the TLP 229 * transport. 230 */ 231 #define MC_CMD_ERR_NO_PCIE 0x1018 232 /* 233 * The operation could not be completed because the datapath has gone 234 * away. This is distinct from MC_CMD_ERR_DATAPATH_DISABLED in that the 235 * datapath absence may be temporary 236 */ 237 #define MC_CMD_ERR_NO_DATAPATH 0x1019 238 /* The operation could not complete because some VIs are allocated */ 239 #define MC_CMD_ERR_VIS_PRESENT 0x101a 240 /* 241 * The operation could not complete because some PIO buffers are 242 * allocated 243 */ 244 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b 245 246 /***********************************/ 247 /* 248 * MC_CMD_CDX_BUS_ENUM_BUSES 249 * CDX bus hosts devices (functions) that are implemented using the Composable 250 * DMA subsystem and directly mapped into the memory space of the FGPA PSX 251 * Application Processors (APUs). As such, they only apply to the PSX APU side, 252 * not the host (PCIe). Unlike PCIe, these devices have no native configuration 253 * space or enumeration mechanism, so this message set provides a minimal 254 * interface for discovery and management (bus reset, FLR, BME) of such 255 * devices. This command returns the number of CDX buses present in the system. 256 */ 257 #define MC_CMD_CDX_BUS_ENUM_BUSES 0x1 258 #define MC_CMD_CDX_BUS_ENUM_BUSES_MSGSET 0x1 259 #undef MC_CMD_0x1_PRIVILEGE_CTG 260 261 #define MC_CMD_0x1_PRIVILEGE_CTG SRIOV_CTG_ADMIN 262 263 /* MC_CMD_CDX_BUS_ENUM_BUSES_IN msgrequest */ 264 #define MC_CMD_CDX_BUS_ENUM_BUSES_IN_LEN 0 265 266 /* MC_CMD_CDX_BUS_ENUM_BUSES_OUT msgresponse */ 267 #define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_LEN 4 268 /* 269 * Number of CDX buses present in the system. Buses are numbered 0 to 270 * BUS_COUNT-1 271 */ 272 #define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT_OFST 0 273 #define MC_CMD_CDX_BUS_ENUM_BUSES_OUT_BUS_COUNT_LEN 4 274 275 /***********************************/ 276 /* 277 * MC_CMD_CDX_BUS_ENUM_DEVICES 278 * Enumerate CDX bus devices on a given bus 279 */ 280 #define MC_CMD_CDX_BUS_ENUM_DEVICES 0x2 281 #define MC_CMD_CDX_BUS_ENUM_DEVICES_MSGSET 0x2 282 #undef MC_CMD_0x2_PRIVILEGE_CTG 283 284 #define MC_CMD_0x2_PRIVILEGE_CTG SRIOV_CTG_ADMIN 285 286 /* MC_CMD_CDX_BUS_ENUM_DEVICES_IN msgrequest */ 287 #define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_LEN 4 288 /* 289 * Bus number to enumerate, in range 0 to BUS_COUNT-1, as returned by 290 * MC_CMD_CDX_BUS_ENUM_BUSES_OUT 291 */ 292 #define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_BUS_OFST 0 293 #define MC_CMD_CDX_BUS_ENUM_DEVICES_IN_BUS_LEN 4 294 295 /* MC_CMD_CDX_BUS_ENUM_DEVICES_OUT msgresponse */ 296 #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_LEN 4 297 /* 298 * Number of devices present on the bus. Devices on the bus are numbered 0 to 299 * DEVICE_COUNT-1. Returns EAGAIN if number of devices unknown or if the target 300 * devices are not ready (e.g. undergoing a bus reset) 301 */ 302 #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_OFST 0 303 #define MC_CMD_CDX_BUS_ENUM_DEVICES_OUT_DEVICE_COUNT_LEN 4 304 305 /***********************************/ 306 /* 307 * MC_CMD_CDX_BUS_GET_DEVICE_CONFIG 308 * Returns device identification and MMIO/MSI resource data for a CDX device. 309 * The expected usage is for the caller to first retrieve the number of devices 310 * on the bus using MC_CMD_BUS_ENUM_DEVICES, then loop through the range (0, 311 * DEVICE_COUNT - 1), retrieving device resource data. May return EAGAIN if the 312 * number of exposed devices or device resources change during enumeration (due 313 * to e.g. a PL reload / bus reset), in which case the caller is expected to 314 * restart the enumeration loop. MMIO addresses are specified in terms of bus 315 * addresses (prior to any potential IOMMU translation). For versal-net, these 316 * are equivalent to APU physical addresses. Implementation note - for this to 317 * work, the implementation needs to keep state (generation count) per client. 318 */ 319 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG 0x3 320 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_MSGSET 0x3 321 #undef MC_CMD_0x3_PRIVILEGE_CTG 322 323 #define MC_CMD_0x3_PRIVILEGE_CTG SRIOV_CTG_ADMIN 324 325 /* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN msgrequest */ 326 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_LEN 8 327 /* Device bus number, in range 0 to BUS_COUNT-1 */ 328 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_BUS_OFST 0 329 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_BUS_LEN 4 330 /* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */ 331 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE_OFST 4 332 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE_LEN 4 333 334 /* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT msgresponse */ 335 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_LEN 88 336 /* 16-bit Vendor identifier, compliant with PCI-SIG VendorID assignment. */ 337 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID_OFST 0 338 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_VENDOR_ID_LEN 2 339 /* 16-bit Device ID assigned by the vendor */ 340 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID_OFST 2 341 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_ID_LEN 2 342 /* 343 * 16-bit Subsystem Vendor ID, , compliant with PCI-SIG VendorID assignment. 344 * For further device differentiation, as required. 0 if unused. 345 */ 346 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_VENDOR_ID_OFST 4 347 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_VENDOR_ID_LEN 2 348 /* 349 * 16-bit Subsystem Device ID assigned by the vendor. For further device 350 * differentiation, as required. 0 if unused. 351 */ 352 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_DEVICE_ID_OFST 6 353 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_SUBSYS_DEVICE_ID_LEN 2 354 /* 24-bit Device Class code, compliant with PCI-SIG Device Class codes */ 355 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_CLASS_OFST 8 356 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_CLASS_LEN 3 357 /* 8-bit vendor-assigned revision */ 358 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_REVISION_OFST 11 359 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_DEVICE_REVISION_LEN 1 360 /* Reserved (alignment) */ 361 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_RESERVED_OFST 12 362 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_RESERVED_LEN 4 363 /* MMIO region 0 base address (bus address), 0 if unused */ 364 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_OFST 16 365 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LEN 8 366 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_OFST 16 367 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_LEN 4 368 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_LBN 128 369 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_LO_WIDTH 32 370 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_OFST 20 371 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_LEN 4 372 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_LBN 160 373 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_BASE_HI_WIDTH 32 374 /* MMIO region 0 size, 0 if unused */ 375 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_OFST 24 376 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LEN 8 377 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_OFST 24 378 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_LEN 4 379 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_LBN 192 380 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_LO_WIDTH 32 381 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_OFST 28 382 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_LEN 4 383 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_LBN 224 384 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION0_SIZE_HI_WIDTH 32 385 /* MMIO region 1 base address (bus address), 0 if unused */ 386 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_OFST 32 387 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LEN 8 388 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_OFST 32 389 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_LEN 4 390 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_LBN 256 391 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_LO_WIDTH 32 392 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_OFST 36 393 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_LEN 4 394 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_LBN 288 395 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_BASE_HI_WIDTH 32 396 /* MMIO region 1 size, 0 if unused */ 397 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_OFST 40 398 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LEN 8 399 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_OFST 40 400 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_LEN 4 401 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_LBN 320 402 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_LO_WIDTH 32 403 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_OFST 44 404 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_LEN 4 405 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_LBN 352 406 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION1_SIZE_HI_WIDTH 32 407 /* MMIO region 2 base address (bus address), 0 if unused */ 408 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_OFST 48 409 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LEN 8 410 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_OFST 48 411 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_LEN 4 412 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_LBN 384 413 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_LO_WIDTH 32 414 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_OFST 52 415 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_LEN 4 416 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_LBN 416 417 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_BASE_HI_WIDTH 32 418 /* MMIO region 2 size, 0 if unused */ 419 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_OFST 56 420 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LEN 8 421 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_OFST 56 422 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_LEN 4 423 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_LBN 448 424 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_LO_WIDTH 32 425 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_OFST 60 426 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_LEN 4 427 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_LBN 480 428 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION2_SIZE_HI_WIDTH 32 429 /* MMIO region 3 base address (bus address), 0 if unused */ 430 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_OFST 64 431 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LEN 8 432 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_OFST 64 433 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_LEN 4 434 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_LBN 512 435 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_LO_WIDTH 32 436 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_OFST 68 437 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_LEN 4 438 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_LBN 544 439 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_BASE_HI_WIDTH 32 440 /* MMIO region 3 size, 0 if unused */ 441 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_OFST 72 442 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LEN 8 443 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_OFST 72 444 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_LEN 4 445 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_LBN 576 446 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_LO_WIDTH 32 447 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_OFST 76 448 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_LEN 4 449 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_LBN 608 450 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MMIO_REGION3_SIZE_HI_WIDTH 32 451 /* MSI vector count */ 452 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MSI_COUNT_OFST 80 453 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_MSI_COUNT_LEN 4 454 /* Requester ID used by device (SMMU StreamID, GIC ITS DeviceID) */ 455 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID_OFST 84 456 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_REQUESTER_ID_LEN 4 457 458 /* MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2 msgresponse */ 459 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_LEN 92 460 /* Requester ID used by device for GIC ITS DeviceID */ 461 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_REQUESTER_DEVICE_ID_OFST 88 462 #define MC_CMD_CDX_BUS_GET_DEVICE_CONFIG_OUT_V2_REQUESTER_DEVICE_ID_LEN 4 463 464 /***********************************/ 465 /* 466 * MC_CMD_CDX_BUS_DOWN 467 * Asserting reset on the CDX bus causes all devices on the bus to be quiesced. 468 * DMA bus mastering is disabled and any pending DMA request are flushed. Once 469 * the response is returned, the devices are guaranteed to no longer issue DMA 470 * requests or raise MSI interrupts. Further device MMIO accesses may have 471 * undefined results. While the bus reset is asserted, any of the enumeration 472 * or device configuration MCDIs will fail with EAGAIN. It is only legal to 473 * reload the relevant PL region containing CDX devices if the corresponding CDX 474 * bus is in reset. Depending on the implementation, the firmware may or may 475 * not enforce this restriction and it is up to the caller to make sure this 476 * requirement is satisfied. 477 */ 478 #define MC_CMD_CDX_BUS_DOWN 0x4 479 #define MC_CMD_CDX_BUS_DOWN_MSGSET 0x4 480 481 /* MC_CMD_CDX_BUS_DOWN_IN msgrequest */ 482 #define MC_CMD_CDX_BUS_DOWN_IN_LEN 4 483 /* Bus number to put in reset, in range 0 to BUS_COUNT-1 */ 484 #define MC_CMD_CDX_BUS_DOWN_IN_BUS_OFST 0 485 #define MC_CMD_CDX_BUS_DOWN_IN_BUS_LEN 4 486 487 /* 488 * MC_CMD_CDX_BUS_DOWN_OUT msgresponse: The bus is quiesced, no further 489 * upstream traffic for devices on this bus. 490 */ 491 #define MC_CMD_CDX_BUS_DOWN_OUT_LEN 0 492 493 /***********************************/ 494 /* 495 * MC_CMD_CDX_BUS_UP 496 * After bus reset is de-asserted, devices are in a state which is functionally 497 * equivalent to each device having been reset with MC_CMD_CDX_DEVICE_RESET. In 498 * other words, device logic is reset in a hardware-specific way, MMIO accesses 499 * are forwarded to the device, DMA bus mastering is disabled and needs to be 500 * re-enabled with MC_CMD_CDX_DEVICE_DMA_ENABLE once the driver is ready to 501 * start servicing DMA. If the underlying number of devices or device resources 502 * changed (e.g. if PL was reloaded) while the bus was in reset, the bus driver 503 * is expected to re-enumerate the bus. Returns EALREADY if the bus was already 504 * up before the call. 505 */ 506 #define MC_CMD_CDX_BUS_UP 0x5 507 #define MC_CMD_CDX_BUS_UP_MSGSET 0x5 508 509 /* MC_CMD_CDX_BUS_UP_IN msgrequest */ 510 #define MC_CMD_CDX_BUS_UP_IN_LEN 4 511 /* Bus number to take out of reset, in range 0 to BUS_COUNT-1 */ 512 #define MC_CMD_CDX_BUS_UP_IN_BUS_OFST 0 513 #define MC_CMD_CDX_BUS_UP_IN_BUS_LEN 4 514 515 /* MC_CMD_CDX_BUS_UP_OUT msgresponse: The bus can now be enumerated. */ 516 #define MC_CMD_CDX_BUS_UP_OUT_LEN 0 517 518 /***********************************/ 519 /* 520 * MC_CMD_CDX_DEVICE_RESET 521 * After this call completes, device DMA and interrupts are quiesced, devices 522 * logic is reset in a hardware-specific way and DMA bus mastering is disabled. 523 */ 524 #define MC_CMD_CDX_DEVICE_RESET 0x6 525 #define MC_CMD_CDX_DEVICE_RESET_MSGSET 0x6 526 #undef MC_CMD_0x6_PRIVILEGE_CTG 527 528 #define MC_CMD_0x6_PRIVILEGE_CTG SRIOV_CTG_ADMIN 529 530 /* MC_CMD_CDX_DEVICE_RESET_IN msgrequest */ 531 #define MC_CMD_CDX_DEVICE_RESET_IN_LEN 8 532 /* Device bus number, in range 0 to BUS_COUNT-1 */ 533 #define MC_CMD_CDX_DEVICE_RESET_IN_BUS_OFST 0 534 #define MC_CMD_CDX_DEVICE_RESET_IN_BUS_LEN 4 535 /* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */ 536 #define MC_CMD_CDX_DEVICE_RESET_IN_DEVICE_OFST 4 537 #define MC_CMD_CDX_DEVICE_RESET_IN_DEVICE_LEN 4 538 539 /* 540 * MC_CMD_CDX_DEVICE_RESET_OUT msgresponse: The device is quiesced and all 541 * pending device initiated DMA has completed. 542 */ 543 #define MC_CMD_CDX_DEVICE_RESET_OUT_LEN 0 544 545 /***********************************/ 546 /* 547 * MC_CMD_CDX_DEVICE_CONTROL_SET 548 * If BUS_MASTER is set to disabled, device DMA and interrupts are quiesced. 549 * Pending DMA requests and MSI interrupts are flushed and no further DMA or 550 * interrupts are issued after this command returns. If BUS_MASTER is set to 551 * enabled, device is allowed to initiate DMA. Whether interrupts are enabled 552 * also depends on the value of MSI_ENABLE bit. Note that, in this case, the 553 * device may start DMA before the host receives and processes the MCDI 554 * response. MSI_ENABLE masks or unmasks device interrupts only. Note that for 555 * interrupts to be delivered to the host, both BUS_MASTER and MSI_ENABLE needs 556 * to be set. MMIO_REGIONS_ENABLE enables or disables host accesses to device 557 * MMIO regions. Note that an implementation is allowed to permanently set this 558 * bit to 1, in which case MC_CMD_CDX_DEVICE_CONTROL_GET will always return 1 559 * for this bit, regardless of the value set here. 560 */ 561 #define MC_CMD_CDX_DEVICE_CONTROL_SET 0x7 562 #define MC_CMD_CDX_DEVICE_CONTROL_SET_MSGSET 0x7 563 #undef MC_CMD_0x7_PRIVILEGE_CTG 564 565 #define MC_CMD_0x7_PRIVILEGE_CTG SRIOV_CTG_ADMIN 566 567 /* MC_CMD_CDX_DEVICE_CONTROL_SET_IN msgrequest */ 568 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_LEN 12 569 /* Device bus number, in range 0 to BUS_COUNT-1 */ 570 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_OFST 0 571 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_LEN 4 572 /* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */ 573 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_DEVICE_OFST 4 574 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_DEVICE_LEN 4 575 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_FLAGS_OFST 8 576 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_FLAGS_LEN 4 577 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_OFST 8 578 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_LBN 0 579 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_BUS_MASTER_ENABLE_WIDTH 1 580 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_OFST 8 581 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_LBN 1 582 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MSI_ENABLE_WIDTH 1 583 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_OFST 8 584 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_LBN 2 585 #define MC_CMD_CDX_DEVICE_CONTROL_SET_IN_MMIO_REGIONS_ENABLE_WIDTH 1 586 587 /* MC_CMD_CDX_DEVICE_CONTROL_SET_OUT msgresponse */ 588 #define MC_CMD_CDX_DEVICE_CONTROL_SET_OUT_LEN 0 589 590 /***********************************/ 591 /* 592 * MC_CMD_CDX_DEVICE_CONTROL_GET 593 * Returns device DMA, interrupt and MMIO region access control bits. See 594 * MC_CMD_CDX_DEVICE_CONTROL_SET for definition of the available control bits. 595 */ 596 #define MC_CMD_CDX_DEVICE_CONTROL_GET 0x8 597 #define MC_CMD_CDX_DEVICE_CONTROL_GET_MSGSET 0x8 598 #undef MC_CMD_0x8_PRIVILEGE_CTG 599 600 #define MC_CMD_0x8_PRIVILEGE_CTG SRIOV_CTG_ADMIN 601 602 /* MC_CMD_CDX_DEVICE_CONTROL_GET_IN msgrequest */ 603 #define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_LEN 8 604 /* Device bus number, in range 0 to BUS_COUNT-1 */ 605 #define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_BUS_OFST 0 606 #define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_BUS_LEN 4 607 /* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */ 608 #define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_DEVICE_OFST 4 609 #define MC_CMD_CDX_DEVICE_CONTROL_GET_IN_DEVICE_LEN 4 610 611 /* MC_CMD_CDX_DEVICE_CONTROL_GET_OUT msgresponse */ 612 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_LEN 4 613 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_FLAGS_OFST 0 614 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_FLAGS_LEN 4 615 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_OFST 0 616 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_LBN 0 617 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_BUS_MASTER_ENABLE_WIDTH 1 618 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_OFST 0 619 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_LBN 1 620 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MSI_ENABLE_WIDTH 1 621 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_OFST 0 622 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_LBN 2 623 #define MC_CMD_CDX_DEVICE_CONTROL_GET_OUT_MMIO_REGIONS_ENABLE_WIDTH 1 624 625 /***********************************/ 626 /* 627 * MC_CMD_CDX_DEVICE_WRITE_MSI_MSG 628 * Populates the MSI message to be used by the hardware to raise the specified 629 * interrupt vector. Versal-net implementation specific limitations are that 630 * only 4 CDX devices with MSI interrupt capability are supported and all 631 * vectors within a device must use the same write address. The command will 632 * return EINVAL if any of these limitations is violated. 633 */ 634 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG 0x9 635 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_MSGSET 0x9 636 #undef MC_CMD_0x9_PRIVILEGE_CTG 637 638 #define MC_CMD_0x9_PRIVILEGE_CTG SRIOV_CTG_ADMIN 639 640 /* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN msgrequest */ 641 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_LEN 28 642 /* Device bus number, in range 0 to BUS_COUNT-1 */ 643 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_BUS_OFST 0 644 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_BUS_LEN 4 645 /* Device number relative to the bus, in range 0 to DEVICE_COUNT-1 for that bus */ 646 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_DEVICE_OFST 4 647 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_DEVICE_LEN 4 648 /* 649 * Device-relative MSI vector number. Must be < MSI_COUNT reported for the 650 * device. 651 */ 652 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_VECTOR_OFST 8 653 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_VECTOR_LEN 4 654 /* Reserved (alignment) */ 655 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_RESERVED_OFST 12 656 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_RESERVED_LEN 4 657 /* 658 * MSI address to be used by the hardware. Typically, on ARM systems this 659 * address is translated by the IOMMU (if enabled) and it is the responsibility 660 * of the entity managing the IOMMU (APU kernel) to supply the correct IOVA 661 * here. 662 */ 663 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_OFST 16 664 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LEN 8 665 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_OFST 16 666 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_LEN 4 667 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_LBN 128 668 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_LO_WIDTH 32 669 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_OFST 20 670 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_LEN 4 671 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_LBN 160 672 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_ADDRESS_HI_WIDTH 32 673 /* 674 * MSI data to be used by the hardware. On versal-net, only the lower 16-bits 675 * are used, the remaining bits are ignored and should be set to zero. 676 */ 677 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_DATA_OFST 24 678 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_IN_MSI_DATA_LEN 4 679 680 /* MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_OUT msgresponse */ 681 #define MC_CMD_CDX_DEVICE_WRITE_MSI_MSG_OUT_LEN 0 682 683 /***********************************/ 684 /* MC_CMD_V2_EXTN - Encapsulation for a v2 extended command */ 685 #define MC_CMD_V2_EXTN 0x7f 686 687 /* MC_CMD_V2_EXTN_IN msgrequest */ 688 #define MC_CMD_V2_EXTN_IN_LEN 4 689 /* the extended command number */ 690 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0 691 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15 692 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15 693 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1 694 /* the actual length of the encapsulated command */ 695 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16 696 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10 697 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26 698 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 2 699 /* Type of command/response */ 700 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_LBN 28 701 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4 702 /* 703 * enum: MCDI command directed to versal-net. MCDI responses of this type 704 * are not defined. 705 */ 706 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM 0x2 707 708 #endif /* MC_CDX_PCOL_H */ 709