1 /* 2 * ti-sysc.c - Texas Instruments sysc interconnect target driver 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/delay.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 #include <linux/of_address.h> 24 #include <linux/of_platform.h> 25 #include <linux/slab.h> 26 #include <linux/iopoll.h> 27 28 #include <linux/platform_data/ti-sysc.h> 29 30 #include <dt-bindings/bus/ti-sysc.h> 31 32 #define MAX_MODULE_SOFTRESET_WAIT 10000 33 34 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 35 36 enum sysc_clocks { 37 SYSC_FCK, 38 SYSC_ICK, 39 SYSC_OPTFCK0, 40 SYSC_OPTFCK1, 41 SYSC_OPTFCK2, 42 SYSC_OPTFCK3, 43 SYSC_OPTFCK4, 44 SYSC_OPTFCK5, 45 SYSC_OPTFCK6, 46 SYSC_OPTFCK7, 47 SYSC_MAX_CLOCKS, 48 }; 49 50 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 51 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 52 "opt5", "opt6", "opt7", 53 }; 54 55 #define SYSC_IDLEMODE_MASK 3 56 #define SYSC_CLOCKACTIVITY_MASK 3 57 58 /** 59 * struct sysc - TI sysc interconnect target module registers and capabilities 60 * @dev: struct device pointer 61 * @module_pa: physical address of the interconnect target module 62 * @module_size: size of the interconnect target module 63 * @module_va: virtual address of the interconnect target module 64 * @offsets: register offsets from module base 65 * @clocks: clocks used by the interconnect target module 66 * @clock_roles: clock role names for the found clocks 67 * @nr_clocks: number of clocks used by the interconnect target module 68 * @legacy_mode: configured for legacy mode if set 69 * @cap: interconnect target module capabilities 70 * @cfg: interconnect target module configuration 71 * @name: name if available 72 * @revision: interconnect target module revision 73 * @needs_resume: runtime resume needed on resume from suspend 74 * @clk_enable_quirk: module specific clock enable quirk 75 * @clk_disable_quirk: module specific clock disable quirk 76 * @reset_done_quirk: module specific reset done quirk 77 */ 78 struct sysc { 79 struct device *dev; 80 u64 module_pa; 81 u32 module_size; 82 void __iomem *module_va; 83 int offsets[SYSC_MAX_REGS]; 84 struct ti_sysc_module_data *mdata; 85 struct clk **clocks; 86 const char **clock_roles; 87 int nr_clocks; 88 struct reset_control *rsts; 89 const char *legacy_mode; 90 const struct sysc_capabilities *cap; 91 struct sysc_config cfg; 92 struct ti_sysc_cookie cookie; 93 const char *name; 94 u32 revision; 95 unsigned int enabled:1; 96 unsigned int needs_resume:1; 97 unsigned int child_needs_resume:1; 98 unsigned int disable_on_idle:1; 99 struct delayed_work idle_work; 100 void (*clk_enable_quirk)(struct sysc *sysc); 101 void (*clk_disable_quirk)(struct sysc *sysc); 102 void (*reset_done_quirk)(struct sysc *sysc); 103 }; 104 105 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 106 bool is_child); 107 108 static void sysc_write(struct sysc *ddata, int offset, u32 value) 109 { 110 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 111 writew_relaxed(value & 0xffff, ddata->module_va + offset); 112 113 /* Only i2c revision has LO and HI register with stride of 4 */ 114 if (ddata->offsets[SYSC_REVISION] >= 0 && 115 offset == ddata->offsets[SYSC_REVISION]) { 116 u16 hi = value >> 16; 117 118 writew_relaxed(hi, ddata->module_va + offset + 4); 119 } 120 121 return; 122 } 123 124 writel_relaxed(value, ddata->module_va + offset); 125 } 126 127 static u32 sysc_read(struct sysc *ddata, int offset) 128 { 129 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 130 u32 val; 131 132 val = readw_relaxed(ddata->module_va + offset); 133 134 /* Only i2c revision has LO and HI register with stride of 4 */ 135 if (ddata->offsets[SYSC_REVISION] >= 0 && 136 offset == ddata->offsets[SYSC_REVISION]) { 137 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 138 139 val |= tmp << 16; 140 } 141 142 return val; 143 } 144 145 return readl_relaxed(ddata->module_va + offset); 146 } 147 148 static bool sysc_opt_clks_needed(struct sysc *ddata) 149 { 150 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 151 } 152 153 static u32 sysc_read_revision(struct sysc *ddata) 154 { 155 int offset = ddata->offsets[SYSC_REVISION]; 156 157 if (offset < 0) 158 return 0; 159 160 return sysc_read(ddata, offset); 161 } 162 163 static u32 sysc_read_sysconfig(struct sysc *ddata) 164 { 165 int offset = ddata->offsets[SYSC_SYSCONFIG]; 166 167 if (offset < 0) 168 return 0; 169 170 return sysc_read(ddata, offset); 171 } 172 173 static u32 sysc_read_sysstatus(struct sysc *ddata) 174 { 175 int offset = ddata->offsets[SYSC_SYSSTATUS]; 176 177 if (offset < 0) 178 return 0; 179 180 return sysc_read(ddata, offset); 181 } 182 183 static int sysc_add_named_clock_from_child(struct sysc *ddata, 184 const char *name, 185 const char *optfck_name) 186 { 187 struct device_node *np = ddata->dev->of_node; 188 struct device_node *child; 189 struct clk_lookup *cl; 190 struct clk *clock; 191 const char *n; 192 193 if (name) 194 n = name; 195 else 196 n = optfck_name; 197 198 /* Does the clock alias already exist? */ 199 clock = of_clk_get_by_name(np, n); 200 if (!IS_ERR(clock)) { 201 clk_put(clock); 202 203 return 0; 204 } 205 206 child = of_get_next_available_child(np, NULL); 207 if (!child) 208 return -ENODEV; 209 210 clock = devm_get_clk_from_child(ddata->dev, child, name); 211 if (IS_ERR(clock)) 212 return PTR_ERR(clock); 213 214 /* 215 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 216 * limit for clk_get(). If cl ever needs to be freed, it should be done 217 * with clkdev_drop(). 218 */ 219 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); 220 if (!cl) 221 return -ENOMEM; 222 223 cl->con_id = n; 224 cl->dev_id = dev_name(ddata->dev); 225 cl->clk = clock; 226 clkdev_add(cl); 227 228 clk_put(clock); 229 230 return 0; 231 } 232 233 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 234 { 235 const char *optfck_name; 236 int error, index; 237 238 if (ddata->nr_clocks < SYSC_OPTFCK0) 239 index = SYSC_OPTFCK0; 240 else 241 index = ddata->nr_clocks; 242 243 if (name) 244 optfck_name = name; 245 else 246 optfck_name = clock_names[index]; 247 248 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 249 if (error) 250 return error; 251 252 ddata->clock_roles[index] = optfck_name; 253 ddata->nr_clocks++; 254 255 return 0; 256 } 257 258 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 259 { 260 int error, i, index = -ENODEV; 261 262 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 263 index = SYSC_FCK; 264 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 265 index = SYSC_ICK; 266 267 if (index < 0) { 268 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 269 if (!ddata->clocks[i]) { 270 index = i; 271 break; 272 } 273 } 274 } 275 276 if (index < 0) { 277 dev_err(ddata->dev, "clock %s not added\n", name); 278 return index; 279 } 280 281 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 282 if (IS_ERR(ddata->clocks[index])) { 283 if (PTR_ERR(ddata->clocks[index]) == -ENOENT) 284 return 0; 285 286 dev_err(ddata->dev, "clock get error for %s: %li\n", 287 name, PTR_ERR(ddata->clocks[index])); 288 289 return PTR_ERR(ddata->clocks[index]); 290 } 291 292 error = clk_prepare(ddata->clocks[index]); 293 if (error) { 294 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 295 name, error); 296 297 return error; 298 } 299 300 return 0; 301 } 302 303 static int sysc_get_clocks(struct sysc *ddata) 304 { 305 struct device_node *np = ddata->dev->of_node; 306 struct property *prop; 307 const char *name; 308 int nr_fck = 0, nr_ick = 0, i, error = 0; 309 310 ddata->clock_roles = devm_kcalloc(ddata->dev, 311 SYSC_MAX_CLOCKS, 312 sizeof(*ddata->clock_roles), 313 GFP_KERNEL); 314 if (!ddata->clock_roles) 315 return -ENOMEM; 316 317 of_property_for_each_string(np, "clock-names", prop, name) { 318 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 319 nr_fck++; 320 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 321 nr_ick++; 322 ddata->clock_roles[ddata->nr_clocks] = name; 323 ddata->nr_clocks++; 324 } 325 326 if (ddata->nr_clocks < 1) 327 return 0; 328 329 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 330 error = sysc_init_ext_opt_clock(ddata, NULL); 331 if (error) 332 return error; 333 } 334 335 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 336 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 337 338 return -EINVAL; 339 } 340 341 if (nr_fck > 1 || nr_ick > 1) { 342 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 343 344 return -EINVAL; 345 } 346 347 ddata->clocks = devm_kcalloc(ddata->dev, 348 ddata->nr_clocks, sizeof(*ddata->clocks), 349 GFP_KERNEL); 350 if (!ddata->clocks) 351 return -ENOMEM; 352 353 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 354 const char *name = ddata->clock_roles[i]; 355 356 if (!name) 357 continue; 358 359 error = sysc_get_one_clock(ddata, name); 360 if (error && error != -ENOENT) 361 return error; 362 } 363 364 return 0; 365 } 366 367 static int sysc_enable_main_clocks(struct sysc *ddata) 368 { 369 struct clk *clock; 370 int i, error; 371 372 if (!ddata->clocks) 373 return 0; 374 375 for (i = 0; i < SYSC_OPTFCK0; i++) { 376 clock = ddata->clocks[i]; 377 378 /* Main clocks may not have ick */ 379 if (IS_ERR_OR_NULL(clock)) 380 continue; 381 382 error = clk_enable(clock); 383 if (error) 384 goto err_disable; 385 } 386 387 return 0; 388 389 err_disable: 390 for (i--; i >= 0; i--) { 391 clock = ddata->clocks[i]; 392 393 /* Main clocks may not have ick */ 394 if (IS_ERR_OR_NULL(clock)) 395 continue; 396 397 clk_disable(clock); 398 } 399 400 return error; 401 } 402 403 static void sysc_disable_main_clocks(struct sysc *ddata) 404 { 405 struct clk *clock; 406 int i; 407 408 if (!ddata->clocks) 409 return; 410 411 for (i = 0; i < SYSC_OPTFCK0; i++) { 412 clock = ddata->clocks[i]; 413 if (IS_ERR_OR_NULL(clock)) 414 continue; 415 416 clk_disable(clock); 417 } 418 } 419 420 static int sysc_enable_opt_clocks(struct sysc *ddata) 421 { 422 struct clk *clock; 423 int i, error; 424 425 if (!ddata->clocks) 426 return 0; 427 428 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 429 clock = ddata->clocks[i]; 430 431 /* Assume no holes for opt clocks */ 432 if (IS_ERR_OR_NULL(clock)) 433 return 0; 434 435 error = clk_enable(clock); 436 if (error) 437 goto err_disable; 438 } 439 440 return 0; 441 442 err_disable: 443 for (i--; i >= 0; i--) { 444 clock = ddata->clocks[i]; 445 if (IS_ERR_OR_NULL(clock)) 446 continue; 447 448 clk_disable(clock); 449 } 450 451 return error; 452 } 453 454 static void sysc_disable_opt_clocks(struct sysc *ddata) 455 { 456 struct clk *clock; 457 int i; 458 459 if (!ddata->clocks) 460 return; 461 462 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 463 clock = ddata->clocks[i]; 464 465 /* Assume no holes for opt clocks */ 466 if (IS_ERR_OR_NULL(clock)) 467 return; 468 469 clk_disable(clock); 470 } 471 } 472 473 static void sysc_clkdm_deny_idle(struct sysc *ddata) 474 { 475 struct ti_sysc_platform_data *pdata; 476 477 if (ddata->legacy_mode) 478 return; 479 480 pdata = dev_get_platdata(ddata->dev); 481 if (pdata && pdata->clkdm_deny_idle) 482 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 483 } 484 485 static void sysc_clkdm_allow_idle(struct sysc *ddata) 486 { 487 struct ti_sysc_platform_data *pdata; 488 489 if (ddata->legacy_mode) 490 return; 491 492 pdata = dev_get_platdata(ddata->dev); 493 if (pdata && pdata->clkdm_allow_idle) 494 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 495 } 496 497 /** 498 * sysc_init_resets - init rstctrl reset line if configured 499 * @ddata: device driver data 500 * 501 * See sysc_rstctrl_reset_deassert(). 502 */ 503 static int sysc_init_resets(struct sysc *ddata) 504 { 505 ddata->rsts = 506 devm_reset_control_get_optional(ddata->dev, "rstctrl"); 507 if (IS_ERR(ddata->rsts)) 508 return PTR_ERR(ddata->rsts); 509 510 return 0; 511 } 512 513 /** 514 * sysc_parse_and_check_child_range - parses module IO region from ranges 515 * @ddata: device driver data 516 * 517 * In general we only need rev, syss, and sysc registers and not the whole 518 * module range. But we do want the offsets for these registers from the 519 * module base. This allows us to check them against the legacy hwmod 520 * platform data. Let's also check the ranges are configured properly. 521 */ 522 static int sysc_parse_and_check_child_range(struct sysc *ddata) 523 { 524 struct device_node *np = ddata->dev->of_node; 525 const __be32 *ranges; 526 u32 nr_addr, nr_size; 527 int len, error; 528 529 ranges = of_get_property(np, "ranges", &len); 530 if (!ranges) { 531 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 532 533 return -ENOENT; 534 } 535 536 len /= sizeof(*ranges); 537 538 if (len < 3) { 539 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 540 541 return -EINVAL; 542 } 543 544 error = of_property_read_u32(np, "#address-cells", &nr_addr); 545 if (error) 546 return -ENOENT; 547 548 error = of_property_read_u32(np, "#size-cells", &nr_size); 549 if (error) 550 return -ENOENT; 551 552 if (nr_addr != 1 || nr_size != 1) { 553 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 554 555 return -EINVAL; 556 } 557 558 ranges++; 559 ddata->module_pa = of_translate_address(np, ranges++); 560 ddata->module_size = be32_to_cpup(ranges); 561 562 return 0; 563 } 564 565 static struct device_node *stdout_path; 566 567 static void sysc_init_stdout_path(struct sysc *ddata) 568 { 569 struct device_node *np = NULL; 570 const char *uart; 571 572 if (IS_ERR(stdout_path)) 573 return; 574 575 if (stdout_path) 576 return; 577 578 np = of_find_node_by_path("/chosen"); 579 if (!np) 580 goto err; 581 582 uart = of_get_property(np, "stdout-path", NULL); 583 if (!uart) 584 goto err; 585 586 np = of_find_node_by_path(uart); 587 if (!np) 588 goto err; 589 590 stdout_path = np; 591 592 return; 593 594 err: 595 stdout_path = ERR_PTR(-ENODEV); 596 } 597 598 static void sysc_check_quirk_stdout(struct sysc *ddata, 599 struct device_node *np) 600 { 601 sysc_init_stdout_path(ddata); 602 if (np != stdout_path) 603 return; 604 605 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 606 SYSC_QUIRK_NO_RESET_ON_INIT; 607 } 608 609 /** 610 * sysc_check_one_child - check child configuration 611 * @ddata: device driver data 612 * @np: child device node 613 * 614 * Let's avoid messy situations where we have new interconnect target 615 * node but children have "ti,hwmods". These belong to the interconnect 616 * target node and are managed by this driver. 617 */ 618 static int sysc_check_one_child(struct sysc *ddata, 619 struct device_node *np) 620 { 621 const char *name; 622 623 name = of_get_property(np, "ti,hwmods", NULL); 624 if (name) 625 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 626 627 sysc_check_quirk_stdout(ddata, np); 628 sysc_parse_dts_quirks(ddata, np, true); 629 630 return 0; 631 } 632 633 static int sysc_check_children(struct sysc *ddata) 634 { 635 struct device_node *child; 636 int error; 637 638 for_each_child_of_node(ddata->dev->of_node, child) { 639 error = sysc_check_one_child(ddata, child); 640 if (error) 641 return error; 642 } 643 644 return 0; 645 } 646 647 /* 648 * So far only I2C uses 16-bit read access with clockactivity with revision 649 * in two registers with stride of 4. We can detect this based on the rev 650 * register size to configure things far enough to be able to properly read 651 * the revision register. 652 */ 653 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 654 { 655 if (resource_size(res) == 8) 656 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 657 } 658 659 /** 660 * sysc_parse_one - parses the interconnect target module registers 661 * @ddata: device driver data 662 * @reg: register to parse 663 */ 664 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 665 { 666 struct resource *res; 667 const char *name; 668 669 switch (reg) { 670 case SYSC_REVISION: 671 case SYSC_SYSCONFIG: 672 case SYSC_SYSSTATUS: 673 name = reg_names[reg]; 674 break; 675 default: 676 return -EINVAL; 677 } 678 679 res = platform_get_resource_byname(to_platform_device(ddata->dev), 680 IORESOURCE_MEM, name); 681 if (!res) { 682 ddata->offsets[reg] = -ENODEV; 683 684 return 0; 685 } 686 687 ddata->offsets[reg] = res->start - ddata->module_pa; 688 if (reg == SYSC_REVISION) 689 sysc_check_quirk_16bit(ddata, res); 690 691 return 0; 692 } 693 694 static int sysc_parse_registers(struct sysc *ddata) 695 { 696 int i, error; 697 698 for (i = 0; i < SYSC_MAX_REGS; i++) { 699 error = sysc_parse_one(ddata, i); 700 if (error) 701 return error; 702 } 703 704 return 0; 705 } 706 707 /** 708 * sysc_check_registers - check for misconfigured register overlaps 709 * @ddata: device driver data 710 */ 711 static int sysc_check_registers(struct sysc *ddata) 712 { 713 int i, j, nr_regs = 0, nr_matches = 0; 714 715 for (i = 0; i < SYSC_MAX_REGS; i++) { 716 if (ddata->offsets[i] < 0) 717 continue; 718 719 if (ddata->offsets[i] > (ddata->module_size - 4)) { 720 dev_err(ddata->dev, "register outside module range"); 721 722 return -EINVAL; 723 } 724 725 for (j = 0; j < SYSC_MAX_REGS; j++) { 726 if (ddata->offsets[j] < 0) 727 continue; 728 729 if (ddata->offsets[i] == ddata->offsets[j]) 730 nr_matches++; 731 } 732 nr_regs++; 733 } 734 735 if (nr_matches > nr_regs) { 736 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 737 nr_regs, nr_matches); 738 739 return -EINVAL; 740 } 741 742 return 0; 743 } 744 745 /** 746 * syc_ioremap - ioremap register space for the interconnect target module 747 * @ddata: device driver data 748 * 749 * Note that the interconnect target module registers can be anywhere 750 * within the interconnect target module range. For example, SGX has 751 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 752 * has them at offset 0x1200 in the CPSW_WR child. Usually the 753 * the interconnect target module registers are at the beginning of 754 * the module range though. 755 */ 756 static int sysc_ioremap(struct sysc *ddata) 757 { 758 int size; 759 760 if (ddata->offsets[SYSC_REVISION] < 0 && 761 ddata->offsets[SYSC_SYSCONFIG] < 0 && 762 ddata->offsets[SYSC_SYSSTATUS] < 0) { 763 size = ddata->module_size; 764 } else { 765 size = max3(ddata->offsets[SYSC_REVISION], 766 ddata->offsets[SYSC_SYSCONFIG], 767 ddata->offsets[SYSC_SYSSTATUS]); 768 769 if (size < SZ_1K) 770 size = SZ_1K; 771 772 if ((size + sizeof(u32)) > ddata->module_size) 773 size = ddata->module_size; 774 } 775 776 ddata->module_va = devm_ioremap(ddata->dev, 777 ddata->module_pa, 778 size + sizeof(u32)); 779 if (!ddata->module_va) 780 return -EIO; 781 782 return 0; 783 } 784 785 /** 786 * sysc_map_and_check_registers - ioremap and check device registers 787 * @ddata: device driver data 788 */ 789 static int sysc_map_and_check_registers(struct sysc *ddata) 790 { 791 int error; 792 793 error = sysc_parse_and_check_child_range(ddata); 794 if (error) 795 return error; 796 797 error = sysc_check_children(ddata); 798 if (error) 799 return error; 800 801 error = sysc_parse_registers(ddata); 802 if (error) 803 return error; 804 805 error = sysc_ioremap(ddata); 806 if (error) 807 return error; 808 809 error = sysc_check_registers(ddata); 810 if (error) 811 return error; 812 813 return 0; 814 } 815 816 /** 817 * sysc_show_rev - read and show interconnect target module revision 818 * @bufp: buffer to print the information to 819 * @ddata: device driver data 820 */ 821 static int sysc_show_rev(char *bufp, struct sysc *ddata) 822 { 823 int len; 824 825 if (ddata->offsets[SYSC_REVISION] < 0) 826 return sprintf(bufp, ":NA"); 827 828 len = sprintf(bufp, ":%08x", ddata->revision); 829 830 return len; 831 } 832 833 static int sysc_show_reg(struct sysc *ddata, 834 char *bufp, enum sysc_registers reg) 835 { 836 if (ddata->offsets[reg] < 0) 837 return sprintf(bufp, ":NA"); 838 839 return sprintf(bufp, ":%x", ddata->offsets[reg]); 840 } 841 842 static int sysc_show_name(char *bufp, struct sysc *ddata) 843 { 844 if (!ddata->name) 845 return 0; 846 847 return sprintf(bufp, ":%s", ddata->name); 848 } 849 850 /** 851 * sysc_show_registers - show information about interconnect target module 852 * @ddata: device driver data 853 */ 854 static void sysc_show_registers(struct sysc *ddata) 855 { 856 char buf[128]; 857 char *bufp = buf; 858 int i; 859 860 for (i = 0; i < SYSC_MAX_REGS; i++) 861 bufp += sysc_show_reg(ddata, bufp, i); 862 863 bufp += sysc_show_rev(bufp, ddata); 864 bufp += sysc_show_name(bufp, ddata); 865 866 dev_dbg(ddata->dev, "%llx:%x%s\n", 867 ddata->module_pa, ddata->module_size, 868 buf); 869 } 870 871 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 872 #define SYSC_CLOCACT_ICK 2 873 874 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 875 static int sysc_enable_module(struct device *dev) 876 { 877 struct sysc *ddata; 878 const struct sysc_regbits *regbits; 879 u32 reg, idlemodes, best_mode; 880 881 ddata = dev_get_drvdata(dev); 882 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 883 return 0; 884 885 regbits = ddata->cap->regbits; 886 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 887 888 /* Set CLOCKACTIVITY, we only use it for ick */ 889 if (regbits->clkact_shift >= 0 && 890 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT || 891 ddata->cfg.sysc_val & BIT(regbits->clkact_shift))) 892 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 893 894 /* Set SIDLE mode */ 895 idlemodes = ddata->cfg.sidlemodes; 896 if (!idlemodes || regbits->sidle_shift < 0) 897 goto set_midle; 898 899 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 900 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 901 best_mode = SYSC_IDLE_NO; 902 } else { 903 best_mode = fls(ddata->cfg.sidlemodes) - 1; 904 if (best_mode > SYSC_IDLE_MASK) { 905 dev_err(dev, "%s: invalid sidlemode\n", __func__); 906 return -EINVAL; 907 } 908 909 /* Set WAKEUP */ 910 if (regbits->enwkup_shift >= 0 && 911 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 912 reg |= BIT(regbits->enwkup_shift); 913 } 914 915 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 916 reg |= best_mode << regbits->sidle_shift; 917 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 918 919 set_midle: 920 /* Set MIDLE mode */ 921 idlemodes = ddata->cfg.midlemodes; 922 if (!idlemodes || regbits->midle_shift < 0) 923 goto set_autoidle; 924 925 best_mode = fls(ddata->cfg.midlemodes) - 1; 926 if (best_mode > SYSC_IDLE_MASK) { 927 dev_err(dev, "%s: invalid midlemode\n", __func__); 928 return -EINVAL; 929 } 930 931 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 932 reg |= best_mode << regbits->midle_shift; 933 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 934 935 set_autoidle: 936 /* Autoidle bit must enabled separately if available */ 937 if (regbits->autoidle_shift >= 0 && 938 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 939 reg |= 1 << regbits->autoidle_shift; 940 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 941 } 942 943 return 0; 944 } 945 946 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 947 { 948 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 949 *best_mode = SYSC_IDLE_SMART_WKUP; 950 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 951 *best_mode = SYSC_IDLE_SMART; 952 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 953 *best_mode = SYSC_IDLE_FORCE; 954 else 955 return -EINVAL; 956 957 return 0; 958 } 959 960 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 961 static int sysc_disable_module(struct device *dev) 962 { 963 struct sysc *ddata; 964 const struct sysc_regbits *regbits; 965 u32 reg, idlemodes, best_mode; 966 int ret; 967 968 ddata = dev_get_drvdata(dev); 969 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 970 return 0; 971 972 regbits = ddata->cap->regbits; 973 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 974 975 /* Set MIDLE mode */ 976 idlemodes = ddata->cfg.midlemodes; 977 if (!idlemodes || regbits->midle_shift < 0) 978 goto set_sidle; 979 980 ret = sysc_best_idle_mode(idlemodes, &best_mode); 981 if (ret) { 982 dev_err(dev, "%s: invalid midlemode\n", __func__); 983 return ret; 984 } 985 986 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 987 reg |= best_mode << regbits->midle_shift; 988 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 989 990 set_sidle: 991 /* Set SIDLE mode */ 992 idlemodes = ddata->cfg.sidlemodes; 993 if (!idlemodes || regbits->sidle_shift < 0) 994 return 0; 995 996 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 997 best_mode = SYSC_IDLE_FORCE; 998 } else { 999 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1000 if (ret) { 1001 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1002 return ret; 1003 } 1004 } 1005 1006 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1007 reg |= best_mode << regbits->sidle_shift; 1008 if (regbits->autoidle_shift >= 0 && 1009 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1010 reg |= 1 << regbits->autoidle_shift; 1011 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1012 1013 return 0; 1014 } 1015 1016 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1017 struct sysc *ddata) 1018 { 1019 struct ti_sysc_platform_data *pdata; 1020 int error; 1021 1022 pdata = dev_get_platdata(ddata->dev); 1023 if (!pdata) 1024 return 0; 1025 1026 if (!pdata->idle_module) 1027 return -ENODEV; 1028 1029 error = pdata->idle_module(dev, &ddata->cookie); 1030 if (error) 1031 dev_err(dev, "%s: could not idle: %i\n", 1032 __func__, error); 1033 1034 if (ddata->disable_on_idle) 1035 reset_control_assert(ddata->rsts); 1036 1037 return 0; 1038 } 1039 1040 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1041 struct sysc *ddata) 1042 { 1043 struct ti_sysc_platform_data *pdata; 1044 int error; 1045 1046 if (ddata->disable_on_idle) 1047 reset_control_deassert(ddata->rsts); 1048 1049 pdata = dev_get_platdata(ddata->dev); 1050 if (!pdata) 1051 return 0; 1052 1053 if (!pdata->enable_module) 1054 return -ENODEV; 1055 1056 error = pdata->enable_module(dev, &ddata->cookie); 1057 if (error) 1058 dev_err(dev, "%s: could not enable: %i\n", 1059 __func__, error); 1060 1061 return 0; 1062 } 1063 1064 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1065 { 1066 struct sysc *ddata; 1067 int error = 0; 1068 1069 ddata = dev_get_drvdata(dev); 1070 1071 if (!ddata->enabled) 1072 return 0; 1073 1074 sysc_clkdm_deny_idle(ddata); 1075 1076 if (ddata->legacy_mode) { 1077 error = sysc_runtime_suspend_legacy(dev, ddata); 1078 if (error) 1079 goto err_allow_idle; 1080 } else { 1081 error = sysc_disable_module(dev); 1082 if (error) 1083 goto err_allow_idle; 1084 } 1085 1086 sysc_disable_main_clocks(ddata); 1087 1088 if (sysc_opt_clks_needed(ddata)) 1089 sysc_disable_opt_clocks(ddata); 1090 1091 ddata->enabled = false; 1092 1093 err_allow_idle: 1094 sysc_clkdm_allow_idle(ddata); 1095 1096 if (ddata->disable_on_idle) 1097 reset_control_assert(ddata->rsts); 1098 1099 return error; 1100 } 1101 1102 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1103 { 1104 struct sysc *ddata; 1105 int error = 0; 1106 1107 ddata = dev_get_drvdata(dev); 1108 1109 if (ddata->enabled) 1110 return 0; 1111 1112 if (ddata->disable_on_idle) 1113 reset_control_deassert(ddata->rsts); 1114 1115 sysc_clkdm_deny_idle(ddata); 1116 1117 if (sysc_opt_clks_needed(ddata)) { 1118 error = sysc_enable_opt_clocks(ddata); 1119 if (error) 1120 goto err_allow_idle; 1121 } 1122 1123 error = sysc_enable_main_clocks(ddata); 1124 if (error) 1125 goto err_opt_clocks; 1126 1127 if (ddata->legacy_mode) { 1128 error = sysc_runtime_resume_legacy(dev, ddata); 1129 if (error) 1130 goto err_main_clocks; 1131 } else { 1132 error = sysc_enable_module(dev); 1133 if (error) 1134 goto err_main_clocks; 1135 } 1136 1137 ddata->enabled = true; 1138 1139 sysc_clkdm_allow_idle(ddata); 1140 1141 return 0; 1142 1143 err_main_clocks: 1144 sysc_disable_main_clocks(ddata); 1145 err_opt_clocks: 1146 if (sysc_opt_clks_needed(ddata)) 1147 sysc_disable_opt_clocks(ddata); 1148 err_allow_idle: 1149 sysc_clkdm_allow_idle(ddata); 1150 1151 return error; 1152 } 1153 1154 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1155 { 1156 struct sysc *ddata; 1157 1158 ddata = dev_get_drvdata(dev); 1159 1160 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1161 return 0; 1162 1163 return pm_runtime_force_suspend(dev); 1164 } 1165 1166 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1167 { 1168 struct sysc *ddata; 1169 1170 ddata = dev_get_drvdata(dev); 1171 1172 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1173 return 0; 1174 1175 return pm_runtime_force_resume(dev); 1176 } 1177 1178 static const struct dev_pm_ops sysc_pm_ops = { 1179 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1180 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1181 sysc_runtime_resume, 1182 NULL) 1183 }; 1184 1185 /* Module revision register based quirks */ 1186 struct sysc_revision_quirk { 1187 const char *name; 1188 u32 base; 1189 int rev_offset; 1190 int sysc_offset; 1191 int syss_offset; 1192 u32 revision; 1193 u32 revision_mask; 1194 u32 quirks; 1195 }; 1196 1197 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1198 optrev_val, optrevmask, optquirkmask) \ 1199 { \ 1200 .name = (optname), \ 1201 .base = (optbase), \ 1202 .rev_offset = (optrev), \ 1203 .sysc_offset = (optsysc), \ 1204 .syss_offset = (optsyss), \ 1205 .revision = (optrev_val), \ 1206 .revision_mask = (optrevmask), \ 1207 .quirks = (optquirkmask), \ 1208 } 1209 1210 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1211 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1212 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1213 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1214 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1215 SYSC_QUIRK_LEGACY_IDLE), 1216 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 1217 SYSC_QUIRK_LEGACY_IDLE), 1218 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1219 SYSC_QUIRK_LEGACY_IDLE), 1220 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, 1221 SYSC_QUIRK_LEGACY_IDLE), 1222 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, 1223 SYSC_QUIRK_LEGACY_IDLE), 1224 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 1225 0), 1226 /* Some timers on omap4 and later */ 1227 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, 1228 0), 1229 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, 1230 0), 1231 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1232 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1233 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1234 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1235 /* Uarts on omap4 and later */ 1236 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1237 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1238 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1239 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1240 1241 /* Quirks that need to be set based on the module address */ 1242 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff, 1243 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1244 SYSC_QUIRK_SWSUP_SIDLE), 1245 1246 /* Quirks that need to be set based on detected module */ 1247 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1248 SYSC_MODULE_QUIRK_HDQ1W), 1249 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1250 SYSC_MODULE_QUIRK_HDQ1W), 1251 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1252 SYSC_MODULE_QUIRK_I2C), 1253 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1254 SYSC_MODULE_QUIRK_I2C), 1255 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1256 SYSC_MODULE_QUIRK_I2C), 1257 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1258 SYSC_MODULE_QUIRK_I2C), 1259 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1260 SYSC_MODULE_QUIRK_WDT), 1261 1262 #ifdef DEBUG 1263 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), 1264 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), 1265 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), 1266 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), 1267 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1268 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1269 0xffff00f0, 0), 1270 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0), 1271 SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0), 1272 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0), 1273 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), 1274 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), 1275 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), 1276 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1277 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), 1278 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), 1279 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), 1280 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), 1281 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), 1282 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), 1283 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1284 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), 1285 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), 1286 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1287 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), 1288 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), 1289 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), 1290 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), 1291 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), 1292 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), 1293 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1294 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), 1295 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), 1296 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), 1297 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), 1298 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), 1299 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1300 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1301 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), 1302 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), 1303 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), 1304 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), 1305 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), 1306 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), 1307 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1308 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1309 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), 1310 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), 1311 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1312 0xffffffff, 0), 1313 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), 1314 #endif 1315 }; 1316 1317 /* 1318 * Early quirks based on module base and register offsets only that are 1319 * needed before the module revision can be read 1320 */ 1321 static void sysc_init_early_quirks(struct sysc *ddata) 1322 { 1323 const struct sysc_revision_quirk *q; 1324 int i; 1325 1326 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1327 q = &sysc_revision_quirks[i]; 1328 1329 if (!q->base) 1330 continue; 1331 1332 if (q->base != ddata->module_pa) 1333 continue; 1334 1335 if (q->rev_offset >= 0 && 1336 q->rev_offset != ddata->offsets[SYSC_REVISION]) 1337 continue; 1338 1339 if (q->sysc_offset >= 0 && 1340 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1341 continue; 1342 1343 if (q->syss_offset >= 0 && 1344 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1345 continue; 1346 1347 ddata->name = q->name; 1348 ddata->cfg.quirks |= q->quirks; 1349 } 1350 } 1351 1352 /* Quirks that also consider the revision register value */ 1353 static void sysc_init_revision_quirks(struct sysc *ddata) 1354 { 1355 const struct sysc_revision_quirk *q; 1356 int i; 1357 1358 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1359 q = &sysc_revision_quirks[i]; 1360 1361 if (q->base && q->base != ddata->module_pa) 1362 continue; 1363 1364 if (q->rev_offset >= 0 && 1365 q->rev_offset != ddata->offsets[SYSC_REVISION]) 1366 continue; 1367 1368 if (q->sysc_offset >= 0 && 1369 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1370 continue; 1371 1372 if (q->syss_offset >= 0 && 1373 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1374 continue; 1375 1376 if (q->revision == ddata->revision || 1377 (q->revision & q->revision_mask) == 1378 (ddata->revision & q->revision_mask)) { 1379 ddata->name = q->name; 1380 ddata->cfg.quirks |= q->quirks; 1381 } 1382 } 1383 } 1384 1385 /* 1-wire needs module's internal clocks enabled for reset */ 1386 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata) 1387 { 1388 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1389 u16 val; 1390 1391 val = sysc_read(ddata, offset); 1392 val |= BIT(5); 1393 sysc_write(ddata, offset, val); 1394 } 1395 1396 /* I2C needs extra enable bit toggling for reset */ 1397 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1398 { 1399 int offset; 1400 u16 val; 1401 1402 /* I2C_CON, omap2/3 is different from omap4 and later */ 1403 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1404 offset = 0x24; 1405 else 1406 offset = 0xa4; 1407 1408 /* I2C_EN */ 1409 val = sysc_read(ddata, offset); 1410 if (enable) 1411 val |= BIT(15); 1412 else 1413 val &= ~BIT(15); 1414 sysc_write(ddata, offset, val); 1415 } 1416 1417 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata) 1418 { 1419 sysc_clk_quirk_i2c(ddata, true); 1420 } 1421 1422 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata) 1423 { 1424 sysc_clk_quirk_i2c(ddata, false); 1425 } 1426 1427 /* Watchdog timer needs a disable sequence after reset */ 1428 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1429 { 1430 int wps, spr, error; 1431 u32 val; 1432 1433 wps = 0x34; 1434 spr = 0x48; 1435 1436 sysc_write(ddata, spr, 0xaaaa); 1437 error = readl_poll_timeout(ddata->module_va + wps, val, 1438 !(val & 0x10), 100, 1439 MAX_MODULE_SOFTRESET_WAIT); 1440 if (error) 1441 dev_warn(ddata->dev, "wdt disable spr failed\n"); 1442 1443 sysc_write(ddata, wps, 0x5555); 1444 error = readl_poll_timeout(ddata->module_va + wps, val, 1445 !(val & 0x10), 100, 1446 MAX_MODULE_SOFTRESET_WAIT); 1447 if (error) 1448 dev_warn(ddata->dev, "wdt disable wps failed\n"); 1449 } 1450 1451 static void sysc_init_module_quirks(struct sysc *ddata) 1452 { 1453 if (ddata->legacy_mode || !ddata->name) 1454 return; 1455 1456 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1457 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w; 1458 1459 return; 1460 } 1461 1462 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1463 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c; 1464 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c; 1465 1466 return; 1467 } 1468 1469 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) 1470 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1471 } 1472 1473 static int sysc_clockdomain_init(struct sysc *ddata) 1474 { 1475 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1476 struct clk *fck = NULL, *ick = NULL; 1477 int error; 1478 1479 if (!pdata || !pdata->init_clockdomain) 1480 return 0; 1481 1482 switch (ddata->nr_clocks) { 1483 case 2: 1484 ick = ddata->clocks[SYSC_ICK]; 1485 /* fallthrough */ 1486 case 1: 1487 fck = ddata->clocks[SYSC_FCK]; 1488 break; 1489 case 0: 1490 return 0; 1491 } 1492 1493 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1494 if (!error || error == -ENODEV) 1495 return 0; 1496 1497 return error; 1498 } 1499 1500 /* 1501 * Note that pdata->init_module() typically does a reset first. After 1502 * pdata->init_module() is done, PM runtime can be used for the interconnect 1503 * target module. 1504 */ 1505 static int sysc_legacy_init(struct sysc *ddata) 1506 { 1507 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1508 int error; 1509 1510 if (!pdata || !pdata->init_module) 1511 return 0; 1512 1513 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 1514 if (error == -EEXIST) 1515 error = 0; 1516 1517 return error; 1518 } 1519 1520 /** 1521 * sysc_rstctrl_reset_deassert - deassert rstctrl reset 1522 * @ddata: device driver data 1523 * @reset: reset before deassert 1524 * 1525 * A module can have both OCP softreset control and external rstctrl. 1526 * If more complicated rstctrl resets are needed, please handle these 1527 * directly from the child device driver and map only the module reset 1528 * for the parent interconnect target module device. 1529 * 1530 * Automatic reset of the module on init can be skipped with the 1531 * "ti,no-reset-on-init" device tree property. 1532 */ 1533 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset) 1534 { 1535 int error, val; 1536 1537 if (!ddata->rsts) 1538 return 0; 1539 1540 if (reset) { 1541 error = reset_control_assert(ddata->rsts); 1542 if (error) 1543 return error; 1544 } 1545 1546 error = reset_control_deassert(ddata->rsts); 1547 if (error == -EEXIST) 1548 return 0; 1549 1550 error = readx_poll_timeout(reset_control_status, ddata->rsts, val, 1551 val == 0, 100, MAX_MODULE_SOFTRESET_WAIT); 1552 1553 return error; 1554 } 1555 1556 /* 1557 * Note that the caller must ensure the interconnect target module is enabled 1558 * before calling reset. Otherwise reset will not complete. 1559 */ 1560 static int sysc_reset(struct sysc *ddata) 1561 { 1562 int sysc_offset, syss_offset, sysc_val, rstval, quirks, error = 0; 1563 u32 sysc_mask, syss_done; 1564 1565 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 1566 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 1567 quirks = ddata->cfg.quirks; 1568 1569 if (ddata->legacy_mode || sysc_offset < 0 || 1570 ddata->cap->regbits->srst_shift < 0 || 1571 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 1572 return 0; 1573 1574 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 1575 1576 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 1577 syss_done = 0; 1578 else 1579 syss_done = ddata->cfg.syss_mask; 1580 1581 if (ddata->clk_disable_quirk) 1582 ddata->clk_disable_quirk(ddata); 1583 1584 sysc_val = sysc_read_sysconfig(ddata); 1585 sysc_val |= sysc_mask; 1586 sysc_write(ddata, sysc_offset, sysc_val); 1587 1588 if (ddata->clk_enable_quirk) 1589 ddata->clk_enable_quirk(ddata); 1590 1591 /* Poll on reset status */ 1592 if (syss_offset >= 0) { 1593 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval, 1594 (rstval & ddata->cfg.syss_mask) == 1595 syss_done, 1596 100, MAX_MODULE_SOFTRESET_WAIT); 1597 1598 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 1599 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval, 1600 !(rstval & sysc_mask), 1601 100, MAX_MODULE_SOFTRESET_WAIT); 1602 } 1603 1604 if (ddata->reset_done_quirk) 1605 ddata->reset_done_quirk(ddata); 1606 1607 return error; 1608 } 1609 1610 /* 1611 * At this point the module is configured enough to read the revision but 1612 * module may not be completely configured yet to use PM runtime. Enable 1613 * all clocks directly during init to configure the quirks needed for PM 1614 * runtime based on the revision register. 1615 */ 1616 static int sysc_init_module(struct sysc *ddata) 1617 { 1618 int error = 0; 1619 bool manage_clocks = true; 1620 1621 error = sysc_rstctrl_reset_deassert(ddata, false); 1622 if (error) 1623 return error; 1624 1625 if (ddata->cfg.quirks & 1626 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) 1627 manage_clocks = false; 1628 1629 error = sysc_clockdomain_init(ddata); 1630 if (error) 1631 return error; 1632 1633 if (manage_clocks) { 1634 sysc_clkdm_deny_idle(ddata); 1635 1636 error = sysc_enable_opt_clocks(ddata); 1637 if (error) 1638 return error; 1639 1640 error = sysc_enable_main_clocks(ddata); 1641 if (error) 1642 goto err_opt_clocks; 1643 } 1644 1645 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 1646 error = sysc_rstctrl_reset_deassert(ddata, true); 1647 if (error) 1648 goto err_main_clocks; 1649 } 1650 1651 ddata->revision = sysc_read_revision(ddata); 1652 sysc_init_revision_quirks(ddata); 1653 sysc_init_module_quirks(ddata); 1654 1655 if (ddata->legacy_mode) { 1656 error = sysc_legacy_init(ddata); 1657 if (error) 1658 goto err_main_clocks; 1659 } 1660 1661 if (!ddata->legacy_mode && manage_clocks) { 1662 error = sysc_enable_module(ddata->dev); 1663 if (error) 1664 goto err_main_clocks; 1665 } 1666 1667 error = sysc_reset(ddata); 1668 if (error) 1669 dev_err(ddata->dev, "Reset failed with %d\n", error); 1670 1671 if (!ddata->legacy_mode && manage_clocks) 1672 sysc_disable_module(ddata->dev); 1673 1674 err_main_clocks: 1675 if (manage_clocks) 1676 sysc_disable_main_clocks(ddata); 1677 err_opt_clocks: 1678 if (manage_clocks) { 1679 sysc_disable_opt_clocks(ddata); 1680 sysc_clkdm_allow_idle(ddata); 1681 } 1682 1683 return error; 1684 } 1685 1686 static int sysc_init_sysc_mask(struct sysc *ddata) 1687 { 1688 struct device_node *np = ddata->dev->of_node; 1689 int error; 1690 u32 val; 1691 1692 error = of_property_read_u32(np, "ti,sysc-mask", &val); 1693 if (error) 1694 return 0; 1695 1696 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 1697 1698 return 0; 1699 } 1700 1701 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 1702 const char *name) 1703 { 1704 struct device_node *np = ddata->dev->of_node; 1705 struct property *prop; 1706 const __be32 *p; 1707 u32 val; 1708 1709 of_property_for_each_u32(np, name, prop, p, val) { 1710 if (val >= SYSC_NR_IDLEMODES) { 1711 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 1712 return -EINVAL; 1713 } 1714 *idlemodes |= (1 << val); 1715 } 1716 1717 return 0; 1718 } 1719 1720 static int sysc_init_idlemodes(struct sysc *ddata) 1721 { 1722 int error; 1723 1724 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 1725 "ti,sysc-midle"); 1726 if (error) 1727 return error; 1728 1729 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 1730 "ti,sysc-sidle"); 1731 if (error) 1732 return error; 1733 1734 return 0; 1735 } 1736 1737 /* 1738 * Only some devices on omap4 and later have SYSCONFIG reset done 1739 * bit. We can detect this if there is no SYSSTATUS at all, or the 1740 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 1741 * have multiple bits for the child devices like OHCI and EHCI. 1742 * Depends on SYSC being parsed first. 1743 */ 1744 static int sysc_init_syss_mask(struct sysc *ddata) 1745 { 1746 struct device_node *np = ddata->dev->of_node; 1747 int error; 1748 u32 val; 1749 1750 error = of_property_read_u32(np, "ti,syss-mask", &val); 1751 if (error) { 1752 if ((ddata->cap->type == TI_SYSC_OMAP4 || 1753 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 1754 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 1755 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 1756 1757 return 0; 1758 } 1759 1760 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 1761 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 1762 1763 ddata->cfg.syss_mask = val; 1764 1765 return 0; 1766 } 1767 1768 /* 1769 * Many child device drivers need to have fck and opt clocks available 1770 * to get the clock rate for device internal configuration etc. 1771 */ 1772 static int sysc_child_add_named_clock(struct sysc *ddata, 1773 struct device *child, 1774 const char *name) 1775 { 1776 struct clk *clk; 1777 struct clk_lookup *l; 1778 int error = 0; 1779 1780 if (!name) 1781 return 0; 1782 1783 clk = clk_get(child, name); 1784 if (!IS_ERR(clk)) { 1785 clk_put(clk); 1786 1787 return -EEXIST; 1788 } 1789 1790 clk = clk_get(ddata->dev, name); 1791 if (IS_ERR(clk)) 1792 return -ENODEV; 1793 1794 l = clkdev_create(clk, name, dev_name(child)); 1795 if (!l) 1796 error = -ENOMEM; 1797 1798 clk_put(clk); 1799 1800 return error; 1801 } 1802 1803 static int sysc_child_add_clocks(struct sysc *ddata, 1804 struct device *child) 1805 { 1806 int i, error; 1807 1808 for (i = 0; i < ddata->nr_clocks; i++) { 1809 error = sysc_child_add_named_clock(ddata, 1810 child, 1811 ddata->clock_roles[i]); 1812 if (error && error != -EEXIST) { 1813 dev_err(ddata->dev, "could not add child clock %s: %i\n", 1814 ddata->clock_roles[i], error); 1815 1816 return error; 1817 } 1818 } 1819 1820 return 0; 1821 } 1822 1823 static struct device_type sysc_device_type = { 1824 }; 1825 1826 static struct sysc *sysc_child_to_parent(struct device *dev) 1827 { 1828 struct device *parent = dev->parent; 1829 1830 if (!parent || parent->type != &sysc_device_type) 1831 return NULL; 1832 1833 return dev_get_drvdata(parent); 1834 } 1835 1836 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 1837 { 1838 struct sysc *ddata; 1839 int error; 1840 1841 ddata = sysc_child_to_parent(dev); 1842 1843 error = pm_generic_runtime_suspend(dev); 1844 if (error) 1845 return error; 1846 1847 if (!ddata->enabled) 1848 return 0; 1849 1850 return sysc_runtime_suspend(ddata->dev); 1851 } 1852 1853 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 1854 { 1855 struct sysc *ddata; 1856 int error; 1857 1858 ddata = sysc_child_to_parent(dev); 1859 1860 if (!ddata->enabled) { 1861 error = sysc_runtime_resume(ddata->dev); 1862 if (error < 0) 1863 dev_err(ddata->dev, 1864 "%s error: %i\n", __func__, error); 1865 } 1866 1867 return pm_generic_runtime_resume(dev); 1868 } 1869 1870 #ifdef CONFIG_PM_SLEEP 1871 static int sysc_child_suspend_noirq(struct device *dev) 1872 { 1873 struct sysc *ddata; 1874 int error; 1875 1876 ddata = sysc_child_to_parent(dev); 1877 1878 dev_dbg(ddata->dev, "%s %s\n", __func__, 1879 ddata->name ? ddata->name : ""); 1880 1881 error = pm_generic_suspend_noirq(dev); 1882 if (error) { 1883 dev_err(dev, "%s error at %i: %i\n", 1884 __func__, __LINE__, error); 1885 1886 return error; 1887 } 1888 1889 if (!pm_runtime_status_suspended(dev)) { 1890 error = pm_generic_runtime_suspend(dev); 1891 if (error) { 1892 dev_dbg(dev, "%s busy at %i: %i\n", 1893 __func__, __LINE__, error); 1894 1895 return 0; 1896 } 1897 1898 error = sysc_runtime_suspend(ddata->dev); 1899 if (error) { 1900 dev_err(dev, "%s error at %i: %i\n", 1901 __func__, __LINE__, error); 1902 1903 return error; 1904 } 1905 1906 ddata->child_needs_resume = true; 1907 } 1908 1909 return 0; 1910 } 1911 1912 static int sysc_child_resume_noirq(struct device *dev) 1913 { 1914 struct sysc *ddata; 1915 int error; 1916 1917 ddata = sysc_child_to_parent(dev); 1918 1919 dev_dbg(ddata->dev, "%s %s\n", __func__, 1920 ddata->name ? ddata->name : ""); 1921 1922 if (ddata->child_needs_resume) { 1923 ddata->child_needs_resume = false; 1924 1925 error = sysc_runtime_resume(ddata->dev); 1926 if (error) 1927 dev_err(ddata->dev, 1928 "%s runtime resume error: %i\n", 1929 __func__, error); 1930 1931 error = pm_generic_runtime_resume(dev); 1932 if (error) 1933 dev_err(ddata->dev, 1934 "%s generic runtime resume: %i\n", 1935 __func__, error); 1936 } 1937 1938 return pm_generic_resume_noirq(dev); 1939 } 1940 #endif 1941 1942 static struct dev_pm_domain sysc_child_pm_domain = { 1943 .ops = { 1944 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 1945 sysc_child_runtime_resume, 1946 NULL) 1947 USE_PLATFORM_PM_SLEEP_OPS 1948 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 1949 sysc_child_resume_noirq) 1950 } 1951 }; 1952 1953 /** 1954 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 1955 * @ddata: device driver data 1956 * @child: child device driver 1957 * 1958 * Allow idle for child devices as done with _od_runtime_suspend(). 1959 * Otherwise many child devices will not idle because of the permanent 1960 * parent usecount set in pm_runtime_irq_safe(). 1961 * 1962 * Note that the long term solution is to just modify the child device 1963 * drivers to not set pm_runtime_irq_safe() and then this can be just 1964 * dropped. 1965 */ 1966 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 1967 { 1968 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1969 dev_pm_domain_set(child, &sysc_child_pm_domain); 1970 } 1971 1972 static int sysc_notifier_call(struct notifier_block *nb, 1973 unsigned long event, void *device) 1974 { 1975 struct device *dev = device; 1976 struct sysc *ddata; 1977 int error; 1978 1979 ddata = sysc_child_to_parent(dev); 1980 if (!ddata) 1981 return NOTIFY_DONE; 1982 1983 switch (event) { 1984 case BUS_NOTIFY_ADD_DEVICE: 1985 error = sysc_child_add_clocks(ddata, dev); 1986 if (error) 1987 return error; 1988 sysc_legacy_idle_quirk(ddata, dev); 1989 break; 1990 default: 1991 break; 1992 } 1993 1994 return NOTIFY_DONE; 1995 } 1996 1997 static struct notifier_block sysc_nb = { 1998 .notifier_call = sysc_notifier_call, 1999 }; 2000 2001 /* Device tree configured quirks */ 2002 struct sysc_dts_quirk { 2003 const char *name; 2004 u32 mask; 2005 }; 2006 2007 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2008 { .name = "ti,no-idle-on-init", 2009 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2010 { .name = "ti,no-reset-on-init", 2011 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2012 { .name = "ti,no-idle", 2013 .mask = SYSC_QUIRK_NO_IDLE, }, 2014 }; 2015 2016 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2017 bool is_child) 2018 { 2019 const struct property *prop; 2020 int i, len; 2021 2022 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2023 const char *name = sysc_dts_quirks[i].name; 2024 2025 prop = of_get_property(np, name, &len); 2026 if (!prop) 2027 continue; 2028 2029 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2030 if (is_child) { 2031 dev_warn(ddata->dev, 2032 "dts flag should be at module level for %s\n", 2033 name); 2034 } 2035 } 2036 } 2037 2038 static int sysc_init_dts_quirks(struct sysc *ddata) 2039 { 2040 struct device_node *np = ddata->dev->of_node; 2041 int error; 2042 u32 val; 2043 2044 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2045 2046 sysc_parse_dts_quirks(ddata, np, false); 2047 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2048 if (!error) { 2049 if (val > 255) { 2050 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2051 val); 2052 } 2053 2054 ddata->cfg.srst_udelay = (u8)val; 2055 } 2056 2057 return 0; 2058 } 2059 2060 static void sysc_unprepare(struct sysc *ddata) 2061 { 2062 int i; 2063 2064 if (!ddata->clocks) 2065 return; 2066 2067 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2068 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2069 clk_unprepare(ddata->clocks[i]); 2070 } 2071 } 2072 2073 /* 2074 * Common sysc register bits found on omap2, also known as type1 2075 */ 2076 static const struct sysc_regbits sysc_regbits_omap2 = { 2077 .dmadisable_shift = -ENODEV, 2078 .midle_shift = 12, 2079 .sidle_shift = 3, 2080 .clkact_shift = 8, 2081 .emufree_shift = 5, 2082 .enwkup_shift = 2, 2083 .srst_shift = 1, 2084 .autoidle_shift = 0, 2085 }; 2086 2087 static const struct sysc_capabilities sysc_omap2 = { 2088 .type = TI_SYSC_OMAP2, 2089 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2090 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2091 SYSC_OMAP2_AUTOIDLE, 2092 .regbits = &sysc_regbits_omap2, 2093 }; 2094 2095 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2096 static const struct sysc_capabilities sysc_omap2_timer = { 2097 .type = TI_SYSC_OMAP2_TIMER, 2098 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2099 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2100 SYSC_OMAP2_AUTOIDLE, 2101 .regbits = &sysc_regbits_omap2, 2102 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2103 }; 2104 2105 /* 2106 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2107 * with different sidle position 2108 */ 2109 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2110 .dmadisable_shift = -ENODEV, 2111 .midle_shift = -ENODEV, 2112 .sidle_shift = 4, 2113 .clkact_shift = -ENODEV, 2114 .enwkup_shift = -ENODEV, 2115 .srst_shift = 1, 2116 .autoidle_shift = 0, 2117 .emufree_shift = -ENODEV, 2118 }; 2119 2120 static const struct sysc_capabilities sysc_omap3_sham = { 2121 .type = TI_SYSC_OMAP3_SHAM, 2122 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2123 .regbits = &sysc_regbits_omap3_sham, 2124 }; 2125 2126 /* 2127 * AES register bits found on omap3 and later, a variant of 2128 * sysc_regbits_omap2 with different sidle position 2129 */ 2130 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2131 .dmadisable_shift = -ENODEV, 2132 .midle_shift = -ENODEV, 2133 .sidle_shift = 6, 2134 .clkact_shift = -ENODEV, 2135 .enwkup_shift = -ENODEV, 2136 .srst_shift = 1, 2137 .autoidle_shift = 0, 2138 .emufree_shift = -ENODEV, 2139 }; 2140 2141 static const struct sysc_capabilities sysc_omap3_aes = { 2142 .type = TI_SYSC_OMAP3_AES, 2143 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2144 .regbits = &sysc_regbits_omap3_aes, 2145 }; 2146 2147 /* 2148 * Common sysc register bits found on omap4, also known as type2 2149 */ 2150 static const struct sysc_regbits sysc_regbits_omap4 = { 2151 .dmadisable_shift = 16, 2152 .midle_shift = 4, 2153 .sidle_shift = 2, 2154 .clkact_shift = -ENODEV, 2155 .enwkup_shift = -ENODEV, 2156 .emufree_shift = 1, 2157 .srst_shift = 0, 2158 .autoidle_shift = -ENODEV, 2159 }; 2160 2161 static const struct sysc_capabilities sysc_omap4 = { 2162 .type = TI_SYSC_OMAP4, 2163 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2164 SYSC_OMAP4_SOFTRESET, 2165 .regbits = &sysc_regbits_omap4, 2166 }; 2167 2168 static const struct sysc_capabilities sysc_omap4_timer = { 2169 .type = TI_SYSC_OMAP4_TIMER, 2170 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2171 SYSC_OMAP4_SOFTRESET, 2172 .regbits = &sysc_regbits_omap4, 2173 }; 2174 2175 /* 2176 * Common sysc register bits found on omap4, also known as type3 2177 */ 2178 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2179 .dmadisable_shift = -ENODEV, 2180 .midle_shift = 2, 2181 .sidle_shift = 0, 2182 .clkact_shift = -ENODEV, 2183 .enwkup_shift = -ENODEV, 2184 .srst_shift = -ENODEV, 2185 .emufree_shift = -ENODEV, 2186 .autoidle_shift = -ENODEV, 2187 }; 2188 2189 static const struct sysc_capabilities sysc_omap4_simple = { 2190 .type = TI_SYSC_OMAP4_SIMPLE, 2191 .regbits = &sysc_regbits_omap4_simple, 2192 }; 2193 2194 /* 2195 * SmartReflex sysc found on omap34xx 2196 */ 2197 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2198 .dmadisable_shift = -ENODEV, 2199 .midle_shift = -ENODEV, 2200 .sidle_shift = -ENODEV, 2201 .clkact_shift = 20, 2202 .enwkup_shift = -ENODEV, 2203 .srst_shift = -ENODEV, 2204 .emufree_shift = -ENODEV, 2205 .autoidle_shift = -ENODEV, 2206 }; 2207 2208 static const struct sysc_capabilities sysc_34xx_sr = { 2209 .type = TI_SYSC_OMAP34XX_SR, 2210 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2211 .regbits = &sysc_regbits_omap34xx_sr, 2212 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2213 SYSC_QUIRK_LEGACY_IDLE, 2214 }; 2215 2216 /* 2217 * SmartReflex sysc found on omap36xx and later 2218 */ 2219 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2220 .dmadisable_shift = -ENODEV, 2221 .midle_shift = -ENODEV, 2222 .sidle_shift = 24, 2223 .clkact_shift = -ENODEV, 2224 .enwkup_shift = 26, 2225 .srst_shift = -ENODEV, 2226 .emufree_shift = -ENODEV, 2227 .autoidle_shift = -ENODEV, 2228 }; 2229 2230 static const struct sysc_capabilities sysc_36xx_sr = { 2231 .type = TI_SYSC_OMAP36XX_SR, 2232 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2233 .regbits = &sysc_regbits_omap36xx_sr, 2234 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2235 }; 2236 2237 static const struct sysc_capabilities sysc_omap4_sr = { 2238 .type = TI_SYSC_OMAP4_SR, 2239 .regbits = &sysc_regbits_omap36xx_sr, 2240 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2241 }; 2242 2243 /* 2244 * McASP register bits found on omap4 and later 2245 */ 2246 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2247 .dmadisable_shift = -ENODEV, 2248 .midle_shift = -ENODEV, 2249 .sidle_shift = 0, 2250 .clkact_shift = -ENODEV, 2251 .enwkup_shift = -ENODEV, 2252 .srst_shift = -ENODEV, 2253 .emufree_shift = -ENODEV, 2254 .autoidle_shift = -ENODEV, 2255 }; 2256 2257 static const struct sysc_capabilities sysc_omap4_mcasp = { 2258 .type = TI_SYSC_OMAP4_MCASP, 2259 .regbits = &sysc_regbits_omap4_mcasp, 2260 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2261 }; 2262 2263 /* 2264 * McASP found on dra7 and later 2265 */ 2266 static const struct sysc_capabilities sysc_dra7_mcasp = { 2267 .type = TI_SYSC_OMAP4_SIMPLE, 2268 .regbits = &sysc_regbits_omap4_simple, 2269 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2270 }; 2271 2272 /* 2273 * FS USB host found on omap4 and later 2274 */ 2275 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2276 .dmadisable_shift = -ENODEV, 2277 .midle_shift = -ENODEV, 2278 .sidle_shift = 24, 2279 .clkact_shift = -ENODEV, 2280 .enwkup_shift = 26, 2281 .srst_shift = -ENODEV, 2282 .emufree_shift = -ENODEV, 2283 .autoidle_shift = -ENODEV, 2284 }; 2285 2286 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2287 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2288 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2289 .regbits = &sysc_regbits_omap4_usb_host_fs, 2290 }; 2291 2292 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2293 .dmadisable_shift = -ENODEV, 2294 .midle_shift = -ENODEV, 2295 .sidle_shift = -ENODEV, 2296 .clkact_shift = -ENODEV, 2297 .enwkup_shift = 4, 2298 .srst_shift = 0, 2299 .emufree_shift = -ENODEV, 2300 .autoidle_shift = -ENODEV, 2301 }; 2302 2303 static const struct sysc_capabilities sysc_dra7_mcan = { 2304 .type = TI_SYSC_DRA7_MCAN, 2305 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2306 .regbits = &sysc_regbits_dra7_mcan, 2307 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2308 }; 2309 2310 static int sysc_init_pdata(struct sysc *ddata) 2311 { 2312 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2313 struct ti_sysc_module_data *mdata; 2314 2315 if (!pdata) 2316 return 0; 2317 2318 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2319 if (!mdata) 2320 return -ENOMEM; 2321 2322 if (ddata->legacy_mode) { 2323 mdata->name = ddata->legacy_mode; 2324 mdata->module_pa = ddata->module_pa; 2325 mdata->module_size = ddata->module_size; 2326 mdata->offsets = ddata->offsets; 2327 mdata->nr_offsets = SYSC_MAX_REGS; 2328 mdata->cap = ddata->cap; 2329 mdata->cfg = &ddata->cfg; 2330 } 2331 2332 ddata->mdata = mdata; 2333 2334 return 0; 2335 } 2336 2337 static int sysc_init_match(struct sysc *ddata) 2338 { 2339 const struct sysc_capabilities *cap; 2340 2341 cap = of_device_get_match_data(ddata->dev); 2342 if (!cap) 2343 return -EINVAL; 2344 2345 ddata->cap = cap; 2346 if (ddata->cap) 2347 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2348 2349 return 0; 2350 } 2351 2352 static void ti_sysc_idle(struct work_struct *work) 2353 { 2354 struct sysc *ddata; 2355 2356 ddata = container_of(work, struct sysc, idle_work.work); 2357 2358 if (pm_runtime_active(ddata->dev)) 2359 pm_runtime_put_sync(ddata->dev); 2360 } 2361 2362 static const struct of_device_id sysc_match_table[] = { 2363 { .compatible = "simple-bus", }, 2364 { /* sentinel */ }, 2365 }; 2366 2367 static int sysc_probe(struct platform_device *pdev) 2368 { 2369 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 2370 struct sysc *ddata; 2371 int error; 2372 2373 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 2374 if (!ddata) 2375 return -ENOMEM; 2376 2377 ddata->dev = &pdev->dev; 2378 platform_set_drvdata(pdev, ddata); 2379 2380 error = sysc_init_match(ddata); 2381 if (error) 2382 return error; 2383 2384 error = sysc_init_dts_quirks(ddata); 2385 if (error) 2386 return error; 2387 2388 error = sysc_map_and_check_registers(ddata); 2389 if (error) 2390 return error; 2391 2392 error = sysc_init_sysc_mask(ddata); 2393 if (error) 2394 return error; 2395 2396 error = sysc_init_idlemodes(ddata); 2397 if (error) 2398 return error; 2399 2400 error = sysc_init_syss_mask(ddata); 2401 if (error) 2402 return error; 2403 2404 error = sysc_init_pdata(ddata); 2405 if (error) 2406 return error; 2407 2408 sysc_init_early_quirks(ddata); 2409 2410 error = sysc_get_clocks(ddata); 2411 if (error) 2412 return error; 2413 2414 error = sysc_init_resets(ddata); 2415 if (error) 2416 goto unprepare; 2417 2418 error = sysc_init_module(ddata); 2419 if (error) 2420 goto unprepare; 2421 2422 pm_runtime_enable(ddata->dev); 2423 error = pm_runtime_get_sync(ddata->dev); 2424 if (error < 0) { 2425 pm_runtime_put_noidle(ddata->dev); 2426 pm_runtime_disable(ddata->dev); 2427 goto unprepare; 2428 } 2429 2430 sysc_show_registers(ddata); 2431 2432 ddata->dev->type = &sysc_device_type; 2433 error = of_platform_populate(ddata->dev->of_node, sysc_match_table, 2434 pdata ? pdata->auxdata : NULL, 2435 ddata->dev); 2436 if (error) 2437 goto err; 2438 2439 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 2440 2441 /* At least earlycon won't survive without deferred idle */ 2442 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | 2443 SYSC_QUIRK_NO_RESET_ON_INIT)) { 2444 schedule_delayed_work(&ddata->idle_work, 3000); 2445 } else { 2446 pm_runtime_put(&pdev->dev); 2447 } 2448 2449 if (!of_get_available_child_count(ddata->dev->of_node)) 2450 ddata->disable_on_idle = true; 2451 2452 return 0; 2453 2454 err: 2455 pm_runtime_put_sync(&pdev->dev); 2456 pm_runtime_disable(&pdev->dev); 2457 unprepare: 2458 sysc_unprepare(ddata); 2459 2460 return error; 2461 } 2462 2463 static int sysc_remove(struct platform_device *pdev) 2464 { 2465 struct sysc *ddata = platform_get_drvdata(pdev); 2466 int error; 2467 2468 cancel_delayed_work_sync(&ddata->idle_work); 2469 2470 error = pm_runtime_get_sync(ddata->dev); 2471 if (error < 0) { 2472 pm_runtime_put_noidle(ddata->dev); 2473 pm_runtime_disable(ddata->dev); 2474 goto unprepare; 2475 } 2476 2477 of_platform_depopulate(&pdev->dev); 2478 2479 pm_runtime_put_sync(&pdev->dev); 2480 pm_runtime_disable(&pdev->dev); 2481 reset_control_assert(ddata->rsts); 2482 2483 unprepare: 2484 sysc_unprepare(ddata); 2485 2486 return 0; 2487 } 2488 2489 static const struct of_device_id sysc_match[] = { 2490 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 2491 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 2492 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 2493 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 2494 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 2495 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 2496 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 2497 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 2498 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 2499 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 2500 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 2501 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 2502 { .compatible = "ti,sysc-usb-host-fs", 2503 .data = &sysc_omap4_usb_host_fs, }, 2504 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 2505 { }, 2506 }; 2507 MODULE_DEVICE_TABLE(of, sysc_match); 2508 2509 static struct platform_driver sysc_driver = { 2510 .probe = sysc_probe, 2511 .remove = sysc_remove, 2512 .driver = { 2513 .name = "ti-sysc", 2514 .of_match_table = sysc_match, 2515 .pm = &sysc_pm_ops, 2516 }, 2517 }; 2518 2519 static int __init sysc_init(void) 2520 { 2521 bus_register_notifier(&platform_bus_type, &sysc_nb); 2522 2523 return platform_driver_register(&sysc_driver); 2524 } 2525 module_init(sysc_init); 2526 2527 static void __exit sysc_exit(void) 2528 { 2529 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 2530 platform_driver_unregister(&sysc_driver); 2531 } 2532 module_exit(sysc_exit); 2533 2534 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 2535 MODULE_LICENSE("GPL v2"); 2536