xref: /linux/drivers/bus/ti-sysc.c (revision 93d4e8bb3f137e8037a65ea96f175f81c25c50e5)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * ti-sysc.c - Texas Instruments sysc interconnect target driver
4  *
5  * TI SoCs have an interconnect target wrapper IP for many devices. The wrapper
6  * IP manages clock gating, resets, and PM capabilities for the connected devices.
7  *
8  * Copyright (C) 2017-2024 Texas Instruments Incorporated - https://www.ti.com/
9  *
10  * Many features are based on the earlier omap_hwmod arch code with thanks to all
11  * the people who developed and debugged the code over the years:
12  *
13  * Copyright (C) 2009-2011 Nokia Corporation
14  * Copyright (C) 2011-2021 Texas Instruments Incorporated - https://www.ti.com/
15  */
16 
17 #include <linux/io.h>
18 #include <linux/clk.h>
19 #include <linux/clkdev.h>
20 #include <linux/cpu_pm.h>
21 #include <linux/delay.h>
22 #include <linux/list.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_domain.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/reset.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/slab.h>
31 #include <linux/sys_soc.h>
32 #include <linux/timekeeping.h>
33 #include <linux/iopoll.h>
34 
35 #include <linux/platform_data/ti-sysc.h>
36 
37 #include <dt-bindings/bus/ti-sysc.h>
38 
39 #define DIS_ISP		BIT(2)
40 #define DIS_IVA		BIT(1)
41 #define DIS_SGX		BIT(0)
42 
43 #define SOC_FLAG(match, flag)	{ .machine = match, .data = (void *)(flag), }
44 
45 #define MAX_MODULE_SOFTRESET_WAIT		10000
46 
47 enum sysc_soc {
48 	SOC_UNKNOWN,
49 	SOC_2420,
50 	SOC_2430,
51 	SOC_3430,
52 	SOC_AM35,
53 	SOC_3630,
54 	SOC_4430,
55 	SOC_4460,
56 	SOC_4470,
57 	SOC_5430,
58 	SOC_AM3,
59 	SOC_AM4,
60 	SOC_DRA7,
61 };
62 
63 struct sysc_address {
64 	unsigned long base;
65 	struct list_head node;
66 };
67 
68 struct sysc_module {
69 	struct sysc *ddata;
70 	struct list_head node;
71 };
72 
73 struct sysc_soc_info {
74 	unsigned long general_purpose:1;
75 	enum sysc_soc soc;
76 	struct mutex list_lock;	/* disabled and restored modules list lock */
77 	struct list_head disabled_modules;
78 	struct list_head restored_modules;
79 	struct notifier_block nb;
80 };
81 
82 enum sysc_clocks {
83 	SYSC_FCK,
84 	SYSC_ICK,
85 	SYSC_OPTFCK0,
86 	SYSC_OPTFCK1,
87 	SYSC_OPTFCK2,
88 	SYSC_OPTFCK3,
89 	SYSC_OPTFCK4,
90 	SYSC_OPTFCK5,
91 	SYSC_OPTFCK6,
92 	SYSC_OPTFCK7,
93 	SYSC_MAX_CLOCKS,
94 };
95 
96 static struct sysc_soc_info *sysc_soc;
97 static const char * const reg_names[] = { "rev", "sysc", "syss", };
98 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
99 	"fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
100 	"opt5", "opt6", "opt7",
101 };
102 
103 #define SYSC_IDLEMODE_MASK		3
104 #define SYSC_CLOCKACTIVITY_MASK		3
105 
106 /**
107  * struct sysc - TI sysc interconnect target module registers and capabilities
108  * @dev: struct device pointer
109  * @module_pa: physical address of the interconnect target module
110  * @module_size: size of the interconnect target module
111  * @module_va: virtual address of the interconnect target module
112  * @offsets: register offsets from module base
113  * @mdata: ti-sysc to hwmod translation data for a module
114  * @clocks: clocks used by the interconnect target module
115  * @clock_roles: clock role names for the found clocks
116  * @nr_clocks: number of clocks used by the interconnect target module
117  * @rsts: resets used by the interconnect target module
118  * @legacy_mode: configured for legacy mode if set
119  * @cap: interconnect target module capabilities
120  * @cfg: interconnect target module configuration
121  * @cookie: data used by legacy platform callbacks
122  * @name: name if available
123  * @revision: interconnect target module revision
124  * @sysconfig: saved sysconfig register value
125  * @reserved: target module is reserved and already in use
126  * @enabled: sysc runtime enabled status
127  * @needs_resume: runtime resume needed on resume from suspend
128  * @child_needs_resume: runtime resume needed for child on resume from suspend
129  * @disable_on_idle: status flag used for disabling modules with resets
130  * @idle_work: work structure used to perform delayed idle on a module
131  * @pre_reset_quirk: module specific pre-reset quirk
132  * @post_reset_quirk: module specific post-reset quirk
133  * @reset_done_quirk: module specific reset done quirk
134  * @module_enable_quirk: module specific enable quirk
135  * @module_disable_quirk: module specific disable quirk
136  * @module_unlock_quirk: module specific sysconfig unlock quirk
137  * @module_lock_quirk: module specific sysconfig lock quirk
138  */
139 struct sysc {
140 	struct device *dev;
141 	u64 module_pa;
142 	u32 module_size;
143 	void __iomem *module_va;
144 	int offsets[SYSC_MAX_REGS];
145 	struct ti_sysc_module_data *mdata;
146 	struct clk **clocks;
147 	const char **clock_roles;
148 	int nr_clocks;
149 	struct reset_control *rsts;
150 	const char *legacy_mode;
151 	const struct sysc_capabilities *cap;
152 	struct sysc_config cfg;
153 	struct ti_sysc_cookie cookie;
154 	const char *name;
155 	u32 revision;
156 	u32 sysconfig;
157 	unsigned int reserved:1;
158 	unsigned int enabled:1;
159 	unsigned int needs_resume:1;
160 	unsigned int child_needs_resume:1;
161 	struct delayed_work idle_work;
162 	void (*pre_reset_quirk)(struct sysc *sysc);
163 	void (*post_reset_quirk)(struct sysc *sysc);
164 	void (*reset_done_quirk)(struct sysc *sysc);
165 	void (*module_enable_quirk)(struct sysc *sysc);
166 	void (*module_disable_quirk)(struct sysc *sysc);
167 	void (*module_unlock_quirk)(struct sysc *sysc);
168 	void (*module_lock_quirk)(struct sysc *sysc);
169 };
170 
171 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
172 				  bool is_child);
173 static int sysc_reset(struct sysc *ddata);
174 
175 static void sysc_write(struct sysc *ddata, int offset, u32 value)
176 {
177 	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
178 		writew_relaxed(value & 0xffff, ddata->module_va + offset);
179 
180 		/* Only i2c revision has LO and HI register with stride of 4 */
181 		if (ddata->offsets[SYSC_REVISION] >= 0 &&
182 		    offset == ddata->offsets[SYSC_REVISION]) {
183 			u16 hi = value >> 16;
184 
185 			writew_relaxed(hi, ddata->module_va + offset + 4);
186 		}
187 
188 		return;
189 	}
190 
191 	writel_relaxed(value, ddata->module_va + offset);
192 }
193 
194 static u32 sysc_read(struct sysc *ddata, int offset)
195 {
196 	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
197 		u32 val;
198 
199 		val = readw_relaxed(ddata->module_va + offset);
200 
201 		/* Only i2c revision has LO and HI register with stride of 4 */
202 		if (ddata->offsets[SYSC_REVISION] >= 0 &&
203 		    offset == ddata->offsets[SYSC_REVISION]) {
204 			u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
205 
206 			val |= tmp << 16;
207 		}
208 
209 		return val;
210 	}
211 
212 	return readl_relaxed(ddata->module_va + offset);
213 }
214 
215 static bool sysc_opt_clks_needed(struct sysc *ddata)
216 {
217 	return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
218 }
219 
220 static u32 sysc_read_revision(struct sysc *ddata)
221 {
222 	int offset = ddata->offsets[SYSC_REVISION];
223 
224 	if (offset < 0)
225 		return 0;
226 
227 	return sysc_read(ddata, offset);
228 }
229 
230 static u32 sysc_read_sysconfig(struct sysc *ddata)
231 {
232 	int offset = ddata->offsets[SYSC_SYSCONFIG];
233 
234 	if (offset < 0)
235 		return 0;
236 
237 	return sysc_read(ddata, offset);
238 }
239 
240 static u32 sysc_read_sysstatus(struct sysc *ddata)
241 {
242 	int offset = ddata->offsets[SYSC_SYSSTATUS];
243 
244 	if (offset < 0)
245 		return 0;
246 
247 	return sysc_read(ddata, offset);
248 }
249 
250 static int sysc_poll_reset_sysstatus(struct sysc *ddata)
251 {
252 	int error, retries;
253 	u32 syss_done, rstval;
254 
255 	if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
256 		syss_done = 0;
257 	else
258 		syss_done = ddata->cfg.syss_mask;
259 
260 	if (likely(!timekeeping_suspended)) {
261 		error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
262 				rstval, (rstval & ddata->cfg.syss_mask) ==
263 				syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
264 	} else {
265 		retries = MAX_MODULE_SOFTRESET_WAIT;
266 		while (retries--) {
267 			rstval = sysc_read_sysstatus(ddata);
268 			if ((rstval & ddata->cfg.syss_mask) == syss_done)
269 				return 0;
270 			udelay(2); /* Account for udelay flakeyness */
271 		}
272 		error = -ETIMEDOUT;
273 	}
274 
275 	return error;
276 }
277 
278 static int sysc_poll_reset_sysconfig(struct sysc *ddata)
279 {
280 	int error, retries;
281 	u32 sysc_mask, rstval;
282 
283 	sysc_mask = BIT(ddata->cap->regbits->srst_shift);
284 
285 	if (likely(!timekeeping_suspended)) {
286 		error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
287 				rstval, !(rstval & sysc_mask),
288 				100, MAX_MODULE_SOFTRESET_WAIT);
289 	} else {
290 		retries = MAX_MODULE_SOFTRESET_WAIT;
291 		while (retries--) {
292 			rstval = sysc_read_sysconfig(ddata);
293 			if (!(rstval & sysc_mask))
294 				return 0;
295 			udelay(2); /* Account for udelay flakeyness */
296 		}
297 		error = -ETIMEDOUT;
298 	}
299 
300 	return error;
301 }
302 
303 /* Poll on reset status */
304 static int sysc_wait_softreset(struct sysc *ddata)
305 {
306 	int syss_offset, error = 0;
307 
308 	if (ddata->cap->regbits->srst_shift < 0)
309 		return 0;
310 
311 	syss_offset = ddata->offsets[SYSC_SYSSTATUS];
312 
313 	if (syss_offset >= 0)
314 		error = sysc_poll_reset_sysstatus(ddata);
315 	else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
316 		error = sysc_poll_reset_sysconfig(ddata);
317 
318 	return error;
319 }
320 
321 static int sysc_add_named_clock_from_child(struct sysc *ddata,
322 					   const char *name,
323 					   const char *optfck_name)
324 {
325 	struct device_node *np = ddata->dev->of_node;
326 	struct device_node *child;
327 	struct clk_lookup *cl;
328 	struct clk *clock;
329 	const char *n;
330 
331 	if (name)
332 		n = name;
333 	else
334 		n = optfck_name;
335 
336 	/* Does the clock alias already exist? */
337 	clock = of_clk_get_by_name(np, n);
338 	if (!IS_ERR(clock)) {
339 		clk_put(clock);
340 
341 		return 0;
342 	}
343 
344 	child = of_get_next_available_child(np, NULL);
345 	if (!child)
346 		return -ENODEV;
347 
348 	clock = devm_get_clk_from_child(ddata->dev, child, name);
349 	if (IS_ERR(clock))
350 		return PTR_ERR(clock);
351 
352 	/*
353 	 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
354 	 * limit for clk_get(). If cl ever needs to be freed, it should be done
355 	 * with clkdev_drop().
356 	 */
357 	cl = kzalloc(sizeof(*cl), GFP_KERNEL);
358 	if (!cl)
359 		return -ENOMEM;
360 
361 	cl->con_id = n;
362 	cl->dev_id = dev_name(ddata->dev);
363 	cl->clk = clock;
364 	clkdev_add(cl);
365 
366 	clk_put(clock);
367 
368 	return 0;
369 }
370 
371 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
372 {
373 	const char *optfck_name;
374 	int error, index;
375 
376 	if (ddata->nr_clocks < SYSC_OPTFCK0)
377 		index = SYSC_OPTFCK0;
378 	else
379 		index = ddata->nr_clocks;
380 
381 	if (name)
382 		optfck_name = name;
383 	else
384 		optfck_name = clock_names[index];
385 
386 	error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
387 	if (error)
388 		return error;
389 
390 	ddata->clock_roles[index] = optfck_name;
391 	ddata->nr_clocks++;
392 
393 	return 0;
394 }
395 
396 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
397 {
398 	int error, i, index = -ENODEV;
399 
400 	if (!strncmp(clock_names[SYSC_FCK], name, 3))
401 		index = SYSC_FCK;
402 	else if (!strncmp(clock_names[SYSC_ICK], name, 3))
403 		index = SYSC_ICK;
404 
405 	if (index < 0) {
406 		for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
407 			if (!ddata->clocks[i]) {
408 				index = i;
409 				break;
410 			}
411 		}
412 	}
413 
414 	if (index < 0) {
415 		dev_err(ddata->dev, "clock %s not added\n", name);
416 		return index;
417 	}
418 
419 	ddata->clocks[index] = devm_clk_get(ddata->dev, name);
420 	if (IS_ERR(ddata->clocks[index])) {
421 		dev_err(ddata->dev, "clock get error for %s: %li\n",
422 			name, PTR_ERR(ddata->clocks[index]));
423 
424 		return PTR_ERR(ddata->clocks[index]);
425 	}
426 
427 	error = clk_prepare(ddata->clocks[index]);
428 	if (error) {
429 		dev_err(ddata->dev, "clock prepare error for %s: %i\n",
430 			name, error);
431 
432 		return error;
433 	}
434 
435 	return 0;
436 }
437 
438 static int sysc_get_clocks(struct sysc *ddata)
439 {
440 	struct device_node *np = ddata->dev->of_node;
441 	struct property *prop;
442 	const char *name;
443 	int nr_fck = 0, nr_ick = 0, i, error = 0;
444 
445 	ddata->clock_roles = devm_kcalloc(ddata->dev,
446 					  SYSC_MAX_CLOCKS,
447 					  sizeof(*ddata->clock_roles),
448 					  GFP_KERNEL);
449 	if (!ddata->clock_roles)
450 		return -ENOMEM;
451 
452 	of_property_for_each_string(np, "clock-names", prop, name) {
453 		if (!strncmp(clock_names[SYSC_FCK], name, 3))
454 			nr_fck++;
455 		if (!strncmp(clock_names[SYSC_ICK], name, 3))
456 			nr_ick++;
457 		ddata->clock_roles[ddata->nr_clocks] = name;
458 		ddata->nr_clocks++;
459 	}
460 
461 	if (ddata->nr_clocks < 1)
462 		return 0;
463 
464 	if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
465 		error = sysc_init_ext_opt_clock(ddata, NULL);
466 		if (error)
467 			return error;
468 	}
469 
470 	if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
471 		dev_err(ddata->dev, "too many clocks for %pOF\n", np);
472 
473 		return -EINVAL;
474 	}
475 
476 	if (nr_fck > 1 || nr_ick > 1) {
477 		dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
478 
479 		return -EINVAL;
480 	}
481 
482 	/* Always add a slot for main clocks fck and ick even if unused */
483 	if (!nr_fck)
484 		ddata->nr_clocks++;
485 	if (!nr_ick)
486 		ddata->nr_clocks++;
487 
488 	ddata->clocks = devm_kcalloc(ddata->dev,
489 				     ddata->nr_clocks, sizeof(*ddata->clocks),
490 				     GFP_KERNEL);
491 	if (!ddata->clocks)
492 		return -ENOMEM;
493 
494 	for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
495 		const char *name = ddata->clock_roles[i];
496 
497 		if (!name)
498 			continue;
499 
500 		error = sysc_get_one_clock(ddata, name);
501 		if (error)
502 			return error;
503 	}
504 
505 	return 0;
506 }
507 
508 static int sysc_enable_main_clocks(struct sysc *ddata)
509 {
510 	struct clk *clock;
511 	int i, error;
512 
513 	if (!ddata->clocks)
514 		return 0;
515 
516 	for (i = 0; i < SYSC_OPTFCK0; i++) {
517 		clock = ddata->clocks[i];
518 
519 		/* Main clocks may not have ick */
520 		if (IS_ERR_OR_NULL(clock))
521 			continue;
522 
523 		error = clk_enable(clock);
524 		if (error)
525 			goto err_disable;
526 	}
527 
528 	return 0;
529 
530 err_disable:
531 	for (i--; i >= 0; i--) {
532 		clock = ddata->clocks[i];
533 
534 		/* Main clocks may not have ick */
535 		if (IS_ERR_OR_NULL(clock))
536 			continue;
537 
538 		clk_disable(clock);
539 	}
540 
541 	return error;
542 }
543 
544 static void sysc_disable_main_clocks(struct sysc *ddata)
545 {
546 	struct clk *clock;
547 	int i;
548 
549 	if (!ddata->clocks)
550 		return;
551 
552 	for (i = 0; i < SYSC_OPTFCK0; i++) {
553 		clock = ddata->clocks[i];
554 		if (IS_ERR_OR_NULL(clock))
555 			continue;
556 
557 		clk_disable(clock);
558 	}
559 }
560 
561 static int sysc_enable_opt_clocks(struct sysc *ddata)
562 {
563 	struct clk *clock;
564 	int i, error;
565 
566 	if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
567 		return 0;
568 
569 	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
570 		clock = ddata->clocks[i];
571 
572 		/* Assume no holes for opt clocks */
573 		if (IS_ERR_OR_NULL(clock))
574 			return 0;
575 
576 		error = clk_enable(clock);
577 		if (error)
578 			goto err_disable;
579 	}
580 
581 	return 0;
582 
583 err_disable:
584 	for (i--; i >= 0; i--) {
585 		clock = ddata->clocks[i];
586 		if (IS_ERR_OR_NULL(clock))
587 			continue;
588 
589 		clk_disable(clock);
590 	}
591 
592 	return error;
593 }
594 
595 static void sysc_disable_opt_clocks(struct sysc *ddata)
596 {
597 	struct clk *clock;
598 	int i;
599 
600 	if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1)
601 		return;
602 
603 	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
604 		clock = ddata->clocks[i];
605 
606 		/* Assume no holes for opt clocks */
607 		if (IS_ERR_OR_NULL(clock))
608 			return;
609 
610 		clk_disable(clock);
611 	}
612 }
613 
614 static void sysc_clkdm_deny_idle(struct sysc *ddata)
615 {
616 	struct ti_sysc_platform_data *pdata;
617 
618 	if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
619 		return;
620 
621 	pdata = dev_get_platdata(ddata->dev);
622 	if (pdata && pdata->clkdm_deny_idle)
623 		pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
624 }
625 
626 static void sysc_clkdm_allow_idle(struct sysc *ddata)
627 {
628 	struct ti_sysc_platform_data *pdata;
629 
630 	if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
631 		return;
632 
633 	pdata = dev_get_platdata(ddata->dev);
634 	if (pdata && pdata->clkdm_allow_idle)
635 		pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
636 }
637 
638 /**
639  * sysc_init_resets - init rstctrl reset line if configured
640  * @ddata: device driver data
641  *
642  * See sysc_rstctrl_reset_deassert().
643  */
644 static int sysc_init_resets(struct sysc *ddata)
645 {
646 	ddata->rsts =
647 		devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
648 
649 	return PTR_ERR_OR_ZERO(ddata->rsts);
650 }
651 
652 /**
653  * sysc_parse_and_check_child_range - parses module IO region from ranges
654  * @ddata: device driver data
655  *
656  * In general we only need rev, syss, and sysc registers and not the whole
657  * module range. But we do want the offsets for these registers from the
658  * module base. This allows us to check them against the legacy hwmod
659  * platform data. Let's also check the ranges are configured properly.
660  */
661 static int sysc_parse_and_check_child_range(struct sysc *ddata)
662 {
663 	struct device_node *np = ddata->dev->of_node;
664 	struct of_range_parser parser;
665 	struct of_range range;
666 	int error;
667 
668 	error = of_range_parser_init(&parser, np);
669 	if (error)
670 		return error;
671 
672 	for_each_of_range(&parser, &range) {
673 		ddata->module_pa = range.cpu_addr;
674 		ddata->module_size = range.size;
675 		break;
676 	}
677 
678 	return 0;
679 }
680 
681 /* Interconnect instances to probe before l4_per instances */
682 static struct resource early_bus_ranges[] = {
683 	/* am3/4 l4_wkup */
684 	{ .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
685 	/* omap4/5 and dra7 l4_cfg */
686 	{ .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
687 	/* omap4 l4_wkup */
688 	{ .start = 0x4a300000, .end = 0x4a300000 + 0x30000,  },
689 	/* omap5 and dra7 l4_wkup without dra7 dcan segment */
690 	{ .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000,  },
691 };
692 
693 static atomic_t sysc_defer = ATOMIC_INIT(10);
694 
695 /**
696  * sysc_defer_non_critical - defer non_critical interconnect probing
697  * @ddata: device driver data
698  *
699  * We want to probe l4_cfg and l4_wkup interconnect instances before any
700  * l4_per instances as l4_per instances depend on resources on l4_cfg and
701  * l4_wkup interconnects.
702  */
703 static int sysc_defer_non_critical(struct sysc *ddata)
704 {
705 	struct resource *res;
706 	int i;
707 
708 	if (!atomic_read(&sysc_defer))
709 		return 0;
710 
711 	for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
712 		res = &early_bus_ranges[i];
713 		if (ddata->module_pa >= res->start &&
714 		    ddata->module_pa <= res->end) {
715 			atomic_set(&sysc_defer, 0);
716 
717 			return 0;
718 		}
719 	}
720 
721 	atomic_dec_if_positive(&sysc_defer);
722 
723 	return -EPROBE_DEFER;
724 }
725 
726 static struct device_node *stdout_path;
727 
728 static void sysc_init_stdout_path(struct sysc *ddata)
729 {
730 	struct device_node *np = NULL;
731 	const char *uart;
732 
733 	if (IS_ERR(stdout_path))
734 		return;
735 
736 	if (stdout_path)
737 		return;
738 
739 	np = of_find_node_by_path("/chosen");
740 	if (!np)
741 		goto err;
742 
743 	uart = of_get_property(np, "stdout-path", NULL);
744 	if (!uart)
745 		goto err;
746 
747 	np = of_find_node_by_path(uart);
748 	if (!np)
749 		goto err;
750 
751 	stdout_path = np;
752 
753 	return;
754 
755 err:
756 	stdout_path = ERR_PTR(-ENODEV);
757 }
758 
759 static void sysc_check_quirk_stdout(struct sysc *ddata,
760 				    struct device_node *np)
761 {
762 	sysc_init_stdout_path(ddata);
763 	if (np != stdout_path)
764 		return;
765 
766 	ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
767 				SYSC_QUIRK_NO_RESET_ON_INIT;
768 }
769 
770 /**
771  * sysc_check_one_child - check child configuration
772  * @ddata: device driver data
773  * @np: child device node
774  *
775  * Let's avoid messy situations where we have new interconnect target
776  * node but children have "ti,hwmods". These belong to the interconnect
777  * target node and are managed by this driver.
778  */
779 static void sysc_check_one_child(struct sysc *ddata,
780 				 struct device_node *np)
781 {
782 	const char *name;
783 
784 	name = of_get_property(np, "ti,hwmods", NULL);
785 	if (name && !of_device_is_compatible(np, "ti,sysc"))
786 		dev_warn(ddata->dev, "really a child ti,hwmods property?");
787 
788 	sysc_check_quirk_stdout(ddata, np);
789 	sysc_parse_dts_quirks(ddata, np, true);
790 }
791 
792 static void sysc_check_children(struct sysc *ddata)
793 {
794 	struct device_node *child;
795 
796 	for_each_child_of_node(ddata->dev->of_node, child)
797 		sysc_check_one_child(ddata, child);
798 }
799 
800 /*
801  * So far only I2C uses 16-bit read access with clockactivity with revision
802  * in two registers with stride of 4. We can detect this based on the rev
803  * register size to configure things far enough to be able to properly read
804  * the revision register.
805  */
806 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
807 {
808 	if (resource_size(res) == 8)
809 		ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
810 }
811 
812 /**
813  * sysc_parse_one - parses the interconnect target module registers
814  * @ddata: device driver data
815  * @reg: register to parse
816  */
817 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
818 {
819 	struct resource *res;
820 	const char *name;
821 
822 	switch (reg) {
823 	case SYSC_REVISION:
824 	case SYSC_SYSCONFIG:
825 	case SYSC_SYSSTATUS:
826 		name = reg_names[reg];
827 		break;
828 	default:
829 		return -EINVAL;
830 	}
831 
832 	res = platform_get_resource_byname(to_platform_device(ddata->dev),
833 					   IORESOURCE_MEM, name);
834 	if (!res) {
835 		ddata->offsets[reg] = -ENODEV;
836 
837 		return 0;
838 	}
839 
840 	ddata->offsets[reg] = res->start - ddata->module_pa;
841 	if (reg == SYSC_REVISION)
842 		sysc_check_quirk_16bit(ddata, res);
843 
844 	return 0;
845 }
846 
847 static int sysc_parse_registers(struct sysc *ddata)
848 {
849 	int i, error;
850 
851 	for (i = 0; i < SYSC_MAX_REGS; i++) {
852 		error = sysc_parse_one(ddata, i);
853 		if (error)
854 			return error;
855 	}
856 
857 	return 0;
858 }
859 
860 /**
861  * sysc_check_registers - check for misconfigured register overlaps
862  * @ddata: device driver data
863  */
864 static int sysc_check_registers(struct sysc *ddata)
865 {
866 	int i, j, nr_regs = 0, nr_matches = 0;
867 
868 	for (i = 0; i < SYSC_MAX_REGS; i++) {
869 		if (ddata->offsets[i] < 0)
870 			continue;
871 
872 		if (ddata->offsets[i] > (ddata->module_size - 4)) {
873 			dev_err(ddata->dev, "register outside module range");
874 
875 				return -EINVAL;
876 		}
877 
878 		for (j = 0; j < SYSC_MAX_REGS; j++) {
879 			if (ddata->offsets[j] < 0)
880 				continue;
881 
882 			if (ddata->offsets[i] == ddata->offsets[j])
883 				nr_matches++;
884 		}
885 		nr_regs++;
886 	}
887 
888 	if (nr_matches > nr_regs) {
889 		dev_err(ddata->dev, "overlapping registers: (%i/%i)",
890 			nr_regs, nr_matches);
891 
892 		return -EINVAL;
893 	}
894 
895 	return 0;
896 }
897 
898 /**
899  * sysc_ioremap - ioremap register space for the interconnect target module
900  * @ddata: device driver data
901  *
902  * Note that the interconnect target module registers can be anywhere
903  * within the interconnect target module range. For example, SGX has
904  * them at offset 0x1fc00 in the 32MB module address space. And cpsw
905  * has them at offset 0x1200 in the CPSW_WR child. Usually the
906  * interconnect target module registers are at the beginning of
907  * the module range though.
908  */
909 static int sysc_ioremap(struct sysc *ddata)
910 {
911 	int size;
912 
913 	if (ddata->offsets[SYSC_REVISION] < 0 &&
914 	    ddata->offsets[SYSC_SYSCONFIG] < 0 &&
915 	    ddata->offsets[SYSC_SYSSTATUS] < 0) {
916 		size = ddata->module_size;
917 	} else {
918 		size = max3(ddata->offsets[SYSC_REVISION],
919 			    ddata->offsets[SYSC_SYSCONFIG],
920 			    ddata->offsets[SYSC_SYSSTATUS]);
921 
922 		if (size < SZ_1K)
923 			size = SZ_1K;
924 
925 		if ((size + sizeof(u32)) > ddata->module_size)
926 			size = ddata->module_size;
927 	}
928 
929 	ddata->module_va = devm_ioremap(ddata->dev,
930 					ddata->module_pa,
931 					size + sizeof(u32));
932 	if (!ddata->module_va)
933 		return -EIO;
934 
935 	return 0;
936 }
937 
938 /**
939  * sysc_map_and_check_registers - ioremap and check device registers
940  * @ddata: device driver data
941  */
942 static int sysc_map_and_check_registers(struct sysc *ddata)
943 {
944 	struct device_node *np = ddata->dev->of_node;
945 	int error;
946 
947 	error = sysc_parse_and_check_child_range(ddata);
948 	if (error)
949 		return error;
950 
951 	error = sysc_defer_non_critical(ddata);
952 	if (error)
953 		return error;
954 
955 	sysc_check_children(ddata);
956 
957 	if (!of_property_present(np, "reg"))
958 		return 0;
959 
960 	error = sysc_parse_registers(ddata);
961 	if (error)
962 		return error;
963 
964 	error = sysc_ioremap(ddata);
965 	if (error)
966 		return error;
967 
968 	error = sysc_check_registers(ddata);
969 	if (error)
970 		return error;
971 
972 	return 0;
973 }
974 
975 /**
976  * sysc_show_rev - read and show interconnect target module revision
977  * @bufp: buffer to print the information to
978  * @ddata: device driver data
979  */
980 static int sysc_show_rev(char *bufp, struct sysc *ddata)
981 {
982 	int len;
983 
984 	if (ddata->offsets[SYSC_REVISION] < 0)
985 		return sprintf(bufp, ":NA");
986 
987 	len = sprintf(bufp, ":%08x", ddata->revision);
988 
989 	return len;
990 }
991 
992 static int sysc_show_reg(struct sysc *ddata,
993 			 char *bufp, enum sysc_registers reg)
994 {
995 	if (ddata->offsets[reg] < 0)
996 		return sprintf(bufp, ":NA");
997 
998 	return sprintf(bufp, ":%x", ddata->offsets[reg]);
999 }
1000 
1001 static int sysc_show_name(char *bufp, struct sysc *ddata)
1002 {
1003 	if (!ddata->name)
1004 		return 0;
1005 
1006 	return sprintf(bufp, ":%s", ddata->name);
1007 }
1008 
1009 /**
1010  * sysc_show_registers - show information about interconnect target module
1011  * @ddata: device driver data
1012  */
1013 static void sysc_show_registers(struct sysc *ddata)
1014 {
1015 	char buf[128];
1016 	char *bufp = buf;
1017 	int i;
1018 
1019 	for (i = 0; i < SYSC_MAX_REGS; i++)
1020 		bufp += sysc_show_reg(ddata, bufp, i);
1021 
1022 	bufp += sysc_show_rev(bufp, ddata);
1023 	bufp += sysc_show_name(bufp, ddata);
1024 
1025 	dev_dbg(ddata->dev, "%llx:%x%s\n",
1026 		ddata->module_pa, ddata->module_size,
1027 		buf);
1028 }
1029 
1030 /**
1031  * sysc_write_sysconfig - handle sysconfig quirks for register write
1032  * @ddata: device driver data
1033  * @value: register value
1034  */
1035 static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
1036 {
1037 	if (ddata->module_unlock_quirk)
1038 		ddata->module_unlock_quirk(ddata);
1039 
1040 	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
1041 
1042 	if (ddata->module_lock_quirk)
1043 		ddata->module_lock_quirk(ddata);
1044 }
1045 
1046 #define SYSC_IDLE_MASK	(SYSC_NR_IDLEMODES - 1)
1047 #define SYSC_CLOCACT_ICK	2
1048 
1049 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1050 static int sysc_enable_module(struct device *dev)
1051 {
1052 	struct sysc *ddata;
1053 	const struct sysc_regbits *regbits;
1054 	u32 reg, idlemodes, best_mode;
1055 	int error;
1056 
1057 	ddata = dev_get_drvdata(dev);
1058 
1059 	/*
1060 	 * Some modules like DSS reset automatically on idle. Enable optional
1061 	 * reset clocks and wait for OCP softreset to complete.
1062 	 */
1063 	if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
1064 		error = sysc_enable_opt_clocks(ddata);
1065 		if (error) {
1066 			dev_err(ddata->dev,
1067 				"Optional clocks failed for enable: %i\n",
1068 				error);
1069 			return error;
1070 		}
1071 	}
1072 	/*
1073 	 * Some modules like i2c and hdq1w have unusable reset status unless
1074 	 * the module reset quirk is enabled. Skip status check on enable.
1075 	 */
1076 	if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
1077 		error = sysc_wait_softreset(ddata);
1078 		if (error)
1079 			dev_warn(ddata->dev, "OCP softreset timed out\n");
1080 	}
1081 	if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
1082 		sysc_disable_opt_clocks(ddata);
1083 
1084 	/*
1085 	 * Some subsystem private interconnects, like DSS top level module,
1086 	 * need only the automatic OCP softreset handling with no sysconfig
1087 	 * register bits to configure.
1088 	 */
1089 	if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1090 		return 0;
1091 
1092 	regbits = ddata->cap->regbits;
1093 	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1094 
1095 	/*
1096 	 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
1097 	 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
1098 	 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
1099 	 */
1100 	if (regbits->clkact_shift >= 0 &&
1101 	    (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
1102 		reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
1103 
1104 	/* Set SIDLE mode */
1105 	idlemodes = ddata->cfg.sidlemodes;
1106 	if (!idlemodes || regbits->sidle_shift < 0)
1107 		goto set_midle;
1108 
1109 	if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
1110 				 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
1111 		best_mode = SYSC_IDLE_NO;
1112 
1113 		/* Clear WAKEUP */
1114 		if (regbits->enwkup_shift >= 0 &&
1115 		    ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1116 			reg &= ~BIT(regbits->enwkup_shift);
1117 	} else {
1118 		best_mode = fls(ddata->cfg.sidlemodes) - 1;
1119 		if (best_mode > SYSC_IDLE_MASK) {
1120 			dev_err(dev, "%s: invalid sidlemode\n", __func__);
1121 			return -EINVAL;
1122 		}
1123 
1124 		/* Set WAKEUP */
1125 		if (regbits->enwkup_shift >= 0 &&
1126 		    ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1127 			reg |= BIT(regbits->enwkup_shift);
1128 	}
1129 
1130 	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1131 	reg |= best_mode << regbits->sidle_shift;
1132 	sysc_write_sysconfig(ddata, reg);
1133 
1134 set_midle:
1135 	/* Set MIDLE mode */
1136 	idlemodes = ddata->cfg.midlemodes;
1137 	if (!idlemodes || regbits->midle_shift < 0)
1138 		goto set_autoidle;
1139 
1140 	best_mode = fls(ddata->cfg.midlemodes) - 1;
1141 	if (best_mode > SYSC_IDLE_MASK) {
1142 		dev_err(dev, "%s: invalid midlemode\n", __func__);
1143 		error = -EINVAL;
1144 		goto save_context;
1145 	}
1146 
1147 	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
1148 		best_mode = SYSC_IDLE_NO;
1149 
1150 	reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1151 	reg |= best_mode << regbits->midle_shift;
1152 	sysc_write_sysconfig(ddata, reg);
1153 
1154 set_autoidle:
1155 	/* Autoidle bit must enabled separately if available */
1156 	if (regbits->autoidle_shift >= 0 &&
1157 	    ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
1158 		reg |= 1 << regbits->autoidle_shift;
1159 		sysc_write_sysconfig(ddata, reg);
1160 	}
1161 
1162 	error = 0;
1163 
1164 save_context:
1165 	/* Save context and flush posted write */
1166 	ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1167 
1168 	if (ddata->module_enable_quirk)
1169 		ddata->module_enable_quirk(ddata);
1170 
1171 	return error;
1172 }
1173 
1174 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
1175 {
1176 	if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
1177 		*best_mode = SYSC_IDLE_SMART_WKUP;
1178 	else if (idlemodes & BIT(SYSC_IDLE_SMART))
1179 		*best_mode = SYSC_IDLE_SMART;
1180 	else if (idlemodes & BIT(SYSC_IDLE_FORCE))
1181 		*best_mode = SYSC_IDLE_FORCE;
1182 	else
1183 		return -EINVAL;
1184 
1185 	return 0;
1186 }
1187 
1188 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
1189 static int sysc_disable_module(struct device *dev)
1190 {
1191 	struct sysc *ddata;
1192 	const struct sysc_regbits *regbits;
1193 	u32 reg, idlemodes, best_mode;
1194 	int ret;
1195 
1196 	ddata = dev_get_drvdata(dev);
1197 	if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
1198 		return 0;
1199 
1200 	if (ddata->module_disable_quirk)
1201 		ddata->module_disable_quirk(ddata);
1202 
1203 	regbits = ddata->cap->regbits;
1204 	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1205 
1206 	/* Set MIDLE mode */
1207 	idlemodes = ddata->cfg.midlemodes;
1208 	if (!idlemodes || regbits->midle_shift < 0)
1209 		goto set_sidle;
1210 
1211 	ret = sysc_best_idle_mode(idlemodes, &best_mode);
1212 	if (ret) {
1213 		dev_err(dev, "%s: invalid midlemode\n", __func__);
1214 		return ret;
1215 	}
1216 
1217 	if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) ||
1218 	    ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
1219 		best_mode = SYSC_IDLE_FORCE;
1220 
1221 	reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
1222 	reg |= best_mode << regbits->midle_shift;
1223 	sysc_write_sysconfig(ddata, reg);
1224 
1225 set_sidle:
1226 	/* Set SIDLE mode */
1227 	idlemodes = ddata->cfg.sidlemodes;
1228 	if (!idlemodes || regbits->sidle_shift < 0) {
1229 		ret = 0;
1230 		goto save_context;
1231 	}
1232 
1233 	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
1234 		best_mode = SYSC_IDLE_FORCE;
1235 	} else {
1236 		ret = sysc_best_idle_mode(idlemodes, &best_mode);
1237 		if (ret) {
1238 			dev_err(dev, "%s: invalid sidlemode\n", __func__);
1239 			ret = -EINVAL;
1240 			goto save_context;
1241 		}
1242 	}
1243 
1244 	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) {
1245 		/* Set WAKEUP */
1246 		if (regbits->enwkup_shift >= 0 &&
1247 		    ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
1248 			reg |= BIT(regbits->enwkup_shift);
1249 	}
1250 
1251 	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1252 	reg |= best_mode << regbits->sidle_shift;
1253 	if (regbits->autoidle_shift >= 0 &&
1254 	    ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1255 		reg |= 1 << regbits->autoidle_shift;
1256 	sysc_write_sysconfig(ddata, reg);
1257 
1258 	ret = 0;
1259 
1260 save_context:
1261 	/* Save context and flush posted write */
1262 	ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1263 
1264 	return ret;
1265 }
1266 
1267 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1268 						      struct sysc *ddata)
1269 {
1270 	struct ti_sysc_platform_data *pdata;
1271 	int error;
1272 
1273 	pdata = dev_get_platdata(ddata->dev);
1274 	if (!pdata)
1275 		return 0;
1276 
1277 	if (!pdata->idle_module)
1278 		return -ENODEV;
1279 
1280 	error = pdata->idle_module(dev, &ddata->cookie);
1281 	if (error)
1282 		dev_err(dev, "%s: could not idle: %i\n",
1283 			__func__, error);
1284 
1285 	reset_control_assert(ddata->rsts);
1286 
1287 	return 0;
1288 }
1289 
1290 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1291 						     struct sysc *ddata)
1292 {
1293 	struct ti_sysc_platform_data *pdata;
1294 	int error;
1295 
1296 	pdata = dev_get_platdata(ddata->dev);
1297 	if (!pdata)
1298 		return 0;
1299 
1300 	if (!pdata->enable_module)
1301 		return -ENODEV;
1302 
1303 	error = pdata->enable_module(dev, &ddata->cookie);
1304 	if (error)
1305 		dev_err(dev, "%s: could not enable: %i\n",
1306 			__func__, error);
1307 
1308 	reset_control_deassert(ddata->rsts);
1309 
1310 	return 0;
1311 }
1312 
1313 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1314 {
1315 	struct sysc *ddata;
1316 	int error = 0;
1317 
1318 	ddata = dev_get_drvdata(dev);
1319 
1320 	if (!ddata->enabled)
1321 		return 0;
1322 
1323 	sysc_clkdm_deny_idle(ddata);
1324 
1325 	if (ddata->legacy_mode) {
1326 		error = sysc_runtime_suspend_legacy(dev, ddata);
1327 		if (error)
1328 			goto err_allow_idle;
1329 	} else {
1330 		error = sysc_disable_module(dev);
1331 		if (error)
1332 			goto err_allow_idle;
1333 	}
1334 
1335 	sysc_disable_main_clocks(ddata);
1336 
1337 	if (sysc_opt_clks_needed(ddata))
1338 		sysc_disable_opt_clocks(ddata);
1339 
1340 	ddata->enabled = false;
1341 
1342 err_allow_idle:
1343 	sysc_clkdm_allow_idle(ddata);
1344 
1345 	reset_control_assert(ddata->rsts);
1346 
1347 	return error;
1348 }
1349 
1350 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1351 {
1352 	struct sysc *ddata;
1353 	int error = 0;
1354 
1355 	ddata = dev_get_drvdata(dev);
1356 
1357 	if (ddata->enabled)
1358 		return 0;
1359 
1360 
1361 	sysc_clkdm_deny_idle(ddata);
1362 
1363 	if (sysc_opt_clks_needed(ddata)) {
1364 		error = sysc_enable_opt_clocks(ddata);
1365 		if (error)
1366 			goto err_allow_idle;
1367 	}
1368 
1369 	error = sysc_enable_main_clocks(ddata);
1370 	if (error)
1371 		goto err_opt_clocks;
1372 
1373 	reset_control_deassert(ddata->rsts);
1374 
1375 	if (ddata->legacy_mode) {
1376 		error = sysc_runtime_resume_legacy(dev, ddata);
1377 		if (error)
1378 			goto err_main_clocks;
1379 	} else {
1380 		error = sysc_enable_module(dev);
1381 		if (error)
1382 			goto err_main_clocks;
1383 	}
1384 
1385 	ddata->enabled = true;
1386 
1387 	sysc_clkdm_allow_idle(ddata);
1388 
1389 	return 0;
1390 
1391 err_main_clocks:
1392 	sysc_disable_main_clocks(ddata);
1393 err_opt_clocks:
1394 	if (sysc_opt_clks_needed(ddata))
1395 		sysc_disable_opt_clocks(ddata);
1396 err_allow_idle:
1397 	sysc_clkdm_allow_idle(ddata);
1398 
1399 	return error;
1400 }
1401 
1402 /*
1403  * Checks if device context was lost. Assumes the sysconfig register value
1404  * after lost context is different from the configured value. Only works for
1405  * enabled devices.
1406  *
1407  * Eventually we may want to also add support to using the context lost
1408  * registers that some SoCs have.
1409  */
1410 static int sysc_check_context(struct sysc *ddata)
1411 {
1412 	u32 reg;
1413 
1414 	if (!ddata->enabled)
1415 		return -ENODATA;
1416 
1417 	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1418 	if (reg == ddata->sysconfig)
1419 		return 0;
1420 
1421 	return -EACCES;
1422 }
1423 
1424 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
1425 {
1426 	struct device *dev = ddata->dev;
1427 	int error;
1428 
1429 	if (ddata->enabled) {
1430 		/* Nothing to do if enabled and context not lost */
1431 		error = sysc_check_context(ddata);
1432 		if (!error)
1433 			return 0;
1434 
1435 		/* Disable target module if it is enabled */
1436 		error = sysc_runtime_suspend(dev);
1437 		if (error)
1438 			dev_warn(dev, "reinit suspend failed: %i\n", error);
1439 	}
1440 
1441 	/* Enable target module */
1442 	error = sysc_runtime_resume(dev);
1443 	if (error)
1444 		dev_warn(dev, "reinit resume failed: %i\n", error);
1445 
1446 	/* Some modules like am335x gpmc need reset and restore of sysconfig */
1447 	if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) {
1448 		error = sysc_reset(ddata);
1449 		if (error)
1450 			dev_warn(dev, "reinit reset failed: %i\n", error);
1451 
1452 		sysc_write_sysconfig(ddata, ddata->sysconfig);
1453 	}
1454 
1455 	if (leave_enabled)
1456 		return error;
1457 
1458 	/* Disable target module if no leave_enabled was set */
1459 	error = sysc_runtime_suspend(dev);
1460 	if (error)
1461 		dev_warn(dev, "reinit suspend failed: %i\n", error);
1462 
1463 	return error;
1464 }
1465 
1466 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1467 {
1468 	struct sysc *ddata;
1469 
1470 	ddata = dev_get_drvdata(dev);
1471 
1472 	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
1473 		return 0;
1474 
1475 	if (!ddata->enabled)
1476 		return 0;
1477 
1478 	ddata->needs_resume = 1;
1479 
1480 	return sysc_runtime_suspend(dev);
1481 }
1482 
1483 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1484 {
1485 	struct sysc *ddata;
1486 	int error = 0;
1487 
1488 	ddata = dev_get_drvdata(dev);
1489 
1490 	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
1491 		return 0;
1492 
1493 	if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
1494 		error = sysc_reinit_module(ddata, ddata->needs_resume);
1495 		if (error)
1496 			dev_warn(dev, "noirq_resume failed: %i\n", error);
1497 	} else if (ddata->needs_resume) {
1498 		error = sysc_runtime_resume(dev);
1499 		if (error)
1500 			dev_warn(dev, "noirq_resume failed: %i\n", error);
1501 	}
1502 
1503 	ddata->needs_resume = 0;
1504 
1505 	return error;
1506 }
1507 
1508 static const struct dev_pm_ops sysc_pm_ops = {
1509 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1510 	SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1511 			   sysc_runtime_resume,
1512 			   NULL)
1513 };
1514 
1515 /* Module revision register based quirks */
1516 struct sysc_revision_quirk {
1517 	const char *name;
1518 	u32 base;
1519 	int rev_offset;
1520 	int sysc_offset;
1521 	int syss_offset;
1522 	u32 revision;
1523 	u32 revision_mask;
1524 	u32 quirks;
1525 };
1526 
1527 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss,		\
1528 		   optrev_val, optrevmask, optquirkmask)		\
1529 	{								\
1530 		.name = (optname),					\
1531 		.base = (optbase),					\
1532 		.rev_offset = (optrev),					\
1533 		.sysc_offset = (optsysc),				\
1534 		.syss_offset = (optsyss),				\
1535 		.revision = (optrev_val),				\
1536 		.revision_mask = (optrevmask),				\
1537 		.quirks = (optquirkmask),				\
1538 	}
1539 
1540 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1541 	/* Quirks that need to be set based on the module address */
1542 	SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
1543 		   SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1544 		   SYSC_QUIRK_SWSUP_SIDLE),
1545 
1546 	/* Quirks that need to be set based on detected module */
1547 	SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
1548 		   SYSC_MODULE_QUIRK_AESS),
1549 	/* Errata i893 handling for dra7 dcan1 and 2 */
1550 	SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1551 		   SYSC_QUIRK_CLKDM_NOAUTO),
1552 	SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
1553 		   SYSC_QUIRK_CLKDM_NOAUTO),
1554 	SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1555 		   SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1556 	SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
1557 		   SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1558 	SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
1559 		   SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET),
1560 	SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1561 		   SYSC_QUIRK_CLKDM_NOAUTO),
1562 	SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
1563 		   SYSC_QUIRK_CLKDM_NOAUTO),
1564 	SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1565 		   SYSC_QUIRK_OPT_CLKS_IN_RESET),
1566 	SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
1567 		   SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST |
1568 		   SYSC_QUIRK_GPMC_DEBUG),
1569 	SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
1570 		   SYSC_QUIRK_OPT_CLKS_NEEDED),
1571 	SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1572 		   SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1573 	SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1574 		   SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1575 	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1576 		   SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1577 	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1578 		   SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1579 	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1580 		   SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1581 	SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1582 		   SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE),
1583 	SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
1584 	SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
1585 		   SYSC_MODULE_QUIRK_SGX),
1586 	SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
1587 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1588 	SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff,
1589 		   SYSC_QUIRK_SWSUP_SIDLE),
1590 	SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
1591 		   SYSC_MODULE_QUIRK_RTC_UNLOCK),
1592 	SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
1593 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1594 	SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
1595 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1596 	SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff,
1597 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1598 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1599 		   SYSC_QUIRK_SWSUP_SIDLE_ACT),
1600 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1601 		   SYSC_QUIRK_SWSUP_SIDLE_ACT),
1602 	/* Uarts on omap4 and later */
1603 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1604 		   SYSC_QUIRK_SWSUP_SIDLE_ACT),
1605 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1606 		   SYSC_QUIRK_SWSUP_SIDLE_ACT),
1607 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
1608 		   SYSC_QUIRK_SWSUP_SIDLE_ACT),
1609 	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
1610 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1611 	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
1612 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY),
1613 	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033,
1614 		   0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1615 		   SYSC_MODULE_QUIRK_OTG),
1616 	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040,
1617 		   0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1618 		   SYSC_MODULE_QUIRK_OTG),
1619 	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1620 		   0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1621 		   SYSC_MODULE_QUIRK_OTG),
1622 	SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
1623 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY |
1624 		   SYSC_QUIRK_REINIT_ON_CTX_LOST),
1625 	SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1626 		   SYSC_MODULE_QUIRK_WDT),
1627 	/* PRUSS on am3, am4 and am5 */
1628 	SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
1629 		   SYSC_MODULE_QUIRK_PRUSS),
1630 	/* Watchdog on am3 and am4 */
1631 	SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1632 		   SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1633 
1634 #ifdef DEBUG
1635 	SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
1636 	SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
1637 	SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
1638 	SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1639 	SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1640 		   0xffff00f0, 0),
1641 	SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
1642 	SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
1643 	SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1644 	SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1645 	SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
1646 	SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
1647 	SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1648 	SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
1649 	SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1650 	SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
1651 	SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
1652 	SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1653 	SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1654 	SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1655 	SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0),
1656 	SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0),
1657 	SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
1658 	SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
1659 	SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
1660 	SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
1661 	SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1662 	SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
1663 	SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0),
1664 	SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
1665 	SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
1666 	SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
1667 	SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1668 	SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
1669 	SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
1670 	SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1671 	SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
1672 	SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
1673 	SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
1674 	SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1675 	SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0),
1676 	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
1677 	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
1678 	SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
1679 	SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1680 	SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1681 	SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
1682 	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
1683 	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
1684 	SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
1685 	SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
1686 	SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
1687 	SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1688 	SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1689 	SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0),
1690 	SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
1691 	SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
1692 	SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0),
1693 	SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0),
1694 	SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
1695 	SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
1696 	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
1697 	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
1698 	/* Some timers on omap4 and later */
1699 	SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
1700 	SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
1701 	SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
1702 	SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
1703 	SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
1704 	SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
1705 	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1706 	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1707 	SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
1708 	SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
1709 #endif
1710 };
1711 
1712 /*
1713  * Early quirks based on module base and register offsets only that are
1714  * needed before the module revision can be read
1715  */
1716 static void sysc_init_early_quirks(struct sysc *ddata)
1717 {
1718 	const struct sysc_revision_quirk *q;
1719 	int i;
1720 
1721 	for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1722 		q = &sysc_revision_quirks[i];
1723 
1724 		if (!q->base)
1725 			continue;
1726 
1727 		if (q->base != ddata->module_pa)
1728 			continue;
1729 
1730 		if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1731 			continue;
1732 
1733 		if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1734 			continue;
1735 
1736 		if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1737 			continue;
1738 
1739 		ddata->name = q->name;
1740 		ddata->cfg.quirks |= q->quirks;
1741 	}
1742 }
1743 
1744 /* Quirks that also consider the revision register value */
1745 static void sysc_init_revision_quirks(struct sysc *ddata)
1746 {
1747 	const struct sysc_revision_quirk *q;
1748 	int i;
1749 
1750 	for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1751 		q = &sysc_revision_quirks[i];
1752 
1753 		if (q->base && q->base != ddata->module_pa)
1754 			continue;
1755 
1756 		if (q->rev_offset != ddata->offsets[SYSC_REVISION])
1757 			continue;
1758 
1759 		if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1760 			continue;
1761 
1762 		if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1763 			continue;
1764 
1765 		if (q->revision == ddata->revision ||
1766 		    (q->revision & q->revision_mask) ==
1767 		    (ddata->revision & q->revision_mask)) {
1768 			ddata->name = q->name;
1769 			ddata->cfg.quirks |= q->quirks;
1770 		}
1771 	}
1772 }
1773 
1774 /*
1775  * DSS needs dispc outputs disabled to reset modules. Returns mask of
1776  * enabled DSS interrupts. Eventually we may be able to do this on
1777  * dispc init rather than top-level DSS init.
1778  */
1779 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
1780 			    bool disable)
1781 {
1782 	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
1783 	const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
1784 	int manager_count;
1785 	bool framedonetv_irq = true;
1786 	u32 val, irq_mask = 0;
1787 
1788 	switch (sysc_soc->soc) {
1789 	case SOC_2420 ... SOC_3630:
1790 		manager_count = 2;
1791 		framedonetv_irq = false;
1792 		break;
1793 	case SOC_4430 ... SOC_4470:
1794 		manager_count = 3;
1795 		break;
1796 	case SOC_5430:
1797 	case SOC_DRA7:
1798 		manager_count = 4;
1799 		break;
1800 	case SOC_AM4:
1801 		manager_count = 1;
1802 		framedonetv_irq = false;
1803 		break;
1804 	case SOC_UNKNOWN:
1805 	default:
1806 		return 0;
1807 	}
1808 
1809 	/* Remap the whole module range to be able to reset dispc outputs */
1810 	devm_iounmap(ddata->dev, ddata->module_va);
1811 	ddata->module_va = devm_ioremap(ddata->dev,
1812 					ddata->module_pa,
1813 					ddata->module_size);
1814 	if (!ddata->module_va)
1815 		return -EIO;
1816 
1817 	/* DISP_CONTROL, shut down lcd and digit on disable if enabled */
1818 	val = sysc_read(ddata, dispc_offset + 0x40);
1819 	lcd_en = val & lcd_en_mask;
1820 	digit_en = val & digit_en_mask;
1821 	if (lcd_en)
1822 		irq_mask |= BIT(0);			/* FRAMEDONE */
1823 	if (digit_en) {
1824 		if (framedonetv_irq)
1825 			irq_mask |= BIT(24);		/* FRAMEDONETV */
1826 		else
1827 			irq_mask |= BIT(2) | BIT(3);	/* EVSYNC bits */
1828 	}
1829 	if (disable && (lcd_en || digit_en))
1830 		sysc_write(ddata, dispc_offset + 0x40,
1831 			   val & ~(lcd_en_mask | digit_en_mask));
1832 
1833 	if (manager_count <= 2)
1834 		return irq_mask;
1835 
1836 	/* DISPC_CONTROL2 */
1837 	val = sysc_read(ddata, dispc_offset + 0x238);
1838 	lcd2_en = val & lcd_en_mask;
1839 	if (lcd2_en)
1840 		irq_mask |= BIT(22);			/* FRAMEDONE2 */
1841 	if (disable && lcd2_en)
1842 		sysc_write(ddata, dispc_offset + 0x238,
1843 			   val & ~lcd_en_mask);
1844 
1845 	if (manager_count <= 3)
1846 		return irq_mask;
1847 
1848 	/* DISPC_CONTROL3 */
1849 	val = sysc_read(ddata, dispc_offset + 0x848);
1850 	lcd3_en = val & lcd_en_mask;
1851 	if (lcd3_en)
1852 		irq_mask |= BIT(30);			/* FRAMEDONE3 */
1853 	if (disable && lcd3_en)
1854 		sysc_write(ddata, dispc_offset + 0x848,
1855 			   val & ~lcd_en_mask);
1856 
1857 	return irq_mask;
1858 }
1859 
1860 /* DSS needs child outputs disabled and SDI registers cleared for reset */
1861 static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
1862 {
1863 	const int dispc_offset = 0x1000;
1864 	int error;
1865 	u32 irq_mask, val;
1866 
1867 	/* Get enabled outputs */
1868 	irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
1869 	if (!irq_mask)
1870 		return;
1871 
1872 	/* Clear IRQSTATUS */
1873 	sysc_write(ddata, dispc_offset + 0x18, irq_mask);
1874 
1875 	/* Disable outputs */
1876 	val = sysc_quirk_dispc(ddata, dispc_offset, true);
1877 
1878 	/* Poll IRQSTATUS */
1879 	error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
1880 				   val, val != irq_mask, 100, 50);
1881 	if (error)
1882 		dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
1883 			 __func__, val, irq_mask);
1884 
1885 	if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) {
1886 		/* Clear DSS_SDI_CONTROL */
1887 		sysc_write(ddata, 0x44, 0);
1888 
1889 		/* Clear DSS_PLL_CONTROL */
1890 		sysc_write(ddata, 0x48, 0);
1891 	}
1892 
1893 	/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
1894 	sysc_write(ddata, 0x40, 0);
1895 }
1896 
1897 /* 1-wire needs module's internal clocks enabled for reset */
1898 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
1899 {
1900 	int offset = 0x0c;	/* HDQ_CTRL_STATUS */
1901 	u16 val;
1902 
1903 	val = sysc_read(ddata, offset);
1904 	val |= BIT(5);
1905 	sysc_write(ddata, offset, val);
1906 }
1907 
1908 /* AESS (Audio Engine SubSystem) needs autogating set after enable */
1909 static void sysc_module_enable_quirk_aess(struct sysc *ddata)
1910 {
1911 	int offset = 0x7c;	/* AESS_AUTO_GATING_ENABLE */
1912 
1913 	sysc_write(ddata, offset, 1);
1914 }
1915 
1916 /* I2C needs to be disabled for reset */
1917 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1918 {
1919 	int offset;
1920 	u16 val;
1921 
1922 	/* I2C_CON, omap2/3 is different from omap4 and later */
1923 	if ((ddata->revision & 0xffffff00) == 0x001f0000)
1924 		offset = 0x24;
1925 	else
1926 		offset = 0xa4;
1927 
1928 	/* I2C_EN */
1929 	val = sysc_read(ddata, offset);
1930 	if (enable)
1931 		val |= BIT(15);
1932 	else
1933 		val &= ~BIT(15);
1934 	sysc_write(ddata, offset, val);
1935 }
1936 
1937 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
1938 {
1939 	sysc_clk_quirk_i2c(ddata, false);
1940 }
1941 
1942 static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
1943 {
1944 	sysc_clk_quirk_i2c(ddata, true);
1945 }
1946 
1947 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
1948 static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
1949 {
1950 	u32 val, kick0_val = 0, kick1_val = 0;
1951 	unsigned long flags;
1952 	int error;
1953 
1954 	if (!lock) {
1955 		kick0_val = 0x83e70b13;
1956 		kick1_val = 0x95a4f1e0;
1957 	}
1958 
1959 	local_irq_save(flags);
1960 	/* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
1961 	error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
1962 					  !(val & BIT(0)), 100, 50);
1963 	if (error)
1964 		dev_warn(ddata->dev, "rtc busy timeout\n");
1965 	/* Now we have ~15 microseconds to read/write various registers */
1966 	sysc_write(ddata, 0x6c, kick0_val);
1967 	sysc_write(ddata, 0x70, kick1_val);
1968 	local_irq_restore(flags);
1969 }
1970 
1971 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
1972 {
1973 	sysc_quirk_rtc(ddata, false);
1974 }
1975 
1976 static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
1977 {
1978 	sysc_quirk_rtc(ddata, true);
1979 }
1980 
1981 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */
1982 static void sysc_module_enable_quirk_otg(struct sysc *ddata)
1983 {
1984 	int offset = 0x414;	/* OTG_FORCESTDBY */
1985 
1986 	sysc_write(ddata, offset, 0);
1987 }
1988 
1989 static void sysc_module_disable_quirk_otg(struct sysc *ddata)
1990 {
1991 	int offset = 0x414;	/* OTG_FORCESTDBY */
1992 	u32 val = BIT(0);	/* ENABLEFORCE */
1993 
1994 	sysc_write(ddata, offset, val);
1995 }
1996 
1997 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1998 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1999 {
2000 	int offset = 0xff08;	/* OCP_DEBUG_CONFIG */
2001 	u32 val = BIT(31);	/* THALIA_INT_BYPASS */
2002 
2003 	sysc_write(ddata, offset, val);
2004 }
2005 
2006 /* Watchdog timer needs a disable sequence after reset */
2007 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
2008 {
2009 	int wps, spr, error;
2010 	u32 val;
2011 
2012 	wps = 0x34;
2013 	spr = 0x48;
2014 
2015 	sysc_write(ddata, spr, 0xaaaa);
2016 	error = readl_poll_timeout(ddata->module_va + wps, val,
2017 				   !(val & 0x10), 100,
2018 				   MAX_MODULE_SOFTRESET_WAIT);
2019 	if (error)
2020 		dev_warn(ddata->dev, "wdt disable step1 failed\n");
2021 
2022 	sysc_write(ddata, spr, 0x5555);
2023 	error = readl_poll_timeout(ddata->module_va + wps, val,
2024 				   !(val & 0x10), 100,
2025 				   MAX_MODULE_SOFTRESET_WAIT);
2026 	if (error)
2027 		dev_warn(ddata->dev, "wdt disable step2 failed\n");
2028 }
2029 
2030 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
2031 static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
2032 {
2033 	u32 reg;
2034 
2035 	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
2036 	reg |= SYSC_PRUSS_STANDBY_INIT;
2037 	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
2038 }
2039 
2040 static void sysc_init_module_quirks(struct sysc *ddata)
2041 {
2042 	if (ddata->legacy_mode || !ddata->name)
2043 		return;
2044 
2045 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
2046 		ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
2047 
2048 		return;
2049 	}
2050 
2051 #ifdef CONFIG_OMAP_GPMC_DEBUG
2052 	if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
2053 		ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT;
2054 
2055 		return;
2056 	}
2057 #endif
2058 
2059 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
2060 		ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
2061 		ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
2062 
2063 		return;
2064 	}
2065 
2066 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
2067 		ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
2068 
2069 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
2070 		ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
2071 
2072 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
2073 		ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
2074 		ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
2075 
2076 		return;
2077 	}
2078 
2079 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) {
2080 		ddata->module_enable_quirk = sysc_module_enable_quirk_otg;
2081 		ddata->module_disable_quirk = sysc_module_disable_quirk_otg;
2082 	}
2083 
2084 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
2085 		ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
2086 
2087 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
2088 		ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
2089 		ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
2090 	}
2091 
2092 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
2093 		ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
2094 }
2095 
2096 static int sysc_clockdomain_init(struct sysc *ddata)
2097 {
2098 	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2099 	struct clk *fck = NULL, *ick = NULL;
2100 	int error;
2101 
2102 	if (!pdata || !pdata->init_clockdomain)
2103 		return 0;
2104 
2105 	switch (ddata->nr_clocks) {
2106 	case 2:
2107 		ick = ddata->clocks[SYSC_ICK];
2108 		fallthrough;
2109 	case 1:
2110 		fck = ddata->clocks[SYSC_FCK];
2111 		break;
2112 	case 0:
2113 		return 0;
2114 	}
2115 
2116 	error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
2117 	if (!error || error == -ENODEV)
2118 		return 0;
2119 
2120 	return error;
2121 }
2122 
2123 /*
2124  * Note that pdata->init_module() typically does a reset first. After
2125  * pdata->init_module() is done, PM runtime can be used for the interconnect
2126  * target module.
2127  */
2128 static int sysc_legacy_init(struct sysc *ddata)
2129 {
2130 	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2131 	int error;
2132 
2133 	if (!pdata || !pdata->init_module)
2134 		return 0;
2135 
2136 	error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
2137 	if (error == -EEXIST)
2138 		error = 0;
2139 
2140 	return error;
2141 }
2142 
2143 /*
2144  * Note that the caller must ensure the interconnect target module is enabled
2145  * before calling reset. Otherwise reset will not complete.
2146  */
2147 static int sysc_reset(struct sysc *ddata)
2148 {
2149 	int sysc_offset, sysc_val, error;
2150 	u32 sysc_mask;
2151 
2152 	sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
2153 
2154 	if (ddata->legacy_mode ||
2155 	    ddata->cap->regbits->srst_shift < 0)
2156 		return 0;
2157 
2158 	sysc_mask = BIT(ddata->cap->regbits->srst_shift);
2159 
2160 	if (ddata->pre_reset_quirk)
2161 		ddata->pre_reset_quirk(ddata);
2162 
2163 	if (sysc_offset >= 0) {
2164 		sysc_val = sysc_read_sysconfig(ddata);
2165 		sysc_val |= sysc_mask;
2166 		sysc_write(ddata, sysc_offset, sysc_val);
2167 
2168 		/*
2169 		 * Some devices need a delay before reading registers
2170 		 * after reset. Presumably a srst_udelay is not needed
2171 		 * for devices that use a rstctrl register reset.
2172 		 */
2173 		if (ddata->cfg.srst_udelay)
2174 			fsleep(ddata->cfg.srst_udelay);
2175 
2176 		/*
2177 		 * Flush posted write. For devices needing srst_udelay
2178 		 * this should trigger an interconnect error if the
2179 		 * srst_udelay value is needed but not configured.
2180 		 */
2181 		sysc_val = sysc_read_sysconfig(ddata);
2182 	}
2183 
2184 	if (ddata->post_reset_quirk)
2185 		ddata->post_reset_quirk(ddata);
2186 
2187 	error = sysc_wait_softreset(ddata);
2188 	if (error)
2189 		dev_warn(ddata->dev, "OCP softreset timed out\n");
2190 
2191 	if (ddata->reset_done_quirk)
2192 		ddata->reset_done_quirk(ddata);
2193 
2194 	return error;
2195 }
2196 
2197 /*
2198  * At this point the module is configured enough to read the revision but
2199  * module may not be completely configured yet to use PM runtime. Enable
2200  * all clocks directly during init to configure the quirks needed for PM
2201  * runtime based on the revision register.
2202  */
2203 static int sysc_init_module(struct sysc *ddata)
2204 {
2205 	bool rstctrl_deasserted = false;
2206 	int error = 0;
2207 
2208 	error = sysc_clockdomain_init(ddata);
2209 	if (error)
2210 		return error;
2211 
2212 	sysc_clkdm_deny_idle(ddata);
2213 
2214 	/*
2215 	 * Always enable clocks. The bootloader may or may not have enabled
2216 	 * the related clocks.
2217 	 */
2218 	error = sysc_enable_opt_clocks(ddata);
2219 	if (error)
2220 		return error;
2221 
2222 	error = sysc_enable_main_clocks(ddata);
2223 	if (error)
2224 		goto err_opt_clocks;
2225 
2226 	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2227 		error = reset_control_deassert(ddata->rsts);
2228 		if (error)
2229 			goto err_main_clocks;
2230 		rstctrl_deasserted = true;
2231 	}
2232 
2233 	ddata->revision = sysc_read_revision(ddata);
2234 	sysc_init_revision_quirks(ddata);
2235 	sysc_init_module_quirks(ddata);
2236 
2237 	if (ddata->legacy_mode) {
2238 		error = sysc_legacy_init(ddata);
2239 		if (error)
2240 			goto err_main_clocks;
2241 	}
2242 
2243 	if (!ddata->legacy_mode) {
2244 		error = sysc_enable_module(ddata->dev);
2245 		if (error)
2246 			goto err_main_clocks;
2247 	}
2248 
2249 	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
2250 		error = sysc_reset(ddata);
2251 		if (error)
2252 			dev_err(ddata->dev, "Reset failed with %d\n", error);
2253 
2254 		if (error && !ddata->legacy_mode)
2255 			sysc_disable_module(ddata->dev);
2256 	}
2257 
2258 err_main_clocks:
2259 	if (error)
2260 		sysc_disable_main_clocks(ddata);
2261 err_opt_clocks:
2262 	/* No re-enable of clockdomain autoidle to prevent module autoidle */
2263 	if (error) {
2264 		sysc_disable_opt_clocks(ddata);
2265 		sysc_clkdm_allow_idle(ddata);
2266 	}
2267 
2268 	if (error && rstctrl_deasserted &&
2269 	    !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
2270 		reset_control_assert(ddata->rsts);
2271 
2272 	return error;
2273 }
2274 
2275 static int sysc_init_sysc_mask(struct sysc *ddata)
2276 {
2277 	struct device_node *np = ddata->dev->of_node;
2278 	int error;
2279 	u32 val;
2280 
2281 	error = of_property_read_u32(np, "ti,sysc-mask", &val);
2282 	if (error)
2283 		return 0;
2284 
2285 	ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
2286 
2287 	return 0;
2288 }
2289 
2290 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
2291 			      const char *name)
2292 {
2293 	struct device_node *np = ddata->dev->of_node;
2294 	struct property *prop;
2295 	const __be32 *p;
2296 	u32 val;
2297 
2298 	of_property_for_each_u32(np, name, prop, p, val) {
2299 		if (val >= SYSC_NR_IDLEMODES) {
2300 			dev_err(ddata->dev, "invalid idlemode: %i\n", val);
2301 			return -EINVAL;
2302 		}
2303 		*idlemodes |=  (1 << val);
2304 	}
2305 
2306 	return 0;
2307 }
2308 
2309 static int sysc_init_idlemodes(struct sysc *ddata)
2310 {
2311 	int error;
2312 
2313 	error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
2314 				   "ti,sysc-midle");
2315 	if (error)
2316 		return error;
2317 
2318 	error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
2319 				   "ti,sysc-sidle");
2320 	if (error)
2321 		return error;
2322 
2323 	return 0;
2324 }
2325 
2326 /*
2327  * Only some devices on omap4 and later have SYSCONFIG reset done
2328  * bit. We can detect this if there is no SYSSTATUS at all, or the
2329  * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
2330  * have multiple bits for the child devices like OHCI and EHCI.
2331  * Depends on SYSC being parsed first.
2332  */
2333 static int sysc_init_syss_mask(struct sysc *ddata)
2334 {
2335 	struct device_node *np = ddata->dev->of_node;
2336 	int error;
2337 	u32 val;
2338 
2339 	error = of_property_read_u32(np, "ti,syss-mask", &val);
2340 	if (error) {
2341 		if ((ddata->cap->type == TI_SYSC_OMAP4 ||
2342 		     ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
2343 		    (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2344 			ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2345 
2346 		return 0;
2347 	}
2348 
2349 	if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
2350 		ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
2351 
2352 	ddata->cfg.syss_mask = val;
2353 
2354 	return 0;
2355 }
2356 
2357 /*
2358  * Many child device drivers need to have fck and opt clocks available
2359  * to get the clock rate for device internal configuration etc.
2360  */
2361 static int sysc_child_add_named_clock(struct sysc *ddata,
2362 				      struct device *child,
2363 				      const char *name)
2364 {
2365 	struct clk *clk;
2366 	struct clk_lookup *l;
2367 	int error = 0;
2368 
2369 	if (!name)
2370 		return 0;
2371 
2372 	clk = clk_get(child, name);
2373 	if (!IS_ERR(clk)) {
2374 		error = -EEXIST;
2375 		goto put_clk;
2376 	}
2377 
2378 	clk = clk_get(ddata->dev, name);
2379 	if (IS_ERR(clk))
2380 		return -ENODEV;
2381 
2382 	l = clkdev_create(clk, name, dev_name(child));
2383 	if (!l)
2384 		error = -ENOMEM;
2385 put_clk:
2386 	clk_put(clk);
2387 
2388 	return error;
2389 }
2390 
2391 static int sysc_child_add_clocks(struct sysc *ddata,
2392 				 struct device *child)
2393 {
2394 	int i, error;
2395 
2396 	for (i = 0; i < ddata->nr_clocks; i++) {
2397 		error = sysc_child_add_named_clock(ddata,
2398 						   child,
2399 						   ddata->clock_roles[i]);
2400 		if (error && error != -EEXIST) {
2401 			dev_err(ddata->dev, "could not add child clock %s: %i\n",
2402 				ddata->clock_roles[i], error);
2403 
2404 			return error;
2405 		}
2406 	}
2407 
2408 	return 0;
2409 }
2410 
2411 static const struct device_type sysc_device_type = {
2412 };
2413 
2414 static struct sysc *sysc_child_to_parent(struct device *dev)
2415 {
2416 	struct device *parent = dev->parent;
2417 
2418 	if (!parent || parent->type != &sysc_device_type)
2419 		return NULL;
2420 
2421 	return dev_get_drvdata(parent);
2422 }
2423 
2424 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
2425 {
2426 	struct sysc *ddata;
2427 	int error;
2428 
2429 	ddata = sysc_child_to_parent(dev);
2430 
2431 	error = pm_generic_runtime_suspend(dev);
2432 	if (error)
2433 		return error;
2434 
2435 	if (!ddata->enabled)
2436 		return 0;
2437 
2438 	return sysc_runtime_suspend(ddata->dev);
2439 }
2440 
2441 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
2442 {
2443 	struct sysc *ddata;
2444 	int error;
2445 
2446 	ddata = sysc_child_to_parent(dev);
2447 
2448 	if (!ddata->enabled) {
2449 		error = sysc_runtime_resume(ddata->dev);
2450 		if (error < 0)
2451 			dev_err(ddata->dev,
2452 				"%s error: %i\n", __func__, error);
2453 	}
2454 
2455 	return pm_generic_runtime_resume(dev);
2456 }
2457 
2458 /* Caller needs to take list_lock if ever used outside of cpu_pm */
2459 static void sysc_reinit_modules(struct sysc_soc_info *soc)
2460 {
2461 	struct sysc_module *module;
2462 	struct sysc *ddata;
2463 
2464 	list_for_each_entry(module, &sysc_soc->restored_modules, node) {
2465 		ddata = module->ddata;
2466 		sysc_reinit_module(ddata, ddata->enabled);
2467 	}
2468 }
2469 
2470 /**
2471  * sysc_context_notifier - optionally reset and restore module after idle
2472  * @nb: notifier block
2473  * @cmd: unused
2474  * @v: unused
2475  *
2476  * Some interconnect target modules need to be restored, or reset and restored
2477  * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
2478  * OTG and GPMC target modules even if the modules are unused.
2479  */
2480 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
2481 				 void *v)
2482 {
2483 	struct sysc_soc_info *soc;
2484 
2485 	soc = container_of(nb, struct sysc_soc_info, nb);
2486 
2487 	switch (cmd) {
2488 	case CPU_CLUSTER_PM_ENTER:
2489 		break;
2490 	case CPU_CLUSTER_PM_ENTER_FAILED:	/* No need to restore context */
2491 		break;
2492 	case CPU_CLUSTER_PM_EXIT:
2493 		sysc_reinit_modules(soc);
2494 		break;
2495 	}
2496 
2497 	return NOTIFY_OK;
2498 }
2499 
2500 /**
2501  * sysc_add_restored - optionally add reset and restore quirk hanlling
2502  * @ddata: device data
2503  */
2504 static void sysc_add_restored(struct sysc *ddata)
2505 {
2506 	struct sysc_module *restored_module;
2507 
2508 	restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
2509 	if (!restored_module)
2510 		return;
2511 
2512 	restored_module->ddata = ddata;
2513 
2514 	mutex_lock(&sysc_soc->list_lock);
2515 
2516 	list_add(&restored_module->node, &sysc_soc->restored_modules);
2517 
2518 	if (sysc_soc->nb.notifier_call)
2519 		goto out_unlock;
2520 
2521 	sysc_soc->nb.notifier_call = sysc_context_notifier;
2522 	cpu_pm_register_notifier(&sysc_soc->nb);
2523 
2524 out_unlock:
2525 	mutex_unlock(&sysc_soc->list_lock);
2526 }
2527 
2528 static int sysc_notifier_call(struct notifier_block *nb,
2529 			      unsigned long event, void *device)
2530 {
2531 	struct device *dev = device;
2532 	struct sysc *ddata;
2533 	int error;
2534 
2535 	ddata = sysc_child_to_parent(dev);
2536 	if (!ddata)
2537 		return NOTIFY_DONE;
2538 
2539 	switch (event) {
2540 	case BUS_NOTIFY_ADD_DEVICE:
2541 		error = sysc_child_add_clocks(ddata, dev);
2542 		if (error)
2543 			return error;
2544 		break;
2545 	default:
2546 		break;
2547 	}
2548 
2549 	return NOTIFY_DONE;
2550 }
2551 
2552 static struct notifier_block sysc_nb = {
2553 	.notifier_call = sysc_notifier_call,
2554 };
2555 
2556 /* Device tree configured quirks */
2557 struct sysc_dts_quirk {
2558 	const char *name;
2559 	u32 mask;
2560 };
2561 
2562 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2563 	{ .name = "ti,no-idle-on-init",
2564 	  .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2565 	{ .name = "ti,no-reset-on-init",
2566 	  .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2567 	{ .name = "ti,no-idle",
2568 	  .mask = SYSC_QUIRK_NO_IDLE, },
2569 };
2570 
2571 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2572 				  bool is_child)
2573 {
2574 	const struct property *prop;
2575 	int i, len;
2576 
2577 	for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2578 		const char *name = sysc_dts_quirks[i].name;
2579 
2580 		prop = of_get_property(np, name, &len);
2581 		if (!prop)
2582 			continue;
2583 
2584 		ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2585 		if (is_child) {
2586 			dev_warn(ddata->dev,
2587 				 "dts flag should be at module level for %s\n",
2588 				 name);
2589 		}
2590 	}
2591 }
2592 
2593 static int sysc_init_dts_quirks(struct sysc *ddata)
2594 {
2595 	struct device_node *np = ddata->dev->of_node;
2596 	int error;
2597 	u32 val;
2598 
2599 	ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2600 
2601 	sysc_parse_dts_quirks(ddata, np, false);
2602 	error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2603 	if (!error) {
2604 		if (val > 255) {
2605 			dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2606 				 val);
2607 		}
2608 
2609 		ddata->cfg.srst_udelay = (u8)val;
2610 	}
2611 
2612 	return 0;
2613 }
2614 
2615 static void sysc_unprepare(struct sysc *ddata)
2616 {
2617 	int i;
2618 
2619 	if (!ddata->clocks)
2620 		return;
2621 
2622 	for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2623 		if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2624 			clk_unprepare(ddata->clocks[i]);
2625 	}
2626 }
2627 
2628 /*
2629  * Common sysc register bits found on omap2, also known as type1
2630  */
2631 static const struct sysc_regbits sysc_regbits_omap2 = {
2632 	.dmadisable_shift = -ENODEV,
2633 	.midle_shift = 12,
2634 	.sidle_shift = 3,
2635 	.clkact_shift = 8,
2636 	.emufree_shift = 5,
2637 	.enwkup_shift = 2,
2638 	.srst_shift = 1,
2639 	.autoidle_shift = 0,
2640 };
2641 
2642 static const struct sysc_capabilities sysc_omap2 = {
2643 	.type = TI_SYSC_OMAP2,
2644 	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2645 		     SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2646 		     SYSC_OMAP2_AUTOIDLE,
2647 	.regbits = &sysc_regbits_omap2,
2648 };
2649 
2650 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2651 static const struct sysc_capabilities sysc_omap2_timer = {
2652 	.type = TI_SYSC_OMAP2_TIMER,
2653 	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2654 		     SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2655 		     SYSC_OMAP2_AUTOIDLE,
2656 	.regbits = &sysc_regbits_omap2,
2657 	.mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2658 };
2659 
2660 /*
2661  * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2662  * with different sidle position
2663  */
2664 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2665 	.dmadisable_shift = -ENODEV,
2666 	.midle_shift = -ENODEV,
2667 	.sidle_shift = 4,
2668 	.clkact_shift = -ENODEV,
2669 	.enwkup_shift = -ENODEV,
2670 	.srst_shift = 1,
2671 	.autoidle_shift = 0,
2672 	.emufree_shift = -ENODEV,
2673 };
2674 
2675 static const struct sysc_capabilities sysc_omap3_sham = {
2676 	.type = TI_SYSC_OMAP3_SHAM,
2677 	.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2678 	.regbits = &sysc_regbits_omap3_sham,
2679 };
2680 
2681 /*
2682  * AES register bits found on omap3 and later, a variant of
2683  * sysc_regbits_omap2 with different sidle position
2684  */
2685 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2686 	.dmadisable_shift = -ENODEV,
2687 	.midle_shift = -ENODEV,
2688 	.sidle_shift = 6,
2689 	.clkact_shift = -ENODEV,
2690 	.enwkup_shift = -ENODEV,
2691 	.srst_shift = 1,
2692 	.autoidle_shift = 0,
2693 	.emufree_shift = -ENODEV,
2694 };
2695 
2696 static const struct sysc_capabilities sysc_omap3_aes = {
2697 	.type = TI_SYSC_OMAP3_AES,
2698 	.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2699 	.regbits = &sysc_regbits_omap3_aes,
2700 };
2701 
2702 /*
2703  * Common sysc register bits found on omap4, also known as type2
2704  */
2705 static const struct sysc_regbits sysc_regbits_omap4 = {
2706 	.dmadisable_shift = 16,
2707 	.midle_shift = 4,
2708 	.sidle_shift = 2,
2709 	.clkact_shift = -ENODEV,
2710 	.enwkup_shift = -ENODEV,
2711 	.emufree_shift = 1,
2712 	.srst_shift = 0,
2713 	.autoidle_shift = -ENODEV,
2714 };
2715 
2716 static const struct sysc_capabilities sysc_omap4 = {
2717 	.type = TI_SYSC_OMAP4,
2718 	.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2719 		     SYSC_OMAP4_SOFTRESET,
2720 	.regbits = &sysc_regbits_omap4,
2721 };
2722 
2723 static const struct sysc_capabilities sysc_omap4_timer = {
2724 	.type = TI_SYSC_OMAP4_TIMER,
2725 	.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2726 		     SYSC_OMAP4_SOFTRESET,
2727 	.regbits = &sysc_regbits_omap4,
2728 };
2729 
2730 /*
2731  * Common sysc register bits found on omap4, also known as type3
2732  */
2733 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2734 	.dmadisable_shift = -ENODEV,
2735 	.midle_shift = 2,
2736 	.sidle_shift = 0,
2737 	.clkact_shift = -ENODEV,
2738 	.enwkup_shift = -ENODEV,
2739 	.srst_shift = -ENODEV,
2740 	.emufree_shift = -ENODEV,
2741 	.autoidle_shift = -ENODEV,
2742 };
2743 
2744 static const struct sysc_capabilities sysc_omap4_simple = {
2745 	.type = TI_SYSC_OMAP4_SIMPLE,
2746 	.regbits = &sysc_regbits_omap4_simple,
2747 };
2748 
2749 /*
2750  * SmartReflex sysc found on omap34xx
2751  */
2752 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2753 	.dmadisable_shift = -ENODEV,
2754 	.midle_shift = -ENODEV,
2755 	.sidle_shift = -ENODEV,
2756 	.clkact_shift = 20,
2757 	.enwkup_shift = -ENODEV,
2758 	.srst_shift = -ENODEV,
2759 	.emufree_shift = -ENODEV,
2760 	.autoidle_shift = -ENODEV,
2761 };
2762 
2763 static const struct sysc_capabilities sysc_34xx_sr = {
2764 	.type = TI_SYSC_OMAP34XX_SR,
2765 	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2766 	.regbits = &sysc_regbits_omap34xx_sr,
2767 	.mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED,
2768 };
2769 
2770 /*
2771  * SmartReflex sysc found on omap36xx and later
2772  */
2773 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2774 	.dmadisable_shift = -ENODEV,
2775 	.midle_shift = -ENODEV,
2776 	.sidle_shift = 24,
2777 	.clkact_shift = -ENODEV,
2778 	.enwkup_shift = 26,
2779 	.srst_shift = -ENODEV,
2780 	.emufree_shift = -ENODEV,
2781 	.autoidle_shift = -ENODEV,
2782 };
2783 
2784 static const struct sysc_capabilities sysc_36xx_sr = {
2785 	.type = TI_SYSC_OMAP36XX_SR,
2786 	.sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2787 	.regbits = &sysc_regbits_omap36xx_sr,
2788 	.mod_quirks = SYSC_QUIRK_UNCACHED,
2789 };
2790 
2791 static const struct sysc_capabilities sysc_omap4_sr = {
2792 	.type = TI_SYSC_OMAP4_SR,
2793 	.regbits = &sysc_regbits_omap36xx_sr,
2794 };
2795 
2796 /*
2797  * McASP register bits found on omap4 and later
2798  */
2799 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2800 	.dmadisable_shift = -ENODEV,
2801 	.midle_shift = -ENODEV,
2802 	.sidle_shift = 0,
2803 	.clkact_shift = -ENODEV,
2804 	.enwkup_shift = -ENODEV,
2805 	.srst_shift = -ENODEV,
2806 	.emufree_shift = -ENODEV,
2807 	.autoidle_shift = -ENODEV,
2808 };
2809 
2810 static const struct sysc_capabilities sysc_omap4_mcasp = {
2811 	.type = TI_SYSC_OMAP4_MCASP,
2812 	.regbits = &sysc_regbits_omap4_mcasp,
2813 	.mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2814 };
2815 
2816 /*
2817  * McASP found on dra7 and later
2818  */
2819 static const struct sysc_capabilities sysc_dra7_mcasp = {
2820 	.type = TI_SYSC_OMAP4_SIMPLE,
2821 	.regbits = &sysc_regbits_omap4_simple,
2822 	.mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2823 };
2824 
2825 /*
2826  * FS USB host found on omap4 and later
2827  */
2828 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2829 	.dmadisable_shift = -ENODEV,
2830 	.midle_shift = -ENODEV,
2831 	.sidle_shift = 24,
2832 	.clkact_shift = -ENODEV,
2833 	.enwkup_shift = 26,
2834 	.srst_shift = -ENODEV,
2835 	.emufree_shift = -ENODEV,
2836 	.autoidle_shift = -ENODEV,
2837 };
2838 
2839 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2840 	.type = TI_SYSC_OMAP4_USB_HOST_FS,
2841 	.sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2842 	.regbits = &sysc_regbits_omap4_usb_host_fs,
2843 };
2844 
2845 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2846 	.dmadisable_shift = -ENODEV,
2847 	.midle_shift = -ENODEV,
2848 	.sidle_shift = -ENODEV,
2849 	.clkact_shift = -ENODEV,
2850 	.enwkup_shift = 4,
2851 	.srst_shift = 0,
2852 	.emufree_shift = -ENODEV,
2853 	.autoidle_shift = -ENODEV,
2854 };
2855 
2856 static const struct sysc_capabilities sysc_dra7_mcan = {
2857 	.type = TI_SYSC_DRA7_MCAN,
2858 	.sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2859 	.regbits = &sysc_regbits_dra7_mcan,
2860 	.mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2861 };
2862 
2863 /*
2864  * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
2865  */
2866 static const struct sysc_capabilities sysc_pruss = {
2867 	.type = TI_SYSC_PRUSS,
2868 	.sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT,
2869 	.regbits = &sysc_regbits_omap4_simple,
2870 	.mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
2871 };
2872 
2873 static int sysc_init_pdata(struct sysc *ddata)
2874 {
2875 	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2876 	struct ti_sysc_module_data *mdata;
2877 
2878 	if (!pdata)
2879 		return 0;
2880 
2881 	mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2882 	if (!mdata)
2883 		return -ENOMEM;
2884 
2885 	if (ddata->legacy_mode) {
2886 		mdata->name = ddata->legacy_mode;
2887 		mdata->module_pa = ddata->module_pa;
2888 		mdata->module_size = ddata->module_size;
2889 		mdata->offsets = ddata->offsets;
2890 		mdata->nr_offsets = SYSC_MAX_REGS;
2891 		mdata->cap = ddata->cap;
2892 		mdata->cfg = &ddata->cfg;
2893 	}
2894 
2895 	ddata->mdata = mdata;
2896 
2897 	return 0;
2898 }
2899 
2900 static int sysc_init_match(struct sysc *ddata)
2901 {
2902 	const struct sysc_capabilities *cap;
2903 
2904 	cap = of_device_get_match_data(ddata->dev);
2905 	if (!cap)
2906 		return -EINVAL;
2907 
2908 	ddata->cap = cap;
2909 	if (ddata->cap)
2910 		ddata->cfg.quirks |= ddata->cap->mod_quirks;
2911 
2912 	return 0;
2913 }
2914 
2915 static void ti_sysc_idle(struct work_struct *work)
2916 {
2917 	struct sysc *ddata;
2918 
2919 	ddata = container_of(work, struct sysc, idle_work.work);
2920 
2921 	/*
2922 	 * One time decrement of clock usage counts if left on from init.
2923 	 * Note that we disable opt clocks unconditionally in this case
2924 	 * as they are enabled unconditionally during init without
2925 	 * considering sysc_opt_clks_needed() at that point.
2926 	 */
2927 	if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2928 				 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2929 		sysc_disable_main_clocks(ddata);
2930 		sysc_disable_opt_clocks(ddata);
2931 		sysc_clkdm_allow_idle(ddata);
2932 	}
2933 
2934 	/* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2935 	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2936 		return;
2937 
2938 	/*
2939 	 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2940 	 * and SYSC_QUIRK_NO_RESET_ON_INIT
2941 	 */
2942 	if (pm_runtime_active(ddata->dev))
2943 		pm_runtime_put_sync(ddata->dev);
2944 }
2945 
2946 /*
2947  * SoC model and features detection. Only needed for SoCs that need
2948  * special handling for quirks, no need to list others.
2949  */
2950 static const struct soc_device_attribute sysc_soc_match[] = {
2951 	SOC_FLAG("OMAP242*", SOC_2420),
2952 	SOC_FLAG("OMAP243*", SOC_2430),
2953 	SOC_FLAG("AM35*", SOC_AM35),
2954 	SOC_FLAG("OMAP3[45]*", SOC_3430),
2955 	SOC_FLAG("OMAP3[67]*", SOC_3630),
2956 	SOC_FLAG("OMAP443*", SOC_4430),
2957 	SOC_FLAG("OMAP446*", SOC_4460),
2958 	SOC_FLAG("OMAP447*", SOC_4470),
2959 	SOC_FLAG("OMAP54*", SOC_5430),
2960 	SOC_FLAG("AM433", SOC_AM3),
2961 	SOC_FLAG("AM43*", SOC_AM4),
2962 	SOC_FLAG("DRA7*", SOC_DRA7),
2963 
2964 	{ /* sentinel */ }
2965 };
2966 
2967 /*
2968  * List of SoCs variants with disabled features. By default we assume all
2969  * devices in the device tree are available so no need to list those SoCs.
2970  */
2971 static const struct soc_device_attribute sysc_soc_feat_match[] = {
2972 	/* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
2973 	SOC_FLAG("AM3505", DIS_SGX),
2974 	SOC_FLAG("OMAP3525", DIS_SGX),
2975 	SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX),
2976 	SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX),
2977 
2978 	/* OMAP3630/DM3730 variants with some accelerators disabled */
2979 	SOC_FLAG("AM3703", DIS_IVA | DIS_SGX),
2980 	SOC_FLAG("DM3725", DIS_SGX),
2981 	SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX),
2982 	SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
2983 	SOC_FLAG("OMAP3621", DIS_ISP),
2984 
2985 	{ /* sentinel */ }
2986 };
2987 
2988 static int sysc_add_disabled(unsigned long base)
2989 {
2990 	struct sysc_address *disabled_module;
2991 
2992 	disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
2993 	if (!disabled_module)
2994 		return -ENOMEM;
2995 
2996 	disabled_module->base = base;
2997 
2998 	mutex_lock(&sysc_soc->list_lock);
2999 	list_add(&disabled_module->node, &sysc_soc->disabled_modules);
3000 	mutex_unlock(&sysc_soc->list_lock);
3001 
3002 	return 0;
3003 }
3004 
3005 /*
3006  * One time init to detect the booted SoC, disable unavailable features
3007  * and initialize list for optional cpu_pm notifier.
3008  *
3009  * Note that we initialize static data shared across all ti-sysc instances
3010  * so ddata is only used for SoC type. This can be called from module_init
3011  * once we no longer need to rely on platform data.
3012  */
3013 static int sysc_init_static_data(struct sysc *ddata)
3014 {
3015 	const struct soc_device_attribute *match;
3016 	struct ti_sysc_platform_data *pdata;
3017 	unsigned long features = 0;
3018 	struct device_node *np;
3019 
3020 	if (sysc_soc)
3021 		return 0;
3022 
3023 	sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
3024 	if (!sysc_soc)
3025 		return -ENOMEM;
3026 
3027 	mutex_init(&sysc_soc->list_lock);
3028 	INIT_LIST_HEAD(&sysc_soc->disabled_modules);
3029 	INIT_LIST_HEAD(&sysc_soc->restored_modules);
3030 	sysc_soc->general_purpose = true;
3031 
3032 	pdata = dev_get_platdata(ddata->dev);
3033 	if (pdata && pdata->soc_type_gp)
3034 		sysc_soc->general_purpose = pdata->soc_type_gp();
3035 
3036 	match = soc_device_match(sysc_soc_match);
3037 	if (match && match->data)
3038 		sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
3039 
3040 	/*
3041 	 * Check and warn about possible old incomplete dtb. We now want to see
3042 	 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs.
3043 	 */
3044 	switch (sysc_soc->soc) {
3045 	case SOC_AM3:
3046 	case SOC_AM4:
3047 	case SOC_4430 ... SOC_4470:
3048 	case SOC_5430:
3049 	case SOC_DRA7:
3050 		np = of_find_node_by_path("/ocp");
3051 		WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"),
3052 			  "ti-sysc: Incomplete old dtb, please update\n");
3053 		break;
3054 	default:
3055 		break;
3056 	}
3057 
3058 	/* Ignore devices that are not available on HS and EMU SoCs */
3059 	if (!sysc_soc->general_purpose) {
3060 		switch (sysc_soc->soc) {
3061 		case SOC_3430 ... SOC_3630:
3062 			sysc_add_disabled(0x48304000);	/* timer12 */
3063 			break;
3064 		case SOC_AM3:
3065 			sysc_add_disabled(0x48310000);  /* rng */
3066 			break;
3067 		default:
3068 			break;
3069 		}
3070 	}
3071 
3072 	match = soc_device_match(sysc_soc_feat_match);
3073 	if (!match)
3074 		return 0;
3075 
3076 	if (match->data)
3077 		features = (unsigned long)match->data;
3078 
3079 	/*
3080 	 * Add disabled devices to the list based on the module base.
3081 	 * Note that this must be done before we attempt to access the
3082 	 * device and have module revision checks working.
3083 	 */
3084 	if (features & DIS_ISP)
3085 		sysc_add_disabled(0x480bd400);
3086 	if (features & DIS_IVA)
3087 		sysc_add_disabled(0x5d000000);
3088 	if (features & DIS_SGX)
3089 		sysc_add_disabled(0x50000000);
3090 
3091 	return 0;
3092 }
3093 
3094 static void sysc_cleanup_static_data(void)
3095 {
3096 	struct sysc_module *restored_module;
3097 	struct sysc_address *disabled_module;
3098 	struct list_head *pos, *tmp;
3099 
3100 	if (!sysc_soc)
3101 		return;
3102 
3103 	if (sysc_soc->nb.notifier_call)
3104 		cpu_pm_unregister_notifier(&sysc_soc->nb);
3105 
3106 	mutex_lock(&sysc_soc->list_lock);
3107 	list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
3108 		restored_module = list_entry(pos, struct sysc_module, node);
3109 		list_del(pos);
3110 		kfree(restored_module);
3111 	}
3112 	list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
3113 		disabled_module = list_entry(pos, struct sysc_address, node);
3114 		list_del(pos);
3115 		kfree(disabled_module);
3116 	}
3117 	mutex_unlock(&sysc_soc->list_lock);
3118 }
3119 
3120 static int sysc_check_disabled_devices(struct sysc *ddata)
3121 {
3122 	struct sysc_address *disabled_module;
3123 	int error = 0;
3124 
3125 	mutex_lock(&sysc_soc->list_lock);
3126 	list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) {
3127 		if (ddata->module_pa == disabled_module->base) {
3128 			dev_dbg(ddata->dev, "module disabled for this SoC\n");
3129 			error = -ENODEV;
3130 			break;
3131 		}
3132 	}
3133 	mutex_unlock(&sysc_soc->list_lock);
3134 
3135 	return error;
3136 }
3137 
3138 /*
3139  * Ignore timers tagged with no-reset and no-idle. These are likely in use,
3140  * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
3141  * are needed, we could also look at the timer register configuration.
3142  */
3143 static int sysc_check_active_timer(struct sysc *ddata)
3144 {
3145 	int error;
3146 
3147 	if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
3148 	    ddata->cap->type != TI_SYSC_OMAP4_TIMER)
3149 		return 0;
3150 
3151 	/*
3152 	 * Quirk for omap3 beagleboard revision A to B4 to use gpt12.
3153 	 * Revision C and later are fixed with commit 23885389dbbb ("ARM:
3154 	 * dts: Fix timer regression for beagleboard revision c"). This all
3155 	 * can be dropped if we stop supporting old beagleboard revisions
3156 	 * A to B4 at some point.
3157 	 */
3158 	if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35)
3159 		error = -ENXIO;
3160 	else
3161 		error = -EBUSY;
3162 
3163 	if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
3164 	    (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
3165 		return error;
3166 
3167 	return 0;
3168 }
3169 
3170 static const struct of_device_id sysc_match_table[] = {
3171 	{ .compatible = "simple-bus", },
3172 	{ /* sentinel */ },
3173 };
3174 
3175 static int sysc_probe(struct platform_device *pdev)
3176 {
3177 	struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
3178 	struct sysc *ddata;
3179 	int error;
3180 
3181 	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
3182 	if (!ddata)
3183 		return -ENOMEM;
3184 
3185 	ddata->offsets[SYSC_REVISION] = -ENODEV;
3186 	ddata->offsets[SYSC_SYSCONFIG] = -ENODEV;
3187 	ddata->offsets[SYSC_SYSSTATUS] = -ENODEV;
3188 	ddata->dev = &pdev->dev;
3189 	platform_set_drvdata(pdev, ddata);
3190 
3191 	error = sysc_init_static_data(ddata);
3192 	if (error)
3193 		return error;
3194 
3195 	error = sysc_init_match(ddata);
3196 	if (error)
3197 		return error;
3198 
3199 	error = sysc_init_dts_quirks(ddata);
3200 	if (error)
3201 		return error;
3202 
3203 	error = sysc_map_and_check_registers(ddata);
3204 	if (error)
3205 		return error;
3206 
3207 	error = sysc_init_sysc_mask(ddata);
3208 	if (error)
3209 		return error;
3210 
3211 	error = sysc_init_idlemodes(ddata);
3212 	if (error)
3213 		return error;
3214 
3215 	error = sysc_init_syss_mask(ddata);
3216 	if (error)
3217 		return error;
3218 
3219 	error = sysc_init_pdata(ddata);
3220 	if (error)
3221 		return error;
3222 
3223 	sysc_init_early_quirks(ddata);
3224 
3225 	error = sysc_check_disabled_devices(ddata);
3226 	if (error)
3227 		return error;
3228 
3229 	error = sysc_check_active_timer(ddata);
3230 	if (error == -ENXIO)
3231 		ddata->reserved = true;
3232 	else if (error)
3233 		return error;
3234 
3235 	error = sysc_get_clocks(ddata);
3236 	if (error)
3237 		return error;
3238 
3239 	error = sysc_init_resets(ddata);
3240 	if (error)
3241 		goto unprepare;
3242 
3243 	error = sysc_init_module(ddata);
3244 	if (error)
3245 		goto unprepare;
3246 
3247 	pm_runtime_enable(ddata->dev);
3248 	error = pm_runtime_resume_and_get(ddata->dev);
3249 	if (error < 0) {
3250 		pm_runtime_disable(ddata->dev);
3251 		goto unprepare;
3252 	}
3253 
3254 	/* Balance use counts as PM runtime should have enabled these all */
3255 	if (!(ddata->cfg.quirks &
3256 	      (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) {
3257 		sysc_disable_main_clocks(ddata);
3258 		sysc_disable_opt_clocks(ddata);
3259 		sysc_clkdm_allow_idle(ddata);
3260 	}
3261 
3262 	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
3263 		reset_control_assert(ddata->rsts);
3264 
3265 	sysc_show_registers(ddata);
3266 
3267 	ddata->dev->type = &sysc_device_type;
3268 
3269 	if (!ddata->reserved) {
3270 		error = of_platform_populate(ddata->dev->of_node,
3271 					     sysc_match_table,
3272 					     pdata ? pdata->auxdata : NULL,
3273 					     ddata->dev);
3274 		if (error)
3275 			goto err;
3276 	}
3277 
3278 	INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
3279 
3280 	/* At least earlycon won't survive without deferred idle */
3281 	if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
3282 				 SYSC_QUIRK_NO_IDLE_ON_INIT |
3283 				 SYSC_QUIRK_NO_RESET_ON_INIT)) {
3284 		schedule_delayed_work(&ddata->idle_work, 3000);
3285 	} else {
3286 		pm_runtime_put(&pdev->dev);
3287 	}
3288 
3289 	if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
3290 		sysc_add_restored(ddata);
3291 
3292 	return 0;
3293 
3294 err:
3295 	pm_runtime_put_sync(&pdev->dev);
3296 	pm_runtime_disable(&pdev->dev);
3297 unprepare:
3298 	sysc_unprepare(ddata);
3299 
3300 	return error;
3301 }
3302 
3303 static void sysc_remove(struct platform_device *pdev)
3304 {
3305 	struct sysc *ddata = platform_get_drvdata(pdev);
3306 	int error;
3307 
3308 	/* Device can still be enabled, see deferred idle quirk in probe */
3309 	if (cancel_delayed_work_sync(&ddata->idle_work))
3310 		ti_sysc_idle(&ddata->idle_work.work);
3311 
3312 	error = pm_runtime_resume_and_get(ddata->dev);
3313 	if (error < 0) {
3314 		pm_runtime_disable(ddata->dev);
3315 		goto unprepare;
3316 	}
3317 
3318 	of_platform_depopulate(&pdev->dev);
3319 
3320 	pm_runtime_put_sync(&pdev->dev);
3321 	pm_runtime_disable(&pdev->dev);
3322 
3323 	if (!reset_control_status(ddata->rsts))
3324 		reset_control_assert(ddata->rsts);
3325 
3326 unprepare:
3327 	sysc_unprepare(ddata);
3328 }
3329 
3330 static const struct of_device_id sysc_match[] = {
3331 	{ .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
3332 	{ .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
3333 	{ .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
3334 	{ .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
3335 	{ .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
3336 	{ .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
3337 	{ .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
3338 	{ .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
3339 	{ .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
3340 	{ .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
3341 	{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
3342 	{ .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
3343 	{ .compatible = "ti,sysc-usb-host-fs",
3344 	  .data = &sysc_omap4_usb_host_fs, },
3345 	{ .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
3346 	{ .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
3347 	{  },
3348 };
3349 MODULE_DEVICE_TABLE(of, sysc_match);
3350 
3351 static struct platform_driver sysc_driver = {
3352 	.probe		= sysc_probe,
3353 	.remove_new	= sysc_remove,
3354 	.driver         = {
3355 		.name   = "ti-sysc",
3356 		.of_match_table	= sysc_match,
3357 		.pm = &sysc_pm_ops,
3358 	},
3359 };
3360 
3361 static int __init sysc_init(void)
3362 {
3363 	bus_register_notifier(&platform_bus_type, &sysc_nb);
3364 
3365 	return platform_driver_register(&sysc_driver);
3366 }
3367 module_init(sysc_init);
3368 
3369 static void __exit sysc_exit(void)
3370 {
3371 	bus_unregister_notifier(&platform_bus_type, &sysc_nb);
3372 	platform_driver_unregister(&sysc_driver);
3373 	sysc_cleanup_static_data();
3374 }
3375 module_exit(sysc_exit);
3376 
3377 MODULE_DESCRIPTION("TI sysc interconnect target driver");
3378 MODULE_LICENSE("GPL v2");
3379