1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 * 5 * TI SoCs have an interconnect target wrapper IP for many devices. The wrapper 6 * IP manages clock gating, resets, and PM capabilities for the connected devices. 7 * 8 * Copyright (C) 2017-2024 Texas Instruments Incorporated - https://www.ti.com/ 9 * 10 * Many features are based on the earlier omap_hwmod arch code with thanks to all 11 * the people who developed and debugged the code over the years: 12 * 13 * Copyright (C) 2009-2011 Nokia Corporation 14 * Copyright (C) 2011-2021 Texas Instruments Incorporated - https://www.ti.com/ 15 */ 16 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/clkdev.h> 20 #include <linux/cpu_pm.h> 21 #include <linux/delay.h> 22 #include <linux/list.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_domain.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/slab.h> 31 #include <linux/sys_soc.h> 32 #include <linux/timekeeping.h> 33 #include <linux/iopoll.h> 34 35 #include <linux/platform_data/ti-sysc.h> 36 37 #include <dt-bindings/bus/ti-sysc.h> 38 39 #define DIS_ISP BIT(2) 40 #define DIS_IVA BIT(1) 41 #define DIS_SGX BIT(0) 42 43 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 44 45 #define MAX_MODULE_SOFTRESET_WAIT 10000 46 47 enum sysc_soc { 48 SOC_UNKNOWN, 49 SOC_2420, 50 SOC_2430, 51 SOC_AM33, 52 SOC_3430, 53 SOC_AM35, 54 SOC_3630, 55 SOC_4430, 56 SOC_4460, 57 SOC_4470, 58 SOC_5430, 59 SOC_AM3, 60 SOC_AM4, 61 SOC_DRA7, 62 }; 63 64 struct sysc_address { 65 unsigned long base; 66 struct list_head node; 67 }; 68 69 struct sysc_module { 70 struct sysc *ddata; 71 struct list_head node; 72 }; 73 74 struct sysc_soc_info { 75 unsigned long general_purpose:1; 76 enum sysc_soc soc; 77 struct mutex list_lock; /* disabled and restored modules list lock */ 78 struct list_head disabled_modules; 79 struct list_head restored_modules; 80 struct notifier_block nb; 81 }; 82 83 enum sysc_clocks { 84 SYSC_FCK, 85 SYSC_ICK, 86 SYSC_OPTFCK0, 87 SYSC_OPTFCK1, 88 SYSC_OPTFCK2, 89 SYSC_OPTFCK3, 90 SYSC_OPTFCK4, 91 SYSC_OPTFCK5, 92 SYSC_OPTFCK6, 93 SYSC_OPTFCK7, 94 SYSC_MAX_CLOCKS, 95 }; 96 97 static struct sysc_soc_info *sysc_soc; 98 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 99 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 100 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 101 "opt5", "opt6", "opt7", 102 }; 103 104 #define SYSC_IDLEMODE_MASK 3 105 #define SYSC_CLOCKACTIVITY_MASK 3 106 107 /** 108 * struct sysc - TI sysc interconnect target module registers and capabilities 109 * @dev: struct device pointer 110 * @module_pa: physical address of the interconnect target module 111 * @module_size: size of the interconnect target module 112 * @module_va: virtual address of the interconnect target module 113 * @offsets: register offsets from module base 114 * @mdata: ti-sysc to hwmod translation data for a module 115 * @clocks: clocks used by the interconnect target module 116 * @clock_roles: clock role names for the found clocks 117 * @nr_clocks: number of clocks used by the interconnect target module 118 * @rsts: resets used by the interconnect target module 119 * @legacy_mode: configured for legacy mode if set 120 * @cap: interconnect target module capabilities 121 * @cfg: interconnect target module configuration 122 * @cookie: data used by legacy platform callbacks 123 * @name: name if available 124 * @revision: interconnect target module revision 125 * @sysconfig: saved sysconfig register value 126 * @reserved: target module is reserved and already in use 127 * @enabled: sysc runtime enabled status 128 * @needs_resume: runtime resume needed on resume from suspend 129 * @child_needs_resume: runtime resume needed for child on resume from suspend 130 * @idle_work: work structure used to perform delayed idle on a module 131 * @pre_reset_quirk: module specific pre-reset quirk 132 * @post_reset_quirk: module specific post-reset quirk 133 * @reset_done_quirk: module specific reset done quirk 134 * @module_enable_quirk: module specific enable quirk 135 * @module_disable_quirk: module specific disable quirk 136 * @module_unlock_quirk: module specific sysconfig unlock quirk 137 * @module_lock_quirk: module specific sysconfig lock quirk 138 */ 139 struct sysc { 140 struct device *dev; 141 u64 module_pa; 142 u32 module_size; 143 void __iomem *module_va; 144 int offsets[SYSC_MAX_REGS]; 145 struct ti_sysc_module_data *mdata; 146 struct clk **clocks; 147 const char **clock_roles; 148 int nr_clocks; 149 struct reset_control *rsts; 150 const char *legacy_mode; 151 const struct sysc_capabilities *cap; 152 struct sysc_config cfg; 153 struct ti_sysc_cookie cookie; 154 const char *name; 155 u32 revision; 156 u32 sysconfig; 157 unsigned int reserved:1; 158 unsigned int enabled:1; 159 unsigned int needs_resume:1; 160 unsigned int child_needs_resume:1; 161 struct delayed_work idle_work; 162 void (*pre_reset_quirk)(struct sysc *sysc); 163 void (*post_reset_quirk)(struct sysc *sysc); 164 void (*reset_done_quirk)(struct sysc *sysc); 165 void (*module_enable_quirk)(struct sysc *sysc); 166 void (*module_disable_quirk)(struct sysc *sysc); 167 void (*module_unlock_quirk)(struct sysc *sysc); 168 void (*module_lock_quirk)(struct sysc *sysc); 169 }; 170 171 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 172 bool is_child); 173 static int sysc_reset(struct sysc *ddata); 174 175 static void sysc_write(struct sysc *ddata, int offset, u32 value) 176 { 177 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 178 writew_relaxed(value & 0xffff, ddata->module_va + offset); 179 180 /* Only i2c revision has LO and HI register with stride of 4 */ 181 if (ddata->offsets[SYSC_REVISION] >= 0 && 182 offset == ddata->offsets[SYSC_REVISION]) { 183 u16 hi = value >> 16; 184 185 writew_relaxed(hi, ddata->module_va + offset + 4); 186 } 187 188 return; 189 } 190 191 writel_relaxed(value, ddata->module_va + offset); 192 } 193 194 static u32 sysc_read(struct sysc *ddata, int offset) 195 { 196 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 197 u32 val; 198 199 val = readw_relaxed(ddata->module_va + offset); 200 201 /* Only i2c revision has LO and HI register with stride of 4 */ 202 if (ddata->offsets[SYSC_REVISION] >= 0 && 203 offset == ddata->offsets[SYSC_REVISION]) { 204 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 205 206 val |= tmp << 16; 207 } 208 209 return val; 210 } 211 212 return readl_relaxed(ddata->module_va + offset); 213 } 214 215 static bool sysc_opt_clks_needed(struct sysc *ddata) 216 { 217 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 218 } 219 220 static u32 sysc_read_revision(struct sysc *ddata) 221 { 222 int offset = ddata->offsets[SYSC_REVISION]; 223 224 if (offset < 0) 225 return 0; 226 227 return sysc_read(ddata, offset); 228 } 229 230 static u32 sysc_read_sysconfig(struct sysc *ddata) 231 { 232 int offset = ddata->offsets[SYSC_SYSCONFIG]; 233 234 if (offset < 0) 235 return 0; 236 237 return sysc_read(ddata, offset); 238 } 239 240 static u32 sysc_read_sysstatus(struct sysc *ddata) 241 { 242 int offset = ddata->offsets[SYSC_SYSSTATUS]; 243 244 if (offset < 0) 245 return 0; 246 247 return sysc_read(ddata, offset); 248 } 249 250 static int sysc_poll_reset_sysstatus(struct sysc *ddata) 251 { 252 int error, retries; 253 u32 syss_done, rstval; 254 255 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 256 syss_done = 0; 257 else 258 syss_done = ddata->cfg.syss_mask; 259 260 if (likely(!timekeeping_suspended)) { 261 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 262 rstval, (rstval & ddata->cfg.syss_mask) == 263 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 264 } else { 265 retries = MAX_MODULE_SOFTRESET_WAIT; 266 while (retries--) { 267 rstval = sysc_read_sysstatus(ddata); 268 if ((rstval & ddata->cfg.syss_mask) == syss_done) 269 return 0; 270 udelay(2); /* Account for udelay flakeyness */ 271 } 272 error = -ETIMEDOUT; 273 } 274 275 return error; 276 } 277 278 static int sysc_poll_reset_sysconfig(struct sysc *ddata) 279 { 280 int error, retries; 281 u32 sysc_mask, rstval; 282 283 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 284 285 if (likely(!timekeeping_suspended)) { 286 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 287 rstval, !(rstval & sysc_mask), 288 100, MAX_MODULE_SOFTRESET_WAIT); 289 } else { 290 retries = MAX_MODULE_SOFTRESET_WAIT; 291 while (retries--) { 292 rstval = sysc_read_sysconfig(ddata); 293 if (!(rstval & sysc_mask)) 294 return 0; 295 udelay(2); /* Account for udelay flakeyness */ 296 } 297 error = -ETIMEDOUT; 298 } 299 300 return error; 301 } 302 303 /* Poll on reset status */ 304 static int sysc_wait_softreset(struct sysc *ddata) 305 { 306 int syss_offset, error = 0; 307 308 if (ddata->cap->regbits->srst_shift < 0) 309 return 0; 310 311 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 312 313 if (syss_offset >= 0) 314 error = sysc_poll_reset_sysstatus(ddata); 315 else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) 316 error = sysc_poll_reset_sysconfig(ddata); 317 318 return error; 319 } 320 321 static int sysc_add_named_clock_from_child(struct sysc *ddata, 322 const char *name, 323 const char *optfck_name) 324 { 325 struct device_node *np = ddata->dev->of_node; 326 struct device_node *child; 327 struct clk_lookup *cl; 328 struct clk *clock; 329 const char *n; 330 331 if (name) 332 n = name; 333 else 334 n = optfck_name; 335 336 /* Does the clock alias already exist? */ 337 clock = of_clk_get_by_name(np, n); 338 if (!IS_ERR(clock)) { 339 clk_put(clock); 340 341 return 0; 342 } 343 344 child = of_get_next_available_child(np, NULL); 345 if (!child) 346 return -ENODEV; 347 348 clock = devm_get_clk_from_child(ddata->dev, child, name); 349 if (IS_ERR(clock)) 350 return PTR_ERR(clock); 351 352 /* 353 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 354 * limit for clk_get(). If cl ever needs to be freed, it should be done 355 * with clkdev_drop(). 356 */ 357 cl = kzalloc(sizeof(*cl), GFP_KERNEL); 358 if (!cl) 359 return -ENOMEM; 360 361 cl->con_id = n; 362 cl->dev_id = dev_name(ddata->dev); 363 cl->clk = clock; 364 clkdev_add(cl); 365 366 clk_put(clock); 367 368 return 0; 369 } 370 371 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 372 { 373 const char *optfck_name; 374 int error, index; 375 376 if (ddata->nr_clocks < SYSC_OPTFCK0) 377 index = SYSC_OPTFCK0; 378 else 379 index = ddata->nr_clocks; 380 381 if (name) 382 optfck_name = name; 383 else 384 optfck_name = clock_names[index]; 385 386 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 387 if (error) 388 return error; 389 390 ddata->clock_roles[index] = optfck_name; 391 ddata->nr_clocks++; 392 393 return 0; 394 } 395 396 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 397 { 398 int error, i, index = -ENODEV; 399 400 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 401 index = SYSC_FCK; 402 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 403 index = SYSC_ICK; 404 405 if (index < 0) { 406 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 407 if (!ddata->clocks[i]) { 408 index = i; 409 break; 410 } 411 } 412 } 413 414 if (index < 0) { 415 dev_err(ddata->dev, "clock %s not added\n", name); 416 return index; 417 } 418 419 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 420 if (IS_ERR(ddata->clocks[index])) { 421 dev_err(ddata->dev, "clock get error for %s: %li\n", 422 name, PTR_ERR(ddata->clocks[index])); 423 424 return PTR_ERR(ddata->clocks[index]); 425 } 426 427 error = clk_prepare(ddata->clocks[index]); 428 if (error) { 429 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 430 name, error); 431 432 return error; 433 } 434 435 return 0; 436 } 437 438 static int sysc_get_clocks(struct sysc *ddata) 439 { 440 struct device_node *np = ddata->dev->of_node; 441 struct property *prop; 442 const char *name; 443 int nr_fck = 0, nr_ick = 0, i, error = 0; 444 445 ddata->clock_roles = devm_kcalloc(ddata->dev, 446 SYSC_MAX_CLOCKS, 447 sizeof(*ddata->clock_roles), 448 GFP_KERNEL); 449 if (!ddata->clock_roles) 450 return -ENOMEM; 451 452 of_property_for_each_string(np, "clock-names", prop, name) { 453 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 454 nr_fck++; 455 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 456 nr_ick++; 457 ddata->clock_roles[ddata->nr_clocks] = name; 458 ddata->nr_clocks++; 459 } 460 461 if (ddata->nr_clocks < 1) 462 return 0; 463 464 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 465 error = sysc_init_ext_opt_clock(ddata, NULL); 466 if (error) 467 return error; 468 } 469 470 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 471 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 472 473 return -EINVAL; 474 } 475 476 if (nr_fck > 1 || nr_ick > 1) { 477 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 478 479 return -EINVAL; 480 } 481 482 /* Always add a slot for main clocks fck and ick even if unused */ 483 if (!nr_fck) 484 ddata->nr_clocks++; 485 if (!nr_ick) 486 ddata->nr_clocks++; 487 488 ddata->clocks = devm_kcalloc(ddata->dev, 489 ddata->nr_clocks, sizeof(*ddata->clocks), 490 GFP_KERNEL); 491 if (!ddata->clocks) 492 return -ENOMEM; 493 494 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 495 const char *name = ddata->clock_roles[i]; 496 497 if (!name) 498 continue; 499 500 error = sysc_get_one_clock(ddata, name); 501 if (error) 502 return error; 503 } 504 505 return 0; 506 } 507 508 static int sysc_enable_main_clocks(struct sysc *ddata) 509 { 510 struct clk *clock; 511 int i, error; 512 513 if (!ddata->clocks) 514 return 0; 515 516 for (i = 0; i < SYSC_OPTFCK0; i++) { 517 clock = ddata->clocks[i]; 518 519 /* Main clocks may not have ick */ 520 if (IS_ERR_OR_NULL(clock)) 521 continue; 522 523 error = clk_enable(clock); 524 if (error) 525 goto err_disable; 526 } 527 528 return 0; 529 530 err_disable: 531 for (i--; i >= 0; i--) { 532 clock = ddata->clocks[i]; 533 534 /* Main clocks may not have ick */ 535 if (IS_ERR_OR_NULL(clock)) 536 continue; 537 538 clk_disable(clock); 539 } 540 541 return error; 542 } 543 544 static void sysc_disable_main_clocks(struct sysc *ddata) 545 { 546 struct clk *clock; 547 int i; 548 549 if (!ddata->clocks) 550 return; 551 552 for (i = 0; i < SYSC_OPTFCK0; i++) { 553 clock = ddata->clocks[i]; 554 if (IS_ERR_OR_NULL(clock)) 555 continue; 556 557 clk_disable(clock); 558 } 559 } 560 561 static int sysc_enable_opt_clocks(struct sysc *ddata) 562 { 563 struct clk *clock; 564 int i, error; 565 566 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 567 return 0; 568 569 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 570 clock = ddata->clocks[i]; 571 572 /* Assume no holes for opt clocks */ 573 if (IS_ERR_OR_NULL(clock)) 574 return 0; 575 576 error = clk_enable(clock); 577 if (error) 578 goto err_disable; 579 } 580 581 return 0; 582 583 err_disable: 584 for (i--; i >= 0; i--) { 585 clock = ddata->clocks[i]; 586 if (IS_ERR_OR_NULL(clock)) 587 continue; 588 589 clk_disable(clock); 590 } 591 592 return error; 593 } 594 595 static void sysc_disable_opt_clocks(struct sysc *ddata) 596 { 597 struct clk *clock; 598 int i; 599 600 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 601 return; 602 603 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 604 clock = ddata->clocks[i]; 605 606 /* Assume no holes for opt clocks */ 607 if (IS_ERR_OR_NULL(clock)) 608 return; 609 610 clk_disable(clock); 611 } 612 } 613 614 static void sysc_clkdm_deny_idle(struct sysc *ddata) 615 { 616 struct ti_sysc_platform_data *pdata; 617 618 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 619 return; 620 621 pdata = dev_get_platdata(ddata->dev); 622 if (pdata && pdata->clkdm_deny_idle) 623 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 624 } 625 626 static void sysc_clkdm_allow_idle(struct sysc *ddata) 627 { 628 struct ti_sysc_platform_data *pdata; 629 630 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 631 return; 632 633 pdata = dev_get_platdata(ddata->dev); 634 if (pdata && pdata->clkdm_allow_idle) 635 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 636 } 637 638 /** 639 * sysc_init_resets - init rstctrl reset line if configured 640 * @ddata: device driver data 641 * 642 * See sysc_rstctrl_reset_deassert(). 643 */ 644 static int sysc_init_resets(struct sysc *ddata) 645 { 646 ddata->rsts = 647 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 648 649 return PTR_ERR_OR_ZERO(ddata->rsts); 650 } 651 652 /** 653 * sysc_parse_and_check_child_range - parses module IO region from ranges 654 * @ddata: device driver data 655 * 656 * In general we only need rev, syss, and sysc registers and not the whole 657 * module range. But we do want the offsets for these registers from the 658 * module base. This allows us to check them against the legacy hwmod 659 * platform data. Let's also check the ranges are configured properly. 660 */ 661 static int sysc_parse_and_check_child_range(struct sysc *ddata) 662 { 663 struct device_node *np = ddata->dev->of_node; 664 struct of_range_parser parser; 665 struct of_range range; 666 int error; 667 668 error = of_range_parser_init(&parser, np); 669 if (error) 670 return error; 671 672 for_each_of_range(&parser, &range) { 673 ddata->module_pa = range.cpu_addr; 674 ddata->module_size = range.size; 675 break; 676 } 677 678 return 0; 679 } 680 681 static struct device_node *stdout_path; 682 683 static void sysc_init_stdout_path(struct sysc *ddata) 684 { 685 struct device_node *np = NULL; 686 const char *uart; 687 688 if (IS_ERR(stdout_path)) 689 return; 690 691 if (stdout_path) 692 return; 693 694 np = of_find_node_by_path("/chosen"); 695 if (!np) 696 goto err; 697 698 uart = of_get_property(np, "stdout-path", NULL); 699 if (!uart) 700 goto err; 701 702 np = of_find_node_by_path(uart); 703 if (!np) 704 goto err; 705 706 stdout_path = np; 707 708 return; 709 710 err: 711 stdout_path = ERR_PTR(-ENODEV); 712 } 713 714 static void sysc_check_quirk_stdout(struct sysc *ddata, 715 struct device_node *np) 716 { 717 sysc_init_stdout_path(ddata); 718 if (np != stdout_path) 719 return; 720 721 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 722 SYSC_QUIRK_NO_RESET_ON_INIT; 723 } 724 725 /** 726 * sysc_check_one_child - check child configuration 727 * @ddata: device driver data 728 * @np: child device node 729 * 730 * Let's avoid messy situations where we have new interconnect target 731 * node but children have "ti,hwmods". These belong to the interconnect 732 * target node and are managed by this driver. 733 */ 734 static void sysc_check_one_child(struct sysc *ddata, 735 struct device_node *np) 736 { 737 const char *name; 738 739 name = of_get_property(np, "ti,hwmods", NULL); 740 if (name && !of_device_is_compatible(np, "ti,sysc")) 741 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 742 743 sysc_check_quirk_stdout(ddata, np); 744 sysc_parse_dts_quirks(ddata, np, true); 745 } 746 747 static void sysc_check_children(struct sysc *ddata) 748 { 749 struct device_node *child; 750 751 for_each_child_of_node(ddata->dev->of_node, child) 752 sysc_check_one_child(ddata, child); 753 } 754 755 /* 756 * So far only I2C uses 16-bit read access with clockactivity with revision 757 * in two registers with stride of 4. We can detect this based on the rev 758 * register size to configure things far enough to be able to properly read 759 * the revision register. 760 */ 761 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 762 { 763 if (resource_size(res) == 8) 764 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 765 } 766 767 /** 768 * sysc_parse_one - parses the interconnect target module registers 769 * @ddata: device driver data 770 * @reg: register to parse 771 */ 772 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 773 { 774 struct resource *res; 775 const char *name; 776 777 switch (reg) { 778 case SYSC_REVISION: 779 case SYSC_SYSCONFIG: 780 case SYSC_SYSSTATUS: 781 name = reg_names[reg]; 782 break; 783 default: 784 return -EINVAL; 785 } 786 787 res = platform_get_resource_byname(to_platform_device(ddata->dev), 788 IORESOURCE_MEM, name); 789 if (!res) { 790 ddata->offsets[reg] = -ENODEV; 791 792 return 0; 793 } 794 795 ddata->offsets[reg] = res->start - ddata->module_pa; 796 if (reg == SYSC_REVISION) 797 sysc_check_quirk_16bit(ddata, res); 798 799 return 0; 800 } 801 802 static int sysc_parse_registers(struct sysc *ddata) 803 { 804 int i, error; 805 806 for (i = 0; i < SYSC_MAX_REGS; i++) { 807 error = sysc_parse_one(ddata, i); 808 if (error) 809 return error; 810 } 811 812 return 0; 813 } 814 815 /** 816 * sysc_check_registers - check for misconfigured register overlaps 817 * @ddata: device driver data 818 */ 819 static int sysc_check_registers(struct sysc *ddata) 820 { 821 int i, j, nr_regs = 0, nr_matches = 0; 822 823 for (i = 0; i < SYSC_MAX_REGS; i++) { 824 if (ddata->offsets[i] < 0) 825 continue; 826 827 if (ddata->offsets[i] > (ddata->module_size - 4)) { 828 dev_err(ddata->dev, "register outside module range"); 829 830 return -EINVAL; 831 } 832 833 for (j = 0; j < SYSC_MAX_REGS; j++) { 834 if (ddata->offsets[j] < 0) 835 continue; 836 837 if (ddata->offsets[i] == ddata->offsets[j]) 838 nr_matches++; 839 } 840 nr_regs++; 841 } 842 843 if (nr_matches > nr_regs) { 844 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 845 nr_regs, nr_matches); 846 847 return -EINVAL; 848 } 849 850 return 0; 851 } 852 853 /** 854 * sysc_ioremap - ioremap register space for the interconnect target module 855 * @ddata: device driver data 856 * 857 * Note that the interconnect target module registers can be anywhere 858 * within the interconnect target module range. For example, SGX has 859 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 860 * has them at offset 0x1200 in the CPSW_WR child. Usually the 861 * interconnect target module registers are at the beginning of 862 * the module range though. 863 */ 864 static int sysc_ioremap(struct sysc *ddata) 865 { 866 int size; 867 868 if (ddata->offsets[SYSC_REVISION] < 0 && 869 ddata->offsets[SYSC_SYSCONFIG] < 0 && 870 ddata->offsets[SYSC_SYSSTATUS] < 0) { 871 size = ddata->module_size; 872 } else { 873 size = max3(ddata->offsets[SYSC_REVISION], 874 ddata->offsets[SYSC_SYSCONFIG], 875 ddata->offsets[SYSC_SYSSTATUS]); 876 877 if (size < SZ_1K) 878 size = SZ_1K; 879 880 if ((size + sizeof(u32)) > ddata->module_size) 881 size = ddata->module_size; 882 } 883 884 ddata->module_va = devm_ioremap(ddata->dev, 885 ddata->module_pa, 886 size + sizeof(u32)); 887 if (!ddata->module_va) 888 return -EIO; 889 890 return 0; 891 } 892 893 /** 894 * sysc_map_and_check_registers - ioremap and check device registers 895 * @ddata: device driver data 896 */ 897 static int sysc_map_and_check_registers(struct sysc *ddata) 898 { 899 struct device_node *np = ddata->dev->of_node; 900 int error; 901 902 error = sysc_parse_and_check_child_range(ddata); 903 if (error) 904 return error; 905 906 sysc_check_children(ddata); 907 908 if (!of_property_present(np, "reg")) 909 return 0; 910 911 error = sysc_parse_registers(ddata); 912 if (error) 913 return error; 914 915 error = sysc_ioremap(ddata); 916 if (error) 917 return error; 918 919 error = sysc_check_registers(ddata); 920 if (error) 921 return error; 922 923 return 0; 924 } 925 926 /** 927 * sysc_show_rev - read and show interconnect target module revision 928 * @bufp: buffer to print the information to 929 * @ddata: device driver data 930 */ 931 static int sysc_show_rev(char *bufp, struct sysc *ddata) 932 { 933 int len; 934 935 if (ddata->offsets[SYSC_REVISION] < 0) 936 return sprintf(bufp, ":NA"); 937 938 len = sprintf(bufp, ":%08x", ddata->revision); 939 940 return len; 941 } 942 943 static int sysc_show_reg(struct sysc *ddata, 944 char *bufp, enum sysc_registers reg) 945 { 946 if (ddata->offsets[reg] < 0) 947 return sprintf(bufp, ":NA"); 948 949 return sprintf(bufp, ":%x", ddata->offsets[reg]); 950 } 951 952 static int sysc_show_name(char *bufp, struct sysc *ddata) 953 { 954 if (!ddata->name) 955 return 0; 956 957 return sprintf(bufp, ":%s", ddata->name); 958 } 959 960 /** 961 * sysc_show_registers - show information about interconnect target module 962 * @ddata: device driver data 963 */ 964 static void sysc_show_registers(struct sysc *ddata) 965 { 966 char buf[128]; 967 char *bufp = buf; 968 int i; 969 970 for (i = 0; i < SYSC_MAX_REGS; i++) 971 bufp += sysc_show_reg(ddata, bufp, i); 972 973 bufp += sysc_show_rev(bufp, ddata); 974 bufp += sysc_show_name(bufp, ddata); 975 976 dev_dbg(ddata->dev, "%llx:%x%s\n", 977 ddata->module_pa, ddata->module_size, 978 buf); 979 } 980 981 /** 982 * sysc_write_sysconfig - handle sysconfig quirks for register write 983 * @ddata: device driver data 984 * @value: register value 985 */ 986 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 987 { 988 if (ddata->module_unlock_quirk) 989 ddata->module_unlock_quirk(ddata); 990 991 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 992 993 if (ddata->module_lock_quirk) 994 ddata->module_lock_quirk(ddata); 995 } 996 997 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 998 #define SYSC_CLOCACT_ICK 2 999 1000 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1001 static int sysc_enable_module(struct device *dev) 1002 { 1003 struct sysc *ddata; 1004 const struct sysc_regbits *regbits; 1005 u32 reg, idlemodes, best_mode; 1006 int error; 1007 1008 ddata = dev_get_drvdata(dev); 1009 1010 /* 1011 * Some modules like DSS reset automatically on idle. Enable optional 1012 * reset clocks and wait for OCP softreset to complete. 1013 */ 1014 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 1015 error = sysc_enable_opt_clocks(ddata); 1016 if (error) { 1017 dev_err(ddata->dev, 1018 "Optional clocks failed for enable: %i\n", 1019 error); 1020 return error; 1021 } 1022 } 1023 /* 1024 * Some modules like i2c and hdq1w have unusable reset status unless 1025 * the module reset quirk is enabled. Skip status check on enable. 1026 */ 1027 if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) { 1028 error = sysc_wait_softreset(ddata); 1029 if (error) 1030 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1031 } 1032 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 1033 sysc_disable_opt_clocks(ddata); 1034 1035 /* 1036 * Some subsystem private interconnects, like DSS top level module, 1037 * need only the automatic OCP softreset handling with no sysconfig 1038 * register bits to configure. 1039 */ 1040 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1041 return 0; 1042 1043 regbits = ddata->cap->regbits; 1044 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1045 1046 /* 1047 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 1048 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 1049 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 1050 */ 1051 if (regbits->clkact_shift >= 0 && 1052 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 1053 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 1054 1055 /* Set SIDLE mode */ 1056 idlemodes = ddata->cfg.sidlemodes; 1057 if (!idlemodes || regbits->sidle_shift < 0) 1058 goto set_midle; 1059 1060 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1061 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1062 best_mode = SYSC_IDLE_NO; 1063 1064 /* Clear WAKEUP */ 1065 if (regbits->enwkup_shift >= 0 && 1066 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1067 reg &= ~BIT(regbits->enwkup_shift); 1068 } else { 1069 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1070 if (best_mode > SYSC_IDLE_MASK) { 1071 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1072 return -EINVAL; 1073 } 1074 1075 /* Set WAKEUP */ 1076 if (regbits->enwkup_shift >= 0 && 1077 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1078 reg |= BIT(regbits->enwkup_shift); 1079 } 1080 1081 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1082 reg |= best_mode << regbits->sidle_shift; 1083 sysc_write_sysconfig(ddata, reg); 1084 1085 set_midle: 1086 /* Set MIDLE mode */ 1087 idlemodes = ddata->cfg.midlemodes; 1088 if (!idlemodes || regbits->midle_shift < 0) 1089 goto set_autoidle; 1090 1091 best_mode = fls(ddata->cfg.midlemodes) - 1; 1092 if (best_mode > SYSC_IDLE_MASK) { 1093 dev_err(dev, "%s: invalid midlemode\n", __func__); 1094 error = -EINVAL; 1095 goto save_context; 1096 } 1097 1098 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1099 best_mode = SYSC_IDLE_NO; 1100 1101 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1102 reg |= best_mode << regbits->midle_shift; 1103 sysc_write_sysconfig(ddata, reg); 1104 1105 set_autoidle: 1106 /* Autoidle bit must enabled separately if available */ 1107 if (regbits->autoidle_shift >= 0 && 1108 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1109 reg |= 1 << regbits->autoidle_shift; 1110 sysc_write_sysconfig(ddata, reg); 1111 } 1112 1113 error = 0; 1114 1115 save_context: 1116 /* Save context and flush posted write */ 1117 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1118 1119 if (ddata->module_enable_quirk) 1120 ddata->module_enable_quirk(ddata); 1121 1122 return error; 1123 } 1124 1125 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1126 { 1127 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1128 *best_mode = SYSC_IDLE_SMART_WKUP; 1129 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1130 *best_mode = SYSC_IDLE_SMART; 1131 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1132 *best_mode = SYSC_IDLE_FORCE; 1133 else 1134 return -EINVAL; 1135 1136 return 0; 1137 } 1138 1139 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1140 static int sysc_disable_module(struct device *dev) 1141 { 1142 struct sysc *ddata; 1143 const struct sysc_regbits *regbits; 1144 u32 reg, idlemodes, best_mode; 1145 int ret; 1146 1147 ddata = dev_get_drvdata(dev); 1148 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1149 return 0; 1150 1151 if (ddata->module_disable_quirk) 1152 ddata->module_disable_quirk(ddata); 1153 1154 regbits = ddata->cap->regbits; 1155 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1156 1157 /* Set MIDLE mode */ 1158 idlemodes = ddata->cfg.midlemodes; 1159 if (!idlemodes || regbits->midle_shift < 0) 1160 goto set_sidle; 1161 1162 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1163 if (ret) { 1164 dev_err(dev, "%s: invalid midlemode\n", __func__); 1165 return ret; 1166 } 1167 1168 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1169 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1170 best_mode = SYSC_IDLE_FORCE; 1171 1172 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1173 reg |= best_mode << regbits->midle_shift; 1174 sysc_write_sysconfig(ddata, reg); 1175 1176 set_sidle: 1177 /* Set SIDLE mode */ 1178 idlemodes = ddata->cfg.sidlemodes; 1179 if (!idlemodes || regbits->sidle_shift < 0) { 1180 ret = 0; 1181 goto save_context; 1182 } 1183 1184 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1185 best_mode = SYSC_IDLE_FORCE; 1186 } else { 1187 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1188 if (ret) { 1189 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1190 ret = -EINVAL; 1191 goto save_context; 1192 } 1193 } 1194 1195 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) { 1196 /* Set WAKEUP */ 1197 if (regbits->enwkup_shift >= 0 && 1198 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1199 reg |= BIT(regbits->enwkup_shift); 1200 } 1201 1202 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1203 reg |= best_mode << regbits->sidle_shift; 1204 if (regbits->autoidle_shift >= 0 && 1205 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1206 reg |= 1 << regbits->autoidle_shift; 1207 sysc_write_sysconfig(ddata, reg); 1208 1209 ret = 0; 1210 1211 save_context: 1212 /* Save context and flush posted write */ 1213 ddata->sysconfig = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1214 1215 return ret; 1216 } 1217 1218 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1219 struct sysc *ddata) 1220 { 1221 struct ti_sysc_platform_data *pdata; 1222 int error; 1223 1224 pdata = dev_get_platdata(ddata->dev); 1225 if (!pdata) 1226 return 0; 1227 1228 if (!pdata->idle_module) 1229 return -ENODEV; 1230 1231 error = pdata->idle_module(dev, &ddata->cookie); 1232 if (error) 1233 dev_err(dev, "%s: could not idle: %i\n", 1234 __func__, error); 1235 1236 reset_control_assert(ddata->rsts); 1237 1238 return 0; 1239 } 1240 1241 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1242 struct sysc *ddata) 1243 { 1244 struct ti_sysc_platform_data *pdata; 1245 int error; 1246 1247 pdata = dev_get_platdata(ddata->dev); 1248 if (!pdata) 1249 return 0; 1250 1251 if (!pdata->enable_module) 1252 return -ENODEV; 1253 1254 error = pdata->enable_module(dev, &ddata->cookie); 1255 if (error) 1256 dev_err(dev, "%s: could not enable: %i\n", 1257 __func__, error); 1258 1259 reset_control_deassert(ddata->rsts); 1260 1261 return 0; 1262 } 1263 1264 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1265 { 1266 struct sysc *ddata; 1267 int error = 0; 1268 1269 ddata = dev_get_drvdata(dev); 1270 1271 if (!ddata->enabled) 1272 return 0; 1273 1274 sysc_clkdm_deny_idle(ddata); 1275 1276 if (ddata->legacy_mode) { 1277 error = sysc_runtime_suspend_legacy(dev, ddata); 1278 if (error) 1279 goto err_allow_idle; 1280 } else { 1281 error = sysc_disable_module(dev); 1282 if (error) 1283 goto err_allow_idle; 1284 } 1285 1286 sysc_disable_main_clocks(ddata); 1287 1288 if (sysc_opt_clks_needed(ddata)) 1289 sysc_disable_opt_clocks(ddata); 1290 1291 ddata->enabled = false; 1292 1293 err_allow_idle: 1294 sysc_clkdm_allow_idle(ddata); 1295 1296 reset_control_assert(ddata->rsts); 1297 1298 return error; 1299 } 1300 1301 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1302 { 1303 struct sysc *ddata; 1304 int error = 0; 1305 1306 ddata = dev_get_drvdata(dev); 1307 1308 if (ddata->enabled) 1309 return 0; 1310 1311 1312 sysc_clkdm_deny_idle(ddata); 1313 1314 if (sysc_opt_clks_needed(ddata)) { 1315 error = sysc_enable_opt_clocks(ddata); 1316 if (error) 1317 goto err_allow_idle; 1318 } 1319 1320 error = sysc_enable_main_clocks(ddata); 1321 if (error) 1322 goto err_opt_clocks; 1323 1324 reset_control_deassert(ddata->rsts); 1325 1326 if (ddata->legacy_mode) { 1327 error = sysc_runtime_resume_legacy(dev, ddata); 1328 if (error) 1329 goto err_main_clocks; 1330 } else { 1331 error = sysc_enable_module(dev); 1332 if (error) 1333 goto err_main_clocks; 1334 } 1335 1336 ddata->enabled = true; 1337 1338 sysc_clkdm_allow_idle(ddata); 1339 1340 return 0; 1341 1342 err_main_clocks: 1343 sysc_disable_main_clocks(ddata); 1344 err_opt_clocks: 1345 if (sysc_opt_clks_needed(ddata)) 1346 sysc_disable_opt_clocks(ddata); 1347 err_allow_idle: 1348 sysc_clkdm_allow_idle(ddata); 1349 1350 return error; 1351 } 1352 1353 /* 1354 * Checks if device context was lost. Assumes the sysconfig register value 1355 * after lost context is different from the configured value. Only works for 1356 * enabled devices. 1357 * 1358 * Eventually we may want to also add support to using the context lost 1359 * registers that some SoCs have. 1360 */ 1361 static int sysc_check_context(struct sysc *ddata) 1362 { 1363 u32 reg; 1364 1365 if (!ddata->enabled) 1366 return -ENODATA; 1367 1368 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1369 if (reg == ddata->sysconfig) 1370 return 0; 1371 1372 return -EACCES; 1373 } 1374 1375 static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled) 1376 { 1377 struct device *dev = ddata->dev; 1378 int error; 1379 1380 if (ddata->enabled) { 1381 /* Nothing to do if enabled and context not lost */ 1382 error = sysc_check_context(ddata); 1383 if (!error) 1384 return 0; 1385 1386 /* Disable target module if it is enabled */ 1387 error = sysc_runtime_suspend(dev); 1388 if (error) 1389 dev_warn(dev, "reinit suspend failed: %i\n", error); 1390 } 1391 1392 /* Enable target module */ 1393 error = sysc_runtime_resume(dev); 1394 if (error) 1395 dev_warn(dev, "reinit resume failed: %i\n", error); 1396 1397 /* Some modules like am335x gpmc need reset and restore of sysconfig */ 1398 if (ddata->cfg.quirks & SYSC_QUIRK_RESET_ON_CTX_LOST) { 1399 error = sysc_reset(ddata); 1400 if (error) 1401 dev_warn(dev, "reinit reset failed: %i\n", error); 1402 1403 sysc_write_sysconfig(ddata, ddata->sysconfig); 1404 } 1405 1406 if (leave_enabled) 1407 return error; 1408 1409 /* Disable target module if no leave_enabled was set */ 1410 error = sysc_runtime_suspend(dev); 1411 if (error) 1412 dev_warn(dev, "reinit suspend failed: %i\n", error); 1413 1414 return error; 1415 } 1416 1417 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1418 { 1419 struct sysc *ddata; 1420 1421 ddata = dev_get_drvdata(dev); 1422 1423 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 1424 return 0; 1425 1426 if (!ddata->enabled) 1427 return 0; 1428 1429 ddata->needs_resume = 1; 1430 1431 return sysc_runtime_suspend(dev); 1432 } 1433 1434 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1435 { 1436 struct sysc *ddata; 1437 int error = 0; 1438 1439 ddata = dev_get_drvdata(dev); 1440 1441 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 1442 return 0; 1443 1444 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) { 1445 error = sysc_reinit_module(ddata, ddata->needs_resume); 1446 if (error) 1447 dev_warn(dev, "noirq_resume failed: %i\n", error); 1448 } else if (ddata->needs_resume) { 1449 error = sysc_runtime_resume(dev); 1450 if (error) 1451 dev_warn(dev, "noirq_resume failed: %i\n", error); 1452 } 1453 1454 ddata->needs_resume = 0; 1455 1456 return error; 1457 } 1458 1459 static const struct dev_pm_ops sysc_pm_ops = { 1460 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1461 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1462 sysc_runtime_resume, 1463 NULL) 1464 }; 1465 1466 /* Module revision register based quirks */ 1467 struct sysc_revision_quirk { 1468 const char *name; 1469 u32 base; 1470 int rev_offset; 1471 int sysc_offset; 1472 int syss_offset; 1473 u32 revision; 1474 u32 revision_mask; 1475 u32 quirks; 1476 }; 1477 1478 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1479 optrev_val, optrevmask, optquirkmask) \ 1480 { \ 1481 .name = (optname), \ 1482 .base = (optbase), \ 1483 .rev_offset = (optrev), \ 1484 .sysc_offset = (optsysc), \ 1485 .syss_offset = (optsyss), \ 1486 .revision = (optrev_val), \ 1487 .revision_mask = (optrevmask), \ 1488 .quirks = (optquirkmask), \ 1489 } 1490 1491 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1492 /* Quirks that need to be set based on the module address */ 1493 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1494 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1495 SYSC_QUIRK_SWSUP_SIDLE), 1496 1497 /* Quirks that need to be set based on detected module */ 1498 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1499 SYSC_MODULE_QUIRK_AESS), 1500 /* Errata i893 handling for dra7 dcan1 and 2 */ 1501 SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1502 SYSC_QUIRK_CLKDM_NOAUTO), 1503 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1504 SYSC_QUIRK_CLKDM_NOAUTO), 1505 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1506 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1507 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1508 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1509 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1510 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1511 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1512 SYSC_QUIRK_CLKDM_NOAUTO), 1513 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1514 SYSC_QUIRK_CLKDM_NOAUTO), 1515 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1516 SYSC_QUIRK_OPT_CLKS_IN_RESET), 1517 SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, 1518 SYSC_QUIRK_REINIT_ON_CTX_LOST | SYSC_QUIRK_RESET_ON_CTX_LOST | 1519 SYSC_QUIRK_GPMC_DEBUG), 1520 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1521 SYSC_QUIRK_OPT_CLKS_NEEDED), 1522 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1523 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1524 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1525 SYSC_MODULE_QUIRK_HDQ1W | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1526 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1527 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1528 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1529 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1530 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1531 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1532 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1533 SYSC_MODULE_QUIRK_I2C | SYSC_MODULE_QUIRK_ENA_RESETDONE), 1534 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1535 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1536 SYSC_MODULE_QUIRK_SGX), 1537 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1538 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1539 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 1540 SYSC_QUIRK_SWSUP_SIDLE), 1541 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1542 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1543 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1544 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1545 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1546 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1547 SYSC_QUIRK("sata", 0, 0xfc, 0x1100, -ENODEV, 0x5e412000, 0xffffffff, 1548 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1549 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1550 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1551 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1552 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1553 /* Uarts on omap4 and later */ 1554 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1555 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1556 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1557 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1558 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, 1559 SYSC_QUIRK_SWSUP_SIDLE_ACT), 1560 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1561 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1562 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1563 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1564 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000033, 1565 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1566 SYSC_MODULE_QUIRK_OTG), 1567 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000040, 1568 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1569 SYSC_MODULE_QUIRK_OTG), 1570 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1571 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1572 SYSC_MODULE_QUIRK_OTG), 1573 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1574 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY | 1575 SYSC_QUIRK_REINIT_ON_CTX_LOST), 1576 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1577 SYSC_MODULE_QUIRK_WDT), 1578 /* PRUSS on am3, am4 and am5 */ 1579 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1580 SYSC_MODULE_QUIRK_PRUSS), 1581 /* Watchdog on am3 and am4 */ 1582 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1583 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1584 1585 #ifdef DEBUG 1586 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1587 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1588 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1589 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1590 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1591 0xffff00f0, 0), 1592 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1593 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1594 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1595 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1596 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1597 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1598 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1599 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1600 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1601 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1602 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1603 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1604 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1605 SYSC_QUIRK("elm", 0x48080000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1606 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x40441403, 0xffff0fff, 0), 1607 SYSC_QUIRK("emif", 0, 0, -ENODEV, -ENODEV, 0x50440500, 0xffffffff, 0), 1608 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1609 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1610 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1611 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1612 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1613 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1614 SYSC_QUIRK("keypad", 0x4a31c000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 0), 1615 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1616 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1617 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1618 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1619 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1620 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1621 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1622 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1623 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1624 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1625 SYSC_QUIRK("pcie", 0x51000000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1626 SYSC_QUIRK("pcie", 0x51800000, -ENODEV, -ENODEV, -ENODEV, 0, 0, 0), 1627 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1628 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1629 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1630 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1631 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1632 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1633 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1634 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1635 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1636 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1637 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1638 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1639 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1640 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 0), 1641 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1642 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1643 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 0), 1644 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 0), 1645 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1646 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1647 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1648 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1649 /* Some timers on omap4 and later */ 1650 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1651 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1652 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1653 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1654 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1655 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1656 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1657 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1658 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1659 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1660 #endif 1661 }; 1662 1663 /* 1664 * Early quirks based on module base and register offsets only that are 1665 * needed before the module revision can be read 1666 */ 1667 static void sysc_init_early_quirks(struct sysc *ddata) 1668 { 1669 const struct sysc_revision_quirk *q; 1670 int i; 1671 1672 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1673 q = &sysc_revision_quirks[i]; 1674 1675 if (!q->base) 1676 continue; 1677 1678 if (q->base != ddata->module_pa) 1679 continue; 1680 1681 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1682 continue; 1683 1684 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1685 continue; 1686 1687 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1688 continue; 1689 1690 ddata->name = q->name; 1691 ddata->cfg.quirks |= q->quirks; 1692 } 1693 } 1694 1695 /* Quirks that also consider the revision register value */ 1696 static void sysc_init_revision_quirks(struct sysc *ddata) 1697 { 1698 const struct sysc_revision_quirk *q; 1699 int i; 1700 1701 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1702 q = &sysc_revision_quirks[i]; 1703 1704 if (q->base && q->base != ddata->module_pa) 1705 continue; 1706 1707 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1708 continue; 1709 1710 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1711 continue; 1712 1713 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1714 continue; 1715 1716 if (q->revision == ddata->revision || 1717 (q->revision & q->revision_mask) == 1718 (ddata->revision & q->revision_mask)) { 1719 ddata->name = q->name; 1720 ddata->cfg.quirks |= q->quirks; 1721 } 1722 } 1723 } 1724 1725 /* 1726 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1727 * enabled DSS interrupts. Eventually we may be able to do this on 1728 * dispc init rather than top-level DSS init. 1729 */ 1730 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1731 bool disable) 1732 { 1733 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1734 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1735 int manager_count; 1736 bool framedonetv_irq = true; 1737 u32 val, irq_mask = 0; 1738 1739 switch (sysc_soc->soc) { 1740 case SOC_2420 ... SOC_3630: 1741 manager_count = 2; 1742 framedonetv_irq = false; 1743 break; 1744 case SOC_4430 ... SOC_4470: 1745 manager_count = 3; 1746 break; 1747 case SOC_5430: 1748 case SOC_DRA7: 1749 manager_count = 4; 1750 break; 1751 case SOC_AM4: 1752 manager_count = 1; 1753 framedonetv_irq = false; 1754 break; 1755 case SOC_UNKNOWN: 1756 default: 1757 return 0; 1758 } 1759 1760 /* Remap the whole module range to be able to reset dispc outputs */ 1761 devm_iounmap(ddata->dev, ddata->module_va); 1762 ddata->module_va = devm_ioremap(ddata->dev, 1763 ddata->module_pa, 1764 ddata->module_size); 1765 if (!ddata->module_va) 1766 return -EIO; 1767 1768 /* DISP_CONTROL, shut down lcd and digit on disable if enabled */ 1769 val = sysc_read(ddata, dispc_offset + 0x40); 1770 lcd_en = val & lcd_en_mask; 1771 digit_en = val & digit_en_mask; 1772 if (lcd_en) 1773 irq_mask |= BIT(0); /* FRAMEDONE */ 1774 if (digit_en) { 1775 if (framedonetv_irq) 1776 irq_mask |= BIT(24); /* FRAMEDONETV */ 1777 else 1778 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1779 } 1780 if (disable && (lcd_en || digit_en)) 1781 sysc_write(ddata, dispc_offset + 0x40, 1782 val & ~(lcd_en_mask | digit_en_mask)); 1783 1784 if (manager_count <= 2) 1785 return irq_mask; 1786 1787 /* DISPC_CONTROL2 */ 1788 val = sysc_read(ddata, dispc_offset + 0x238); 1789 lcd2_en = val & lcd_en_mask; 1790 if (lcd2_en) 1791 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1792 if (disable && lcd2_en) 1793 sysc_write(ddata, dispc_offset + 0x238, 1794 val & ~lcd_en_mask); 1795 1796 if (manager_count <= 3) 1797 return irq_mask; 1798 1799 /* DISPC_CONTROL3 */ 1800 val = sysc_read(ddata, dispc_offset + 0x848); 1801 lcd3_en = val & lcd_en_mask; 1802 if (lcd3_en) 1803 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1804 if (disable && lcd3_en) 1805 sysc_write(ddata, dispc_offset + 0x848, 1806 val & ~lcd_en_mask); 1807 1808 return irq_mask; 1809 } 1810 1811 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1812 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1813 { 1814 const int dispc_offset = 0x1000; 1815 int error; 1816 u32 irq_mask, val; 1817 1818 /* Get enabled outputs */ 1819 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1820 if (!irq_mask) 1821 return; 1822 1823 /* Clear IRQSTATUS */ 1824 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1825 1826 /* Disable outputs */ 1827 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1828 1829 /* Poll IRQSTATUS */ 1830 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1831 val, val != irq_mask, 100, 50); 1832 if (error) 1833 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1834 __func__, val, irq_mask); 1835 1836 if (sysc_soc->soc == SOC_3430 || sysc_soc->soc == SOC_AM35) { 1837 /* Clear DSS_SDI_CONTROL */ 1838 sysc_write(ddata, 0x44, 0); 1839 1840 /* Clear DSS_PLL_CONTROL */ 1841 sysc_write(ddata, 0x48, 0); 1842 } 1843 1844 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1845 sysc_write(ddata, 0x40, 0); 1846 } 1847 1848 /* 1-wire needs module's internal clocks enabled for reset */ 1849 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1850 { 1851 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1852 u16 val; 1853 1854 val = sysc_read(ddata, offset); 1855 val |= BIT(5); 1856 sysc_write(ddata, offset, val); 1857 } 1858 1859 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1860 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1861 { 1862 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1863 1864 sysc_write(ddata, offset, 1); 1865 } 1866 1867 /* I2C needs to be disabled for reset */ 1868 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1869 { 1870 int offset; 1871 u16 val; 1872 1873 /* I2C_CON, omap2/3 is different from omap4 and later */ 1874 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1875 offset = 0x24; 1876 else 1877 offset = 0xa4; 1878 1879 /* I2C_EN */ 1880 val = sysc_read(ddata, offset); 1881 if (enable) 1882 val |= BIT(15); 1883 else 1884 val &= ~BIT(15); 1885 sysc_write(ddata, offset, val); 1886 } 1887 1888 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1889 { 1890 sysc_clk_quirk_i2c(ddata, false); 1891 } 1892 1893 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1894 { 1895 sysc_clk_quirk_i2c(ddata, true); 1896 } 1897 1898 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1899 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1900 { 1901 u32 val, kick0_val = 0, kick1_val = 0; 1902 unsigned long flags; 1903 int error; 1904 1905 if (!lock) { 1906 kick0_val = 0x83e70b13; 1907 kick1_val = 0x95a4f1e0; 1908 } 1909 1910 local_irq_save(flags); 1911 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1912 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1913 !(val & BIT(0)), 100, 50); 1914 if (error) 1915 dev_warn(ddata->dev, "rtc busy timeout\n"); 1916 /* Now we have ~15 microseconds to read/write various registers */ 1917 sysc_write(ddata, 0x6c, kick0_val); 1918 sysc_write(ddata, 0x70, kick1_val); 1919 local_irq_restore(flags); 1920 } 1921 1922 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1923 { 1924 sysc_quirk_rtc(ddata, false); 1925 } 1926 1927 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1928 { 1929 sysc_quirk_rtc(ddata, true); 1930 } 1931 1932 /* OTG omap2430 glue layer up to omap4 needs OTG_FORCESTDBY configured */ 1933 static void sysc_module_enable_quirk_otg(struct sysc *ddata) 1934 { 1935 int offset = 0x414; /* OTG_FORCESTDBY */ 1936 1937 sysc_write(ddata, offset, 0); 1938 } 1939 1940 static void sysc_module_disable_quirk_otg(struct sysc *ddata) 1941 { 1942 int offset = 0x414; /* OTG_FORCESTDBY */ 1943 u32 val = BIT(0); /* ENABLEFORCE */ 1944 1945 sysc_write(ddata, offset, val); 1946 } 1947 1948 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1949 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1950 { 1951 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1952 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1953 1954 sysc_write(ddata, offset, val); 1955 } 1956 1957 /* Watchdog timer needs a disable sequence after reset */ 1958 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1959 { 1960 int wps, spr, error; 1961 u32 val; 1962 1963 wps = 0x34; 1964 spr = 0x48; 1965 1966 sysc_write(ddata, spr, 0xaaaa); 1967 error = readl_poll_timeout(ddata->module_va + wps, val, 1968 !(val & 0x10), 100, 1969 MAX_MODULE_SOFTRESET_WAIT); 1970 if (error) 1971 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1972 1973 sysc_write(ddata, spr, 0x5555); 1974 error = readl_poll_timeout(ddata->module_va + wps, val, 1975 !(val & 0x10), 100, 1976 MAX_MODULE_SOFTRESET_WAIT); 1977 if (error) 1978 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1979 } 1980 1981 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 1982 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 1983 { 1984 u32 reg; 1985 1986 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1987 reg |= SYSC_PRUSS_STANDBY_INIT; 1988 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1989 } 1990 1991 static void sysc_module_enable_quirk_pruss(struct sysc *ddata) 1992 { 1993 u32 reg; 1994 1995 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1996 1997 /* 1998 * Clearing the SYSC_PRUSS_STANDBY_INIT bit - Updates OCP master 1999 * port configuration to enable memory access outside of the 2000 * PRU-ICSS subsystem. 2001 */ 2002 reg &= (~SYSC_PRUSS_STANDBY_INIT); 2003 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 2004 } 2005 2006 static void sysc_init_module_quirks(struct sysc *ddata) 2007 { 2008 if (ddata->legacy_mode || !ddata->name) 2009 return; 2010 2011 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 2012 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 2013 2014 return; 2015 } 2016 2017 #ifdef CONFIG_OMAP_GPMC_DEBUG 2018 if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { 2019 ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; 2020 2021 return; 2022 } 2023 #endif 2024 2025 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 2026 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 2027 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 2028 2029 return; 2030 } 2031 2032 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 2033 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 2034 2035 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 2036 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 2037 2038 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 2039 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 2040 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 2041 2042 return; 2043 } 2044 2045 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_OTG) { 2046 ddata->module_enable_quirk = sysc_module_enable_quirk_otg; 2047 ddata->module_disable_quirk = sysc_module_disable_quirk_otg; 2048 } 2049 2050 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 2051 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 2052 2053 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 2054 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 2055 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 2056 } 2057 2058 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) { 2059 ddata->module_enable_quirk = sysc_module_enable_quirk_pruss; 2060 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 2061 } 2062 } 2063 2064 static int sysc_clockdomain_init(struct sysc *ddata) 2065 { 2066 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2067 struct clk *fck = NULL, *ick = NULL; 2068 int error; 2069 2070 if (!pdata || !pdata->init_clockdomain) 2071 return 0; 2072 2073 switch (ddata->nr_clocks) { 2074 case 2: 2075 ick = ddata->clocks[SYSC_ICK]; 2076 fallthrough; 2077 case 1: 2078 fck = ddata->clocks[SYSC_FCK]; 2079 break; 2080 case 0: 2081 return 0; 2082 } 2083 2084 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 2085 if (!error || error == -ENODEV) 2086 return 0; 2087 2088 return error; 2089 } 2090 2091 /* 2092 * Note that pdata->init_module() typically does a reset first. After 2093 * pdata->init_module() is done, PM runtime can be used for the interconnect 2094 * target module. 2095 */ 2096 static int sysc_legacy_init(struct sysc *ddata) 2097 { 2098 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2099 int error; 2100 2101 if (!pdata || !pdata->init_module) 2102 return 0; 2103 2104 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 2105 if (error == -EEXIST) 2106 error = 0; 2107 2108 return error; 2109 } 2110 2111 /* 2112 * Note that the caller must ensure the interconnect target module is enabled 2113 * before calling reset. Otherwise reset will not complete. 2114 */ 2115 static int sysc_reset(struct sysc *ddata) 2116 { 2117 int sysc_offset, sysc_val, error; 2118 u32 sysc_mask; 2119 2120 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 2121 2122 if (ddata->legacy_mode || 2123 ddata->cap->regbits->srst_shift < 0) 2124 return 0; 2125 2126 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 2127 2128 if (ddata->pre_reset_quirk) 2129 ddata->pre_reset_quirk(ddata); 2130 2131 if (sysc_offset >= 0) { 2132 sysc_val = sysc_read_sysconfig(ddata); 2133 sysc_val |= sysc_mask; 2134 sysc_write(ddata, sysc_offset, sysc_val); 2135 2136 /* 2137 * Some devices need a delay before reading registers 2138 * after reset. Presumably a srst_udelay is not needed 2139 * for devices that use a rstctrl register reset. 2140 */ 2141 if (ddata->cfg.srst_udelay) 2142 fsleep(ddata->cfg.srst_udelay); 2143 2144 /* 2145 * Flush posted write. For devices needing srst_udelay 2146 * this should trigger an interconnect error if the 2147 * srst_udelay value is needed but not configured. 2148 */ 2149 sysc_val = sysc_read_sysconfig(ddata); 2150 } 2151 2152 if (ddata->post_reset_quirk) 2153 ddata->post_reset_quirk(ddata); 2154 2155 error = sysc_wait_softreset(ddata); 2156 if (error) 2157 dev_warn(ddata->dev, "OCP softreset timed out\n"); 2158 2159 if (ddata->reset_done_quirk) 2160 ddata->reset_done_quirk(ddata); 2161 2162 return error; 2163 } 2164 2165 /* 2166 * At this point the module is configured enough to read the revision but 2167 * module may not be completely configured yet to use PM runtime. Enable 2168 * all clocks directly during init to configure the quirks needed for PM 2169 * runtime based on the revision register. 2170 */ 2171 static int sysc_init_module(struct sysc *ddata) 2172 { 2173 bool rstctrl_deasserted = false; 2174 int error = sysc_clockdomain_init(ddata); 2175 2176 if (error) 2177 return error; 2178 2179 sysc_clkdm_deny_idle(ddata); 2180 2181 /* 2182 * Always enable clocks. The bootloader may or may not have enabled 2183 * the related clocks. 2184 */ 2185 error = sysc_enable_opt_clocks(ddata); 2186 if (error) 2187 return error; 2188 2189 error = sysc_enable_main_clocks(ddata); 2190 if (error) 2191 goto err_opt_clocks; 2192 2193 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2194 error = reset_control_deassert(ddata->rsts); 2195 if (error) 2196 goto err_main_clocks; 2197 rstctrl_deasserted = true; 2198 } 2199 2200 ddata->revision = sysc_read_revision(ddata); 2201 sysc_init_revision_quirks(ddata); 2202 sysc_init_module_quirks(ddata); 2203 2204 if (ddata->legacy_mode) { 2205 error = sysc_legacy_init(ddata); 2206 if (error) 2207 goto err_main_clocks; 2208 } 2209 2210 if (!ddata->legacy_mode) { 2211 error = sysc_enable_module(ddata->dev); 2212 if (error) 2213 goto err_main_clocks; 2214 } 2215 2216 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 2217 error = sysc_reset(ddata); 2218 if (error) 2219 dev_err(ddata->dev, "Reset failed with %d\n", error); 2220 2221 if (error && !ddata->legacy_mode) 2222 sysc_disable_module(ddata->dev); 2223 } 2224 2225 err_main_clocks: 2226 if (error) 2227 sysc_disable_main_clocks(ddata); 2228 err_opt_clocks: 2229 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 2230 if (error) { 2231 sysc_disable_opt_clocks(ddata); 2232 sysc_clkdm_allow_idle(ddata); 2233 } 2234 2235 if (error && rstctrl_deasserted && 2236 !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2237 reset_control_assert(ddata->rsts); 2238 2239 return error; 2240 } 2241 2242 static int sysc_init_sysc_mask(struct sysc *ddata) 2243 { 2244 struct device_node *np = ddata->dev->of_node; 2245 int error; 2246 u32 val; 2247 2248 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2249 if (error) 2250 return 0; 2251 2252 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2253 2254 return 0; 2255 } 2256 2257 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2258 const char *name) 2259 { 2260 struct device_node *np = ddata->dev->of_node; 2261 u32 val; 2262 2263 of_property_for_each_u32(np, name, val) { 2264 if (val >= SYSC_NR_IDLEMODES) { 2265 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2266 return -EINVAL; 2267 } 2268 *idlemodes |= (1 << val); 2269 } 2270 2271 return 0; 2272 } 2273 2274 static int sysc_init_idlemodes(struct sysc *ddata) 2275 { 2276 int error; 2277 2278 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2279 "ti,sysc-midle"); 2280 if (error) 2281 return error; 2282 2283 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2284 "ti,sysc-sidle"); 2285 if (error) 2286 return error; 2287 2288 return 0; 2289 } 2290 2291 /* 2292 * Only some devices on omap4 and later have SYSCONFIG reset done 2293 * bit. We can detect this if there is no SYSSTATUS at all, or the 2294 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2295 * have multiple bits for the child devices like OHCI and EHCI. 2296 * Depends on SYSC being parsed first. 2297 */ 2298 static int sysc_init_syss_mask(struct sysc *ddata) 2299 { 2300 struct device_node *np = ddata->dev->of_node; 2301 int error; 2302 u32 val; 2303 2304 error = of_property_read_u32(np, "ti,syss-mask", &val); 2305 if (error) { 2306 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2307 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2308 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2309 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2310 2311 return 0; 2312 } 2313 2314 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2315 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2316 2317 ddata->cfg.syss_mask = val; 2318 2319 return 0; 2320 } 2321 2322 /* 2323 * Many child device drivers need to have fck and opt clocks available 2324 * to get the clock rate for device internal configuration etc. 2325 */ 2326 static int sysc_child_add_named_clock(struct sysc *ddata, 2327 struct device *child, 2328 const char *name) 2329 { 2330 struct clk *clk; 2331 struct clk_lookup *l; 2332 int error = 0; 2333 2334 if (!name) 2335 return 0; 2336 2337 clk = clk_get(child, name); 2338 if (!IS_ERR(clk)) { 2339 error = -EEXIST; 2340 goto put_clk; 2341 } 2342 2343 clk = clk_get(ddata->dev, name); 2344 if (IS_ERR(clk)) 2345 return -ENODEV; 2346 2347 l = clkdev_create(clk, name, dev_name(child)); 2348 if (!l) 2349 error = -ENOMEM; 2350 put_clk: 2351 clk_put(clk); 2352 2353 return error; 2354 } 2355 2356 static int sysc_child_add_clocks(struct sysc *ddata, 2357 struct device *child) 2358 { 2359 int i, error; 2360 2361 for (i = 0; i < ddata->nr_clocks; i++) { 2362 error = sysc_child_add_named_clock(ddata, 2363 child, 2364 ddata->clock_roles[i]); 2365 if (error && error != -EEXIST) { 2366 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2367 ddata->clock_roles[i], error); 2368 2369 return error; 2370 } 2371 } 2372 2373 return 0; 2374 } 2375 2376 static const struct device_type sysc_device_type = { 2377 }; 2378 2379 static struct sysc *sysc_child_to_parent(struct device *dev) 2380 { 2381 struct device *parent = dev->parent; 2382 2383 if (!parent || parent->type != &sysc_device_type) 2384 return NULL; 2385 2386 return dev_get_drvdata(parent); 2387 } 2388 2389 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2390 { 2391 struct sysc *ddata; 2392 int error; 2393 2394 ddata = sysc_child_to_parent(dev); 2395 2396 error = pm_generic_runtime_suspend(dev); 2397 if (error) 2398 return error; 2399 2400 if (!ddata->enabled) 2401 return 0; 2402 2403 return sysc_runtime_suspend(ddata->dev); 2404 } 2405 2406 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2407 { 2408 struct sysc *ddata; 2409 int error; 2410 2411 ddata = sysc_child_to_parent(dev); 2412 2413 if (!ddata->enabled) { 2414 error = sysc_runtime_resume(ddata->dev); 2415 if (error < 0) 2416 dev_err(ddata->dev, 2417 "%s error: %i\n", __func__, error); 2418 } 2419 2420 return pm_generic_runtime_resume(dev); 2421 } 2422 2423 /* Caller needs to take list_lock if ever used outside of cpu_pm */ 2424 static void sysc_reinit_modules(struct sysc_soc_info *soc) 2425 { 2426 struct sysc_module *module; 2427 struct sysc *ddata; 2428 2429 list_for_each_entry(module, &sysc_soc->restored_modules, node) { 2430 ddata = module->ddata; 2431 sysc_reinit_module(ddata, ddata->enabled); 2432 } 2433 } 2434 2435 /** 2436 * sysc_context_notifier - optionally reset and restore module after idle 2437 * @nb: notifier block 2438 * @cmd: unused 2439 * @v: unused 2440 * 2441 * Some interconnect target modules need to be restored, or reset and restored 2442 * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x 2443 * OTG and GPMC target modules even if the modules are unused. 2444 */ 2445 static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd, 2446 void *v) 2447 { 2448 struct sysc_soc_info *soc; 2449 2450 soc = container_of(nb, struct sysc_soc_info, nb); 2451 2452 switch (cmd) { 2453 case CPU_CLUSTER_PM_ENTER: 2454 break; 2455 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 2456 break; 2457 case CPU_CLUSTER_PM_EXIT: 2458 sysc_reinit_modules(soc); 2459 break; 2460 } 2461 2462 return NOTIFY_OK; 2463 } 2464 2465 /** 2466 * sysc_add_restored - optionally add reset and restore quirk hanlling 2467 * @ddata: device data 2468 */ 2469 static void sysc_add_restored(struct sysc *ddata) 2470 { 2471 struct sysc_module *restored_module; 2472 2473 restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL); 2474 if (!restored_module) 2475 return; 2476 2477 restored_module->ddata = ddata; 2478 2479 mutex_lock(&sysc_soc->list_lock); 2480 2481 list_add(&restored_module->node, &sysc_soc->restored_modules); 2482 2483 if (sysc_soc->nb.notifier_call) 2484 goto out_unlock; 2485 2486 sysc_soc->nb.notifier_call = sysc_context_notifier; 2487 cpu_pm_register_notifier(&sysc_soc->nb); 2488 2489 out_unlock: 2490 mutex_unlock(&sysc_soc->list_lock); 2491 } 2492 2493 static int sysc_notifier_call(struct notifier_block *nb, 2494 unsigned long event, void *device) 2495 { 2496 struct device *dev = device; 2497 struct sysc *ddata; 2498 int error; 2499 2500 ddata = sysc_child_to_parent(dev); 2501 if (!ddata) 2502 return NOTIFY_DONE; 2503 2504 switch (event) { 2505 case BUS_NOTIFY_ADD_DEVICE: 2506 error = sysc_child_add_clocks(ddata, dev); 2507 if (error) 2508 return error; 2509 break; 2510 default: 2511 break; 2512 } 2513 2514 return NOTIFY_DONE; 2515 } 2516 2517 static struct notifier_block sysc_nb = { 2518 .notifier_call = sysc_notifier_call, 2519 }; 2520 2521 /* Device tree configured quirks */ 2522 struct sysc_dts_quirk { 2523 const char *name; 2524 u32 mask; 2525 }; 2526 2527 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2528 { .name = "ti,no-idle-on-init", 2529 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2530 { .name = "ti,no-reset-on-init", 2531 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2532 { .name = "ti,no-idle", 2533 .mask = SYSC_QUIRK_NO_IDLE, }, 2534 }; 2535 2536 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2537 bool is_child) 2538 { 2539 int i; 2540 2541 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2542 const char *name = sysc_dts_quirks[i].name; 2543 2544 if (!of_property_present(np, name)) 2545 continue; 2546 2547 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2548 if (is_child) { 2549 dev_warn(ddata->dev, 2550 "dts flag should be at module level for %s\n", 2551 name); 2552 } 2553 } 2554 } 2555 2556 static int sysc_init_dts_quirks(struct sysc *ddata) 2557 { 2558 struct device_node *np = ddata->dev->of_node; 2559 int error; 2560 u32 val; 2561 2562 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2563 2564 sysc_parse_dts_quirks(ddata, np, false); 2565 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2566 if (!error) { 2567 if (val > 255) { 2568 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2569 val); 2570 } 2571 2572 ddata->cfg.srst_udelay = (u8)val; 2573 } 2574 2575 return 0; 2576 } 2577 2578 static void sysc_unprepare(struct sysc *ddata) 2579 { 2580 int i; 2581 2582 if (!ddata->clocks) 2583 return; 2584 2585 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2586 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2587 clk_unprepare(ddata->clocks[i]); 2588 } 2589 } 2590 2591 /* 2592 * Common sysc register bits found on omap2, also known as type1 2593 */ 2594 static const struct sysc_regbits sysc_regbits_omap2 = { 2595 .dmadisable_shift = -ENODEV, 2596 .midle_shift = 12, 2597 .sidle_shift = 3, 2598 .clkact_shift = 8, 2599 .emufree_shift = 5, 2600 .enwkup_shift = 2, 2601 .srst_shift = 1, 2602 .autoidle_shift = 0, 2603 }; 2604 2605 static const struct sysc_capabilities sysc_omap2 = { 2606 .type = TI_SYSC_OMAP2, 2607 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2608 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2609 SYSC_OMAP2_AUTOIDLE, 2610 .regbits = &sysc_regbits_omap2, 2611 }; 2612 2613 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2614 static const struct sysc_capabilities sysc_omap2_timer = { 2615 .type = TI_SYSC_OMAP2_TIMER, 2616 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2617 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2618 SYSC_OMAP2_AUTOIDLE, 2619 .regbits = &sysc_regbits_omap2, 2620 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2621 }; 2622 2623 /* 2624 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2625 * with different sidle position 2626 */ 2627 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2628 .dmadisable_shift = -ENODEV, 2629 .midle_shift = -ENODEV, 2630 .sidle_shift = 4, 2631 .clkact_shift = -ENODEV, 2632 .enwkup_shift = -ENODEV, 2633 .srst_shift = 1, 2634 .autoidle_shift = 0, 2635 .emufree_shift = -ENODEV, 2636 }; 2637 2638 static const struct sysc_capabilities sysc_omap3_sham = { 2639 .type = TI_SYSC_OMAP3_SHAM, 2640 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2641 .regbits = &sysc_regbits_omap3_sham, 2642 }; 2643 2644 /* 2645 * AES register bits found on omap3 and later, a variant of 2646 * sysc_regbits_omap2 with different sidle position 2647 */ 2648 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2649 .dmadisable_shift = -ENODEV, 2650 .midle_shift = -ENODEV, 2651 .sidle_shift = 6, 2652 .clkact_shift = -ENODEV, 2653 .enwkup_shift = -ENODEV, 2654 .srst_shift = 1, 2655 .autoidle_shift = 0, 2656 .emufree_shift = -ENODEV, 2657 }; 2658 2659 static const struct sysc_capabilities sysc_omap3_aes = { 2660 .type = TI_SYSC_OMAP3_AES, 2661 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2662 .regbits = &sysc_regbits_omap3_aes, 2663 }; 2664 2665 /* 2666 * Common sysc register bits found on omap4, also known as type2 2667 */ 2668 static const struct sysc_regbits sysc_regbits_omap4 = { 2669 .dmadisable_shift = 16, 2670 .midle_shift = 4, 2671 .sidle_shift = 2, 2672 .clkact_shift = -ENODEV, 2673 .enwkup_shift = -ENODEV, 2674 .emufree_shift = 1, 2675 .srst_shift = 0, 2676 .autoidle_shift = -ENODEV, 2677 }; 2678 2679 static const struct sysc_capabilities sysc_omap4 = { 2680 .type = TI_SYSC_OMAP4, 2681 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2682 SYSC_OMAP4_SOFTRESET, 2683 .regbits = &sysc_regbits_omap4, 2684 }; 2685 2686 static const struct sysc_capabilities sysc_omap4_timer = { 2687 .type = TI_SYSC_OMAP4_TIMER, 2688 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2689 SYSC_OMAP4_SOFTRESET, 2690 .regbits = &sysc_regbits_omap4, 2691 }; 2692 2693 /* 2694 * Common sysc register bits found on omap4, also known as type3 2695 */ 2696 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2697 .dmadisable_shift = -ENODEV, 2698 .midle_shift = 2, 2699 .sidle_shift = 0, 2700 .clkact_shift = -ENODEV, 2701 .enwkup_shift = -ENODEV, 2702 .srst_shift = -ENODEV, 2703 .emufree_shift = -ENODEV, 2704 .autoidle_shift = -ENODEV, 2705 }; 2706 2707 static const struct sysc_capabilities sysc_omap4_simple = { 2708 .type = TI_SYSC_OMAP4_SIMPLE, 2709 .regbits = &sysc_regbits_omap4_simple, 2710 }; 2711 2712 /* 2713 * SmartReflex sysc found on omap34xx 2714 */ 2715 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2716 .dmadisable_shift = -ENODEV, 2717 .midle_shift = -ENODEV, 2718 .sidle_shift = -ENODEV, 2719 .clkact_shift = 20, 2720 .enwkup_shift = -ENODEV, 2721 .srst_shift = -ENODEV, 2722 .emufree_shift = -ENODEV, 2723 .autoidle_shift = -ENODEV, 2724 }; 2725 2726 static const struct sysc_capabilities sysc_34xx_sr = { 2727 .type = TI_SYSC_OMAP34XX_SR, 2728 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2729 .regbits = &sysc_regbits_omap34xx_sr, 2730 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED, 2731 }; 2732 2733 /* 2734 * SmartReflex sysc found on omap36xx and later 2735 */ 2736 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2737 .dmadisable_shift = -ENODEV, 2738 .midle_shift = -ENODEV, 2739 .sidle_shift = 24, 2740 .clkact_shift = -ENODEV, 2741 .enwkup_shift = 26, 2742 .srst_shift = -ENODEV, 2743 .emufree_shift = -ENODEV, 2744 .autoidle_shift = -ENODEV, 2745 }; 2746 2747 static const struct sysc_capabilities sysc_36xx_sr = { 2748 .type = TI_SYSC_OMAP36XX_SR, 2749 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2750 .regbits = &sysc_regbits_omap36xx_sr, 2751 .mod_quirks = SYSC_QUIRK_UNCACHED, 2752 }; 2753 2754 static const struct sysc_capabilities sysc_omap4_sr = { 2755 .type = TI_SYSC_OMAP4_SR, 2756 .regbits = &sysc_regbits_omap36xx_sr, 2757 }; 2758 2759 /* 2760 * McASP register bits found on omap4 and later 2761 */ 2762 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2763 .dmadisable_shift = -ENODEV, 2764 .midle_shift = -ENODEV, 2765 .sidle_shift = 0, 2766 .clkact_shift = -ENODEV, 2767 .enwkup_shift = -ENODEV, 2768 .srst_shift = -ENODEV, 2769 .emufree_shift = -ENODEV, 2770 .autoidle_shift = -ENODEV, 2771 }; 2772 2773 static const struct sysc_capabilities sysc_omap4_mcasp = { 2774 .type = TI_SYSC_OMAP4_MCASP, 2775 .regbits = &sysc_regbits_omap4_mcasp, 2776 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2777 }; 2778 2779 /* 2780 * McASP found on dra7 and later 2781 */ 2782 static const struct sysc_capabilities sysc_dra7_mcasp = { 2783 .type = TI_SYSC_OMAP4_SIMPLE, 2784 .regbits = &sysc_regbits_omap4_simple, 2785 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2786 }; 2787 2788 /* 2789 * FS USB host found on omap4 and later 2790 */ 2791 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2792 .dmadisable_shift = -ENODEV, 2793 .midle_shift = -ENODEV, 2794 .sidle_shift = 24, 2795 .clkact_shift = -ENODEV, 2796 .enwkup_shift = 26, 2797 .srst_shift = -ENODEV, 2798 .emufree_shift = -ENODEV, 2799 .autoidle_shift = -ENODEV, 2800 }; 2801 2802 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2803 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2804 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2805 .regbits = &sysc_regbits_omap4_usb_host_fs, 2806 }; 2807 2808 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2809 .dmadisable_shift = -ENODEV, 2810 .midle_shift = -ENODEV, 2811 .sidle_shift = -ENODEV, 2812 .clkact_shift = -ENODEV, 2813 .enwkup_shift = 4, 2814 .srst_shift = 0, 2815 .emufree_shift = -ENODEV, 2816 .autoidle_shift = -ENODEV, 2817 }; 2818 2819 static const struct sysc_capabilities sysc_dra7_mcan = { 2820 .type = TI_SYSC_DRA7_MCAN, 2821 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2822 .regbits = &sysc_regbits_dra7_mcan, 2823 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2824 }; 2825 2826 /* 2827 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2828 */ 2829 static const struct sysc_capabilities sysc_pruss = { 2830 .type = TI_SYSC_PRUSS, 2831 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2832 .regbits = &sysc_regbits_omap4_simple, 2833 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2834 }; 2835 2836 static int sysc_init_pdata(struct sysc *ddata) 2837 { 2838 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2839 struct ti_sysc_module_data *mdata; 2840 2841 if (!pdata) 2842 return 0; 2843 2844 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2845 if (!mdata) 2846 return -ENOMEM; 2847 2848 if (ddata->legacy_mode) { 2849 mdata->name = ddata->legacy_mode; 2850 mdata->module_pa = ddata->module_pa; 2851 mdata->module_size = ddata->module_size; 2852 mdata->offsets = ddata->offsets; 2853 mdata->nr_offsets = SYSC_MAX_REGS; 2854 mdata->cap = ddata->cap; 2855 mdata->cfg = &ddata->cfg; 2856 } 2857 2858 ddata->mdata = mdata; 2859 2860 return 0; 2861 } 2862 2863 static int sysc_init_match(struct sysc *ddata) 2864 { 2865 const struct sysc_capabilities *cap; 2866 2867 cap = of_device_get_match_data(ddata->dev); 2868 if (!cap) 2869 return -EINVAL; 2870 2871 ddata->cap = cap; 2872 if (ddata->cap) 2873 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2874 2875 return 0; 2876 } 2877 2878 static void ti_sysc_idle(struct work_struct *work) 2879 { 2880 struct sysc *ddata; 2881 2882 ddata = container_of(work, struct sysc, idle_work.work); 2883 2884 /* 2885 * One time decrement of clock usage counts if left on from init. 2886 * Note that we disable opt clocks unconditionally in this case 2887 * as they are enabled unconditionally during init without 2888 * considering sysc_opt_clks_needed() at that point. 2889 */ 2890 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2891 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2892 sysc_disable_main_clocks(ddata); 2893 sysc_disable_opt_clocks(ddata); 2894 sysc_clkdm_allow_idle(ddata); 2895 } 2896 2897 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2898 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2899 return; 2900 2901 /* 2902 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2903 * and SYSC_QUIRK_NO_RESET_ON_INIT 2904 */ 2905 if (pm_runtime_active(ddata->dev)) 2906 pm_runtime_put_sync(ddata->dev); 2907 } 2908 2909 /* 2910 * SoC model and features detection. Only needed for SoCs that need 2911 * special handling for quirks, no need to list others. 2912 */ 2913 static const struct soc_device_attribute sysc_soc_match[] = { 2914 SOC_FLAG("OMAP242*", SOC_2420), 2915 SOC_FLAG("OMAP243*", SOC_2430), 2916 SOC_FLAG("AM33*", SOC_AM33), 2917 SOC_FLAG("AM35*", SOC_AM35), 2918 SOC_FLAG("OMAP3[45]*", SOC_3430), 2919 SOC_FLAG("OMAP3[67]*", SOC_3630), 2920 SOC_FLAG("OMAP443*", SOC_4430), 2921 SOC_FLAG("OMAP446*", SOC_4460), 2922 SOC_FLAG("OMAP447*", SOC_4470), 2923 SOC_FLAG("OMAP54*", SOC_5430), 2924 SOC_FLAG("AM433", SOC_AM3), 2925 SOC_FLAG("AM43*", SOC_AM4), 2926 SOC_FLAG("DRA7*", SOC_DRA7), 2927 2928 { /* sentinel */ } 2929 }; 2930 2931 /* 2932 * List of SoCs variants with disabled features. By default we assume all 2933 * devices in the device tree are available so no need to list those SoCs. 2934 */ 2935 static const struct soc_device_attribute sysc_soc_feat_match[] = { 2936 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 2937 SOC_FLAG("AM3505", DIS_SGX), 2938 SOC_FLAG("OMAP3525", DIS_SGX), 2939 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 2940 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 2941 2942 /* OMAP3630/DM3730 variants with some accelerators disabled */ 2943 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 2944 SOC_FLAG("DM3725", DIS_SGX), 2945 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 2946 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 2947 SOC_FLAG("OMAP3621", DIS_ISP), 2948 2949 { /* sentinel */ } 2950 }; 2951 2952 static int sysc_add_disabled(unsigned long base) 2953 { 2954 struct sysc_address *disabled_module; 2955 2956 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 2957 if (!disabled_module) 2958 return -ENOMEM; 2959 2960 disabled_module->base = base; 2961 2962 mutex_lock(&sysc_soc->list_lock); 2963 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 2964 mutex_unlock(&sysc_soc->list_lock); 2965 2966 return 0; 2967 } 2968 2969 /* 2970 * One time init to detect the booted SoC, disable unavailable features 2971 * and initialize list for optional cpu_pm notifier. 2972 * 2973 * Note that we initialize static data shared across all ti-sysc instances 2974 * so ddata is only used for SoC type. This can be called from module_init 2975 * once we no longer need to rely on platform data. 2976 */ 2977 static int sysc_init_static_data(struct sysc *ddata) 2978 { 2979 const struct soc_device_attribute *match; 2980 struct ti_sysc_platform_data *pdata; 2981 unsigned long features = 0; 2982 struct device_node *np; 2983 2984 if (sysc_soc) 2985 return 0; 2986 2987 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 2988 if (!sysc_soc) 2989 return -ENOMEM; 2990 2991 mutex_init(&sysc_soc->list_lock); 2992 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 2993 INIT_LIST_HEAD(&sysc_soc->restored_modules); 2994 sysc_soc->general_purpose = true; 2995 2996 pdata = dev_get_platdata(ddata->dev); 2997 if (pdata && pdata->soc_type_gp) 2998 sysc_soc->general_purpose = pdata->soc_type_gp(); 2999 3000 match = soc_device_match(sysc_soc_match); 3001 if (match && match->data) 3002 sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data; 3003 3004 /* 3005 * Check and warn about possible old incomplete dtb. We now want to see 3006 * simple-pm-bus instead of simple-bus in the dtb for genpd using SoCs. 3007 */ 3008 switch (sysc_soc->soc) { 3009 case SOC_AM3: 3010 case SOC_AM4: 3011 case SOC_4430 ... SOC_4470: 3012 case SOC_5430: 3013 case SOC_DRA7: 3014 np = of_find_node_by_path("/ocp"); 3015 WARN_ONCE(np && of_device_is_compatible(np, "simple-bus"), 3016 "ti-sysc: Incomplete old dtb, please update\n"); 3017 break; 3018 default: 3019 break; 3020 } 3021 3022 /* Ignore devices that are not available on HS and EMU SoCs */ 3023 if (!sysc_soc->general_purpose) { 3024 switch (sysc_soc->soc) { 3025 case SOC_3430 ... SOC_3630: 3026 sysc_add_disabled(0x48304000); /* timer12 */ 3027 break; 3028 case SOC_AM3: 3029 sysc_add_disabled(0x48310000); /* rng */ 3030 break; 3031 default: 3032 break; 3033 } 3034 } 3035 3036 match = soc_device_match(sysc_soc_feat_match); 3037 if (!match) 3038 return 0; 3039 3040 if (match->data) 3041 features = (unsigned long)match->data; 3042 3043 /* 3044 * Add disabled devices to the list based on the module base. 3045 * Note that this must be done before we attempt to access the 3046 * device and have module revision checks working. 3047 */ 3048 if (features & DIS_ISP) 3049 sysc_add_disabled(0x480bd400); 3050 if (features & DIS_IVA) 3051 sysc_add_disabled(0x5d000000); 3052 if (features & DIS_SGX) 3053 sysc_add_disabled(0x50000000); 3054 3055 return 0; 3056 } 3057 3058 static void sysc_cleanup_static_data(void) 3059 { 3060 struct sysc_module *restored_module; 3061 struct sysc_address *disabled_module; 3062 struct list_head *pos, *tmp; 3063 3064 if (!sysc_soc) 3065 return; 3066 3067 if (sysc_soc->nb.notifier_call) 3068 cpu_pm_unregister_notifier(&sysc_soc->nb); 3069 3070 mutex_lock(&sysc_soc->list_lock); 3071 list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) { 3072 restored_module = list_entry(pos, struct sysc_module, node); 3073 list_del(pos); 3074 kfree(restored_module); 3075 } 3076 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 3077 disabled_module = list_entry(pos, struct sysc_address, node); 3078 list_del(pos); 3079 kfree(disabled_module); 3080 } 3081 mutex_unlock(&sysc_soc->list_lock); 3082 } 3083 3084 static int sysc_check_disabled_devices(struct sysc *ddata) 3085 { 3086 struct sysc_address *disabled_module; 3087 int error = 0; 3088 3089 mutex_lock(&sysc_soc->list_lock); 3090 list_for_each_entry(disabled_module, &sysc_soc->disabled_modules, node) { 3091 if (ddata->module_pa == disabled_module->base) { 3092 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 3093 error = -ENODEV; 3094 break; 3095 } 3096 } 3097 mutex_unlock(&sysc_soc->list_lock); 3098 3099 return error; 3100 } 3101 3102 /* 3103 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 3104 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 3105 * are needed, we could also look at the timer register configuration. 3106 */ 3107 static int sysc_check_active_timer(struct sysc *ddata) 3108 { 3109 int error; 3110 3111 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 3112 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 3113 return 0; 3114 3115 /* 3116 * Quirk for omap3 beagleboard revision A to B4 to use gpt12. 3117 * Revision C and later are fixed with commit 23885389dbbb ("ARM: 3118 * dts: Fix timer regression for beagleboard revision c"). This all 3119 * can be dropped if we stop supporting old beagleboard revisions 3120 * A to B4 at some point. 3121 */ 3122 switch (sysc_soc->soc) { 3123 case SOC_AM33: 3124 case SOC_3430: 3125 case SOC_AM35: 3126 error = -ENXIO; 3127 break; 3128 default: 3129 error = -EBUSY; 3130 } 3131 3132 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 3133 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 3134 return error; 3135 3136 return 0; 3137 } 3138 3139 static const struct of_device_id sysc_match_table[] = { 3140 { .compatible = "simple-bus", }, 3141 { /* sentinel */ }, 3142 }; 3143 3144 static int sysc_probe(struct platform_device *pdev) 3145 { 3146 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 3147 struct sysc *ddata; 3148 int error; 3149 3150 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 3151 if (!ddata) 3152 return -ENOMEM; 3153 3154 ddata->offsets[SYSC_REVISION] = -ENODEV; 3155 ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; 3156 ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; 3157 ddata->dev = &pdev->dev; 3158 platform_set_drvdata(pdev, ddata); 3159 3160 error = sysc_init_static_data(ddata); 3161 if (error) 3162 return error; 3163 3164 error = sysc_init_match(ddata); 3165 if (error) 3166 return error; 3167 3168 error = sysc_init_dts_quirks(ddata); 3169 if (error) 3170 return error; 3171 3172 error = sysc_map_and_check_registers(ddata); 3173 if (error) 3174 return error; 3175 3176 error = sysc_init_sysc_mask(ddata); 3177 if (error) 3178 return error; 3179 3180 error = sysc_init_idlemodes(ddata); 3181 if (error) 3182 return error; 3183 3184 error = sysc_init_syss_mask(ddata); 3185 if (error) 3186 return error; 3187 3188 error = sysc_init_pdata(ddata); 3189 if (error) 3190 return error; 3191 3192 sysc_init_early_quirks(ddata); 3193 3194 error = sysc_check_disabled_devices(ddata); 3195 if (error) 3196 return error; 3197 3198 error = sysc_check_active_timer(ddata); 3199 if (error == -ENXIO) 3200 ddata->reserved = true; 3201 else if (error) 3202 return error; 3203 3204 error = sysc_get_clocks(ddata); 3205 if (error) 3206 return error; 3207 3208 error = sysc_init_resets(ddata); 3209 if (error) 3210 goto unprepare; 3211 3212 error = sysc_init_module(ddata); 3213 if (error) 3214 goto unprepare; 3215 3216 pm_runtime_enable(ddata->dev); 3217 error = pm_runtime_resume_and_get(ddata->dev); 3218 if (error < 0) { 3219 pm_runtime_disable(ddata->dev); 3220 goto unprepare; 3221 } 3222 3223 /* Balance use counts as PM runtime should have enabled these all */ 3224 if (!(ddata->cfg.quirks & 3225 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 3226 sysc_disable_main_clocks(ddata); 3227 sysc_disable_opt_clocks(ddata); 3228 sysc_clkdm_allow_idle(ddata); 3229 } 3230 3231 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 3232 reset_control_assert(ddata->rsts); 3233 3234 sysc_show_registers(ddata); 3235 3236 ddata->dev->type = &sysc_device_type; 3237 3238 if (!ddata->reserved) { 3239 error = of_platform_populate(ddata->dev->of_node, 3240 sysc_match_table, 3241 pdata ? pdata->auxdata : NULL, 3242 ddata->dev); 3243 if (error) 3244 goto err; 3245 } 3246 3247 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 3248 3249 /* At least earlycon won't survive without deferred idle */ 3250 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 3251 SYSC_QUIRK_NO_IDLE_ON_INIT | 3252 SYSC_QUIRK_NO_RESET_ON_INIT)) { 3253 schedule_delayed_work(&ddata->idle_work, 3000); 3254 } else { 3255 pm_runtime_put(&pdev->dev); 3256 } 3257 3258 if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST) 3259 sysc_add_restored(ddata); 3260 3261 return 0; 3262 3263 err: 3264 pm_runtime_put_sync(&pdev->dev); 3265 pm_runtime_disable(&pdev->dev); 3266 unprepare: 3267 sysc_unprepare(ddata); 3268 3269 return error; 3270 } 3271 3272 static void sysc_remove(struct platform_device *pdev) 3273 { 3274 struct sysc *ddata = platform_get_drvdata(pdev); 3275 int error; 3276 3277 /* Device can still be enabled, see deferred idle quirk in probe */ 3278 if (cancel_delayed_work_sync(&ddata->idle_work)) 3279 ti_sysc_idle(&ddata->idle_work.work); 3280 3281 error = pm_runtime_resume_and_get(ddata->dev); 3282 if (error < 0) { 3283 pm_runtime_disable(ddata->dev); 3284 goto unprepare; 3285 } 3286 3287 of_platform_depopulate(&pdev->dev); 3288 3289 pm_runtime_put_sync(&pdev->dev); 3290 pm_runtime_disable(&pdev->dev); 3291 3292 if (!reset_control_status(ddata->rsts)) 3293 reset_control_assert(ddata->rsts); 3294 3295 unprepare: 3296 sysc_unprepare(ddata); 3297 } 3298 3299 static const struct of_device_id sysc_match[] = { 3300 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3301 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3302 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3303 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3304 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3305 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3306 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3307 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3308 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3309 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3310 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3311 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3312 { .compatible = "ti,sysc-usb-host-fs", 3313 .data = &sysc_omap4_usb_host_fs, }, 3314 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3315 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3316 { }, 3317 }; 3318 MODULE_DEVICE_TABLE(of, sysc_match); 3319 3320 static struct platform_driver sysc_driver = { 3321 .probe = sysc_probe, 3322 .remove = sysc_remove, 3323 .driver = { 3324 .name = "ti-sysc", 3325 .of_match_table = sysc_match, 3326 .pm = &sysc_pm_ops, 3327 }, 3328 }; 3329 3330 static int __init sysc_init(void) 3331 { 3332 bus_register_notifier(&platform_bus_type, &sysc_nb); 3333 3334 return platform_driver_register(&sysc_driver); 3335 } 3336 module_init(sysc_init); 3337 3338 static void __exit sysc_exit(void) 3339 { 3340 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3341 platform_driver_unregister(&sysc_driver); 3342 sysc_cleanup_static_data(); 3343 } 3344 module_exit(sysc_exit); 3345 3346 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3347 MODULE_LICENSE("GPL v2"); 3348