xref: /linux/drivers/bus/ti-sysc.c (revision 2c97b5ae83dca56718774e7b4bf9640f05d11867)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * ti-sysc.c - Texas Instruments sysc interconnect target driver
4  */
5 
6 #include <linux/io.h>
7 #include <linux/clk.h>
8 #include <linux/clkdev.h>
9 #include <linux/delay.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/pm_domain.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/slab.h>
18 #include <linux/iopoll.h>
19 
20 #include <linux/platform_data/ti-sysc.h>
21 
22 #include <dt-bindings/bus/ti-sysc.h>
23 
24 #define MAX_MODULE_SOFTRESET_WAIT		10000
25 
26 static const char * const reg_names[] = { "rev", "sysc", "syss", };
27 
28 enum sysc_clocks {
29 	SYSC_FCK,
30 	SYSC_ICK,
31 	SYSC_OPTFCK0,
32 	SYSC_OPTFCK1,
33 	SYSC_OPTFCK2,
34 	SYSC_OPTFCK3,
35 	SYSC_OPTFCK4,
36 	SYSC_OPTFCK5,
37 	SYSC_OPTFCK6,
38 	SYSC_OPTFCK7,
39 	SYSC_MAX_CLOCKS,
40 };
41 
42 static const char * const clock_names[SYSC_MAX_CLOCKS] = {
43 	"fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
44 	"opt5", "opt6", "opt7",
45 };
46 
47 #define SYSC_IDLEMODE_MASK		3
48 #define SYSC_CLOCKACTIVITY_MASK		3
49 
50 /**
51  * struct sysc - TI sysc interconnect target module registers and capabilities
52  * @dev: struct device pointer
53  * @module_pa: physical address of the interconnect target module
54  * @module_size: size of the interconnect target module
55  * @module_va: virtual address of the interconnect target module
56  * @offsets: register offsets from module base
57  * @mdata: ti-sysc to hwmod translation data for a module
58  * @clocks: clocks used by the interconnect target module
59  * @clock_roles: clock role names for the found clocks
60  * @nr_clocks: number of clocks used by the interconnect target module
61  * @rsts: resets used by the interconnect target module
62  * @legacy_mode: configured for legacy mode if set
63  * @cap: interconnect target module capabilities
64  * @cfg: interconnect target module configuration
65  * @cookie: data used by legacy platform callbacks
66  * @name: name if available
67  * @revision: interconnect target module revision
68  * @enabled: sysc runtime enabled status
69  * @needs_resume: runtime resume needed on resume from suspend
70  * @child_needs_resume: runtime resume needed for child on resume from suspend
71  * @disable_on_idle: status flag used for disabling modules with resets
72  * @idle_work: work structure used to perform delayed idle on a module
73  * @clk_enable_quirk: module specific clock enable quirk
74  * @clk_disable_quirk: module specific clock disable quirk
75  * @reset_done_quirk: module specific reset done quirk
76  * @module_enable_quirk: module specific enable quirk
77  * @module_disable_quirk: module specific disable quirk
78  */
79 struct sysc {
80 	struct device *dev;
81 	u64 module_pa;
82 	u32 module_size;
83 	void __iomem *module_va;
84 	int offsets[SYSC_MAX_REGS];
85 	struct ti_sysc_module_data *mdata;
86 	struct clk **clocks;
87 	const char **clock_roles;
88 	int nr_clocks;
89 	struct reset_control *rsts;
90 	const char *legacy_mode;
91 	const struct sysc_capabilities *cap;
92 	struct sysc_config cfg;
93 	struct ti_sysc_cookie cookie;
94 	const char *name;
95 	u32 revision;
96 	unsigned int enabled:1;
97 	unsigned int needs_resume:1;
98 	unsigned int child_needs_resume:1;
99 	struct delayed_work idle_work;
100 	void (*clk_enable_quirk)(struct sysc *sysc);
101 	void (*clk_disable_quirk)(struct sysc *sysc);
102 	void (*reset_done_quirk)(struct sysc *sysc);
103 	void (*module_enable_quirk)(struct sysc *sysc);
104 	void (*module_disable_quirk)(struct sysc *sysc);
105 };
106 
107 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
108 				  bool is_child);
109 
110 static void sysc_write(struct sysc *ddata, int offset, u32 value)
111 {
112 	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
113 		writew_relaxed(value & 0xffff, ddata->module_va + offset);
114 
115 		/* Only i2c revision has LO and HI register with stride of 4 */
116 		if (ddata->offsets[SYSC_REVISION] >= 0 &&
117 		    offset == ddata->offsets[SYSC_REVISION]) {
118 			u16 hi = value >> 16;
119 
120 			writew_relaxed(hi, ddata->module_va + offset + 4);
121 		}
122 
123 		return;
124 	}
125 
126 	writel_relaxed(value, ddata->module_va + offset);
127 }
128 
129 static u32 sysc_read(struct sysc *ddata, int offset)
130 {
131 	if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
132 		u32 val;
133 
134 		val = readw_relaxed(ddata->module_va + offset);
135 
136 		/* Only i2c revision has LO and HI register with stride of 4 */
137 		if (ddata->offsets[SYSC_REVISION] >= 0 &&
138 		    offset == ddata->offsets[SYSC_REVISION]) {
139 			u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
140 
141 			val |= tmp << 16;
142 		}
143 
144 		return val;
145 	}
146 
147 	return readl_relaxed(ddata->module_va + offset);
148 }
149 
150 static bool sysc_opt_clks_needed(struct sysc *ddata)
151 {
152 	return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED);
153 }
154 
155 static u32 sysc_read_revision(struct sysc *ddata)
156 {
157 	int offset = ddata->offsets[SYSC_REVISION];
158 
159 	if (offset < 0)
160 		return 0;
161 
162 	return sysc_read(ddata, offset);
163 }
164 
165 static u32 sysc_read_sysconfig(struct sysc *ddata)
166 {
167 	int offset = ddata->offsets[SYSC_SYSCONFIG];
168 
169 	if (offset < 0)
170 		return 0;
171 
172 	return sysc_read(ddata, offset);
173 }
174 
175 static u32 sysc_read_sysstatus(struct sysc *ddata)
176 {
177 	int offset = ddata->offsets[SYSC_SYSSTATUS];
178 
179 	if (offset < 0)
180 		return 0;
181 
182 	return sysc_read(ddata, offset);
183 }
184 
185 static int sysc_add_named_clock_from_child(struct sysc *ddata,
186 					   const char *name,
187 					   const char *optfck_name)
188 {
189 	struct device_node *np = ddata->dev->of_node;
190 	struct device_node *child;
191 	struct clk_lookup *cl;
192 	struct clk *clock;
193 	const char *n;
194 
195 	if (name)
196 		n = name;
197 	else
198 		n = optfck_name;
199 
200 	/* Does the clock alias already exist? */
201 	clock = of_clk_get_by_name(np, n);
202 	if (!IS_ERR(clock)) {
203 		clk_put(clock);
204 
205 		return 0;
206 	}
207 
208 	child = of_get_next_available_child(np, NULL);
209 	if (!child)
210 		return -ENODEV;
211 
212 	clock = devm_get_clk_from_child(ddata->dev, child, name);
213 	if (IS_ERR(clock))
214 		return PTR_ERR(clock);
215 
216 	/*
217 	 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
218 	 * limit for clk_get(). If cl ever needs to be freed, it should be done
219 	 * with clkdev_drop().
220 	 */
221 	cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
222 	if (!cl)
223 		return -ENOMEM;
224 
225 	cl->con_id = n;
226 	cl->dev_id = dev_name(ddata->dev);
227 	cl->clk = clock;
228 	clkdev_add(cl);
229 
230 	clk_put(clock);
231 
232 	return 0;
233 }
234 
235 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name)
236 {
237 	const char *optfck_name;
238 	int error, index;
239 
240 	if (ddata->nr_clocks < SYSC_OPTFCK0)
241 		index = SYSC_OPTFCK0;
242 	else
243 		index = ddata->nr_clocks;
244 
245 	if (name)
246 		optfck_name = name;
247 	else
248 		optfck_name = clock_names[index];
249 
250 	error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
251 	if (error)
252 		return error;
253 
254 	ddata->clock_roles[index] = optfck_name;
255 	ddata->nr_clocks++;
256 
257 	return 0;
258 }
259 
260 static int sysc_get_one_clock(struct sysc *ddata, const char *name)
261 {
262 	int error, i, index = -ENODEV;
263 
264 	if (!strncmp(clock_names[SYSC_FCK], name, 3))
265 		index = SYSC_FCK;
266 	else if (!strncmp(clock_names[SYSC_ICK], name, 3))
267 		index = SYSC_ICK;
268 
269 	if (index < 0) {
270 		for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
271 			if (!ddata->clocks[i]) {
272 				index = i;
273 				break;
274 			}
275 		}
276 	}
277 
278 	if (index < 0) {
279 		dev_err(ddata->dev, "clock %s not added\n", name);
280 		return index;
281 	}
282 
283 	ddata->clocks[index] = devm_clk_get(ddata->dev, name);
284 	if (IS_ERR(ddata->clocks[index])) {
285 		dev_err(ddata->dev, "clock get error for %s: %li\n",
286 			name, PTR_ERR(ddata->clocks[index]));
287 
288 		return PTR_ERR(ddata->clocks[index]);
289 	}
290 
291 	error = clk_prepare(ddata->clocks[index]);
292 	if (error) {
293 		dev_err(ddata->dev, "clock prepare error for %s: %i\n",
294 			name, error);
295 
296 		return error;
297 	}
298 
299 	return 0;
300 }
301 
302 static int sysc_get_clocks(struct sysc *ddata)
303 {
304 	struct device_node *np = ddata->dev->of_node;
305 	struct property *prop;
306 	const char *name;
307 	int nr_fck = 0, nr_ick = 0, i, error = 0;
308 
309 	ddata->clock_roles = devm_kcalloc(ddata->dev,
310 					  SYSC_MAX_CLOCKS,
311 					  sizeof(*ddata->clock_roles),
312 					  GFP_KERNEL);
313 	if (!ddata->clock_roles)
314 		return -ENOMEM;
315 
316 	of_property_for_each_string(np, "clock-names", prop, name) {
317 		if (!strncmp(clock_names[SYSC_FCK], name, 3))
318 			nr_fck++;
319 		if (!strncmp(clock_names[SYSC_ICK], name, 3))
320 			nr_ick++;
321 		ddata->clock_roles[ddata->nr_clocks] = name;
322 		ddata->nr_clocks++;
323 	}
324 
325 	if (ddata->nr_clocks < 1)
326 		return 0;
327 
328 	if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
329 		error = sysc_init_ext_opt_clock(ddata, NULL);
330 		if (error)
331 			return error;
332 	}
333 
334 	if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
335 		dev_err(ddata->dev, "too many clocks for %pOF\n", np);
336 
337 		return -EINVAL;
338 	}
339 
340 	if (nr_fck > 1 || nr_ick > 1) {
341 		dev_err(ddata->dev, "max one fck and ick for %pOF\n", np);
342 
343 		return -EINVAL;
344 	}
345 
346 	ddata->clocks = devm_kcalloc(ddata->dev,
347 				     ddata->nr_clocks, sizeof(*ddata->clocks),
348 				     GFP_KERNEL);
349 	if (!ddata->clocks)
350 		return -ENOMEM;
351 
352 	for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
353 		const char *name = ddata->clock_roles[i];
354 
355 		if (!name)
356 			continue;
357 
358 		error = sysc_get_one_clock(ddata, name);
359 		if (error)
360 			return error;
361 	}
362 
363 	return 0;
364 }
365 
366 static int sysc_enable_main_clocks(struct sysc *ddata)
367 {
368 	struct clk *clock;
369 	int i, error;
370 
371 	if (!ddata->clocks)
372 		return 0;
373 
374 	for (i = 0; i < SYSC_OPTFCK0; i++) {
375 		clock = ddata->clocks[i];
376 
377 		/* Main clocks may not have ick */
378 		if (IS_ERR_OR_NULL(clock))
379 			continue;
380 
381 		error = clk_enable(clock);
382 		if (error)
383 			goto err_disable;
384 	}
385 
386 	return 0;
387 
388 err_disable:
389 	for (i--; i >= 0; i--) {
390 		clock = ddata->clocks[i];
391 
392 		/* Main clocks may not have ick */
393 		if (IS_ERR_OR_NULL(clock))
394 			continue;
395 
396 		clk_disable(clock);
397 	}
398 
399 	return error;
400 }
401 
402 static void sysc_disable_main_clocks(struct sysc *ddata)
403 {
404 	struct clk *clock;
405 	int i;
406 
407 	if (!ddata->clocks)
408 		return;
409 
410 	for (i = 0; i < SYSC_OPTFCK0; i++) {
411 		clock = ddata->clocks[i];
412 		if (IS_ERR_OR_NULL(clock))
413 			continue;
414 
415 		clk_disable(clock);
416 	}
417 }
418 
419 static int sysc_enable_opt_clocks(struct sysc *ddata)
420 {
421 	struct clk *clock;
422 	int i, error;
423 
424 	if (!ddata->clocks)
425 		return 0;
426 
427 	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
428 		clock = ddata->clocks[i];
429 
430 		/* Assume no holes for opt clocks */
431 		if (IS_ERR_OR_NULL(clock))
432 			return 0;
433 
434 		error = clk_enable(clock);
435 		if (error)
436 			goto err_disable;
437 	}
438 
439 	return 0;
440 
441 err_disable:
442 	for (i--; i >= 0; i--) {
443 		clock = ddata->clocks[i];
444 		if (IS_ERR_OR_NULL(clock))
445 			continue;
446 
447 		clk_disable(clock);
448 	}
449 
450 	return error;
451 }
452 
453 static void sysc_disable_opt_clocks(struct sysc *ddata)
454 {
455 	struct clk *clock;
456 	int i;
457 
458 	if (!ddata->clocks)
459 		return;
460 
461 	for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
462 		clock = ddata->clocks[i];
463 
464 		/* Assume no holes for opt clocks */
465 		if (IS_ERR_OR_NULL(clock))
466 			return;
467 
468 		clk_disable(clock);
469 	}
470 }
471 
472 static void sysc_clkdm_deny_idle(struct sysc *ddata)
473 {
474 	struct ti_sysc_platform_data *pdata;
475 
476 	if (ddata->legacy_mode)
477 		return;
478 
479 	pdata = dev_get_platdata(ddata->dev);
480 	if (pdata && pdata->clkdm_deny_idle)
481 		pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
482 }
483 
484 static void sysc_clkdm_allow_idle(struct sysc *ddata)
485 {
486 	struct ti_sysc_platform_data *pdata;
487 
488 	if (ddata->legacy_mode)
489 		return;
490 
491 	pdata = dev_get_platdata(ddata->dev);
492 	if (pdata && pdata->clkdm_allow_idle)
493 		pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
494 }
495 
496 /**
497  * sysc_init_resets - init rstctrl reset line if configured
498  * @ddata: device driver data
499  *
500  * See sysc_rstctrl_reset_deassert().
501  */
502 static int sysc_init_resets(struct sysc *ddata)
503 {
504 	ddata->rsts =
505 		devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
506 	if (IS_ERR(ddata->rsts))
507 		return PTR_ERR(ddata->rsts);
508 
509 	return 0;
510 }
511 
512 /**
513  * sysc_parse_and_check_child_range - parses module IO region from ranges
514  * @ddata: device driver data
515  *
516  * In general we only need rev, syss, and sysc registers and not the whole
517  * module range. But we do want the offsets for these registers from the
518  * module base. This allows us to check them against the legacy hwmod
519  * platform data. Let's also check the ranges are configured properly.
520  */
521 static int sysc_parse_and_check_child_range(struct sysc *ddata)
522 {
523 	struct device_node *np = ddata->dev->of_node;
524 	const __be32 *ranges;
525 	u32 nr_addr, nr_size;
526 	int len, error;
527 
528 	ranges = of_get_property(np, "ranges", &len);
529 	if (!ranges) {
530 		dev_err(ddata->dev, "missing ranges for %pOF\n", np);
531 
532 		return -ENOENT;
533 	}
534 
535 	len /= sizeof(*ranges);
536 
537 	if (len < 3) {
538 		dev_err(ddata->dev, "incomplete ranges for %pOF\n", np);
539 
540 		return -EINVAL;
541 	}
542 
543 	error = of_property_read_u32(np, "#address-cells", &nr_addr);
544 	if (error)
545 		return -ENOENT;
546 
547 	error = of_property_read_u32(np, "#size-cells", &nr_size);
548 	if (error)
549 		return -ENOENT;
550 
551 	if (nr_addr != 1 || nr_size != 1) {
552 		dev_err(ddata->dev, "invalid ranges for %pOF\n", np);
553 
554 		return -EINVAL;
555 	}
556 
557 	ranges++;
558 	ddata->module_pa = of_translate_address(np, ranges++);
559 	ddata->module_size = be32_to_cpup(ranges);
560 
561 	return 0;
562 }
563 
564 static struct device_node *stdout_path;
565 
566 static void sysc_init_stdout_path(struct sysc *ddata)
567 {
568 	struct device_node *np = NULL;
569 	const char *uart;
570 
571 	if (IS_ERR(stdout_path))
572 		return;
573 
574 	if (stdout_path)
575 		return;
576 
577 	np = of_find_node_by_path("/chosen");
578 	if (!np)
579 		goto err;
580 
581 	uart = of_get_property(np, "stdout-path", NULL);
582 	if (!uart)
583 		goto err;
584 
585 	np = of_find_node_by_path(uart);
586 	if (!np)
587 		goto err;
588 
589 	stdout_path = np;
590 
591 	return;
592 
593 err:
594 	stdout_path = ERR_PTR(-ENODEV);
595 }
596 
597 static void sysc_check_quirk_stdout(struct sysc *ddata,
598 				    struct device_node *np)
599 {
600 	sysc_init_stdout_path(ddata);
601 	if (np != stdout_path)
602 		return;
603 
604 	ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT |
605 				SYSC_QUIRK_NO_RESET_ON_INIT;
606 }
607 
608 /**
609  * sysc_check_one_child - check child configuration
610  * @ddata: device driver data
611  * @np: child device node
612  *
613  * Let's avoid messy situations where we have new interconnect target
614  * node but children have "ti,hwmods". These belong to the interconnect
615  * target node and are managed by this driver.
616  */
617 static void sysc_check_one_child(struct sysc *ddata,
618 				 struct device_node *np)
619 {
620 	const char *name;
621 
622 	name = of_get_property(np, "ti,hwmods", NULL);
623 	if (name)
624 		dev_warn(ddata->dev, "really a child ti,hwmods property?");
625 
626 	sysc_check_quirk_stdout(ddata, np);
627 	sysc_parse_dts_quirks(ddata, np, true);
628 }
629 
630 static void sysc_check_children(struct sysc *ddata)
631 {
632 	struct device_node *child;
633 
634 	for_each_child_of_node(ddata->dev->of_node, child)
635 		sysc_check_one_child(ddata, child);
636 }
637 
638 /*
639  * So far only I2C uses 16-bit read access with clockactivity with revision
640  * in two registers with stride of 4. We can detect this based on the rev
641  * register size to configure things far enough to be able to properly read
642  * the revision register.
643  */
644 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res)
645 {
646 	if (resource_size(res) == 8)
647 		ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT;
648 }
649 
650 /**
651  * sysc_parse_one - parses the interconnect target module registers
652  * @ddata: device driver data
653  * @reg: register to parse
654  */
655 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg)
656 {
657 	struct resource *res;
658 	const char *name;
659 
660 	switch (reg) {
661 	case SYSC_REVISION:
662 	case SYSC_SYSCONFIG:
663 	case SYSC_SYSSTATUS:
664 		name = reg_names[reg];
665 		break;
666 	default:
667 		return -EINVAL;
668 	}
669 
670 	res = platform_get_resource_byname(to_platform_device(ddata->dev),
671 					   IORESOURCE_MEM, name);
672 	if (!res) {
673 		ddata->offsets[reg] = -ENODEV;
674 
675 		return 0;
676 	}
677 
678 	ddata->offsets[reg] = res->start - ddata->module_pa;
679 	if (reg == SYSC_REVISION)
680 		sysc_check_quirk_16bit(ddata, res);
681 
682 	return 0;
683 }
684 
685 static int sysc_parse_registers(struct sysc *ddata)
686 {
687 	int i, error;
688 
689 	for (i = 0; i < SYSC_MAX_REGS; i++) {
690 		error = sysc_parse_one(ddata, i);
691 		if (error)
692 			return error;
693 	}
694 
695 	return 0;
696 }
697 
698 /**
699  * sysc_check_registers - check for misconfigured register overlaps
700  * @ddata: device driver data
701  */
702 static int sysc_check_registers(struct sysc *ddata)
703 {
704 	int i, j, nr_regs = 0, nr_matches = 0;
705 
706 	for (i = 0; i < SYSC_MAX_REGS; i++) {
707 		if (ddata->offsets[i] < 0)
708 			continue;
709 
710 		if (ddata->offsets[i] > (ddata->module_size - 4)) {
711 			dev_err(ddata->dev, "register outside module range");
712 
713 				return -EINVAL;
714 		}
715 
716 		for (j = 0; j < SYSC_MAX_REGS; j++) {
717 			if (ddata->offsets[j] < 0)
718 				continue;
719 
720 			if (ddata->offsets[i] == ddata->offsets[j])
721 				nr_matches++;
722 		}
723 		nr_regs++;
724 	}
725 
726 	if (nr_matches > nr_regs) {
727 		dev_err(ddata->dev, "overlapping registers: (%i/%i)",
728 			nr_regs, nr_matches);
729 
730 		return -EINVAL;
731 	}
732 
733 	return 0;
734 }
735 
736 /**
737  * syc_ioremap - ioremap register space for the interconnect target module
738  * @ddata: device driver data
739  *
740  * Note that the interconnect target module registers can be anywhere
741  * within the interconnect target module range. For example, SGX has
742  * them at offset 0x1fc00 in the 32MB module address space. And cpsw
743  * has them at offset 0x1200 in the CPSW_WR child. Usually the
744  * the interconnect target module registers are at the beginning of
745  * the module range though.
746  */
747 static int sysc_ioremap(struct sysc *ddata)
748 {
749 	int size;
750 
751 	if (ddata->offsets[SYSC_REVISION] < 0 &&
752 	    ddata->offsets[SYSC_SYSCONFIG] < 0 &&
753 	    ddata->offsets[SYSC_SYSSTATUS] < 0) {
754 		size = ddata->module_size;
755 	} else {
756 		size = max3(ddata->offsets[SYSC_REVISION],
757 			    ddata->offsets[SYSC_SYSCONFIG],
758 			    ddata->offsets[SYSC_SYSSTATUS]);
759 
760 		if (size < SZ_1K)
761 			size = SZ_1K;
762 
763 		if ((size + sizeof(u32)) > ddata->module_size)
764 			size = ddata->module_size;
765 	}
766 
767 	ddata->module_va = devm_ioremap(ddata->dev,
768 					ddata->module_pa,
769 					size + sizeof(u32));
770 	if (!ddata->module_va)
771 		return -EIO;
772 
773 	return 0;
774 }
775 
776 /**
777  * sysc_map_and_check_registers - ioremap and check device registers
778  * @ddata: device driver data
779  */
780 static int sysc_map_and_check_registers(struct sysc *ddata)
781 {
782 	int error;
783 
784 	error = sysc_parse_and_check_child_range(ddata);
785 	if (error)
786 		return error;
787 
788 	sysc_check_children(ddata);
789 
790 	error = sysc_parse_registers(ddata);
791 	if (error)
792 		return error;
793 
794 	error = sysc_ioremap(ddata);
795 	if (error)
796 		return error;
797 
798 	error = sysc_check_registers(ddata);
799 	if (error)
800 		return error;
801 
802 	return 0;
803 }
804 
805 /**
806  * sysc_show_rev - read and show interconnect target module revision
807  * @bufp: buffer to print the information to
808  * @ddata: device driver data
809  */
810 static int sysc_show_rev(char *bufp, struct sysc *ddata)
811 {
812 	int len;
813 
814 	if (ddata->offsets[SYSC_REVISION] < 0)
815 		return sprintf(bufp, ":NA");
816 
817 	len = sprintf(bufp, ":%08x", ddata->revision);
818 
819 	return len;
820 }
821 
822 static int sysc_show_reg(struct sysc *ddata,
823 			 char *bufp, enum sysc_registers reg)
824 {
825 	if (ddata->offsets[reg] < 0)
826 		return sprintf(bufp, ":NA");
827 
828 	return sprintf(bufp, ":%x", ddata->offsets[reg]);
829 }
830 
831 static int sysc_show_name(char *bufp, struct sysc *ddata)
832 {
833 	if (!ddata->name)
834 		return 0;
835 
836 	return sprintf(bufp, ":%s", ddata->name);
837 }
838 
839 /**
840  * sysc_show_registers - show information about interconnect target module
841  * @ddata: device driver data
842  */
843 static void sysc_show_registers(struct sysc *ddata)
844 {
845 	char buf[128];
846 	char *bufp = buf;
847 	int i;
848 
849 	for (i = 0; i < SYSC_MAX_REGS; i++)
850 		bufp += sysc_show_reg(ddata, bufp, i);
851 
852 	bufp += sysc_show_rev(bufp, ddata);
853 	bufp += sysc_show_name(bufp, ddata);
854 
855 	dev_dbg(ddata->dev, "%llx:%x%s\n",
856 		ddata->module_pa, ddata->module_size,
857 		buf);
858 }
859 
860 #define SYSC_IDLE_MASK	(SYSC_NR_IDLEMODES - 1)
861 #define SYSC_CLOCACT_ICK	2
862 
863 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
864 static int sysc_enable_module(struct device *dev)
865 {
866 	struct sysc *ddata;
867 	const struct sysc_regbits *regbits;
868 	u32 reg, idlemodes, best_mode;
869 
870 	ddata = dev_get_drvdata(dev);
871 	if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
872 		return 0;
873 
874 	regbits = ddata->cap->regbits;
875 	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
876 
877 	/* Set CLOCKACTIVITY, we only use it for ick */
878 	if (regbits->clkact_shift >= 0 &&
879 	    (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
880 	     ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
881 		reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
882 
883 	/* Set SIDLE mode */
884 	idlemodes = ddata->cfg.sidlemodes;
885 	if (!idlemodes || regbits->sidle_shift < 0)
886 		goto set_midle;
887 
888 	if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE |
889 				 SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
890 		best_mode = SYSC_IDLE_NO;
891 	} else {
892 		best_mode = fls(ddata->cfg.sidlemodes) - 1;
893 		if (best_mode > SYSC_IDLE_MASK) {
894 			dev_err(dev, "%s: invalid sidlemode\n", __func__);
895 			return -EINVAL;
896 		}
897 
898 		/* Set WAKEUP */
899 		if (regbits->enwkup_shift >= 0 &&
900 		    ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
901 			reg |= BIT(regbits->enwkup_shift);
902 	}
903 
904 	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
905 	reg |= best_mode << regbits->sidle_shift;
906 	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
907 
908 set_midle:
909 	/* Set MIDLE mode */
910 	idlemodes = ddata->cfg.midlemodes;
911 	if (!idlemodes || regbits->midle_shift < 0)
912 		goto set_autoidle;
913 
914 	best_mode = fls(ddata->cfg.midlemodes) - 1;
915 	if (best_mode > SYSC_IDLE_MASK) {
916 		dev_err(dev, "%s: invalid midlemode\n", __func__);
917 		return -EINVAL;
918 	}
919 
920 	reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
921 	reg |= best_mode << regbits->midle_shift;
922 	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
923 
924 set_autoidle:
925 	/* Autoidle bit must enabled separately if available */
926 	if (regbits->autoidle_shift >= 0 &&
927 	    ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
928 		reg |= 1 << regbits->autoidle_shift;
929 		sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
930 	}
931 
932 	if (ddata->module_enable_quirk)
933 		ddata->module_enable_quirk(ddata);
934 
935 	return 0;
936 }
937 
938 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
939 {
940 	if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
941 		*best_mode = SYSC_IDLE_SMART_WKUP;
942 	else if (idlemodes & BIT(SYSC_IDLE_SMART))
943 		*best_mode = SYSC_IDLE_SMART;
944 	else if (idlemodes & BIT(SYSC_IDLE_FORCE))
945 		*best_mode = SYSC_IDLE_FORCE;
946 	else
947 		return -EINVAL;
948 
949 	return 0;
950 }
951 
952 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
953 static int sysc_disable_module(struct device *dev)
954 {
955 	struct sysc *ddata;
956 	const struct sysc_regbits *regbits;
957 	u32 reg, idlemodes, best_mode;
958 	int ret;
959 
960 	ddata = dev_get_drvdata(dev);
961 	if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
962 		return 0;
963 
964 	if (ddata->module_disable_quirk)
965 		ddata->module_disable_quirk(ddata);
966 
967 	regbits = ddata->cap->regbits;
968 	reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
969 
970 	/* Set MIDLE mode */
971 	idlemodes = ddata->cfg.midlemodes;
972 	if (!idlemodes || regbits->midle_shift < 0)
973 		goto set_sidle;
974 
975 	ret = sysc_best_idle_mode(idlemodes, &best_mode);
976 	if (ret) {
977 		dev_err(dev, "%s: invalid midlemode\n", __func__);
978 		return ret;
979 	}
980 
981 	reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
982 	reg |= best_mode << regbits->midle_shift;
983 	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
984 
985 set_sidle:
986 	/* Set SIDLE mode */
987 	idlemodes = ddata->cfg.sidlemodes;
988 	if (!idlemodes || regbits->sidle_shift < 0)
989 		return 0;
990 
991 	if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
992 		best_mode = SYSC_IDLE_FORCE;
993 	} else {
994 		ret = sysc_best_idle_mode(idlemodes, &best_mode);
995 		if (ret) {
996 			dev_err(dev, "%s: invalid sidlemode\n", __func__);
997 			return ret;
998 		}
999 	}
1000 
1001 	reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
1002 	reg |= best_mode << regbits->sidle_shift;
1003 	if (regbits->autoidle_shift >= 0 &&
1004 	    ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
1005 		reg |= 1 << regbits->autoidle_shift;
1006 	sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
1007 
1008 	return 0;
1009 }
1010 
1011 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
1012 						      struct sysc *ddata)
1013 {
1014 	struct ti_sysc_platform_data *pdata;
1015 	int error;
1016 
1017 	pdata = dev_get_platdata(ddata->dev);
1018 	if (!pdata)
1019 		return 0;
1020 
1021 	if (!pdata->idle_module)
1022 		return -ENODEV;
1023 
1024 	error = pdata->idle_module(dev, &ddata->cookie);
1025 	if (error)
1026 		dev_err(dev, "%s: could not idle: %i\n",
1027 			__func__, error);
1028 
1029 	reset_control_assert(ddata->rsts);
1030 
1031 	return 0;
1032 }
1033 
1034 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
1035 						     struct sysc *ddata)
1036 {
1037 	struct ti_sysc_platform_data *pdata;
1038 	int error;
1039 
1040 	reset_control_deassert(ddata->rsts);
1041 
1042 	pdata = dev_get_platdata(ddata->dev);
1043 	if (!pdata)
1044 		return 0;
1045 
1046 	if (!pdata->enable_module)
1047 		return -ENODEV;
1048 
1049 	error = pdata->enable_module(dev, &ddata->cookie);
1050 	if (error)
1051 		dev_err(dev, "%s: could not enable: %i\n",
1052 			__func__, error);
1053 
1054 	return 0;
1055 }
1056 
1057 static int __maybe_unused sysc_runtime_suspend(struct device *dev)
1058 {
1059 	struct sysc *ddata;
1060 	int error = 0;
1061 
1062 	ddata = dev_get_drvdata(dev);
1063 
1064 	if (!ddata->enabled)
1065 		return 0;
1066 
1067 	sysc_clkdm_deny_idle(ddata);
1068 
1069 	if (ddata->legacy_mode) {
1070 		error = sysc_runtime_suspend_legacy(dev, ddata);
1071 		if (error)
1072 			goto err_allow_idle;
1073 	} else {
1074 		error = sysc_disable_module(dev);
1075 		if (error)
1076 			goto err_allow_idle;
1077 	}
1078 
1079 	sysc_disable_main_clocks(ddata);
1080 
1081 	if (sysc_opt_clks_needed(ddata))
1082 		sysc_disable_opt_clocks(ddata);
1083 
1084 	ddata->enabled = false;
1085 
1086 err_allow_idle:
1087 	reset_control_assert(ddata->rsts);
1088 
1089 	sysc_clkdm_allow_idle(ddata);
1090 
1091 	return error;
1092 }
1093 
1094 static int __maybe_unused sysc_runtime_resume(struct device *dev)
1095 {
1096 	struct sysc *ddata;
1097 	int error = 0;
1098 
1099 	ddata = dev_get_drvdata(dev);
1100 
1101 	if (ddata->enabled)
1102 		return 0;
1103 
1104 
1105 	sysc_clkdm_deny_idle(ddata);
1106 
1107 	reset_control_deassert(ddata->rsts);
1108 
1109 	if (sysc_opt_clks_needed(ddata)) {
1110 		error = sysc_enable_opt_clocks(ddata);
1111 		if (error)
1112 			goto err_allow_idle;
1113 	}
1114 
1115 	error = sysc_enable_main_clocks(ddata);
1116 	if (error)
1117 		goto err_opt_clocks;
1118 
1119 	if (ddata->legacy_mode) {
1120 		error = sysc_runtime_resume_legacy(dev, ddata);
1121 		if (error)
1122 			goto err_main_clocks;
1123 	} else {
1124 		error = sysc_enable_module(dev);
1125 		if (error)
1126 			goto err_main_clocks;
1127 	}
1128 
1129 	ddata->enabled = true;
1130 
1131 	sysc_clkdm_allow_idle(ddata);
1132 
1133 	return 0;
1134 
1135 err_main_clocks:
1136 	sysc_disable_main_clocks(ddata);
1137 err_opt_clocks:
1138 	if (sysc_opt_clks_needed(ddata))
1139 		sysc_disable_opt_clocks(ddata);
1140 err_allow_idle:
1141 	sysc_clkdm_allow_idle(ddata);
1142 
1143 	return error;
1144 }
1145 
1146 static int __maybe_unused sysc_noirq_suspend(struct device *dev)
1147 {
1148 	struct sysc *ddata;
1149 
1150 	ddata = dev_get_drvdata(dev);
1151 
1152 	if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1153 		return 0;
1154 
1155 	return pm_runtime_force_suspend(dev);
1156 }
1157 
1158 static int __maybe_unused sysc_noirq_resume(struct device *dev)
1159 {
1160 	struct sysc *ddata;
1161 
1162 	ddata = dev_get_drvdata(dev);
1163 
1164 	if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1165 		return 0;
1166 
1167 	return pm_runtime_force_resume(dev);
1168 }
1169 
1170 static const struct dev_pm_ops sysc_pm_ops = {
1171 	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
1172 	SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
1173 			   sysc_runtime_resume,
1174 			   NULL)
1175 };
1176 
1177 /* Module revision register based quirks */
1178 struct sysc_revision_quirk {
1179 	const char *name;
1180 	u32 base;
1181 	int rev_offset;
1182 	int sysc_offset;
1183 	int syss_offset;
1184 	u32 revision;
1185 	u32 revision_mask;
1186 	u32 quirks;
1187 };
1188 
1189 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss,		\
1190 		   optrev_val, optrevmask, optquirkmask)		\
1191 	{								\
1192 		.name = (optname),					\
1193 		.base = (optbase),					\
1194 		.rev_offset = (optrev),					\
1195 		.sysc_offset = (optsysc),				\
1196 		.syss_offset = (optsyss),				\
1197 		.revision = (optrev_val),				\
1198 		.revision_mask = (optrevmask),				\
1199 		.quirks = (optquirkmask),				\
1200 	}
1201 
1202 static const struct sysc_revision_quirk sysc_revision_quirks[] = {
1203 	/* These drivers need to be fixed to not use pm_runtime_irq_safe() */
1204 	SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
1205 		   SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET),
1206 	SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
1207 		   SYSC_QUIRK_LEGACY_IDLE),
1208 	SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
1209 		   SYSC_QUIRK_LEGACY_IDLE),
1210 	SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
1211 		   SYSC_QUIRK_LEGACY_IDLE),
1212 	SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
1213 		   SYSC_QUIRK_LEGACY_IDLE),
1214 	SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
1215 		   SYSC_QUIRK_LEGACY_IDLE),
1216 	SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
1217 		   0),
1218 	/* Some timers on omap4 and later */
1219 	SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff,
1220 		   0),
1221 	SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff,
1222 		   0),
1223 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
1224 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1225 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
1226 		   SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1227 	/* Uarts on omap4 and later */
1228 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1229 		   SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1230 	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1231 		   SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE),
1232 
1233 	/* Quirks that need to be set based on the module address */
1234 	SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff,
1235 		   SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT |
1236 		   SYSC_QUIRK_SWSUP_SIDLE),
1237 
1238 	/* Quirks that need to be set based on detected module */
1239 	SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
1240 		   SYSC_MODULE_QUIRK_HDQ1W),
1241 	SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
1242 		   SYSC_MODULE_QUIRK_HDQ1W),
1243 	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
1244 		   SYSC_MODULE_QUIRK_I2C),
1245 	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
1246 		   SYSC_MODULE_QUIRK_I2C),
1247 	SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
1248 		   SYSC_MODULE_QUIRK_I2C),
1249 	SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
1250 		   SYSC_MODULE_QUIRK_I2C),
1251 	SYSC_QUIRK("gpu", 0x50000000, 0x14, -1, -1, 0x00010201, 0xffffffff, 0),
1252 	SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff,
1253 		   SYSC_MODULE_QUIRK_SGX),
1254 	SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1255 		   SYSC_MODULE_QUIRK_WDT),
1256 	/* Watchdog on am3 and am4 */
1257 	SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
1258 		   SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE),
1259 
1260 #ifdef DEBUG
1261 	SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0),
1262 	SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0),
1263 	SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
1264 	SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0),
1265 	SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1266 	SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
1267 		   0xffff00f0, 0),
1268 	SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
1269 	SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
1270 	SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
1271 	SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
1272 	SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1273 	SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
1274 	SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
1275 	SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
1276 	SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -1, 0x40000000 , 0xffffffff, 0),
1277 	SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
1278 	SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
1279 	SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0),
1280 	SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
1281 	SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0),
1282 	SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
1283 	SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0),
1284 	SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
1285 	SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
1286 	SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0),
1287 	SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
1288 	SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0),
1289 	SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0),
1290 	SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0),
1291 	SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0),
1292 	SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0),
1293 	SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0),
1294 	SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
1295 	SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0),
1296 	SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0),
1297 	SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0),
1298 	SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0),
1299 	SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0),
1300 	SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
1301 	SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
1302 	SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
1303 	SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
1304 	SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
1305 	SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0),
1306 	SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0),
1307 	SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0),
1308 	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
1309 	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
1310 	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
1311 	SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0),
1312 	SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
1313 		   0xffffffff, 0),
1314 	SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0),
1315 #endif
1316 };
1317 
1318 /*
1319  * Early quirks based on module base and register offsets only that are
1320  * needed before the module revision can be read
1321  */
1322 static void sysc_init_early_quirks(struct sysc *ddata)
1323 {
1324 	const struct sysc_revision_quirk *q;
1325 	int i;
1326 
1327 	for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1328 		q = &sysc_revision_quirks[i];
1329 
1330 		if (!q->base)
1331 			continue;
1332 
1333 		if (q->base != ddata->module_pa)
1334 			continue;
1335 
1336 		if (q->rev_offset >= 0 &&
1337 		    q->rev_offset != ddata->offsets[SYSC_REVISION])
1338 			continue;
1339 
1340 		if (q->sysc_offset >= 0 &&
1341 		    q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1342 			continue;
1343 
1344 		if (q->syss_offset >= 0 &&
1345 		    q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1346 			continue;
1347 
1348 		ddata->name = q->name;
1349 		ddata->cfg.quirks |= q->quirks;
1350 	}
1351 }
1352 
1353 /* Quirks that also consider the revision register value */
1354 static void sysc_init_revision_quirks(struct sysc *ddata)
1355 {
1356 	const struct sysc_revision_quirk *q;
1357 	int i;
1358 
1359 	for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
1360 		q = &sysc_revision_quirks[i];
1361 
1362 		if (q->base && q->base != ddata->module_pa)
1363 			continue;
1364 
1365 		if (q->rev_offset >= 0 &&
1366 		    q->rev_offset != ddata->offsets[SYSC_REVISION])
1367 			continue;
1368 
1369 		if (q->sysc_offset >= 0 &&
1370 		    q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
1371 			continue;
1372 
1373 		if (q->syss_offset >= 0 &&
1374 		    q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
1375 			continue;
1376 
1377 		if (q->revision == ddata->revision ||
1378 		    (q->revision & q->revision_mask) ==
1379 		    (ddata->revision & q->revision_mask)) {
1380 			ddata->name = q->name;
1381 			ddata->cfg.quirks |= q->quirks;
1382 		}
1383 	}
1384 }
1385 
1386 /* 1-wire needs module's internal clocks enabled for reset */
1387 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata)
1388 {
1389 	int offset = 0x0c;	/* HDQ_CTRL_STATUS */
1390 	u16 val;
1391 
1392 	val = sysc_read(ddata, offset);
1393 	val |= BIT(5);
1394 	sysc_write(ddata, offset, val);
1395 }
1396 
1397 /* I2C needs extra enable bit toggling for reset */
1398 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
1399 {
1400 	int offset;
1401 	u16 val;
1402 
1403 	/* I2C_CON, omap2/3 is different from omap4 and later */
1404 	if ((ddata->revision & 0xffffff00) == 0x001f0000)
1405 		offset = 0x24;
1406 	else
1407 		offset = 0xa4;
1408 
1409 	/* I2C_EN */
1410 	val = sysc_read(ddata, offset);
1411 	if (enable)
1412 		val |= BIT(15);
1413 	else
1414 		val &= ~BIT(15);
1415 	sysc_write(ddata, offset, val);
1416 }
1417 
1418 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata)
1419 {
1420 	sysc_clk_quirk_i2c(ddata, true);
1421 }
1422 
1423 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata)
1424 {
1425 	sysc_clk_quirk_i2c(ddata, false);
1426 }
1427 
1428 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
1429 static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
1430 {
1431 	int offset = 0xff08;	/* OCP_DEBUG_CONFIG */
1432 	u32 val = BIT(31);	/* THALIA_INT_BYPASS */
1433 
1434 	sysc_write(ddata, offset, val);
1435 }
1436 
1437 /* Watchdog timer needs a disable sequence after reset */
1438 static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
1439 {
1440 	int wps, spr, error;
1441 	u32 val;
1442 
1443 	wps = 0x34;
1444 	spr = 0x48;
1445 
1446 	sysc_write(ddata, spr, 0xaaaa);
1447 	error = readl_poll_timeout(ddata->module_va + wps, val,
1448 				   !(val & 0x10), 100,
1449 				   MAX_MODULE_SOFTRESET_WAIT);
1450 	if (error)
1451 		dev_warn(ddata->dev, "wdt disable step1 failed\n");
1452 
1453 	sysc_write(ddata, spr, 0x5555);
1454 	error = readl_poll_timeout(ddata->module_va + wps, val,
1455 				   !(val & 0x10), 100,
1456 				   MAX_MODULE_SOFTRESET_WAIT);
1457 	if (error)
1458 		dev_warn(ddata->dev, "wdt disable step2 failed\n");
1459 }
1460 
1461 static void sysc_init_module_quirks(struct sysc *ddata)
1462 {
1463 	if (ddata->legacy_mode || !ddata->name)
1464 		return;
1465 
1466 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
1467 		ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w;
1468 
1469 		return;
1470 	}
1471 
1472 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
1473 		ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c;
1474 		ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c;
1475 
1476 		return;
1477 	}
1478 
1479 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
1480 		ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
1481 
1482 	if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
1483 		ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
1484 		ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
1485 	}
1486 }
1487 
1488 static int sysc_clockdomain_init(struct sysc *ddata)
1489 {
1490 	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1491 	struct clk *fck = NULL, *ick = NULL;
1492 	int error;
1493 
1494 	if (!pdata || !pdata->init_clockdomain)
1495 		return 0;
1496 
1497 	switch (ddata->nr_clocks) {
1498 	case 2:
1499 		ick = ddata->clocks[SYSC_ICK];
1500 		/* fallthrough */
1501 	case 1:
1502 		fck = ddata->clocks[SYSC_FCK];
1503 		break;
1504 	case 0:
1505 		return 0;
1506 	}
1507 
1508 	error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
1509 	if (!error || error == -ENODEV)
1510 		return 0;
1511 
1512 	return error;
1513 }
1514 
1515 /*
1516  * Note that pdata->init_module() typically does a reset first. After
1517  * pdata->init_module() is done, PM runtime can be used for the interconnect
1518  * target module.
1519  */
1520 static int sysc_legacy_init(struct sysc *ddata)
1521 {
1522 	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1523 	int error;
1524 
1525 	if (!pdata || !pdata->init_module)
1526 		return 0;
1527 
1528 	error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
1529 	if (error == -EEXIST)
1530 		error = 0;
1531 
1532 	return error;
1533 }
1534 
1535 /**
1536  * sysc_rstctrl_reset_deassert - deassert rstctrl reset
1537  * @ddata: device driver data
1538  * @reset: reset before deassert
1539  *
1540  * A module can have both OCP softreset control and external rstctrl.
1541  * If more complicated rstctrl resets are needed, please handle these
1542  * directly from the child device driver and map only the module reset
1543  * for the parent interconnect target module device.
1544  *
1545  * Automatic reset of the module on init can be skipped with the
1546  * "ti,no-reset-on-init" device tree property.
1547  */
1548 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset)
1549 {
1550 	int error;
1551 
1552 	if (!ddata->rsts)
1553 		return 0;
1554 
1555 	if (reset) {
1556 		error = reset_control_assert(ddata->rsts);
1557 		if (error)
1558 			return error;
1559 	}
1560 
1561 	reset_control_deassert(ddata->rsts);
1562 
1563 	return 0;
1564 }
1565 
1566 /*
1567  * Note that the caller must ensure the interconnect target module is enabled
1568  * before calling reset. Otherwise reset will not complete.
1569  */
1570 static int sysc_reset(struct sysc *ddata)
1571 {
1572 	int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1573 	u32 sysc_mask, syss_done;
1574 
1575 	sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1576 	syss_offset = ddata->offsets[SYSC_SYSSTATUS];
1577 
1578 	if (ddata->legacy_mode || sysc_offset < 0 ||
1579 	    ddata->cap->regbits->srst_shift < 0 ||
1580 	    ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
1581 		return 0;
1582 
1583 	sysc_mask = BIT(ddata->cap->regbits->srst_shift);
1584 
1585 	if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1586 		syss_done = 0;
1587 	else
1588 		syss_done = ddata->cfg.syss_mask;
1589 
1590 	if (ddata->clk_disable_quirk)
1591 		ddata->clk_disable_quirk(ddata);
1592 
1593 	sysc_val = sysc_read_sysconfig(ddata);
1594 	sysc_val |= sysc_mask;
1595 	sysc_write(ddata, sysc_offset, sysc_val);
1596 
1597 	if (ddata->clk_enable_quirk)
1598 		ddata->clk_enable_quirk(ddata);
1599 
1600 	/* Poll on reset status */
1601 	if (syss_offset >= 0) {
1602 		error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1603 					   (rstval & ddata->cfg.syss_mask) ==
1604 					   syss_done,
1605 					   100, MAX_MODULE_SOFTRESET_WAIT);
1606 
1607 	} else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1608 		error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1609 					   !(rstval & sysc_mask),
1610 					   100, MAX_MODULE_SOFTRESET_WAIT);
1611 	}
1612 
1613 	if (ddata->reset_done_quirk)
1614 		ddata->reset_done_quirk(ddata);
1615 
1616 	return error;
1617 }
1618 
1619 /*
1620  * At this point the module is configured enough to read the revision but
1621  * module may not be completely configured yet to use PM runtime. Enable
1622  * all clocks directly during init to configure the quirks needed for PM
1623  * runtime based on the revision register.
1624  */
1625 static int sysc_init_module(struct sysc *ddata)
1626 {
1627 	int error = 0;
1628 	bool manage_clocks = true;
1629 
1630 	error = sysc_rstctrl_reset_deassert(ddata, false);
1631 	if (error)
1632 		return error;
1633 
1634 	if (ddata->cfg.quirks &
1635 	    (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))
1636 		manage_clocks = false;
1637 
1638 	error = sysc_clockdomain_init(ddata);
1639 	if (error)
1640 		return error;
1641 
1642 	sysc_clkdm_deny_idle(ddata);
1643 
1644 	/*
1645 	 * Always enable clocks. The bootloader may or may not have enabled
1646 	 * the related clocks.
1647 	 */
1648 	error = sysc_enable_opt_clocks(ddata);
1649 	if (error)
1650 		return error;
1651 
1652 	error = sysc_enable_main_clocks(ddata);
1653 	if (error)
1654 		goto err_opt_clocks;
1655 
1656 	if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
1657 		error = sysc_rstctrl_reset_deassert(ddata, true);
1658 		if (error)
1659 			goto err_main_clocks;
1660 	}
1661 
1662 	ddata->revision = sysc_read_revision(ddata);
1663 	sysc_init_revision_quirks(ddata);
1664 	sysc_init_module_quirks(ddata);
1665 
1666 	if (ddata->legacy_mode) {
1667 		error = sysc_legacy_init(ddata);
1668 		if (error)
1669 			goto err_main_clocks;
1670 	}
1671 
1672 	if (!ddata->legacy_mode) {
1673 		error = sysc_enable_module(ddata->dev);
1674 		if (error)
1675 			goto err_main_clocks;
1676 	}
1677 
1678 	error = sysc_reset(ddata);
1679 	if (error)
1680 		dev_err(ddata->dev, "Reset failed with %d\n", error);
1681 
1682 	if (!ddata->legacy_mode && manage_clocks)
1683 		sysc_disable_module(ddata->dev);
1684 
1685 err_main_clocks:
1686 	if (manage_clocks)
1687 		sysc_disable_main_clocks(ddata);
1688 err_opt_clocks:
1689 	/* No re-enable of clockdomain autoidle to prevent module autoidle */
1690 	if (manage_clocks) {
1691 		sysc_disable_opt_clocks(ddata);
1692 		sysc_clkdm_allow_idle(ddata);
1693 	}
1694 
1695 	return error;
1696 }
1697 
1698 static int sysc_init_sysc_mask(struct sysc *ddata)
1699 {
1700 	struct device_node *np = ddata->dev->of_node;
1701 	int error;
1702 	u32 val;
1703 
1704 	error = of_property_read_u32(np, "ti,sysc-mask", &val);
1705 	if (error)
1706 		return 0;
1707 
1708 	ddata->cfg.sysc_val = val & ddata->cap->sysc_mask;
1709 
1710 	return 0;
1711 }
1712 
1713 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes,
1714 			      const char *name)
1715 {
1716 	struct device_node *np = ddata->dev->of_node;
1717 	struct property *prop;
1718 	const __be32 *p;
1719 	u32 val;
1720 
1721 	of_property_for_each_u32(np, name, prop, p, val) {
1722 		if (val >= SYSC_NR_IDLEMODES) {
1723 			dev_err(ddata->dev, "invalid idlemode: %i\n", val);
1724 			return -EINVAL;
1725 		}
1726 		*idlemodes |=  (1 << val);
1727 	}
1728 
1729 	return 0;
1730 }
1731 
1732 static int sysc_init_idlemodes(struct sysc *ddata)
1733 {
1734 	int error;
1735 
1736 	error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes,
1737 				   "ti,sysc-midle");
1738 	if (error)
1739 		return error;
1740 
1741 	error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes,
1742 				   "ti,sysc-sidle");
1743 	if (error)
1744 		return error;
1745 
1746 	return 0;
1747 }
1748 
1749 /*
1750  * Only some devices on omap4 and later have SYSCONFIG reset done
1751  * bit. We can detect this if there is no SYSSTATUS at all, or the
1752  * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers
1753  * have multiple bits for the child devices like OHCI and EHCI.
1754  * Depends on SYSC being parsed first.
1755  */
1756 static int sysc_init_syss_mask(struct sysc *ddata)
1757 {
1758 	struct device_node *np = ddata->dev->of_node;
1759 	int error;
1760 	u32 val;
1761 
1762 	error = of_property_read_u32(np, "ti,syss-mask", &val);
1763 	if (error) {
1764 		if ((ddata->cap->type == TI_SYSC_OMAP4 ||
1765 		     ddata->cap->type == TI_SYSC_OMAP4_TIMER) &&
1766 		    (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1767 			ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1768 
1769 		return 0;
1770 	}
1771 
1772 	if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET))
1773 		ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS;
1774 
1775 	ddata->cfg.syss_mask = val;
1776 
1777 	return 0;
1778 }
1779 
1780 /*
1781  * Many child device drivers need to have fck and opt clocks available
1782  * to get the clock rate for device internal configuration etc.
1783  */
1784 static int sysc_child_add_named_clock(struct sysc *ddata,
1785 				      struct device *child,
1786 				      const char *name)
1787 {
1788 	struct clk *clk;
1789 	struct clk_lookup *l;
1790 	int error = 0;
1791 
1792 	if (!name)
1793 		return 0;
1794 
1795 	clk = clk_get(child, name);
1796 	if (!IS_ERR(clk)) {
1797 		clk_put(clk);
1798 
1799 		return -EEXIST;
1800 	}
1801 
1802 	clk = clk_get(ddata->dev, name);
1803 	if (IS_ERR(clk))
1804 		return -ENODEV;
1805 
1806 	l = clkdev_create(clk, name, dev_name(child));
1807 	if (!l)
1808 		error = -ENOMEM;
1809 
1810 	clk_put(clk);
1811 
1812 	return error;
1813 }
1814 
1815 static int sysc_child_add_clocks(struct sysc *ddata,
1816 				 struct device *child)
1817 {
1818 	int i, error;
1819 
1820 	for (i = 0; i < ddata->nr_clocks; i++) {
1821 		error = sysc_child_add_named_clock(ddata,
1822 						   child,
1823 						   ddata->clock_roles[i]);
1824 		if (error && error != -EEXIST) {
1825 			dev_err(ddata->dev, "could not add child clock %s: %i\n",
1826 				ddata->clock_roles[i], error);
1827 
1828 			return error;
1829 		}
1830 	}
1831 
1832 	return 0;
1833 }
1834 
1835 static struct device_type sysc_device_type = {
1836 };
1837 
1838 static struct sysc *sysc_child_to_parent(struct device *dev)
1839 {
1840 	struct device *parent = dev->parent;
1841 
1842 	if (!parent || parent->type != &sysc_device_type)
1843 		return NULL;
1844 
1845 	return dev_get_drvdata(parent);
1846 }
1847 
1848 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev)
1849 {
1850 	struct sysc *ddata;
1851 	int error;
1852 
1853 	ddata = sysc_child_to_parent(dev);
1854 
1855 	error = pm_generic_runtime_suspend(dev);
1856 	if (error)
1857 		return error;
1858 
1859 	if (!ddata->enabled)
1860 		return 0;
1861 
1862 	return sysc_runtime_suspend(ddata->dev);
1863 }
1864 
1865 static int __maybe_unused sysc_child_runtime_resume(struct device *dev)
1866 {
1867 	struct sysc *ddata;
1868 	int error;
1869 
1870 	ddata = sysc_child_to_parent(dev);
1871 
1872 	if (!ddata->enabled) {
1873 		error = sysc_runtime_resume(ddata->dev);
1874 		if (error < 0)
1875 			dev_err(ddata->dev,
1876 				"%s error: %i\n", __func__, error);
1877 	}
1878 
1879 	return pm_generic_runtime_resume(dev);
1880 }
1881 
1882 #ifdef CONFIG_PM_SLEEP
1883 static int sysc_child_suspend_noirq(struct device *dev)
1884 {
1885 	struct sysc *ddata;
1886 	int error;
1887 
1888 	ddata = sysc_child_to_parent(dev);
1889 
1890 	dev_dbg(ddata->dev, "%s %s\n", __func__,
1891 		ddata->name ? ddata->name : "");
1892 
1893 	error = pm_generic_suspend_noirq(dev);
1894 	if (error) {
1895 		dev_err(dev, "%s error at %i: %i\n",
1896 			__func__, __LINE__, error);
1897 
1898 		return error;
1899 	}
1900 
1901 	if (!pm_runtime_status_suspended(dev)) {
1902 		error = pm_generic_runtime_suspend(dev);
1903 		if (error) {
1904 			dev_dbg(dev, "%s busy at %i: %i\n",
1905 				__func__, __LINE__, error);
1906 
1907 			return 0;
1908 		}
1909 
1910 		error = sysc_runtime_suspend(ddata->dev);
1911 		if (error) {
1912 			dev_err(dev, "%s error at %i: %i\n",
1913 				__func__, __LINE__, error);
1914 
1915 			return error;
1916 		}
1917 
1918 		ddata->child_needs_resume = true;
1919 	}
1920 
1921 	return 0;
1922 }
1923 
1924 static int sysc_child_resume_noirq(struct device *dev)
1925 {
1926 	struct sysc *ddata;
1927 	int error;
1928 
1929 	ddata = sysc_child_to_parent(dev);
1930 
1931 	dev_dbg(ddata->dev, "%s %s\n", __func__,
1932 		ddata->name ? ddata->name : "");
1933 
1934 	if (ddata->child_needs_resume) {
1935 		ddata->child_needs_resume = false;
1936 
1937 		error = sysc_runtime_resume(ddata->dev);
1938 		if (error)
1939 			dev_err(ddata->dev,
1940 				"%s runtime resume error: %i\n",
1941 				__func__, error);
1942 
1943 		error = pm_generic_runtime_resume(dev);
1944 		if (error)
1945 			dev_err(ddata->dev,
1946 				"%s generic runtime resume: %i\n",
1947 				__func__, error);
1948 	}
1949 
1950 	return pm_generic_resume_noirq(dev);
1951 }
1952 #endif
1953 
1954 static struct dev_pm_domain sysc_child_pm_domain = {
1955 	.ops = {
1956 		SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1957 				   sysc_child_runtime_resume,
1958 				   NULL)
1959 		USE_PLATFORM_PM_SLEEP_OPS
1960 		SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq,
1961 					      sysc_child_resume_noirq)
1962 	}
1963 };
1964 
1965 /**
1966  * sysc_legacy_idle_quirk - handle children in omap_device compatible way
1967  * @ddata: device driver data
1968  * @child: child device driver
1969  *
1970  * Allow idle for child devices as done with _od_runtime_suspend().
1971  * Otherwise many child devices will not idle because of the permanent
1972  * parent usecount set in pm_runtime_irq_safe().
1973  *
1974  * Note that the long term solution is to just modify the child device
1975  * drivers to not set pm_runtime_irq_safe() and then this can be just
1976  * dropped.
1977  */
1978 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child)
1979 {
1980 	if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1981 		dev_pm_domain_set(child, &sysc_child_pm_domain);
1982 }
1983 
1984 static int sysc_notifier_call(struct notifier_block *nb,
1985 			      unsigned long event, void *device)
1986 {
1987 	struct device *dev = device;
1988 	struct sysc *ddata;
1989 	int error;
1990 
1991 	ddata = sysc_child_to_parent(dev);
1992 	if (!ddata)
1993 		return NOTIFY_DONE;
1994 
1995 	switch (event) {
1996 	case BUS_NOTIFY_ADD_DEVICE:
1997 		error = sysc_child_add_clocks(ddata, dev);
1998 		if (error)
1999 			return error;
2000 		sysc_legacy_idle_quirk(ddata, dev);
2001 		break;
2002 	default:
2003 		break;
2004 	}
2005 
2006 	return NOTIFY_DONE;
2007 }
2008 
2009 static struct notifier_block sysc_nb = {
2010 	.notifier_call = sysc_notifier_call,
2011 };
2012 
2013 /* Device tree configured quirks */
2014 struct sysc_dts_quirk {
2015 	const char *name;
2016 	u32 mask;
2017 };
2018 
2019 static const struct sysc_dts_quirk sysc_dts_quirks[] = {
2020 	{ .name = "ti,no-idle-on-init",
2021 	  .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
2022 	{ .name = "ti,no-reset-on-init",
2023 	  .mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
2024 	{ .name = "ti,no-idle",
2025 	  .mask = SYSC_QUIRK_NO_IDLE, },
2026 };
2027 
2028 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np,
2029 				  bool is_child)
2030 {
2031 	const struct property *prop;
2032 	int i, len;
2033 
2034 	for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
2035 		const char *name = sysc_dts_quirks[i].name;
2036 
2037 		prop = of_get_property(np, name, &len);
2038 		if (!prop)
2039 			continue;
2040 
2041 		ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
2042 		if (is_child) {
2043 			dev_warn(ddata->dev,
2044 				 "dts flag should be at module level for %s\n",
2045 				 name);
2046 		}
2047 	}
2048 }
2049 
2050 static int sysc_init_dts_quirks(struct sysc *ddata)
2051 {
2052 	struct device_node *np = ddata->dev->of_node;
2053 	int error;
2054 	u32 val;
2055 
2056 	ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL);
2057 
2058 	sysc_parse_dts_quirks(ddata, np, false);
2059 	error = of_property_read_u32(np, "ti,sysc-delay-us", &val);
2060 	if (!error) {
2061 		if (val > 255) {
2062 			dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n",
2063 				 val);
2064 		}
2065 
2066 		ddata->cfg.srst_udelay = (u8)val;
2067 	}
2068 
2069 	return 0;
2070 }
2071 
2072 static void sysc_unprepare(struct sysc *ddata)
2073 {
2074 	int i;
2075 
2076 	if (!ddata->clocks)
2077 		return;
2078 
2079 	for (i = 0; i < SYSC_MAX_CLOCKS; i++) {
2080 		if (!IS_ERR_OR_NULL(ddata->clocks[i]))
2081 			clk_unprepare(ddata->clocks[i]);
2082 	}
2083 }
2084 
2085 /*
2086  * Common sysc register bits found on omap2, also known as type1
2087  */
2088 static const struct sysc_regbits sysc_regbits_omap2 = {
2089 	.dmadisable_shift = -ENODEV,
2090 	.midle_shift = 12,
2091 	.sidle_shift = 3,
2092 	.clkact_shift = 8,
2093 	.emufree_shift = 5,
2094 	.enwkup_shift = 2,
2095 	.srst_shift = 1,
2096 	.autoidle_shift = 0,
2097 };
2098 
2099 static const struct sysc_capabilities sysc_omap2 = {
2100 	.type = TI_SYSC_OMAP2,
2101 	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2102 		     SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2103 		     SYSC_OMAP2_AUTOIDLE,
2104 	.regbits = &sysc_regbits_omap2,
2105 };
2106 
2107 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */
2108 static const struct sysc_capabilities sysc_omap2_timer = {
2109 	.type = TI_SYSC_OMAP2_TIMER,
2110 	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE |
2111 		     SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET |
2112 		     SYSC_OMAP2_AUTOIDLE,
2113 	.regbits = &sysc_regbits_omap2,
2114 	.mod_quirks = SYSC_QUIRK_USE_CLOCKACT,
2115 };
2116 
2117 /*
2118  * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2
2119  * with different sidle position
2120  */
2121 static const struct sysc_regbits sysc_regbits_omap3_sham = {
2122 	.dmadisable_shift = -ENODEV,
2123 	.midle_shift = -ENODEV,
2124 	.sidle_shift = 4,
2125 	.clkact_shift = -ENODEV,
2126 	.enwkup_shift = -ENODEV,
2127 	.srst_shift = 1,
2128 	.autoidle_shift = 0,
2129 	.emufree_shift = -ENODEV,
2130 };
2131 
2132 static const struct sysc_capabilities sysc_omap3_sham = {
2133 	.type = TI_SYSC_OMAP3_SHAM,
2134 	.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2135 	.regbits = &sysc_regbits_omap3_sham,
2136 };
2137 
2138 /*
2139  * AES register bits found on omap3 and later, a variant of
2140  * sysc_regbits_omap2 with different sidle position
2141  */
2142 static const struct sysc_regbits sysc_regbits_omap3_aes = {
2143 	.dmadisable_shift = -ENODEV,
2144 	.midle_shift = -ENODEV,
2145 	.sidle_shift = 6,
2146 	.clkact_shift = -ENODEV,
2147 	.enwkup_shift = -ENODEV,
2148 	.srst_shift = 1,
2149 	.autoidle_shift = 0,
2150 	.emufree_shift = -ENODEV,
2151 };
2152 
2153 static const struct sysc_capabilities sysc_omap3_aes = {
2154 	.type = TI_SYSC_OMAP3_AES,
2155 	.sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE,
2156 	.regbits = &sysc_regbits_omap3_aes,
2157 };
2158 
2159 /*
2160  * Common sysc register bits found on omap4, also known as type2
2161  */
2162 static const struct sysc_regbits sysc_regbits_omap4 = {
2163 	.dmadisable_shift = 16,
2164 	.midle_shift = 4,
2165 	.sidle_shift = 2,
2166 	.clkact_shift = -ENODEV,
2167 	.enwkup_shift = -ENODEV,
2168 	.emufree_shift = 1,
2169 	.srst_shift = 0,
2170 	.autoidle_shift = -ENODEV,
2171 };
2172 
2173 static const struct sysc_capabilities sysc_omap4 = {
2174 	.type = TI_SYSC_OMAP4,
2175 	.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2176 		     SYSC_OMAP4_SOFTRESET,
2177 	.regbits = &sysc_regbits_omap4,
2178 };
2179 
2180 static const struct sysc_capabilities sysc_omap4_timer = {
2181 	.type = TI_SYSC_OMAP4_TIMER,
2182 	.sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU |
2183 		     SYSC_OMAP4_SOFTRESET,
2184 	.regbits = &sysc_regbits_omap4,
2185 };
2186 
2187 /*
2188  * Common sysc register bits found on omap4, also known as type3
2189  */
2190 static const struct sysc_regbits sysc_regbits_omap4_simple = {
2191 	.dmadisable_shift = -ENODEV,
2192 	.midle_shift = 2,
2193 	.sidle_shift = 0,
2194 	.clkact_shift = -ENODEV,
2195 	.enwkup_shift = -ENODEV,
2196 	.srst_shift = -ENODEV,
2197 	.emufree_shift = -ENODEV,
2198 	.autoidle_shift = -ENODEV,
2199 };
2200 
2201 static const struct sysc_capabilities sysc_omap4_simple = {
2202 	.type = TI_SYSC_OMAP4_SIMPLE,
2203 	.regbits = &sysc_regbits_omap4_simple,
2204 };
2205 
2206 /*
2207  * SmartReflex sysc found on omap34xx
2208  */
2209 static const struct sysc_regbits sysc_regbits_omap34xx_sr = {
2210 	.dmadisable_shift = -ENODEV,
2211 	.midle_shift = -ENODEV,
2212 	.sidle_shift = -ENODEV,
2213 	.clkact_shift = 20,
2214 	.enwkup_shift = -ENODEV,
2215 	.srst_shift = -ENODEV,
2216 	.emufree_shift = -ENODEV,
2217 	.autoidle_shift = -ENODEV,
2218 };
2219 
2220 static const struct sysc_capabilities sysc_34xx_sr = {
2221 	.type = TI_SYSC_OMAP34XX_SR,
2222 	.sysc_mask = SYSC_OMAP2_CLOCKACTIVITY,
2223 	.regbits = &sysc_regbits_omap34xx_sr,
2224 	.mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED |
2225 		      SYSC_QUIRK_LEGACY_IDLE,
2226 };
2227 
2228 /*
2229  * SmartReflex sysc found on omap36xx and later
2230  */
2231 static const struct sysc_regbits sysc_regbits_omap36xx_sr = {
2232 	.dmadisable_shift = -ENODEV,
2233 	.midle_shift = -ENODEV,
2234 	.sidle_shift = 24,
2235 	.clkact_shift = -ENODEV,
2236 	.enwkup_shift = 26,
2237 	.srst_shift = -ENODEV,
2238 	.emufree_shift = -ENODEV,
2239 	.autoidle_shift = -ENODEV,
2240 };
2241 
2242 static const struct sysc_capabilities sysc_36xx_sr = {
2243 	.type = TI_SYSC_OMAP36XX_SR,
2244 	.sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP,
2245 	.regbits = &sysc_regbits_omap36xx_sr,
2246 	.mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE,
2247 };
2248 
2249 static const struct sysc_capabilities sysc_omap4_sr = {
2250 	.type = TI_SYSC_OMAP4_SR,
2251 	.regbits = &sysc_regbits_omap36xx_sr,
2252 	.mod_quirks = SYSC_QUIRK_LEGACY_IDLE,
2253 };
2254 
2255 /*
2256  * McASP register bits found on omap4 and later
2257  */
2258 static const struct sysc_regbits sysc_regbits_omap4_mcasp = {
2259 	.dmadisable_shift = -ENODEV,
2260 	.midle_shift = -ENODEV,
2261 	.sidle_shift = 0,
2262 	.clkact_shift = -ENODEV,
2263 	.enwkup_shift = -ENODEV,
2264 	.srst_shift = -ENODEV,
2265 	.emufree_shift = -ENODEV,
2266 	.autoidle_shift = -ENODEV,
2267 };
2268 
2269 static const struct sysc_capabilities sysc_omap4_mcasp = {
2270 	.type = TI_SYSC_OMAP4_MCASP,
2271 	.regbits = &sysc_regbits_omap4_mcasp,
2272 	.mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2273 };
2274 
2275 /*
2276  * McASP found on dra7 and later
2277  */
2278 static const struct sysc_capabilities sysc_dra7_mcasp = {
2279 	.type = TI_SYSC_OMAP4_SIMPLE,
2280 	.regbits = &sysc_regbits_omap4_simple,
2281 	.mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED,
2282 };
2283 
2284 /*
2285  * FS USB host found on omap4 and later
2286  */
2287 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = {
2288 	.dmadisable_shift = -ENODEV,
2289 	.midle_shift = -ENODEV,
2290 	.sidle_shift = 24,
2291 	.clkact_shift = -ENODEV,
2292 	.enwkup_shift = 26,
2293 	.srst_shift = -ENODEV,
2294 	.emufree_shift = -ENODEV,
2295 	.autoidle_shift = -ENODEV,
2296 };
2297 
2298 static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
2299 	.type = TI_SYSC_OMAP4_USB_HOST_FS,
2300 	.sysc_mask = SYSC_OMAP2_ENAWAKEUP,
2301 	.regbits = &sysc_regbits_omap4_usb_host_fs,
2302 };
2303 
2304 static const struct sysc_regbits sysc_regbits_dra7_mcan = {
2305 	.dmadisable_shift = -ENODEV,
2306 	.midle_shift = -ENODEV,
2307 	.sidle_shift = -ENODEV,
2308 	.clkact_shift = -ENODEV,
2309 	.enwkup_shift = 4,
2310 	.srst_shift = 0,
2311 	.emufree_shift = -ENODEV,
2312 	.autoidle_shift = -ENODEV,
2313 };
2314 
2315 static const struct sysc_capabilities sysc_dra7_mcan = {
2316 	.type = TI_SYSC_DRA7_MCAN,
2317 	.sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
2318 	.regbits = &sysc_regbits_dra7_mcan,
2319 	.mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
2320 };
2321 
2322 static int sysc_init_pdata(struct sysc *ddata)
2323 {
2324 	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
2325 	struct ti_sysc_module_data *mdata;
2326 
2327 	if (!pdata)
2328 		return 0;
2329 
2330 	mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
2331 	if (!mdata)
2332 		return -ENOMEM;
2333 
2334 	if (ddata->legacy_mode) {
2335 		mdata->name = ddata->legacy_mode;
2336 		mdata->module_pa = ddata->module_pa;
2337 		mdata->module_size = ddata->module_size;
2338 		mdata->offsets = ddata->offsets;
2339 		mdata->nr_offsets = SYSC_MAX_REGS;
2340 		mdata->cap = ddata->cap;
2341 		mdata->cfg = &ddata->cfg;
2342 	}
2343 
2344 	ddata->mdata = mdata;
2345 
2346 	return 0;
2347 }
2348 
2349 static int sysc_init_match(struct sysc *ddata)
2350 {
2351 	const struct sysc_capabilities *cap;
2352 
2353 	cap = of_device_get_match_data(ddata->dev);
2354 	if (!cap)
2355 		return -EINVAL;
2356 
2357 	ddata->cap = cap;
2358 	if (ddata->cap)
2359 		ddata->cfg.quirks |= ddata->cap->mod_quirks;
2360 
2361 	return 0;
2362 }
2363 
2364 static void ti_sysc_idle(struct work_struct *work)
2365 {
2366 	struct sysc *ddata;
2367 
2368 	ddata = container_of(work, struct sysc, idle_work.work);
2369 
2370 	/*
2371 	 * One time decrement of clock usage counts if left on from init.
2372 	 * Note that we disable opt clocks unconditionally in this case
2373 	 * as they are enabled unconditionally during init without
2374 	 * considering sysc_opt_clks_needed() at that point.
2375 	 */
2376 	if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2377 				 SYSC_QUIRK_NO_IDLE_ON_INIT)) {
2378 		sysc_disable_main_clocks(ddata);
2379 		sysc_disable_opt_clocks(ddata);
2380 		sysc_clkdm_allow_idle(ddata);
2381 	}
2382 
2383 	/* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
2384 	if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
2385 		return;
2386 
2387 	/*
2388 	 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
2389 	 * and SYSC_QUIRK_NO_RESET_ON_INIT
2390 	 */
2391 	if (pm_runtime_active(ddata->dev))
2392 		pm_runtime_put_sync(ddata->dev);
2393 }
2394 
2395 static const struct of_device_id sysc_match_table[] = {
2396 	{ .compatible = "simple-bus", },
2397 	{ /* sentinel */ },
2398 };
2399 
2400 static int sysc_probe(struct platform_device *pdev)
2401 {
2402 	struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev);
2403 	struct sysc *ddata;
2404 	int error;
2405 
2406 	ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
2407 	if (!ddata)
2408 		return -ENOMEM;
2409 
2410 	ddata->dev = &pdev->dev;
2411 	platform_set_drvdata(pdev, ddata);
2412 
2413 	error = sysc_init_match(ddata);
2414 	if (error)
2415 		return error;
2416 
2417 	error = sysc_init_dts_quirks(ddata);
2418 	if (error)
2419 		return error;
2420 
2421 	error = sysc_map_and_check_registers(ddata);
2422 	if (error)
2423 		return error;
2424 
2425 	error = sysc_init_sysc_mask(ddata);
2426 	if (error)
2427 		return error;
2428 
2429 	error = sysc_init_idlemodes(ddata);
2430 	if (error)
2431 		return error;
2432 
2433 	error = sysc_init_syss_mask(ddata);
2434 	if (error)
2435 		return error;
2436 
2437 	error = sysc_init_pdata(ddata);
2438 	if (error)
2439 		return error;
2440 
2441 	sysc_init_early_quirks(ddata);
2442 
2443 	error = sysc_get_clocks(ddata);
2444 	if (error)
2445 		return error;
2446 
2447 	error = sysc_init_resets(ddata);
2448 	if (error)
2449 		goto unprepare;
2450 
2451 	error = sysc_init_module(ddata);
2452 	if (error)
2453 		goto unprepare;
2454 
2455 	pm_runtime_enable(ddata->dev);
2456 	error = pm_runtime_get_sync(ddata->dev);
2457 	if (error < 0) {
2458 		pm_runtime_put_noidle(ddata->dev);
2459 		pm_runtime_disable(ddata->dev);
2460 		goto unprepare;
2461 	}
2462 
2463 	/* Balance reset counts */
2464 	if (ddata->rsts)
2465 		reset_control_assert(ddata->rsts);
2466 
2467 	sysc_show_registers(ddata);
2468 
2469 	ddata->dev->type = &sysc_device_type;
2470 	error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
2471 				     pdata ? pdata->auxdata : NULL,
2472 				     ddata->dev);
2473 	if (error)
2474 		goto err;
2475 
2476 	INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
2477 
2478 	/* At least earlycon won't survive without deferred idle */
2479 	if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE |
2480 				 SYSC_QUIRK_NO_IDLE_ON_INIT |
2481 				 SYSC_QUIRK_NO_RESET_ON_INIT)) {
2482 		schedule_delayed_work(&ddata->idle_work, 3000);
2483 	} else {
2484 		pm_runtime_put(&pdev->dev);
2485 	}
2486 
2487 	return 0;
2488 
2489 err:
2490 	pm_runtime_put_sync(&pdev->dev);
2491 	pm_runtime_disable(&pdev->dev);
2492 unprepare:
2493 	sysc_unprepare(ddata);
2494 
2495 	return error;
2496 }
2497 
2498 static int sysc_remove(struct platform_device *pdev)
2499 {
2500 	struct sysc *ddata = platform_get_drvdata(pdev);
2501 	int error;
2502 
2503 	cancel_delayed_work_sync(&ddata->idle_work);
2504 
2505 	error = pm_runtime_get_sync(ddata->dev);
2506 	if (error < 0) {
2507 		pm_runtime_put_noidle(ddata->dev);
2508 		pm_runtime_disable(ddata->dev);
2509 		goto unprepare;
2510 	}
2511 
2512 	of_platform_depopulate(&pdev->dev);
2513 
2514 	pm_runtime_put_sync(&pdev->dev);
2515 	pm_runtime_disable(&pdev->dev);
2516 	reset_control_assert(ddata->rsts);
2517 
2518 unprepare:
2519 	sysc_unprepare(ddata);
2520 
2521 	return 0;
2522 }
2523 
2524 static const struct of_device_id sysc_match[] = {
2525 	{ .compatible = "ti,sysc-omap2", .data = &sysc_omap2, },
2526 	{ .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, },
2527 	{ .compatible = "ti,sysc-omap4", .data = &sysc_omap4, },
2528 	{ .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, },
2529 	{ .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, },
2530 	{ .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, },
2531 	{ .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, },
2532 	{ .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, },
2533 	{ .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, },
2534 	{ .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, },
2535 	{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
2536 	{ .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, },
2537 	{ .compatible = "ti,sysc-usb-host-fs",
2538 	  .data = &sysc_omap4_usb_host_fs, },
2539 	{ .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
2540 	{  },
2541 };
2542 MODULE_DEVICE_TABLE(of, sysc_match);
2543 
2544 static struct platform_driver sysc_driver = {
2545 	.probe		= sysc_probe,
2546 	.remove		= sysc_remove,
2547 	.driver         = {
2548 		.name   = "ti-sysc",
2549 		.of_match_table	= sysc_match,
2550 		.pm = &sysc_pm_ops,
2551 	},
2552 };
2553 
2554 static int __init sysc_init(void)
2555 {
2556 	bus_register_notifier(&platform_bus_type, &sysc_nb);
2557 
2558 	return platform_driver_register(&sysc_driver);
2559 }
2560 module_init(sysc_init);
2561 
2562 static void __exit sysc_exit(void)
2563 {
2564 	bus_unregister_notifier(&platform_bus_type, &sysc_nb);
2565 	platform_driver_unregister(&sysc_driver);
2566 }
2567 module_exit(sysc_exit);
2568 
2569 MODULE_DESCRIPTION("TI sysc interconnect target driver");
2570 MODULE_LICENSE("GPL v2");
2571