1 /* 2 * ti-sysc.c - Texas Instruments sysc interconnect target driver 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/clk.h> 16 #include <linux/clkdev.h> 17 #include <linux/delay.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 #include <linux/of_address.h> 24 #include <linux/of_platform.h> 25 #include <linux/slab.h> 26 #include <linux/iopoll.h> 27 28 #include <linux/platform_data/ti-sysc.h> 29 30 #include <dt-bindings/bus/ti-sysc.h> 31 32 #define MAX_MODULE_SOFTRESET_WAIT 10000 33 34 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 35 36 enum sysc_clocks { 37 SYSC_FCK, 38 SYSC_ICK, 39 SYSC_OPTFCK0, 40 SYSC_OPTFCK1, 41 SYSC_OPTFCK2, 42 SYSC_OPTFCK3, 43 SYSC_OPTFCK4, 44 SYSC_OPTFCK5, 45 SYSC_OPTFCK6, 46 SYSC_OPTFCK7, 47 SYSC_MAX_CLOCKS, 48 }; 49 50 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 51 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 52 "opt5", "opt6", "opt7", 53 }; 54 55 #define SYSC_IDLEMODE_MASK 3 56 #define SYSC_CLOCKACTIVITY_MASK 3 57 58 /** 59 * struct sysc - TI sysc interconnect target module registers and capabilities 60 * @dev: struct device pointer 61 * @module_pa: physical address of the interconnect target module 62 * @module_size: size of the interconnect target module 63 * @module_va: virtual address of the interconnect target module 64 * @offsets: register offsets from module base 65 * @clocks: clocks used by the interconnect target module 66 * @clock_roles: clock role names for the found clocks 67 * @nr_clocks: number of clocks used by the interconnect target module 68 * @legacy_mode: configured for legacy mode if set 69 * @cap: interconnect target module capabilities 70 * @cfg: interconnect target module configuration 71 * @name: name if available 72 * @revision: interconnect target module revision 73 * @needs_resume: runtime resume needed on resume from suspend 74 * @clk_enable_quirk: module specific clock enable quirk 75 * @clk_disable_quirk: module specific clock disable quirk 76 * @reset_done_quirk: module specific reset done quirk 77 */ 78 struct sysc { 79 struct device *dev; 80 u64 module_pa; 81 u32 module_size; 82 void __iomem *module_va; 83 int offsets[SYSC_MAX_REGS]; 84 struct ti_sysc_module_data *mdata; 85 struct clk **clocks; 86 const char **clock_roles; 87 int nr_clocks; 88 struct reset_control *rsts; 89 const char *legacy_mode; 90 const struct sysc_capabilities *cap; 91 struct sysc_config cfg; 92 struct ti_sysc_cookie cookie; 93 const char *name; 94 u32 revision; 95 unsigned int enabled:1; 96 unsigned int needs_resume:1; 97 unsigned int child_needs_resume:1; 98 unsigned int disable_on_idle:1; 99 struct delayed_work idle_work; 100 void (*clk_enable_quirk)(struct sysc *sysc); 101 void (*clk_disable_quirk)(struct sysc *sysc); 102 void (*reset_done_quirk)(struct sysc *sysc); 103 }; 104 105 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 106 bool is_child); 107 108 static void sysc_write(struct sysc *ddata, int offset, u32 value) 109 { 110 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 111 writew_relaxed(value & 0xffff, ddata->module_va + offset); 112 113 /* Only i2c revision has LO and HI register with stride of 4 */ 114 if (ddata->offsets[SYSC_REVISION] >= 0 && 115 offset == ddata->offsets[SYSC_REVISION]) { 116 u16 hi = value >> 16; 117 118 writew_relaxed(hi, ddata->module_va + offset + 4); 119 } 120 121 return; 122 } 123 124 writel_relaxed(value, ddata->module_va + offset); 125 } 126 127 static u32 sysc_read(struct sysc *ddata, int offset) 128 { 129 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 130 u32 val; 131 132 val = readw_relaxed(ddata->module_va + offset); 133 134 /* Only i2c revision has LO and HI register with stride of 4 */ 135 if (ddata->offsets[SYSC_REVISION] >= 0 && 136 offset == ddata->offsets[SYSC_REVISION]) { 137 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 138 139 val |= tmp << 16; 140 } 141 142 return val; 143 } 144 145 return readl_relaxed(ddata->module_va + offset); 146 } 147 148 static bool sysc_opt_clks_needed(struct sysc *ddata) 149 { 150 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 151 } 152 153 static u32 sysc_read_revision(struct sysc *ddata) 154 { 155 int offset = ddata->offsets[SYSC_REVISION]; 156 157 if (offset < 0) 158 return 0; 159 160 return sysc_read(ddata, offset); 161 } 162 163 static u32 sysc_read_sysconfig(struct sysc *ddata) 164 { 165 int offset = ddata->offsets[SYSC_SYSCONFIG]; 166 167 if (offset < 0) 168 return 0; 169 170 return sysc_read(ddata, offset); 171 } 172 173 static u32 sysc_read_sysstatus(struct sysc *ddata) 174 { 175 int offset = ddata->offsets[SYSC_SYSSTATUS]; 176 177 if (offset < 0) 178 return 0; 179 180 return sysc_read(ddata, offset); 181 } 182 183 static int sysc_add_named_clock_from_child(struct sysc *ddata, 184 const char *name, 185 const char *optfck_name) 186 { 187 struct device_node *np = ddata->dev->of_node; 188 struct device_node *child; 189 struct clk_lookup *cl; 190 struct clk *clock; 191 const char *n; 192 193 if (name) 194 n = name; 195 else 196 n = optfck_name; 197 198 /* Does the clock alias already exist? */ 199 clock = of_clk_get_by_name(np, n); 200 if (!IS_ERR(clock)) { 201 clk_put(clock); 202 203 return 0; 204 } 205 206 child = of_get_next_available_child(np, NULL); 207 if (!child) 208 return -ENODEV; 209 210 clock = devm_get_clk_from_child(ddata->dev, child, name); 211 if (IS_ERR(clock)) 212 return PTR_ERR(clock); 213 214 /* 215 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 216 * limit for clk_get(). If cl ever needs to be freed, it should be done 217 * with clkdev_drop(). 218 */ 219 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); 220 if (!cl) 221 return -ENOMEM; 222 223 cl->con_id = n; 224 cl->dev_id = dev_name(ddata->dev); 225 cl->clk = clock; 226 clkdev_add(cl); 227 228 clk_put(clock); 229 230 return 0; 231 } 232 233 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 234 { 235 const char *optfck_name; 236 int error, index; 237 238 if (ddata->nr_clocks < SYSC_OPTFCK0) 239 index = SYSC_OPTFCK0; 240 else 241 index = ddata->nr_clocks; 242 243 if (name) 244 optfck_name = name; 245 else 246 optfck_name = clock_names[index]; 247 248 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 249 if (error) 250 return error; 251 252 ddata->clock_roles[index] = optfck_name; 253 ddata->nr_clocks++; 254 255 return 0; 256 } 257 258 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 259 { 260 int error, i, index = -ENODEV; 261 262 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 263 index = SYSC_FCK; 264 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 265 index = SYSC_ICK; 266 267 if (index < 0) { 268 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 269 if (!ddata->clocks[i]) { 270 index = i; 271 break; 272 } 273 } 274 } 275 276 if (index < 0) { 277 dev_err(ddata->dev, "clock %s not added\n", name); 278 return index; 279 } 280 281 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 282 if (IS_ERR(ddata->clocks[index])) { 283 if (PTR_ERR(ddata->clocks[index]) == -ENOENT) 284 return 0; 285 286 dev_err(ddata->dev, "clock get error for %s: %li\n", 287 name, PTR_ERR(ddata->clocks[index])); 288 289 return PTR_ERR(ddata->clocks[index]); 290 } 291 292 error = clk_prepare(ddata->clocks[index]); 293 if (error) { 294 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 295 name, error); 296 297 return error; 298 } 299 300 return 0; 301 } 302 303 static int sysc_get_clocks(struct sysc *ddata) 304 { 305 struct device_node *np = ddata->dev->of_node; 306 struct property *prop; 307 const char *name; 308 int nr_fck = 0, nr_ick = 0, i, error = 0; 309 310 ddata->clock_roles = devm_kcalloc(ddata->dev, 311 SYSC_MAX_CLOCKS, 312 sizeof(*ddata->clock_roles), 313 GFP_KERNEL); 314 if (!ddata->clock_roles) 315 return -ENOMEM; 316 317 of_property_for_each_string(np, "clock-names", prop, name) { 318 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 319 nr_fck++; 320 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 321 nr_ick++; 322 ddata->clock_roles[ddata->nr_clocks] = name; 323 ddata->nr_clocks++; 324 } 325 326 if (ddata->nr_clocks < 1) 327 return 0; 328 329 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 330 error = sysc_init_ext_opt_clock(ddata, NULL); 331 if (error) 332 return error; 333 } 334 335 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 336 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 337 338 return -EINVAL; 339 } 340 341 if (nr_fck > 1 || nr_ick > 1) { 342 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 343 344 return -EINVAL; 345 } 346 347 ddata->clocks = devm_kcalloc(ddata->dev, 348 ddata->nr_clocks, sizeof(*ddata->clocks), 349 GFP_KERNEL); 350 if (!ddata->clocks) 351 return -ENOMEM; 352 353 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 354 const char *name = ddata->clock_roles[i]; 355 356 if (!name) 357 continue; 358 359 error = sysc_get_one_clock(ddata, name); 360 if (error && error != -ENOENT) 361 return error; 362 } 363 364 return 0; 365 } 366 367 static int sysc_enable_main_clocks(struct sysc *ddata) 368 { 369 struct clk *clock; 370 int i, error; 371 372 if (!ddata->clocks) 373 return 0; 374 375 for (i = 0; i < SYSC_OPTFCK0; i++) { 376 clock = ddata->clocks[i]; 377 378 /* Main clocks may not have ick */ 379 if (IS_ERR_OR_NULL(clock)) 380 continue; 381 382 error = clk_enable(clock); 383 if (error) 384 goto err_disable; 385 } 386 387 return 0; 388 389 err_disable: 390 for (i--; i >= 0; i--) { 391 clock = ddata->clocks[i]; 392 393 /* Main clocks may not have ick */ 394 if (IS_ERR_OR_NULL(clock)) 395 continue; 396 397 clk_disable(clock); 398 } 399 400 return error; 401 } 402 403 static void sysc_disable_main_clocks(struct sysc *ddata) 404 { 405 struct clk *clock; 406 int i; 407 408 if (!ddata->clocks) 409 return; 410 411 for (i = 0; i < SYSC_OPTFCK0; i++) { 412 clock = ddata->clocks[i]; 413 if (IS_ERR_OR_NULL(clock)) 414 continue; 415 416 clk_disable(clock); 417 } 418 } 419 420 static int sysc_enable_opt_clocks(struct sysc *ddata) 421 { 422 struct clk *clock; 423 int i, error; 424 425 if (!ddata->clocks) 426 return 0; 427 428 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 429 clock = ddata->clocks[i]; 430 431 /* Assume no holes for opt clocks */ 432 if (IS_ERR_OR_NULL(clock)) 433 return 0; 434 435 error = clk_enable(clock); 436 if (error) 437 goto err_disable; 438 } 439 440 return 0; 441 442 err_disable: 443 for (i--; i >= 0; i--) { 444 clock = ddata->clocks[i]; 445 if (IS_ERR_OR_NULL(clock)) 446 continue; 447 448 clk_disable(clock); 449 } 450 451 return error; 452 } 453 454 static void sysc_disable_opt_clocks(struct sysc *ddata) 455 { 456 struct clk *clock; 457 int i; 458 459 if (!ddata->clocks) 460 return; 461 462 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 463 clock = ddata->clocks[i]; 464 465 /* Assume no holes for opt clocks */ 466 if (IS_ERR_OR_NULL(clock)) 467 return; 468 469 clk_disable(clock); 470 } 471 } 472 473 static void sysc_clkdm_deny_idle(struct sysc *ddata) 474 { 475 struct ti_sysc_platform_data *pdata; 476 477 if (ddata->legacy_mode) 478 return; 479 480 pdata = dev_get_platdata(ddata->dev); 481 if (pdata && pdata->clkdm_deny_idle) 482 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 483 } 484 485 static void sysc_clkdm_allow_idle(struct sysc *ddata) 486 { 487 struct ti_sysc_platform_data *pdata; 488 489 if (ddata->legacy_mode) 490 return; 491 492 pdata = dev_get_platdata(ddata->dev); 493 if (pdata && pdata->clkdm_allow_idle) 494 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 495 } 496 497 /** 498 * sysc_init_resets - init rstctrl reset line if configured 499 * @ddata: device driver data 500 * 501 * See sysc_rstctrl_reset_deassert(). 502 */ 503 static int sysc_init_resets(struct sysc *ddata) 504 { 505 ddata->rsts = 506 devm_reset_control_get_optional(ddata->dev, "rstctrl"); 507 if (IS_ERR(ddata->rsts)) 508 return PTR_ERR(ddata->rsts); 509 510 return 0; 511 } 512 513 /** 514 * sysc_parse_and_check_child_range - parses module IO region from ranges 515 * @ddata: device driver data 516 * 517 * In general we only need rev, syss, and sysc registers and not the whole 518 * module range. But we do want the offsets for these registers from the 519 * module base. This allows us to check them against the legacy hwmod 520 * platform data. Let's also check the ranges are configured properly. 521 */ 522 static int sysc_parse_and_check_child_range(struct sysc *ddata) 523 { 524 struct device_node *np = ddata->dev->of_node; 525 const __be32 *ranges; 526 u32 nr_addr, nr_size; 527 int len, error; 528 529 ranges = of_get_property(np, "ranges", &len); 530 if (!ranges) { 531 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 532 533 return -ENOENT; 534 } 535 536 len /= sizeof(*ranges); 537 538 if (len < 3) { 539 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 540 541 return -EINVAL; 542 } 543 544 error = of_property_read_u32(np, "#address-cells", &nr_addr); 545 if (error) 546 return -ENOENT; 547 548 error = of_property_read_u32(np, "#size-cells", &nr_size); 549 if (error) 550 return -ENOENT; 551 552 if (nr_addr != 1 || nr_size != 1) { 553 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 554 555 return -EINVAL; 556 } 557 558 ranges++; 559 ddata->module_pa = of_translate_address(np, ranges++); 560 ddata->module_size = be32_to_cpup(ranges); 561 562 return 0; 563 } 564 565 static struct device_node *stdout_path; 566 567 static void sysc_init_stdout_path(struct sysc *ddata) 568 { 569 struct device_node *np = NULL; 570 const char *uart; 571 572 if (IS_ERR(stdout_path)) 573 return; 574 575 if (stdout_path) 576 return; 577 578 np = of_find_node_by_path("/chosen"); 579 if (!np) 580 goto err; 581 582 uart = of_get_property(np, "stdout-path", NULL); 583 if (!uart) 584 goto err; 585 586 np = of_find_node_by_path(uart); 587 if (!np) 588 goto err; 589 590 stdout_path = np; 591 592 return; 593 594 err: 595 stdout_path = ERR_PTR(-ENODEV); 596 } 597 598 static void sysc_check_quirk_stdout(struct sysc *ddata, 599 struct device_node *np) 600 { 601 sysc_init_stdout_path(ddata); 602 if (np != stdout_path) 603 return; 604 605 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 606 SYSC_QUIRK_NO_RESET_ON_INIT; 607 } 608 609 /** 610 * sysc_check_one_child - check child configuration 611 * @ddata: device driver data 612 * @np: child device node 613 * 614 * Let's avoid messy situations where we have new interconnect target 615 * node but children have "ti,hwmods". These belong to the interconnect 616 * target node and are managed by this driver. 617 */ 618 static int sysc_check_one_child(struct sysc *ddata, 619 struct device_node *np) 620 { 621 const char *name; 622 623 name = of_get_property(np, "ti,hwmods", NULL); 624 if (name) 625 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 626 627 sysc_check_quirk_stdout(ddata, np); 628 sysc_parse_dts_quirks(ddata, np, true); 629 630 return 0; 631 } 632 633 static int sysc_check_children(struct sysc *ddata) 634 { 635 struct device_node *child; 636 int error; 637 638 for_each_child_of_node(ddata->dev->of_node, child) { 639 error = sysc_check_one_child(ddata, child); 640 if (error) 641 return error; 642 } 643 644 return 0; 645 } 646 647 /* 648 * So far only I2C uses 16-bit read access with clockactivity with revision 649 * in two registers with stride of 4. We can detect this based on the rev 650 * register size to configure things far enough to be able to properly read 651 * the revision register. 652 */ 653 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 654 { 655 if (resource_size(res) == 8) 656 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 657 } 658 659 /** 660 * sysc_parse_one - parses the interconnect target module registers 661 * @ddata: device driver data 662 * @reg: register to parse 663 */ 664 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 665 { 666 struct resource *res; 667 const char *name; 668 669 switch (reg) { 670 case SYSC_REVISION: 671 case SYSC_SYSCONFIG: 672 case SYSC_SYSSTATUS: 673 name = reg_names[reg]; 674 break; 675 default: 676 return -EINVAL; 677 } 678 679 res = platform_get_resource_byname(to_platform_device(ddata->dev), 680 IORESOURCE_MEM, name); 681 if (!res) { 682 ddata->offsets[reg] = -ENODEV; 683 684 return 0; 685 } 686 687 ddata->offsets[reg] = res->start - ddata->module_pa; 688 if (reg == SYSC_REVISION) 689 sysc_check_quirk_16bit(ddata, res); 690 691 return 0; 692 } 693 694 static int sysc_parse_registers(struct sysc *ddata) 695 { 696 int i, error; 697 698 for (i = 0; i < SYSC_MAX_REGS; i++) { 699 error = sysc_parse_one(ddata, i); 700 if (error) 701 return error; 702 } 703 704 return 0; 705 } 706 707 /** 708 * sysc_check_registers - check for misconfigured register overlaps 709 * @ddata: device driver data 710 */ 711 static int sysc_check_registers(struct sysc *ddata) 712 { 713 int i, j, nr_regs = 0, nr_matches = 0; 714 715 for (i = 0; i < SYSC_MAX_REGS; i++) { 716 if (ddata->offsets[i] < 0) 717 continue; 718 719 if (ddata->offsets[i] > (ddata->module_size - 4)) { 720 dev_err(ddata->dev, "register outside module range"); 721 722 return -EINVAL; 723 } 724 725 for (j = 0; j < SYSC_MAX_REGS; j++) { 726 if (ddata->offsets[j] < 0) 727 continue; 728 729 if (ddata->offsets[i] == ddata->offsets[j]) 730 nr_matches++; 731 } 732 nr_regs++; 733 } 734 735 if (nr_matches > nr_regs) { 736 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 737 nr_regs, nr_matches); 738 739 return -EINVAL; 740 } 741 742 return 0; 743 } 744 745 /** 746 * syc_ioremap - ioremap register space for the interconnect target module 747 * @ddata: device driver data 748 * 749 * Note that the interconnect target module registers can be anywhere 750 * within the interconnect target module range. For example, SGX has 751 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 752 * has them at offset 0x1200 in the CPSW_WR child. Usually the 753 * the interconnect target module registers are at the beginning of 754 * the module range though. 755 */ 756 static int sysc_ioremap(struct sysc *ddata) 757 { 758 int size; 759 760 if (ddata->offsets[SYSC_REVISION] < 0 && 761 ddata->offsets[SYSC_SYSCONFIG] < 0 && 762 ddata->offsets[SYSC_SYSSTATUS] < 0) { 763 size = ddata->module_size; 764 } else { 765 size = max3(ddata->offsets[SYSC_REVISION], 766 ddata->offsets[SYSC_SYSCONFIG], 767 ddata->offsets[SYSC_SYSSTATUS]); 768 769 if (size < SZ_1K) 770 size = SZ_1K; 771 772 if ((size + sizeof(u32)) > ddata->module_size) 773 size = ddata->module_size; 774 } 775 776 ddata->module_va = devm_ioremap(ddata->dev, 777 ddata->module_pa, 778 size + sizeof(u32)); 779 if (!ddata->module_va) 780 return -EIO; 781 782 return 0; 783 } 784 785 /** 786 * sysc_map_and_check_registers - ioremap and check device registers 787 * @ddata: device driver data 788 */ 789 static int sysc_map_and_check_registers(struct sysc *ddata) 790 { 791 int error; 792 793 error = sysc_parse_and_check_child_range(ddata); 794 if (error) 795 return error; 796 797 error = sysc_check_children(ddata); 798 if (error) 799 return error; 800 801 error = sysc_parse_registers(ddata); 802 if (error) 803 return error; 804 805 error = sysc_ioremap(ddata); 806 if (error) 807 return error; 808 809 error = sysc_check_registers(ddata); 810 if (error) 811 return error; 812 813 return 0; 814 } 815 816 /** 817 * sysc_show_rev - read and show interconnect target module revision 818 * @bufp: buffer to print the information to 819 * @ddata: device driver data 820 */ 821 static int sysc_show_rev(char *bufp, struct sysc *ddata) 822 { 823 int len; 824 825 if (ddata->offsets[SYSC_REVISION] < 0) 826 return sprintf(bufp, ":NA"); 827 828 len = sprintf(bufp, ":%08x", ddata->revision); 829 830 return len; 831 } 832 833 static int sysc_show_reg(struct sysc *ddata, 834 char *bufp, enum sysc_registers reg) 835 { 836 if (ddata->offsets[reg] < 0) 837 return sprintf(bufp, ":NA"); 838 839 return sprintf(bufp, ":%x", ddata->offsets[reg]); 840 } 841 842 static int sysc_show_name(char *bufp, struct sysc *ddata) 843 { 844 if (!ddata->name) 845 return 0; 846 847 return sprintf(bufp, ":%s", ddata->name); 848 } 849 850 /** 851 * sysc_show_registers - show information about interconnect target module 852 * @ddata: device driver data 853 */ 854 static void sysc_show_registers(struct sysc *ddata) 855 { 856 char buf[128]; 857 char *bufp = buf; 858 int i; 859 860 for (i = 0; i < SYSC_MAX_REGS; i++) 861 bufp += sysc_show_reg(ddata, bufp, i); 862 863 bufp += sysc_show_rev(bufp, ddata); 864 bufp += sysc_show_name(bufp, ddata); 865 866 dev_dbg(ddata->dev, "%llx:%x%s\n", 867 ddata->module_pa, ddata->module_size, 868 buf); 869 } 870 871 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 872 #define SYSC_CLOCACT_ICK 2 873 874 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 875 static int sysc_enable_module(struct device *dev) 876 { 877 struct sysc *ddata; 878 const struct sysc_regbits *regbits; 879 u32 reg, idlemodes, best_mode; 880 881 ddata = dev_get_drvdata(dev); 882 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 883 return 0; 884 885 regbits = ddata->cap->regbits; 886 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 887 888 /* Set CLOCKACTIVITY, we only use it for ick */ 889 if (regbits->clkact_shift >= 0 && 890 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT || 891 ddata->cfg.sysc_val & BIT(regbits->clkact_shift))) 892 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 893 894 /* Set SIDLE mode */ 895 idlemodes = ddata->cfg.sidlemodes; 896 if (!idlemodes || regbits->sidle_shift < 0) 897 goto set_midle; 898 899 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 900 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 901 best_mode = SYSC_IDLE_NO; 902 } else { 903 best_mode = fls(ddata->cfg.sidlemodes) - 1; 904 if (best_mode > SYSC_IDLE_MASK) { 905 dev_err(dev, "%s: invalid sidlemode\n", __func__); 906 return -EINVAL; 907 } 908 909 /* Set WAKEUP */ 910 if (regbits->enwkup_shift >= 0 && 911 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 912 reg |= BIT(regbits->enwkup_shift); 913 } 914 915 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 916 reg |= best_mode << regbits->sidle_shift; 917 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 918 919 set_midle: 920 /* Set MIDLE mode */ 921 idlemodes = ddata->cfg.midlemodes; 922 if (!idlemodes || regbits->midle_shift < 0) 923 goto set_autoidle; 924 925 best_mode = fls(ddata->cfg.midlemodes) - 1; 926 if (best_mode > SYSC_IDLE_MASK) { 927 dev_err(dev, "%s: invalid midlemode\n", __func__); 928 return -EINVAL; 929 } 930 931 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 932 reg |= best_mode << regbits->midle_shift; 933 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 934 935 set_autoidle: 936 /* Autoidle bit must enabled separately if available */ 937 if (regbits->autoidle_shift >= 0 && 938 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 939 reg |= 1 << regbits->autoidle_shift; 940 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 941 } 942 943 return 0; 944 } 945 946 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 947 { 948 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 949 *best_mode = SYSC_IDLE_SMART_WKUP; 950 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 951 *best_mode = SYSC_IDLE_SMART; 952 else if (idlemodes & SYSC_IDLE_FORCE) 953 *best_mode = SYSC_IDLE_FORCE; 954 else 955 return -EINVAL; 956 957 return 0; 958 } 959 960 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 961 static int sysc_disable_module(struct device *dev) 962 { 963 struct sysc *ddata; 964 const struct sysc_regbits *regbits; 965 u32 reg, idlemodes, best_mode; 966 int ret; 967 968 ddata = dev_get_drvdata(dev); 969 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 970 return 0; 971 972 regbits = ddata->cap->regbits; 973 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 974 975 /* Set MIDLE mode */ 976 idlemodes = ddata->cfg.midlemodes; 977 if (!idlemodes || regbits->midle_shift < 0) 978 goto set_sidle; 979 980 ret = sysc_best_idle_mode(idlemodes, &best_mode); 981 if (ret) { 982 dev_err(dev, "%s: invalid midlemode\n", __func__); 983 return ret; 984 } 985 986 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 987 reg |= best_mode << regbits->midle_shift; 988 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 989 990 set_sidle: 991 /* Set SIDLE mode */ 992 idlemodes = ddata->cfg.sidlemodes; 993 if (!idlemodes || regbits->sidle_shift < 0) 994 return 0; 995 996 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 997 best_mode = SYSC_IDLE_FORCE; 998 } else { 999 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1000 if (ret) { 1001 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1002 return ret; 1003 } 1004 } 1005 1006 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1007 reg |= best_mode << regbits->sidle_shift; 1008 if (regbits->autoidle_shift >= 0 && 1009 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1010 reg |= 1 << regbits->autoidle_shift; 1011 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1012 1013 return 0; 1014 } 1015 1016 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1017 struct sysc *ddata) 1018 { 1019 struct ti_sysc_platform_data *pdata; 1020 int error; 1021 1022 pdata = dev_get_platdata(ddata->dev); 1023 if (!pdata) 1024 return 0; 1025 1026 if (!pdata->idle_module) 1027 return -ENODEV; 1028 1029 error = pdata->idle_module(dev, &ddata->cookie); 1030 if (error) 1031 dev_err(dev, "%s: could not idle: %i\n", 1032 __func__, error); 1033 1034 if (ddata->disable_on_idle) 1035 reset_control_assert(ddata->rsts); 1036 1037 return 0; 1038 } 1039 1040 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1041 struct sysc *ddata) 1042 { 1043 struct ti_sysc_platform_data *pdata; 1044 int error; 1045 1046 if (ddata->disable_on_idle) 1047 reset_control_deassert(ddata->rsts); 1048 1049 pdata = dev_get_platdata(ddata->dev); 1050 if (!pdata) 1051 return 0; 1052 1053 if (!pdata->enable_module) 1054 return -ENODEV; 1055 1056 error = pdata->enable_module(dev, &ddata->cookie); 1057 if (error) 1058 dev_err(dev, "%s: could not enable: %i\n", 1059 __func__, error); 1060 1061 return 0; 1062 } 1063 1064 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1065 { 1066 struct sysc *ddata; 1067 int error = 0; 1068 1069 ddata = dev_get_drvdata(dev); 1070 1071 if (!ddata->enabled) 1072 return 0; 1073 1074 sysc_clkdm_deny_idle(ddata); 1075 1076 if (ddata->legacy_mode) { 1077 error = sysc_runtime_suspend_legacy(dev, ddata); 1078 if (error) 1079 goto err_allow_idle; 1080 } else { 1081 error = sysc_disable_module(dev); 1082 if (error) 1083 goto err_allow_idle; 1084 } 1085 1086 sysc_disable_main_clocks(ddata); 1087 1088 if (sysc_opt_clks_needed(ddata)) 1089 sysc_disable_opt_clocks(ddata); 1090 1091 ddata->enabled = false; 1092 1093 err_allow_idle: 1094 sysc_clkdm_allow_idle(ddata); 1095 1096 if (ddata->disable_on_idle) 1097 reset_control_assert(ddata->rsts); 1098 1099 return error; 1100 } 1101 1102 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1103 { 1104 struct sysc *ddata; 1105 int error = 0; 1106 1107 ddata = dev_get_drvdata(dev); 1108 1109 if (ddata->enabled) 1110 return 0; 1111 1112 if (ddata->disable_on_idle) 1113 reset_control_deassert(ddata->rsts); 1114 1115 sysc_clkdm_deny_idle(ddata); 1116 1117 if (sysc_opt_clks_needed(ddata)) { 1118 error = sysc_enable_opt_clocks(ddata); 1119 if (error) 1120 goto err_allow_idle; 1121 } 1122 1123 error = sysc_enable_main_clocks(ddata); 1124 if (error) 1125 goto err_opt_clocks; 1126 1127 if (ddata->legacy_mode) { 1128 error = sysc_runtime_resume_legacy(dev, ddata); 1129 if (error) 1130 goto err_main_clocks; 1131 } else { 1132 error = sysc_enable_module(dev); 1133 if (error) 1134 goto err_main_clocks; 1135 } 1136 1137 ddata->enabled = true; 1138 1139 sysc_clkdm_allow_idle(ddata); 1140 1141 return 0; 1142 1143 err_main_clocks: 1144 sysc_disable_main_clocks(ddata); 1145 err_opt_clocks: 1146 if (sysc_opt_clks_needed(ddata)) 1147 sysc_disable_opt_clocks(ddata); 1148 err_allow_idle: 1149 sysc_clkdm_allow_idle(ddata); 1150 1151 return error; 1152 } 1153 1154 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1155 { 1156 struct sysc *ddata; 1157 1158 ddata = dev_get_drvdata(dev); 1159 1160 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1161 return 0; 1162 1163 return pm_runtime_force_suspend(dev); 1164 } 1165 1166 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1167 { 1168 struct sysc *ddata; 1169 1170 ddata = dev_get_drvdata(dev); 1171 1172 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1173 return 0; 1174 1175 return pm_runtime_force_resume(dev); 1176 } 1177 1178 static const struct dev_pm_ops sysc_pm_ops = { 1179 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1180 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1181 sysc_runtime_resume, 1182 NULL) 1183 }; 1184 1185 /* Module revision register based quirks */ 1186 struct sysc_revision_quirk { 1187 const char *name; 1188 u32 base; 1189 int rev_offset; 1190 int sysc_offset; 1191 int syss_offset; 1192 u32 revision; 1193 u32 revision_mask; 1194 u32 quirks; 1195 }; 1196 1197 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1198 optrev_val, optrevmask, optquirkmask) \ 1199 { \ 1200 .name = (optname), \ 1201 .base = (optbase), \ 1202 .rev_offset = (optrev), \ 1203 .sysc_offset = (optsysc), \ 1204 .syss_offset = (optsyss), \ 1205 .revision = (optrev_val), \ 1206 .revision_mask = (optrevmask), \ 1207 .quirks = (optquirkmask), \ 1208 } 1209 1210 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1211 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1212 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1213 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1214 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1215 SYSC_QUIRK_LEGACY_IDLE), 1216 SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 1217 SYSC_QUIRK_LEGACY_IDLE), 1218 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1219 SYSC_QUIRK_LEGACY_IDLE), 1220 SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff, 1221 SYSC_QUIRK_LEGACY_IDLE), 1222 SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff, 1223 SYSC_QUIRK_LEGACY_IDLE), 1224 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 1225 0), 1226 /* Some timers on omap4 and later */ 1227 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x50002100, 0xffffffff, 1228 0), 1229 SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffff00ff, 1230 0), 1231 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1232 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1233 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1234 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1235 /* Uarts on omap4 and later */ 1236 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1237 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1238 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1239 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1240 1241 /* Quirks that need to be set based on the module address */ 1242 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -1, 0x50000800, 0xffffffff, 1243 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1244 SYSC_QUIRK_SWSUP_SIDLE), 1245 1246 /* Quirks that need to be set based on detected module */ 1247 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1248 SYSC_MODULE_QUIRK_HDQ1W), 1249 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1250 SYSC_MODULE_QUIRK_HDQ1W), 1251 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1252 SYSC_MODULE_QUIRK_I2C), 1253 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1254 SYSC_MODULE_QUIRK_I2C), 1255 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1256 SYSC_MODULE_QUIRK_I2C), 1257 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1258 SYSC_MODULE_QUIRK_I2C), 1259 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1260 SYSC_MODULE_QUIRK_WDT), 1261 1262 #ifdef DEBUG 1263 SYSC_QUIRK("adc", 0, 0, 0x10, -1, 0x47300001, 0xffffffff, 0), 1264 SYSC_QUIRK("atl", 0, 0, -1, -1, 0x0a070100, 0xffffffff, 0), 1265 SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0), 1266 SYSC_QUIRK("cm", 0, 0, -1, -1, 0x40000301, 0xffffffff, 0), 1267 SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1268 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1269 0xffff00f0, 0), 1270 SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0), 1271 SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0), 1272 SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0), 1273 SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0), 1274 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0), 1275 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1276 SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0), 1277 SYSC_QUIRK("lcdc", 0, 0, 0x54, -1, 0x4f201000, 0xffffffff, 0), 1278 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0), 1279 SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44307b02, 0xffffffff, 0), 1280 SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0), 1281 SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffff00ff, 0), 1282 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1283 SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0), 1284 SYSC_QUIRK("m3", 0, 0, -1, -1, 0x5f580105, 0x0fff0f00, 0), 1285 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1286 SYSC_QUIRK("ocp2scp", 0, 0, -1, -1, 0x50060007, 0xffffffff, 0), 1287 SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff, 0), 1288 SYSC_QUIRK("padconf", 0, 0, -1, -1, 0x40001100, 0xffffffff, 0), 1289 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff, 0), 1290 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x00004102, 0xffffffff, 0), 1291 SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000400, 0xffffffff, 0), 1292 SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0), 1293 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4e8b0100, 0xffffffff, 0), 1294 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x4f000100, 0xffffffff, 0), 1295 SYSC_QUIRK("scm", 0, 0, -1, -1, 0x40000900, 0xffffffff, 0), 1296 SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff, 0), 1297 SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffff0ff0, 0), 1298 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1299 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1300 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0), 1301 SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0), 1302 SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0), 1303 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -1, 0x00000020, 0xffffffff, 0), 1304 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -1, 0x4eb01908, 0xffff00f0, 0), 1305 SYSC_QUIRK("timer32k", 0, 0, 0x4, -1, 0x00000060, 0xffffffff, 0), 1306 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1307 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1308 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0), 1309 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -1, 0x50700101, 0xffffffff, 0), 1310 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1311 0xffffffff, 0), 1312 SYSC_QUIRK("vfpe", 0, 0, 0x104, -1, 0x4d001200, 0xffffffff, 0), 1313 #endif 1314 }; 1315 1316 /* 1317 * Early quirks based on module base and register offsets only that are 1318 * needed before the module revision can be read 1319 */ 1320 static void sysc_init_early_quirks(struct sysc *ddata) 1321 { 1322 const struct sysc_revision_quirk *q; 1323 int i; 1324 1325 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1326 q = &sysc_revision_quirks[i]; 1327 1328 if (!q->base) 1329 continue; 1330 1331 if (q->base != ddata->module_pa) 1332 continue; 1333 1334 if (q->rev_offset >= 0 && 1335 q->rev_offset != ddata->offsets[SYSC_REVISION]) 1336 continue; 1337 1338 if (q->sysc_offset >= 0 && 1339 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1340 continue; 1341 1342 if (q->syss_offset >= 0 && 1343 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1344 continue; 1345 1346 ddata->name = q->name; 1347 ddata->cfg.quirks |= q->quirks; 1348 } 1349 } 1350 1351 /* Quirks that also consider the revision register value */ 1352 static void sysc_init_revision_quirks(struct sysc *ddata) 1353 { 1354 const struct sysc_revision_quirk *q; 1355 int i; 1356 1357 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1358 q = &sysc_revision_quirks[i]; 1359 1360 if (q->base && q->base != ddata->module_pa) 1361 continue; 1362 1363 if (q->rev_offset >= 0 && 1364 q->rev_offset != ddata->offsets[SYSC_REVISION]) 1365 continue; 1366 1367 if (q->sysc_offset >= 0 && 1368 q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1369 continue; 1370 1371 if (q->syss_offset >= 0 && 1372 q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1373 continue; 1374 1375 if (q->revision == ddata->revision || 1376 (q->revision & q->revision_mask) == 1377 (ddata->revision & q->revision_mask)) { 1378 ddata->name = q->name; 1379 ddata->cfg.quirks |= q->quirks; 1380 } 1381 } 1382 } 1383 1384 /* 1-wire needs module's internal clocks enabled for reset */ 1385 static void sysc_clk_enable_quirk_hdq1w(struct sysc *ddata) 1386 { 1387 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1388 u16 val; 1389 1390 val = sysc_read(ddata, offset); 1391 val |= BIT(5); 1392 sysc_write(ddata, offset, val); 1393 } 1394 1395 /* I2C needs extra enable bit toggling for reset */ 1396 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1397 { 1398 int offset; 1399 u16 val; 1400 1401 /* I2C_CON, omap2/3 is different from omap4 and later */ 1402 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1403 offset = 0x24; 1404 else 1405 offset = 0xa4; 1406 1407 /* I2C_EN */ 1408 val = sysc_read(ddata, offset); 1409 if (enable) 1410 val |= BIT(15); 1411 else 1412 val &= ~BIT(15); 1413 sysc_write(ddata, offset, val); 1414 } 1415 1416 static void sysc_clk_enable_quirk_i2c(struct sysc *ddata) 1417 { 1418 sysc_clk_quirk_i2c(ddata, true); 1419 } 1420 1421 static void sysc_clk_disable_quirk_i2c(struct sysc *ddata) 1422 { 1423 sysc_clk_quirk_i2c(ddata, false); 1424 } 1425 1426 /* Watchdog timer needs a disable sequence after reset */ 1427 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1428 { 1429 int wps, spr, error; 1430 u32 val; 1431 1432 wps = 0x34; 1433 spr = 0x48; 1434 1435 sysc_write(ddata, spr, 0xaaaa); 1436 error = readl_poll_timeout(ddata->module_va + wps, val, 1437 !(val & 0x10), 100, 1438 MAX_MODULE_SOFTRESET_WAIT); 1439 if (error) 1440 dev_warn(ddata->dev, "wdt disable spr failed\n"); 1441 1442 sysc_write(ddata, wps, 0x5555); 1443 error = readl_poll_timeout(ddata->module_va + wps, val, 1444 !(val & 0x10), 100, 1445 MAX_MODULE_SOFTRESET_WAIT); 1446 if (error) 1447 dev_warn(ddata->dev, "wdt disable wps failed\n"); 1448 } 1449 1450 static void sysc_init_module_quirks(struct sysc *ddata) 1451 { 1452 if (ddata->legacy_mode || !ddata->name) 1453 return; 1454 1455 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1456 ddata->clk_enable_quirk = sysc_clk_enable_quirk_hdq1w; 1457 1458 return; 1459 } 1460 1461 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1462 ddata->clk_enable_quirk = sysc_clk_enable_quirk_i2c; 1463 ddata->clk_disable_quirk = sysc_clk_disable_quirk_i2c; 1464 1465 return; 1466 } 1467 1468 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) 1469 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1470 } 1471 1472 static int sysc_clockdomain_init(struct sysc *ddata) 1473 { 1474 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1475 struct clk *fck = NULL, *ick = NULL; 1476 int error; 1477 1478 if (!pdata || !pdata->init_clockdomain) 1479 return 0; 1480 1481 switch (ddata->nr_clocks) { 1482 case 2: 1483 ick = ddata->clocks[SYSC_ICK]; 1484 /* fallthrough */ 1485 case 1: 1486 fck = ddata->clocks[SYSC_FCK]; 1487 break; 1488 case 0: 1489 return 0; 1490 } 1491 1492 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1493 if (!error || error == -ENODEV) 1494 return 0; 1495 1496 return error; 1497 } 1498 1499 /* 1500 * Note that pdata->init_module() typically does a reset first. After 1501 * pdata->init_module() is done, PM runtime can be used for the interconnect 1502 * target module. 1503 */ 1504 static int sysc_legacy_init(struct sysc *ddata) 1505 { 1506 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1507 int error; 1508 1509 if (!pdata || !pdata->init_module) 1510 return 0; 1511 1512 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 1513 if (error == -EEXIST) 1514 error = 0; 1515 1516 return error; 1517 } 1518 1519 /** 1520 * sysc_rstctrl_reset_deassert - deassert rstctrl reset 1521 * @ddata: device driver data 1522 * @reset: reset before deassert 1523 * 1524 * A module can have both OCP softreset control and external rstctrl. 1525 * If more complicated rstctrl resets are needed, please handle these 1526 * directly from the child device driver and map only the module reset 1527 * for the parent interconnect target module device. 1528 * 1529 * Automatic reset of the module on init can be skipped with the 1530 * "ti,no-reset-on-init" device tree property. 1531 */ 1532 static int sysc_rstctrl_reset_deassert(struct sysc *ddata, bool reset) 1533 { 1534 int error, val; 1535 1536 if (!ddata->rsts) 1537 return 0; 1538 1539 if (reset) { 1540 error = reset_control_assert(ddata->rsts); 1541 if (error) 1542 return error; 1543 } 1544 1545 error = reset_control_deassert(ddata->rsts); 1546 if (error == -EEXIST) 1547 return 0; 1548 1549 error = readx_poll_timeout(reset_control_status, ddata->rsts, val, 1550 val == 0, 100, MAX_MODULE_SOFTRESET_WAIT); 1551 1552 return error; 1553 } 1554 1555 /* 1556 * Note that the caller must ensure the interconnect target module is enabled 1557 * before calling reset. Otherwise reset will not complete. 1558 */ 1559 static int sysc_reset(struct sysc *ddata) 1560 { 1561 int sysc_offset, syss_offset, sysc_val, rstval, quirks, error = 0; 1562 u32 sysc_mask, syss_done; 1563 1564 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 1565 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 1566 quirks = ddata->cfg.quirks; 1567 1568 if (ddata->legacy_mode || sysc_offset < 0 || 1569 ddata->cap->regbits->srst_shift < 0 || 1570 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 1571 return 0; 1572 1573 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 1574 1575 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 1576 syss_done = 0; 1577 else 1578 syss_done = ddata->cfg.syss_mask; 1579 1580 if (ddata->clk_disable_quirk) 1581 ddata->clk_disable_quirk(ddata); 1582 1583 sysc_val = sysc_read_sysconfig(ddata); 1584 sysc_val |= sysc_mask; 1585 sysc_write(ddata, sysc_offset, sysc_val); 1586 1587 if (ddata->clk_enable_quirk) 1588 ddata->clk_enable_quirk(ddata); 1589 1590 /* Poll on reset status */ 1591 if (syss_offset >= 0) { 1592 error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval, 1593 (rstval & ddata->cfg.syss_mask) == 1594 syss_done, 1595 100, MAX_MODULE_SOFTRESET_WAIT); 1596 1597 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 1598 error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval, 1599 !(rstval & sysc_mask), 1600 100, MAX_MODULE_SOFTRESET_WAIT); 1601 } 1602 1603 if (ddata->reset_done_quirk) 1604 ddata->reset_done_quirk(ddata); 1605 1606 return error; 1607 } 1608 1609 /* 1610 * At this point the module is configured enough to read the revision but 1611 * module may not be completely configured yet to use PM runtime. Enable 1612 * all clocks directly during init to configure the quirks needed for PM 1613 * runtime based on the revision register. 1614 */ 1615 static int sysc_init_module(struct sysc *ddata) 1616 { 1617 int error = 0; 1618 bool manage_clocks = true; 1619 1620 error = sysc_rstctrl_reset_deassert(ddata, false); 1621 if (error) 1622 return error; 1623 1624 if (ddata->cfg.quirks & 1625 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT)) 1626 manage_clocks = false; 1627 1628 error = sysc_clockdomain_init(ddata); 1629 if (error) 1630 return error; 1631 1632 if (manage_clocks) { 1633 sysc_clkdm_deny_idle(ddata); 1634 1635 error = sysc_enable_opt_clocks(ddata); 1636 if (error) 1637 return error; 1638 1639 error = sysc_enable_main_clocks(ddata); 1640 if (error) 1641 goto err_opt_clocks; 1642 } 1643 1644 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 1645 error = sysc_rstctrl_reset_deassert(ddata, true); 1646 if (error) 1647 goto err_main_clocks; 1648 } 1649 1650 ddata->revision = sysc_read_revision(ddata); 1651 sysc_init_revision_quirks(ddata); 1652 sysc_init_module_quirks(ddata); 1653 1654 if (ddata->legacy_mode) { 1655 error = sysc_legacy_init(ddata); 1656 if (error) 1657 goto err_main_clocks; 1658 } 1659 1660 if (!ddata->legacy_mode && manage_clocks) { 1661 error = sysc_enable_module(ddata->dev); 1662 if (error) 1663 goto err_main_clocks; 1664 } 1665 1666 error = sysc_reset(ddata); 1667 if (error) 1668 dev_err(ddata->dev, "Reset failed with %d\n", error); 1669 1670 if (!ddata->legacy_mode && manage_clocks) 1671 sysc_disable_module(ddata->dev); 1672 1673 err_main_clocks: 1674 if (manage_clocks) 1675 sysc_disable_main_clocks(ddata); 1676 err_opt_clocks: 1677 if (manage_clocks) { 1678 sysc_disable_opt_clocks(ddata); 1679 sysc_clkdm_allow_idle(ddata); 1680 } 1681 1682 return error; 1683 } 1684 1685 static int sysc_init_sysc_mask(struct sysc *ddata) 1686 { 1687 struct device_node *np = ddata->dev->of_node; 1688 int error; 1689 u32 val; 1690 1691 error = of_property_read_u32(np, "ti,sysc-mask", &val); 1692 if (error) 1693 return 0; 1694 1695 if (val) 1696 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 1697 else 1698 ddata->cfg.sysc_val = ddata->cap->sysc_mask; 1699 1700 return 0; 1701 } 1702 1703 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 1704 const char *name) 1705 { 1706 struct device_node *np = ddata->dev->of_node; 1707 struct property *prop; 1708 const __be32 *p; 1709 u32 val; 1710 1711 of_property_for_each_u32(np, name, prop, p, val) { 1712 if (val >= SYSC_NR_IDLEMODES) { 1713 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 1714 return -EINVAL; 1715 } 1716 *idlemodes |= (1 << val); 1717 } 1718 1719 return 0; 1720 } 1721 1722 static int sysc_init_idlemodes(struct sysc *ddata) 1723 { 1724 int error; 1725 1726 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 1727 "ti,sysc-midle"); 1728 if (error) 1729 return error; 1730 1731 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 1732 "ti,sysc-sidle"); 1733 if (error) 1734 return error; 1735 1736 return 0; 1737 } 1738 1739 /* 1740 * Only some devices on omap4 and later have SYSCONFIG reset done 1741 * bit. We can detect this if there is no SYSSTATUS at all, or the 1742 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 1743 * have multiple bits for the child devices like OHCI and EHCI. 1744 * Depends on SYSC being parsed first. 1745 */ 1746 static int sysc_init_syss_mask(struct sysc *ddata) 1747 { 1748 struct device_node *np = ddata->dev->of_node; 1749 int error; 1750 u32 val; 1751 1752 error = of_property_read_u32(np, "ti,syss-mask", &val); 1753 if (error) { 1754 if ((ddata->cap->type == TI_SYSC_OMAP4 || 1755 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 1756 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 1757 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 1758 1759 return 0; 1760 } 1761 1762 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 1763 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 1764 1765 ddata->cfg.syss_mask = val; 1766 1767 return 0; 1768 } 1769 1770 /* 1771 * Many child device drivers need to have fck and opt clocks available 1772 * to get the clock rate for device internal configuration etc. 1773 */ 1774 static int sysc_child_add_named_clock(struct sysc *ddata, 1775 struct device *child, 1776 const char *name) 1777 { 1778 struct clk *clk; 1779 struct clk_lookup *l; 1780 int error = 0; 1781 1782 if (!name) 1783 return 0; 1784 1785 clk = clk_get(child, name); 1786 if (!IS_ERR(clk)) { 1787 clk_put(clk); 1788 1789 return -EEXIST; 1790 } 1791 1792 clk = clk_get(ddata->dev, name); 1793 if (IS_ERR(clk)) 1794 return -ENODEV; 1795 1796 l = clkdev_create(clk, name, dev_name(child)); 1797 if (!l) 1798 error = -ENOMEM; 1799 1800 clk_put(clk); 1801 1802 return error; 1803 } 1804 1805 static int sysc_child_add_clocks(struct sysc *ddata, 1806 struct device *child) 1807 { 1808 int i, error; 1809 1810 for (i = 0; i < ddata->nr_clocks; i++) { 1811 error = sysc_child_add_named_clock(ddata, 1812 child, 1813 ddata->clock_roles[i]); 1814 if (error && error != -EEXIST) { 1815 dev_err(ddata->dev, "could not add child clock %s: %i\n", 1816 ddata->clock_roles[i], error); 1817 1818 return error; 1819 } 1820 } 1821 1822 return 0; 1823 } 1824 1825 static struct device_type sysc_device_type = { 1826 }; 1827 1828 static struct sysc *sysc_child_to_parent(struct device *dev) 1829 { 1830 struct device *parent = dev->parent; 1831 1832 if (!parent || parent->type != &sysc_device_type) 1833 return NULL; 1834 1835 return dev_get_drvdata(parent); 1836 } 1837 1838 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 1839 { 1840 struct sysc *ddata; 1841 int error; 1842 1843 ddata = sysc_child_to_parent(dev); 1844 1845 error = pm_generic_runtime_suspend(dev); 1846 if (error) 1847 return error; 1848 1849 if (!ddata->enabled) 1850 return 0; 1851 1852 return sysc_runtime_suspend(ddata->dev); 1853 } 1854 1855 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 1856 { 1857 struct sysc *ddata; 1858 int error; 1859 1860 ddata = sysc_child_to_parent(dev); 1861 1862 if (!ddata->enabled) { 1863 error = sysc_runtime_resume(ddata->dev); 1864 if (error < 0) 1865 dev_err(ddata->dev, 1866 "%s error: %i\n", __func__, error); 1867 } 1868 1869 return pm_generic_runtime_resume(dev); 1870 } 1871 1872 #ifdef CONFIG_PM_SLEEP 1873 static int sysc_child_suspend_noirq(struct device *dev) 1874 { 1875 struct sysc *ddata; 1876 int error; 1877 1878 ddata = sysc_child_to_parent(dev); 1879 1880 dev_dbg(ddata->dev, "%s %s\n", __func__, 1881 ddata->name ? ddata->name : ""); 1882 1883 error = pm_generic_suspend_noirq(dev); 1884 if (error) { 1885 dev_err(dev, "%s error at %i: %i\n", 1886 __func__, __LINE__, error); 1887 1888 return error; 1889 } 1890 1891 if (!pm_runtime_status_suspended(dev)) { 1892 error = pm_generic_runtime_suspend(dev); 1893 if (error) { 1894 dev_dbg(dev, "%s busy at %i: %i\n", 1895 __func__, __LINE__, error); 1896 1897 return 0; 1898 } 1899 1900 error = sysc_runtime_suspend(ddata->dev); 1901 if (error) { 1902 dev_err(dev, "%s error at %i: %i\n", 1903 __func__, __LINE__, error); 1904 1905 return error; 1906 } 1907 1908 ddata->child_needs_resume = true; 1909 } 1910 1911 return 0; 1912 } 1913 1914 static int sysc_child_resume_noirq(struct device *dev) 1915 { 1916 struct sysc *ddata; 1917 int error; 1918 1919 ddata = sysc_child_to_parent(dev); 1920 1921 dev_dbg(ddata->dev, "%s %s\n", __func__, 1922 ddata->name ? ddata->name : ""); 1923 1924 if (ddata->child_needs_resume) { 1925 ddata->child_needs_resume = false; 1926 1927 error = sysc_runtime_resume(ddata->dev); 1928 if (error) 1929 dev_err(ddata->dev, 1930 "%s runtime resume error: %i\n", 1931 __func__, error); 1932 1933 error = pm_generic_runtime_resume(dev); 1934 if (error) 1935 dev_err(ddata->dev, 1936 "%s generic runtime resume: %i\n", 1937 __func__, error); 1938 } 1939 1940 return pm_generic_resume_noirq(dev); 1941 } 1942 #endif 1943 1944 static struct dev_pm_domain sysc_child_pm_domain = { 1945 .ops = { 1946 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 1947 sysc_child_runtime_resume, 1948 NULL) 1949 USE_PLATFORM_PM_SLEEP_OPS 1950 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 1951 sysc_child_resume_noirq) 1952 } 1953 }; 1954 1955 /** 1956 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 1957 * @ddata: device driver data 1958 * @child: child device driver 1959 * 1960 * Allow idle for child devices as done with _od_runtime_suspend(). 1961 * Otherwise many child devices will not idle because of the permanent 1962 * parent usecount set in pm_runtime_irq_safe(). 1963 * 1964 * Note that the long term solution is to just modify the child device 1965 * drivers to not set pm_runtime_irq_safe() and then this can be just 1966 * dropped. 1967 */ 1968 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 1969 { 1970 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 1971 dev_pm_domain_set(child, &sysc_child_pm_domain); 1972 } 1973 1974 static int sysc_notifier_call(struct notifier_block *nb, 1975 unsigned long event, void *device) 1976 { 1977 struct device *dev = device; 1978 struct sysc *ddata; 1979 int error; 1980 1981 ddata = sysc_child_to_parent(dev); 1982 if (!ddata) 1983 return NOTIFY_DONE; 1984 1985 switch (event) { 1986 case BUS_NOTIFY_ADD_DEVICE: 1987 error = sysc_child_add_clocks(ddata, dev); 1988 if (error) 1989 return error; 1990 sysc_legacy_idle_quirk(ddata, dev); 1991 break; 1992 default: 1993 break; 1994 } 1995 1996 return NOTIFY_DONE; 1997 } 1998 1999 static struct notifier_block sysc_nb = { 2000 .notifier_call = sysc_notifier_call, 2001 }; 2002 2003 /* Device tree configured quirks */ 2004 struct sysc_dts_quirk { 2005 const char *name; 2006 u32 mask; 2007 }; 2008 2009 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2010 { .name = "ti,no-idle-on-init", 2011 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2012 { .name = "ti,no-reset-on-init", 2013 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2014 { .name = "ti,no-idle", 2015 .mask = SYSC_QUIRK_NO_IDLE, }, 2016 }; 2017 2018 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2019 bool is_child) 2020 { 2021 const struct property *prop; 2022 int i, len; 2023 2024 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2025 const char *name = sysc_dts_quirks[i].name; 2026 2027 prop = of_get_property(np, name, &len); 2028 if (!prop) 2029 continue; 2030 2031 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2032 if (is_child) { 2033 dev_warn(ddata->dev, 2034 "dts flag should be at module level for %s\n", 2035 name); 2036 } 2037 } 2038 } 2039 2040 static int sysc_init_dts_quirks(struct sysc *ddata) 2041 { 2042 struct device_node *np = ddata->dev->of_node; 2043 int error; 2044 u32 val; 2045 2046 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2047 2048 sysc_parse_dts_quirks(ddata, np, false); 2049 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2050 if (!error) { 2051 if (val > 255) { 2052 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2053 val); 2054 } 2055 2056 ddata->cfg.srst_udelay = (u8)val; 2057 } 2058 2059 return 0; 2060 } 2061 2062 static void sysc_unprepare(struct sysc *ddata) 2063 { 2064 int i; 2065 2066 if (!ddata->clocks) 2067 return; 2068 2069 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2070 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2071 clk_unprepare(ddata->clocks[i]); 2072 } 2073 } 2074 2075 /* 2076 * Common sysc register bits found on omap2, also known as type1 2077 */ 2078 static const struct sysc_regbits sysc_regbits_omap2 = { 2079 .dmadisable_shift = -ENODEV, 2080 .midle_shift = 12, 2081 .sidle_shift = 3, 2082 .clkact_shift = 8, 2083 .emufree_shift = 5, 2084 .enwkup_shift = 2, 2085 .srst_shift = 1, 2086 .autoidle_shift = 0, 2087 }; 2088 2089 static const struct sysc_capabilities sysc_omap2 = { 2090 .type = TI_SYSC_OMAP2, 2091 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2092 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2093 SYSC_OMAP2_AUTOIDLE, 2094 .regbits = &sysc_regbits_omap2, 2095 }; 2096 2097 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2098 static const struct sysc_capabilities sysc_omap2_timer = { 2099 .type = TI_SYSC_OMAP2_TIMER, 2100 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2101 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2102 SYSC_OMAP2_AUTOIDLE, 2103 .regbits = &sysc_regbits_omap2, 2104 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2105 }; 2106 2107 /* 2108 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2109 * with different sidle position 2110 */ 2111 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2112 .dmadisable_shift = -ENODEV, 2113 .midle_shift = -ENODEV, 2114 .sidle_shift = 4, 2115 .clkact_shift = -ENODEV, 2116 .enwkup_shift = -ENODEV, 2117 .srst_shift = 1, 2118 .autoidle_shift = 0, 2119 .emufree_shift = -ENODEV, 2120 }; 2121 2122 static const struct sysc_capabilities sysc_omap3_sham = { 2123 .type = TI_SYSC_OMAP3_SHAM, 2124 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2125 .regbits = &sysc_regbits_omap3_sham, 2126 }; 2127 2128 /* 2129 * AES register bits found on omap3 and later, a variant of 2130 * sysc_regbits_omap2 with different sidle position 2131 */ 2132 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2133 .dmadisable_shift = -ENODEV, 2134 .midle_shift = -ENODEV, 2135 .sidle_shift = 6, 2136 .clkact_shift = -ENODEV, 2137 .enwkup_shift = -ENODEV, 2138 .srst_shift = 1, 2139 .autoidle_shift = 0, 2140 .emufree_shift = -ENODEV, 2141 }; 2142 2143 static const struct sysc_capabilities sysc_omap3_aes = { 2144 .type = TI_SYSC_OMAP3_AES, 2145 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2146 .regbits = &sysc_regbits_omap3_aes, 2147 }; 2148 2149 /* 2150 * Common sysc register bits found on omap4, also known as type2 2151 */ 2152 static const struct sysc_regbits sysc_regbits_omap4 = { 2153 .dmadisable_shift = 16, 2154 .midle_shift = 4, 2155 .sidle_shift = 2, 2156 .clkact_shift = -ENODEV, 2157 .enwkup_shift = -ENODEV, 2158 .emufree_shift = 1, 2159 .srst_shift = 0, 2160 .autoidle_shift = -ENODEV, 2161 }; 2162 2163 static const struct sysc_capabilities sysc_omap4 = { 2164 .type = TI_SYSC_OMAP4, 2165 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2166 SYSC_OMAP4_SOFTRESET, 2167 .regbits = &sysc_regbits_omap4, 2168 }; 2169 2170 static const struct sysc_capabilities sysc_omap4_timer = { 2171 .type = TI_SYSC_OMAP4_TIMER, 2172 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2173 SYSC_OMAP4_SOFTRESET, 2174 .regbits = &sysc_regbits_omap4, 2175 }; 2176 2177 /* 2178 * Common sysc register bits found on omap4, also known as type3 2179 */ 2180 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2181 .dmadisable_shift = -ENODEV, 2182 .midle_shift = 2, 2183 .sidle_shift = 0, 2184 .clkact_shift = -ENODEV, 2185 .enwkup_shift = -ENODEV, 2186 .srst_shift = -ENODEV, 2187 .emufree_shift = -ENODEV, 2188 .autoidle_shift = -ENODEV, 2189 }; 2190 2191 static const struct sysc_capabilities sysc_omap4_simple = { 2192 .type = TI_SYSC_OMAP4_SIMPLE, 2193 .regbits = &sysc_regbits_omap4_simple, 2194 }; 2195 2196 /* 2197 * SmartReflex sysc found on omap34xx 2198 */ 2199 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2200 .dmadisable_shift = -ENODEV, 2201 .midle_shift = -ENODEV, 2202 .sidle_shift = -ENODEV, 2203 .clkact_shift = 20, 2204 .enwkup_shift = -ENODEV, 2205 .srst_shift = -ENODEV, 2206 .emufree_shift = -ENODEV, 2207 .autoidle_shift = -ENODEV, 2208 }; 2209 2210 static const struct sysc_capabilities sysc_34xx_sr = { 2211 .type = TI_SYSC_OMAP34XX_SR, 2212 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2213 .regbits = &sysc_regbits_omap34xx_sr, 2214 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2215 SYSC_QUIRK_LEGACY_IDLE, 2216 }; 2217 2218 /* 2219 * SmartReflex sysc found on omap36xx and later 2220 */ 2221 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2222 .dmadisable_shift = -ENODEV, 2223 .midle_shift = -ENODEV, 2224 .sidle_shift = 24, 2225 .clkact_shift = -ENODEV, 2226 .enwkup_shift = 26, 2227 .srst_shift = -ENODEV, 2228 .emufree_shift = -ENODEV, 2229 .autoidle_shift = -ENODEV, 2230 }; 2231 2232 static const struct sysc_capabilities sysc_36xx_sr = { 2233 .type = TI_SYSC_OMAP36XX_SR, 2234 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2235 .regbits = &sysc_regbits_omap36xx_sr, 2236 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2237 }; 2238 2239 static const struct sysc_capabilities sysc_omap4_sr = { 2240 .type = TI_SYSC_OMAP4_SR, 2241 .regbits = &sysc_regbits_omap36xx_sr, 2242 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2243 }; 2244 2245 /* 2246 * McASP register bits found on omap4 and later 2247 */ 2248 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2249 .dmadisable_shift = -ENODEV, 2250 .midle_shift = -ENODEV, 2251 .sidle_shift = 0, 2252 .clkact_shift = -ENODEV, 2253 .enwkup_shift = -ENODEV, 2254 .srst_shift = -ENODEV, 2255 .emufree_shift = -ENODEV, 2256 .autoidle_shift = -ENODEV, 2257 }; 2258 2259 static const struct sysc_capabilities sysc_omap4_mcasp = { 2260 .type = TI_SYSC_OMAP4_MCASP, 2261 .regbits = &sysc_regbits_omap4_mcasp, 2262 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2263 }; 2264 2265 /* 2266 * McASP found on dra7 and later 2267 */ 2268 static const struct sysc_capabilities sysc_dra7_mcasp = { 2269 .type = TI_SYSC_OMAP4_SIMPLE, 2270 .regbits = &sysc_regbits_omap4_simple, 2271 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2272 }; 2273 2274 /* 2275 * FS USB host found on omap4 and later 2276 */ 2277 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2278 .dmadisable_shift = -ENODEV, 2279 .midle_shift = -ENODEV, 2280 .sidle_shift = 24, 2281 .clkact_shift = -ENODEV, 2282 .enwkup_shift = 26, 2283 .srst_shift = -ENODEV, 2284 .emufree_shift = -ENODEV, 2285 .autoidle_shift = -ENODEV, 2286 }; 2287 2288 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2289 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2290 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2291 .regbits = &sysc_regbits_omap4_usb_host_fs, 2292 }; 2293 2294 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2295 .dmadisable_shift = -ENODEV, 2296 .midle_shift = -ENODEV, 2297 .sidle_shift = -ENODEV, 2298 .clkact_shift = -ENODEV, 2299 .enwkup_shift = 4, 2300 .srst_shift = 0, 2301 .emufree_shift = -ENODEV, 2302 .autoidle_shift = -ENODEV, 2303 }; 2304 2305 static const struct sysc_capabilities sysc_dra7_mcan = { 2306 .type = TI_SYSC_DRA7_MCAN, 2307 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2308 .regbits = &sysc_regbits_dra7_mcan, 2309 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2310 }; 2311 2312 static int sysc_init_pdata(struct sysc *ddata) 2313 { 2314 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2315 struct ti_sysc_module_data *mdata; 2316 2317 if (!pdata) 2318 return 0; 2319 2320 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2321 if (!mdata) 2322 return -ENOMEM; 2323 2324 if (ddata->legacy_mode) { 2325 mdata->name = ddata->legacy_mode; 2326 mdata->module_pa = ddata->module_pa; 2327 mdata->module_size = ddata->module_size; 2328 mdata->offsets = ddata->offsets; 2329 mdata->nr_offsets = SYSC_MAX_REGS; 2330 mdata->cap = ddata->cap; 2331 mdata->cfg = &ddata->cfg; 2332 } 2333 2334 ddata->mdata = mdata; 2335 2336 return 0; 2337 } 2338 2339 static int sysc_init_match(struct sysc *ddata) 2340 { 2341 const struct sysc_capabilities *cap; 2342 2343 cap = of_device_get_match_data(ddata->dev); 2344 if (!cap) 2345 return -EINVAL; 2346 2347 ddata->cap = cap; 2348 if (ddata->cap) 2349 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2350 2351 return 0; 2352 } 2353 2354 static void ti_sysc_idle(struct work_struct *work) 2355 { 2356 struct sysc *ddata; 2357 2358 ddata = container_of(work, struct sysc, idle_work.work); 2359 2360 if (pm_runtime_active(ddata->dev)) 2361 pm_runtime_put_sync(ddata->dev); 2362 } 2363 2364 static const struct of_device_id sysc_match_table[] = { 2365 { .compatible = "simple-bus", }, 2366 { /* sentinel */ }, 2367 }; 2368 2369 static int sysc_probe(struct platform_device *pdev) 2370 { 2371 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 2372 struct sysc *ddata; 2373 int error; 2374 2375 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 2376 if (!ddata) 2377 return -ENOMEM; 2378 2379 ddata->dev = &pdev->dev; 2380 platform_set_drvdata(pdev, ddata); 2381 2382 error = sysc_init_match(ddata); 2383 if (error) 2384 return error; 2385 2386 error = sysc_init_dts_quirks(ddata); 2387 if (error) 2388 goto unprepare; 2389 2390 error = sysc_map_and_check_registers(ddata); 2391 if (error) 2392 goto unprepare; 2393 2394 error = sysc_init_sysc_mask(ddata); 2395 if (error) 2396 goto unprepare; 2397 2398 error = sysc_init_idlemodes(ddata); 2399 if (error) 2400 goto unprepare; 2401 2402 error = sysc_init_syss_mask(ddata); 2403 if (error) 2404 goto unprepare; 2405 2406 error = sysc_init_pdata(ddata); 2407 if (error) 2408 goto unprepare; 2409 2410 sysc_init_early_quirks(ddata); 2411 2412 error = sysc_get_clocks(ddata); 2413 if (error) 2414 return error; 2415 2416 error = sysc_init_resets(ddata); 2417 if (error) 2418 return error; 2419 2420 error = sysc_init_module(ddata); 2421 if (error) 2422 goto unprepare; 2423 2424 pm_runtime_enable(ddata->dev); 2425 error = pm_runtime_get_sync(ddata->dev); 2426 if (error < 0) { 2427 pm_runtime_put_noidle(ddata->dev); 2428 pm_runtime_disable(ddata->dev); 2429 goto unprepare; 2430 } 2431 2432 sysc_show_registers(ddata); 2433 2434 ddata->dev->type = &sysc_device_type; 2435 error = of_platform_populate(ddata->dev->of_node, sysc_match_table, 2436 pdata ? pdata->auxdata : NULL, 2437 ddata->dev); 2438 if (error) 2439 goto err; 2440 2441 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 2442 2443 /* At least earlycon won't survive without deferred idle */ 2444 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT | 2445 SYSC_QUIRK_NO_RESET_ON_INIT)) { 2446 schedule_delayed_work(&ddata->idle_work, 3000); 2447 } else { 2448 pm_runtime_put(&pdev->dev); 2449 } 2450 2451 if (!of_get_available_child_count(ddata->dev->of_node)) 2452 ddata->disable_on_idle = true; 2453 2454 return 0; 2455 2456 err: 2457 pm_runtime_put_sync(&pdev->dev); 2458 pm_runtime_disable(&pdev->dev); 2459 unprepare: 2460 sysc_unprepare(ddata); 2461 2462 return error; 2463 } 2464 2465 static int sysc_remove(struct platform_device *pdev) 2466 { 2467 struct sysc *ddata = platform_get_drvdata(pdev); 2468 int error; 2469 2470 cancel_delayed_work_sync(&ddata->idle_work); 2471 2472 error = pm_runtime_get_sync(ddata->dev); 2473 if (error < 0) { 2474 pm_runtime_put_noidle(ddata->dev); 2475 pm_runtime_disable(ddata->dev); 2476 goto unprepare; 2477 } 2478 2479 of_platform_depopulate(&pdev->dev); 2480 2481 pm_runtime_put_sync(&pdev->dev); 2482 pm_runtime_disable(&pdev->dev); 2483 reset_control_assert(ddata->rsts); 2484 2485 unprepare: 2486 sysc_unprepare(ddata); 2487 2488 return 0; 2489 } 2490 2491 static const struct of_device_id sysc_match[] = { 2492 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 2493 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 2494 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 2495 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 2496 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 2497 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 2498 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 2499 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 2500 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 2501 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 2502 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 2503 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 2504 { .compatible = "ti,sysc-usb-host-fs", 2505 .data = &sysc_omap4_usb_host_fs, }, 2506 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 2507 { }, 2508 }; 2509 MODULE_DEVICE_TABLE(of, sysc_match); 2510 2511 static struct platform_driver sysc_driver = { 2512 .probe = sysc_probe, 2513 .remove = sysc_remove, 2514 .driver = { 2515 .name = "ti-sysc", 2516 .of_match_table = sysc_match, 2517 .pm = &sysc_pm_ops, 2518 }, 2519 }; 2520 2521 static int __init sysc_init(void) 2522 { 2523 bus_register_notifier(&platform_bus_type, &sysc_nb); 2524 2525 return platform_driver_register(&sysc_driver); 2526 } 2527 module_init(sysc_init); 2528 2529 static void __exit sysc_exit(void) 2530 { 2531 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 2532 platform_driver_unregister(&sysc_driver); 2533 } 2534 module_exit(sysc_exit); 2535 2536 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 2537 MODULE_LICENSE("GPL v2"); 2538