1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timer.h> 18 #include <linux/workqueue.h> 19 20 #define MHI_PCI_DEFAULT_BAR_NUM 0 21 22 #define MHI_POST_RESET_DELAY_MS 2000 23 24 #define HEALTH_CHECK_PERIOD (HZ * 2) 25 26 /* PCI VID definitions */ 27 #define PCI_VENDOR_ID_THALES 0x1269 28 #define PCI_VENDOR_ID_QUECTEL 0x1eac 29 #define PCI_VENDOR_ID_NETPRISMA 0x203e 30 31 #define MHI_EDL_DB 91 32 #define MHI_EDL_COOKIE 0xEDEDEDED 33 34 /** 35 * struct mhi_pci_dev_info - MHI PCI device specific information 36 * @config: MHI controller configuration 37 * @vf_config: MHI controller configuration for Virtual function (optional) 38 * @name: name of the PCI module 39 * @fw: firmware path (if any) 40 * @edl: emergency download mode firmware path (if any) 41 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 42 * @bar_num: PCI base address register to use for MHI MMIO register space 43 * @dma_data_width: DMA transfer word size (32 or 64 bits) 44 * @vf_dma_data_width: DMA transfer word size for VF's (optional) 45 * @mru_default: default MRU size for MBIM network packets 46 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 47 * of inband wake support (such as sdx24) 48 * @no_m3: M3 not supported 49 * @reset_on_remove: Set true for devices that require SoC during driver removal 50 */ 51 struct mhi_pci_dev_info { 52 const struct mhi_controller_config *config; 53 const struct mhi_controller_config *vf_config; 54 const char *name; 55 const char *fw; 56 const char *edl; 57 bool edl_trigger; 58 unsigned int bar_num; 59 unsigned int dma_data_width; 60 unsigned int vf_dma_data_width; 61 unsigned int mru_default; 62 bool sideband_wake; 63 bool no_m3; 64 bool reset_on_remove; 65 }; 66 67 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 68 { \ 69 .num = ch_num, \ 70 .name = ch_name, \ 71 .num_elements = el_count, \ 72 .event_ring = ev_ring, \ 73 .dir = DMA_TO_DEVICE, \ 74 .ee_mask = BIT(MHI_EE_AMSS), \ 75 .pollcfg = 0, \ 76 .doorbell = MHI_DB_BRST_DISABLE, \ 77 .lpm_notify = false, \ 78 .offload_channel = false, \ 79 .doorbell_mode_switch = false, \ 80 } \ 81 82 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 83 { \ 84 .num = ch_num, \ 85 .name = ch_name, \ 86 .num_elements = el_count, \ 87 .event_ring = ev_ring, \ 88 .dir = DMA_FROM_DEVICE, \ 89 .ee_mask = BIT(MHI_EE_AMSS), \ 90 .pollcfg = 0, \ 91 .doorbell = MHI_DB_BRST_DISABLE, \ 92 .lpm_notify = false, \ 93 .offload_channel = false, \ 94 .doorbell_mode_switch = false, \ 95 } 96 97 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 98 { \ 99 .num_elements = el_count, \ 100 .irq_moderation_ms = 0, \ 101 .irq = (ev_ring) + 1, \ 102 .priority = 1, \ 103 .mode = MHI_DB_BRST_DISABLE, \ 104 .data_type = MHI_ER_CTRL, \ 105 .hardware_event = false, \ 106 .client_managed = false, \ 107 .offload_channel = false, \ 108 } 109 110 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 111 { \ 112 .num = ch_num, \ 113 .name = ch_name, \ 114 .num_elements = el_count, \ 115 .event_ring = ev_ring, \ 116 .dir = DMA_TO_DEVICE, \ 117 .ee_mask = BIT(MHI_EE_AMSS), \ 118 .pollcfg = 0, \ 119 .doorbell = MHI_DB_BRST_ENABLE, \ 120 .lpm_notify = false, \ 121 .offload_channel = false, \ 122 .doorbell_mode_switch = true, \ 123 } \ 124 125 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 126 { \ 127 .num = ch_num, \ 128 .name = ch_name, \ 129 .num_elements = el_count, \ 130 .event_ring = ev_ring, \ 131 .dir = DMA_FROM_DEVICE, \ 132 .ee_mask = BIT(MHI_EE_AMSS), \ 133 .pollcfg = 0, \ 134 .doorbell = MHI_DB_BRST_ENABLE, \ 135 .lpm_notify = false, \ 136 .offload_channel = false, \ 137 .doorbell_mode_switch = true, \ 138 } 139 140 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 141 { \ 142 .num = ch_num, \ 143 .name = ch_name, \ 144 .num_elements = el_count, \ 145 .event_ring = ev_ring, \ 146 .dir = DMA_TO_DEVICE, \ 147 .ee_mask = BIT(MHI_EE_SBL), \ 148 .pollcfg = 0, \ 149 .doorbell = MHI_DB_BRST_DISABLE, \ 150 .lpm_notify = false, \ 151 .offload_channel = false, \ 152 .doorbell_mode_switch = false, \ 153 } \ 154 155 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 156 { \ 157 .num = ch_num, \ 158 .name = ch_name, \ 159 .num_elements = el_count, \ 160 .event_ring = ev_ring, \ 161 .dir = DMA_FROM_DEVICE, \ 162 .ee_mask = BIT(MHI_EE_SBL), \ 163 .pollcfg = 0, \ 164 .doorbell = MHI_DB_BRST_DISABLE, \ 165 .lpm_notify = false, \ 166 .offload_channel = false, \ 167 .doorbell_mode_switch = false, \ 168 } 169 170 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 171 { \ 172 .num = ch_num, \ 173 .name = ch_name, \ 174 .num_elements = el_count, \ 175 .event_ring = ev_ring, \ 176 .dir = DMA_TO_DEVICE, \ 177 .ee_mask = BIT(MHI_EE_FP), \ 178 .pollcfg = 0, \ 179 .doorbell = MHI_DB_BRST_DISABLE, \ 180 .lpm_notify = false, \ 181 .offload_channel = false, \ 182 .doorbell_mode_switch = false, \ 183 } \ 184 185 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 186 { \ 187 .num = ch_num, \ 188 .name = ch_name, \ 189 .num_elements = el_count, \ 190 .event_ring = ev_ring, \ 191 .dir = DMA_FROM_DEVICE, \ 192 .ee_mask = BIT(MHI_EE_FP), \ 193 .pollcfg = 0, \ 194 .doorbell = MHI_DB_BRST_DISABLE, \ 195 .lpm_notify = false, \ 196 .offload_channel = false, \ 197 .doorbell_mode_switch = false, \ 198 } 199 200 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 201 { \ 202 .num_elements = el_count, \ 203 .irq_moderation_ms = 5, \ 204 .irq = (ev_ring) + 1, \ 205 .priority = 1, \ 206 .mode = MHI_DB_BRST_DISABLE, \ 207 .data_type = MHI_ER_DATA, \ 208 .hardware_event = false, \ 209 .client_managed = false, \ 210 .offload_channel = false, \ 211 } 212 213 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 214 { \ 215 .num_elements = el_count, \ 216 .irq_moderation_ms = 0, \ 217 .irq = (ev_ring) + 1, \ 218 .priority = 1, \ 219 .mode = MHI_DB_BRST_DISABLE, \ 220 .data_type = MHI_ER_DATA, \ 221 .hardware_event = false, \ 222 .client_managed = false, \ 223 .offload_channel = false, \ 224 } 225 226 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 227 { \ 228 .num_elements = el_count, \ 229 .irq_moderation_ms = 1, \ 230 .irq = (ev_ring) + 1, \ 231 .priority = 1, \ 232 .mode = MHI_DB_BRST_DISABLE, \ 233 .data_type = MHI_ER_DATA, \ 234 .hardware_event = true, \ 235 .client_managed = false, \ 236 .offload_channel = false, \ 237 .channel = ch_num, \ 238 } 239 240 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { 241 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), 242 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), 243 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), 244 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), 245 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), 246 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), 247 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), 248 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), 249 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), 250 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), 251 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), 252 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), 253 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), 254 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), 255 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), 256 MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6), 257 MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6), 258 MHI_CHANNEL_CONFIG_UL(50, "IP_ETH0", 256, 7), 259 MHI_CHANNEL_CONFIG_DL(51, "IP_ETH0", 256, 7), 260 MHI_CHANNEL_CONFIG_UL(52, "IP_ETH1", 256, 8), 261 MHI_CHANNEL_CONFIG_DL(53, "IP_ETH1", 256, 8), 262 263 }; 264 265 static struct mhi_event_config mhi_qcom_qdu100_events[] = { 266 /* first ring is control+data ring */ 267 MHI_EVENT_CONFIG_CTRL(0, 64), 268 /* SAHARA dedicated event ring */ 269 MHI_EVENT_CONFIG_SW_DATA(1, 256), 270 /* Software channels dedicated event ring */ 271 MHI_EVENT_CONFIG_SW_DATA(2, 64), 272 MHI_EVENT_CONFIG_SW_DATA(3, 256), 273 MHI_EVENT_CONFIG_SW_DATA(4, 256), 274 /* Software IP channels dedicated event ring */ 275 MHI_EVENT_CONFIG_SW_DATA(5, 512), 276 MHI_EVENT_CONFIG_SW_DATA(6, 512), 277 MHI_EVENT_CONFIG_SW_DATA(7, 512), 278 MHI_EVENT_CONFIG_SW_DATA(8, 512), 279 }; 280 281 static const struct mhi_controller_config mhi_qcom_qdu100_config = { 282 .max_channels = 128, 283 .timeout_ms = 120000, 284 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), 285 .ch_cfg = mhi_qcom_qdu100_channels, 286 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), 287 .event_cfg = mhi_qcom_qdu100_events, 288 }; 289 290 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { 291 .name = "qcom-qdu100", 292 .fw = "qcom/qdu100/xbl_s.melf", 293 .edl_trigger = true, 294 .config = &mhi_qcom_qdu100_config, 295 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 296 .dma_data_width = 32, 297 .vf_dma_data_width = 40, 298 .sideband_wake = false, 299 .no_m3 = true, 300 .reset_on_remove = true, 301 }; 302 303 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { 304 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), 305 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), 306 }; 307 308 static struct mhi_event_config mhi_qcom_sa8775p_events[] = { 309 /* first ring is control+data ring */ 310 MHI_EVENT_CONFIG_CTRL(0, 64), 311 /* Software channels dedicated event ring */ 312 MHI_EVENT_CONFIG_SW_DATA(1, 64), 313 MHI_EVENT_CONFIG_SW_DATA(2, 64), 314 }; 315 316 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 317 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 318 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 319 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 320 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 321 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 322 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 323 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 324 MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), 325 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 326 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 327 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 328 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 329 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 330 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 331 }; 332 333 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 334 /* first ring is control+data ring */ 335 MHI_EVENT_CONFIG_CTRL(0, 64), 336 /* DIAG dedicated event ring */ 337 MHI_EVENT_CONFIG_DATA(1, 128), 338 /* Software channels dedicated event ring */ 339 MHI_EVENT_CONFIG_SW_DATA(2, 64), 340 MHI_EVENT_CONFIG_SW_DATA(3, 64), 341 /* Hardware channels request dedicated hardware event rings */ 342 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 343 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 344 }; 345 346 static const struct mhi_controller_config mhi_qcom_sa8775p_config = { 347 .max_channels = 128, 348 .timeout_ms = 8000, 349 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels), 350 .ch_cfg = mhi_qcom_sa8775p_channels, 351 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events), 352 .event_cfg = mhi_qcom_sa8775p_events, 353 }; 354 355 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 356 .max_channels = 128, 357 .timeout_ms = 8000, 358 .ready_timeout_ms = 50000, 359 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 360 .ch_cfg = modem_qcom_v1_mhi_channels, 361 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 362 .event_cfg = modem_qcom_v1_mhi_events, 363 }; 364 365 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 366 .max_channels = 128, 367 .timeout_ms = 8000, 368 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 369 .ch_cfg = modem_qcom_v1_mhi_channels, 370 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 371 .event_cfg = modem_qcom_v1_mhi_events, 372 }; 373 374 static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { 375 .name = "qcom-sa8775p", 376 .edl_trigger = false, 377 .config = &mhi_qcom_sa8775p_config, 378 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 379 .dma_data_width = 32, 380 .mru_default = 32768, 381 .sideband_wake = false, 382 }; 383 384 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 385 .name = "qcom-sdx75m", 386 .fw = "qcom/sdx75m/xbl.elf", 387 .edl = "qcom/sdx75m/edl.mbn", 388 .edl_trigger = true, 389 .config = &modem_qcom_v2_mhiv_config, 390 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 391 .dma_data_width = 32, 392 .sideband_wake = false, 393 }; 394 395 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 396 .name = "qcom-sdx65m", 397 .fw = "qcom/sdx65m/xbl.elf", 398 .edl = "qcom/sdx65m/edl.mbn", 399 .edl_trigger = true, 400 .config = &modem_qcom_v1_mhiv_config, 401 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 402 .dma_data_width = 32, 403 .sideband_wake = false, 404 }; 405 406 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 407 .name = "qcom-sdx55m", 408 .fw = "qcom/sdx55m/sbl1.mbn", 409 .edl = "qcom/sdx55m/edl.mbn", 410 .edl_trigger = true, 411 .config = &modem_qcom_v1_mhiv_config, 412 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 413 .dma_data_width = 32, 414 .mru_default = 32768, 415 .sideband_wake = false, 416 }; 417 418 static const struct mhi_pci_dev_info mhi_qcom_sdx35_info = { 419 .name = "qcom-sdx35m", 420 .config = &modem_qcom_v2_mhiv_config, 421 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 422 .dma_data_width = 32, 423 .mru_default = 32768, 424 .sideband_wake = false, 425 .edl_trigger = true, 426 }; 427 428 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 429 .name = "qcom-sdx24", 430 .edl = "qcom/prog_firehose_sdx24.mbn", 431 .config = &modem_qcom_v1_mhiv_config, 432 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 433 .dma_data_width = 32, 434 .sideband_wake = true, 435 }; 436 437 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 438 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 439 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 440 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 441 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 442 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 443 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 444 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 445 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 446 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 447 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 448 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 449 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 450 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 451 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 452 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 453 }; 454 455 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 456 MHI_EVENT_CONFIG_CTRL(0, 128), 457 MHI_EVENT_CONFIG_DATA(1, 128), 458 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 459 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 460 }; 461 462 static const struct mhi_controller_config modem_quectel_em1xx_config = { 463 .max_channels = 128, 464 .timeout_ms = 20000, 465 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 466 .ch_cfg = mhi_quectel_em1xx_channels, 467 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 468 .event_cfg = mhi_quectel_em1xx_events, 469 }; 470 471 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 472 .name = "quectel-em1xx", 473 .edl = "qcom/prog_firehose_sdx24.mbn", 474 .config = &modem_quectel_em1xx_config, 475 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 476 .dma_data_width = 32, 477 .mru_default = 32768, 478 .sideband_wake = true, 479 }; 480 481 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 482 .name = "quectel-rm5xx", 483 .edl = "qcom/prog_firehose_sdx6x.elf", 484 .config = &modem_quectel_em1xx_config, 485 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 486 .dma_data_width = 32, 487 .mru_default = 32768, 488 .sideband_wake = true, 489 }; 490 491 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 492 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 493 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 494 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 495 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 496 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 497 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 498 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 499 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 500 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 501 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 502 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 503 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 504 }; 505 506 static const struct mhi_channel_config mhi_foxconn_sdx61_channels[] = { 507 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 508 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 509 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 510 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 511 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 512 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 513 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 514 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 515 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 516 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 517 MHI_CHANNEL_CONFIG_UL(50, "NMEA", 32, 0), 518 MHI_CHANNEL_CONFIG_DL(51, "NMEA", 32, 0), 519 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 520 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 521 }; 522 523 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 524 MHI_EVENT_CONFIG_CTRL(0, 128), 525 MHI_EVENT_CONFIG_DATA(1, 128), 526 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 527 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 528 }; 529 530 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 531 .max_channels = 128, 532 .timeout_ms = 20000, 533 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 534 .ch_cfg = mhi_foxconn_sdx55_channels, 535 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 536 .event_cfg = mhi_foxconn_sdx55_events, 537 }; 538 539 static const struct mhi_controller_config modem_foxconn_sdx61_config = { 540 .max_channels = 128, 541 .timeout_ms = 20000, 542 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx61_channels), 543 .ch_cfg = mhi_foxconn_sdx61_channels, 544 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 545 .event_cfg = mhi_foxconn_sdx55_events, 546 }; 547 548 static const struct mhi_controller_config modem_foxconn_sdx72_config = { 549 .max_channels = 128, 550 .timeout_ms = 20000, 551 .ready_timeout_ms = 50000, 552 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 553 .ch_cfg = mhi_foxconn_sdx55_channels, 554 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 555 .event_cfg = mhi_foxconn_sdx55_events, 556 }; 557 558 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 559 .name = "foxconn-sdx55", 560 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 561 .edl_trigger = true, 562 .config = &modem_foxconn_sdx55_config, 563 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 564 .dma_data_width = 32, 565 .mru_default = 32768, 566 .sideband_wake = false, 567 }; 568 569 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 570 .name = "foxconn-t99w175", 571 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 572 .edl_trigger = true, 573 .config = &modem_foxconn_sdx55_config, 574 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 575 .dma_data_width = 32, 576 .mru_default = 32768, 577 .sideband_wake = false, 578 }; 579 580 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 581 .name = "foxconn-dw5930e", 582 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 583 .edl_trigger = true, 584 .config = &modem_foxconn_sdx55_config, 585 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 586 .dma_data_width = 32, 587 .mru_default = 32768, 588 .sideband_wake = false, 589 }; 590 591 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 592 .name = "foxconn-t99w368", 593 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 594 .edl_trigger = true, 595 .config = &modem_foxconn_sdx55_config, 596 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 597 .dma_data_width = 32, 598 .mru_default = 32768, 599 .sideband_wake = false, 600 }; 601 602 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 603 .name = "foxconn-t99w373", 604 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 605 .edl_trigger = true, 606 .config = &modem_foxconn_sdx55_config, 607 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 608 .dma_data_width = 32, 609 .mru_default = 32768, 610 .sideband_wake = false, 611 }; 612 613 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 614 .name = "foxconn-t99w510", 615 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn", 616 .edl_trigger = true, 617 .config = &modem_foxconn_sdx55_config, 618 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 619 .dma_data_width = 32, 620 .mru_default = 32768, 621 .sideband_wake = false, 622 }; 623 624 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 625 .name = "foxconn-dw5932e", 626 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 627 .edl_trigger = true, 628 .config = &modem_foxconn_sdx55_config, 629 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 630 .dma_data_width = 32, 631 .mru_default = 32768, 632 .sideband_wake = false, 633 }; 634 635 static const struct mhi_pci_dev_info mhi_foxconn_t99w640_info = { 636 .name = "foxconn-t99w640", 637 .edl = "qcom/sdx72m/foxconn/edl.mbn", 638 .edl_trigger = true, 639 .config = &modem_foxconn_sdx72_config, 640 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 641 .dma_data_width = 32, 642 .mru_default = 32768, 643 .sideband_wake = false, 644 }; 645 646 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 647 .name = "foxconn-dw5934e", 648 .edl = "qcom/sdx72m/foxconn/edl.mbn", 649 .edl_trigger = true, 650 .config = &modem_foxconn_sdx72_config, 651 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 652 .dma_data_width = 32, 653 .mru_default = 32768, 654 .sideband_wake = false, 655 }; 656 657 static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = { 658 .name = "foxconn-t99w696", 659 .edl = "qcom/sdx61/foxconn/prog_firehose_lite.elf", 660 .edl_trigger = true, 661 .config = &modem_foxconn_sdx61_config, 662 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 663 .dma_data_width = 32, 664 .mru_default = 32768, 665 .sideband_wake = false, 666 }; 667 668 static const struct mhi_pci_dev_info mhi_foxconn_t99w760_info = { 669 .name = "foxconn-t99w760", 670 .edl = "qcom/sdx35/foxconn/xbl_s_devprg_ns.melf", 671 .edl_trigger = true, 672 .config = &modem_foxconn_sdx61_config, 673 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 674 .dma_data_width = 32, 675 .mru_default = 32768, 676 .sideband_wake = false, 677 }; 678 679 static const struct mhi_channel_config mhi_mv3x_channels[] = { 680 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 681 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 682 /* MBIM Control Channel */ 683 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 684 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 685 /* MBIM Data Channel */ 686 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 687 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 688 }; 689 690 static struct mhi_event_config mhi_mv3x_events[] = { 691 MHI_EVENT_CONFIG_CTRL(0, 256), 692 MHI_EVENT_CONFIG_DATA(1, 256), 693 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 694 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 695 }; 696 697 static const struct mhi_controller_config modem_mv3x_config = { 698 .max_channels = 128, 699 .timeout_ms = 20000, 700 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 701 .ch_cfg = mhi_mv3x_channels, 702 .num_events = ARRAY_SIZE(mhi_mv3x_events), 703 .event_cfg = mhi_mv3x_events, 704 }; 705 706 static const struct mhi_pci_dev_info mhi_mv31_info = { 707 .name = "cinterion-mv31", 708 .config = &modem_mv3x_config, 709 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 710 .dma_data_width = 32, 711 .mru_default = 32768, 712 }; 713 714 static const struct mhi_pci_dev_info mhi_mv32_info = { 715 .name = "cinterion-mv32", 716 .config = &modem_mv3x_config, 717 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 718 .dma_data_width = 32, 719 .mru_default = 32768, 720 }; 721 722 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 723 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 724 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 725 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 726 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 727 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 728 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 729 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 730 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 731 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 732 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 733 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 734 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 735 }; 736 737 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 738 /* first ring is control+data and DIAG ring */ 739 MHI_EVENT_CONFIG_CTRL(0, 2048), 740 /* Hardware channels request dedicated hardware event rings */ 741 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 742 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 743 }; 744 745 static const struct mhi_controller_config modem_sierra_em919x_config = { 746 .max_channels = 128, 747 .timeout_ms = 24000, 748 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 749 .ch_cfg = mhi_sierra_em919x_channels, 750 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 751 .event_cfg = modem_sierra_em919x_mhi_events, 752 }; 753 754 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 755 .name = "sierra-em919x", 756 .config = &modem_sierra_em919x_config, 757 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 758 .dma_data_width = 32, 759 .mru_default = 32768, 760 .sideband_wake = false, 761 }; 762 763 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 764 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 765 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 766 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 767 MHI_CHANNEL_CONFIG_DL(21, "IPCR", 16, 0), 768 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 769 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 770 }; 771 772 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 773 MHI_EVENT_CONFIG_CTRL(0, 128), 774 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 775 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 776 }; 777 778 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 779 .max_channels = 128, 780 .timeout_ms = 20000, 781 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 782 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 783 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 784 .event_cfg = mhi_telit_fn980_hw_v1_events, 785 }; 786 787 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 788 .name = "telit-fn980-hwv1", 789 .fw = "qcom/sdx55m/sbl1.mbn", 790 .edl = "qcom/sdx55m/edl.mbn", 791 .config = &modem_telit_fn980_hw_v1_config, 792 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 793 .dma_data_width = 32, 794 .mru_default = 32768, 795 .sideband_wake = false, 796 }; 797 798 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 799 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 800 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 801 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 802 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 803 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 804 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 805 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 806 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 807 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 808 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 809 MHI_CHANNEL_CONFIG_UL(94, "NMEA", 32, 1), 810 MHI_CHANNEL_CONFIG_DL(95, "NMEA", 32, 1), 811 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 812 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 813 }; 814 815 static struct mhi_event_config mhi_telit_fn990_events[] = { 816 MHI_EVENT_CONFIG_CTRL(0, 128), 817 MHI_EVENT_CONFIG_DATA(1, 128), 818 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 819 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 820 }; 821 822 static const struct mhi_controller_config modem_telit_fn990_config = { 823 .max_channels = 128, 824 .timeout_ms = 20000, 825 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 826 .ch_cfg = mhi_telit_fn990_channels, 827 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 828 .event_cfg = mhi_telit_fn990_events, 829 }; 830 831 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 832 .name = "telit-fn990", 833 .config = &modem_telit_fn990_config, 834 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 835 .dma_data_width = 32, 836 .sideband_wake = false, 837 .mru_default = 32768, 838 }; 839 840 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = { 841 .name = "telit-fe990a", 842 .config = &modem_telit_fn990_config, 843 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 844 .dma_data_width = 32, 845 .sideband_wake = false, 846 .mru_default = 32768, 847 }; 848 849 static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = { 850 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 851 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 852 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 853 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 854 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 855 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 856 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 857 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 858 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 859 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 860 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 861 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 862 MHI_CHANNEL_CONFIG_UL(94, "NMEA", 32, 1), 863 MHI_CHANNEL_CONFIG_DL(95, "NMEA", 32, 1), 864 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 865 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 866 }; 867 868 static const struct mhi_controller_config modem_telit_fn920c04_config = { 869 .max_channels = 128, 870 .timeout_ms = 50000, 871 .num_channels = ARRAY_SIZE(mhi_telit_fn920c04_channels), 872 .ch_cfg = mhi_telit_fn920c04_channels, 873 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 874 .event_cfg = mhi_telit_fn990_events, 875 }; 876 877 static const struct mhi_pci_dev_info mhi_telit_fn920c04_info = { 878 .name = "telit-fn920c04", 879 .config = &modem_telit_fn920c04_config, 880 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 881 .dma_data_width = 32, 882 .sideband_wake = false, 883 .mru_default = 32768, 884 .edl_trigger = true, 885 }; 886 887 static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = { 888 .name = "telit-fn990b40", 889 .config = &modem_telit_fn920c04_config, 890 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 891 .dma_data_width = 32, 892 .sideband_wake = false, 893 .mru_default = 32768, 894 .edl_trigger = true, 895 }; 896 897 static const struct mhi_pci_dev_info mhi_telit_fe990b40_info = { 898 .name = "telit-fe990b40", 899 .config = &modem_telit_fn920c04_config, 900 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 901 .dma_data_width = 32, 902 .sideband_wake = false, 903 .mru_default = 32768, 904 .edl_trigger = true, 905 }; 906 907 static const struct mhi_pci_dev_info mhi_telit_fe912c04_info = { 908 .name = "telit-fe912c04", 909 .config = &modem_telit_fn920c04_config, 910 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 911 .dma_data_width = 32, 912 .sideband_wake = false, 913 .mru_default = 32768, 914 .edl_trigger = true, 915 }; 916 917 static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { 918 .name = "netprisma-lcur57", 919 .edl = "qcom/prog_firehose_sdx24.mbn", 920 .config = &modem_quectel_em1xx_config, 921 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 922 .dma_data_width = 32, 923 .mru_default = 32768, 924 .sideband_wake = true, 925 }; 926 927 static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { 928 .name = "netprisma-fcun69", 929 .edl = "qcom/prog_firehose_sdx6x.elf", 930 .config = &modem_quectel_em1xx_config, 931 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 932 .dma_data_width = 32, 933 .mru_default = 32768, 934 .sideband_wake = true, 935 }; 936 937 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 938 static const struct pci_device_id mhi_pci_id_table[] = { 939 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), 940 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, 941 /* Telit FN920C04 (sdx35) */ 942 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020), 943 .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info }, 944 /* Telit FE912C04 (sdx35) */ 945 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2045), 946 .driver_data = (kernel_ulong_t) &mhi_telit_fe912c04_info }, 947 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x011a), 948 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx35_info }, 949 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 950 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 951 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 952 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 953 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 954 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 955 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 956 /* EM929x (sdx65), use the same configuration as EM919x */ 957 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x18d7, 0x0301), 958 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 959 /* Telit FN980 hardware revision v1 */ 960 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 961 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 962 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 963 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 964 /* Telit FN990 */ 965 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 966 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 967 /* Telit FE990A */ 968 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 969 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info }, 970 /* Foxconn T99W696, all variants */ 971 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, PCI_ANY_ID), 972 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info }, 973 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 974 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 975 /* Telit FN990B40 (sdx72) */ 976 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a), 977 .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info }, 978 /* Telit FE990B40 (sdx72) */ 979 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x2025), 980 .driver_data = (kernel_ulong_t) &mhi_telit_fe990b40_info }, 981 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 982 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 983 /* QDU100, x100-DU */ 984 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), 985 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, 986 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 987 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 988 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 989 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 990 /* RM520N-GL (sdx6x), eSIM */ 991 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 992 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 993 /* RM520N-GL (sdx6x), Lenovo variant */ 994 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 995 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 996 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 997 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 998 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 999 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 1000 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 1001 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 1002 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1003 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 1004 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 1005 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 1006 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 1007 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 1008 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 1009 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 1010 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 1011 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1012 /* T99W175 (sdx55) */ 1013 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 1014 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1015 /* T99W368 (sdx65) */ 1016 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 1017 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 1018 /* T99W373 (sdx62) */ 1019 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 1020 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 1021 /* T99W510 (sdx24), variant 1 */ 1022 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 1023 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1024 /* T99W510 (sdx24), variant 2 */ 1025 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 1026 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1027 /* T99W510 (sdx24), variant 3 */ 1028 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 1029 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1030 /* DW5932e-eSIM (sdx62), With eSIM */ 1031 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 1032 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 1033 /* DW5932e (sdx62), Non-eSIM */ 1034 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 1035 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 1036 /* T99W640 (sdx72) */ 1037 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 1038 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w640_info }, 1039 /* DW5934e(sdx72), With eSIM */ 1040 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 1041 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1042 /* DW5934e(sdx72), Non-eSIM */ 1043 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 1044 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe123), 1046 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w760_info }, 1047 /* MV31-W (Cinterion) */ 1048 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 1049 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1050 /* MV31-W (Cinterion), based on new baseline */ 1051 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 1052 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1053 /* MV32-WA (Cinterion) */ 1054 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 1055 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1056 /* MV32-WB (Cinterion) */ 1057 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 1058 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1059 /* T99W175 (sdx55), HP variant */ 1060 { PCI_DEVICE(0x03f0, 0x0a6c), 1061 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1062 /* NETPRISMA LCUR57 (SDX24) */ 1063 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000), 1064 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info }, 1065 /* NETPRISMA FCUN69 (SDX6X) */ 1066 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), 1067 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, 1068 { } 1069 }; 1070 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 1071 1072 enum mhi_pci_device_status { 1073 MHI_PCI_DEV_STARTED, 1074 MHI_PCI_DEV_SUSPENDED, 1075 }; 1076 1077 struct mhi_pci_device { 1078 struct mhi_controller mhi_cntrl; 1079 struct pci_saved_state *pci_state; 1080 struct work_struct recovery_work; 1081 struct timer_list health_check_timer; 1082 unsigned long status; 1083 bool reset_on_remove; 1084 }; 1085 1086 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 1087 void __iomem *addr, u32 *out) 1088 { 1089 *out = readl(addr); 1090 return 0; 1091 } 1092 1093 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 1094 void __iomem *addr, u32 val) 1095 { 1096 writel(val, addr); 1097 } 1098 1099 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 1100 enum mhi_callback cb) 1101 { 1102 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1103 1104 /* Nothing to do for now */ 1105 switch (cb) { 1106 case MHI_CB_FATAL_ERROR: 1107 case MHI_CB_SYS_ERROR: 1108 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 1109 pm_runtime_forbid(&pdev->dev); 1110 break; 1111 case MHI_CB_EE_MISSION_MODE: 1112 pm_runtime_allow(&pdev->dev); 1113 break; 1114 default: 1115 break; 1116 } 1117 } 1118 1119 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 1120 { 1121 /* no-op */ 1122 } 1123 1124 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 1125 { 1126 /* no-op */ 1127 } 1128 1129 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 1130 { 1131 /* no-op */ 1132 } 1133 1134 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 1135 { 1136 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1137 u16 vendor = 0; 1138 1139 if (pci_read_config_word(pci_physfn(pdev), PCI_VENDOR_ID, &vendor)) 1140 return false; 1141 1142 if (vendor == (u16) ~0 || vendor == 0) 1143 return false; 1144 1145 return true; 1146 } 1147 1148 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 1149 unsigned int bar_num, u64 dma_mask) 1150 { 1151 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1152 int err; 1153 1154 err = pcim_enable_device(pdev); 1155 if (err) { 1156 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 1157 return err; 1158 } 1159 1160 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev)); 1161 if (IS_ERR(mhi_cntrl->regs)) { 1162 err = PTR_ERR(mhi_cntrl->regs); 1163 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 1164 return err; 1165 } 1166 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 1167 1168 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 1169 if (err) { 1170 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 1171 return err; 1172 } 1173 1174 pci_set_master(pdev); 1175 1176 return 0; 1177 } 1178 1179 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 1180 const struct mhi_controller_config *mhi_cntrl_config) 1181 { 1182 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1183 int nr_vectors, i; 1184 int *irq; 1185 1186 /* 1187 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 1188 * No explicit pci_free_irq_vectors required, done by pcim_release. 1189 */ 1190 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 1191 1192 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); 1193 if (nr_vectors < 0) { 1194 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 1195 nr_vectors); 1196 return nr_vectors; 1197 } 1198 1199 if (nr_vectors < mhi_cntrl->nr_irqs) { 1200 dev_warn(&pdev->dev, "using shared MSI\n"); 1201 1202 /* Patch msi vectors, use only one (shared) */ 1203 for (i = 0; i < mhi_cntrl_config->num_events; i++) 1204 mhi_cntrl_config->event_cfg[i].irq = 0; 1205 mhi_cntrl->nr_irqs = 1; 1206 } 1207 1208 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 1209 if (!irq) 1210 return -ENOMEM; 1211 1212 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 1213 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 1214 1215 irq[i] = pci_irq_vector(pdev, vector); 1216 } 1217 1218 mhi_cntrl->irq = irq; 1219 1220 return 0; 1221 } 1222 1223 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 1224 { 1225 /* The runtime_get() MHI callback means: 1226 * Do whatever is requested to leave M3. 1227 */ 1228 return pm_runtime_get(mhi_cntrl->cntrl_dev); 1229 } 1230 1231 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 1232 { 1233 /* The runtime_put() MHI callback means: 1234 * Device can be moved in M3 state. 1235 */ 1236 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 1237 pm_runtime_put(mhi_cntrl->cntrl_dev); 1238 } 1239 1240 static void mhi_pci_recovery_work(struct work_struct *work) 1241 { 1242 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 1243 recovery_work); 1244 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1245 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1246 int err; 1247 1248 dev_warn(&pdev->dev, "device recovery started\n"); 1249 1250 if (pdev->is_physfn) 1251 timer_delete(&mhi_pdev->health_check_timer); 1252 1253 pm_runtime_forbid(&pdev->dev); 1254 1255 /* Clean up MHI state */ 1256 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1257 mhi_power_down(mhi_cntrl, false); 1258 mhi_unprepare_after_power_down(mhi_cntrl); 1259 } 1260 1261 pci_set_power_state(pdev, PCI_D0); 1262 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1263 pci_restore_state(pdev); 1264 1265 if (!mhi_pci_is_alive(mhi_cntrl)) 1266 goto err_try_reset; 1267 1268 err = mhi_prepare_for_power_up(mhi_cntrl); 1269 if (err) 1270 goto err_try_reset; 1271 1272 err = mhi_sync_power_up(mhi_cntrl); 1273 if (err) 1274 goto err_unprepare; 1275 1276 dev_dbg(&pdev->dev, "Recovery completed\n"); 1277 1278 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1279 1280 if (pdev->is_physfn) 1281 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1282 1283 return; 1284 1285 err_unprepare: 1286 mhi_unprepare_after_power_down(mhi_cntrl); 1287 err_try_reset: 1288 err = pci_try_reset_function(pdev); 1289 if (err) 1290 dev_err(&pdev->dev, "Recovery failed: %d\n", err); 1291 } 1292 1293 static void health_check(struct timer_list *t) 1294 { 1295 struct mhi_pci_device *mhi_pdev = timer_container_of(mhi_pdev, t, 1296 health_check_timer); 1297 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1298 1299 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1300 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1301 return; 1302 1303 if (!mhi_pci_is_alive(mhi_cntrl)) { 1304 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1305 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1306 return; 1307 } 1308 1309 /* reschedule in two seconds */ 1310 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1311 } 1312 1313 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1314 { 1315 void __iomem *base = mhi_cntrl->regs; 1316 void __iomem *edl_db; 1317 int ret; 1318 u32 val; 1319 1320 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1321 if (ret) { 1322 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1323 return ret; 1324 } 1325 1326 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1327 mhi_cntrl->runtime_get(mhi_cntrl); 1328 1329 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1330 if (ret) 1331 goto err_get_chdb; 1332 1333 edl_db = base + val + (8 * MHI_EDL_DB); 1334 1335 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1336 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1337 1338 mhi_soc_reset(mhi_cntrl); 1339 1340 err_get_chdb: 1341 mhi_cntrl->runtime_put(mhi_cntrl); 1342 mhi_device_put(mhi_cntrl->mhi_dev); 1343 1344 return ret; 1345 } 1346 1347 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1348 { 1349 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1350 const struct mhi_controller_config *mhi_cntrl_config; 1351 struct mhi_pci_device *mhi_pdev; 1352 struct mhi_controller *mhi_cntrl; 1353 unsigned int dma_data_width; 1354 int err; 1355 1356 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1357 1358 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1359 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1360 if (!mhi_pdev) 1361 return -ENOMEM; 1362 1363 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1364 1365 if (pdev->is_virtfn && info->vf_config) 1366 mhi_cntrl_config = info->vf_config; 1367 else 1368 mhi_cntrl_config = info->config; 1369 1370 /* Initialize health check monitor only for Physical functions */ 1371 if (pdev->is_physfn) 1372 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1373 1374 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1375 1376 dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ? 1377 info->vf_dma_data_width : info->dma_data_width; 1378 1379 mhi_cntrl->cntrl_dev = &pdev->dev; 1380 mhi_cntrl->iova_start = 0; 1381 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width); 1382 mhi_cntrl->fw_image = info->fw; 1383 mhi_cntrl->edl_image = info->edl; 1384 1385 mhi_cntrl->read_reg = mhi_pci_read_reg; 1386 mhi_cntrl->write_reg = mhi_pci_write_reg; 1387 mhi_cntrl->status_cb = mhi_pci_status_cb; 1388 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1389 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1390 mhi_cntrl->mru = info->mru_default; 1391 mhi_cntrl->name = info->name; 1392 1393 if (pdev->is_physfn) 1394 mhi_pdev->reset_on_remove = info->reset_on_remove; 1395 1396 if (info->edl_trigger) 1397 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1398 1399 if (info->sideband_wake) { 1400 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1401 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1402 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1403 } 1404 1405 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_width)); 1406 if (err) 1407 return err; 1408 1409 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1410 if (err) 1411 return err; 1412 1413 pci_set_drvdata(pdev, mhi_pdev); 1414 1415 /* Have stored pci confspace at hand for restore in sudden PCI error. 1416 * cache the state locally and discard the PCI core one. 1417 */ 1418 pci_save_state(pdev); 1419 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1420 pci_load_saved_state(pdev, NULL); 1421 1422 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1423 if (err) 1424 return err; 1425 1426 /* MHI bus does not power up the controller by default */ 1427 err = mhi_prepare_for_power_up(mhi_cntrl); 1428 if (err) { 1429 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1430 goto err_unregister; 1431 } 1432 1433 err = mhi_async_power_up(mhi_cntrl); 1434 if (err) { 1435 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1436 goto err_unprepare; 1437 } 1438 1439 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1440 1441 /* start health check */ 1442 if (pdev->is_physfn) 1443 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1444 1445 /* Allow runtime suspend only if both PME from D3Hot and M3 are supported */ 1446 if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) { 1447 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1448 pm_runtime_use_autosuspend(&pdev->dev); 1449 pm_runtime_mark_last_busy(&pdev->dev); 1450 pm_runtime_put_noidle(&pdev->dev); 1451 } 1452 1453 return 0; 1454 1455 err_unprepare: 1456 mhi_unprepare_after_power_down(mhi_cntrl); 1457 err_unregister: 1458 mhi_unregister_controller(mhi_cntrl); 1459 1460 return err; 1461 } 1462 1463 static void mhi_pci_remove(struct pci_dev *pdev) 1464 { 1465 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1466 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1467 1468 pm_runtime_forbid(&pdev->dev); 1469 pci_disable_sriov(pdev); 1470 1471 if (pdev->is_physfn) 1472 timer_delete_sync(&mhi_pdev->health_check_timer); 1473 cancel_work_sync(&mhi_pdev->recovery_work); 1474 1475 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1476 mhi_power_down(mhi_cntrl, true); 1477 mhi_unprepare_after_power_down(mhi_cntrl); 1478 } 1479 1480 /* balancing probe put_noidle */ 1481 if (pci_pme_capable(pdev, PCI_D3hot)) 1482 pm_runtime_get_noresume(&pdev->dev); 1483 1484 if (mhi_pdev->reset_on_remove) 1485 mhi_soc_reset(mhi_cntrl); 1486 1487 mhi_unregister_controller(mhi_cntrl); 1488 } 1489 1490 static void mhi_pci_shutdown(struct pci_dev *pdev) 1491 { 1492 mhi_pci_remove(pdev); 1493 pci_set_power_state(pdev, PCI_D3hot); 1494 } 1495 1496 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1497 { 1498 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1499 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1500 1501 dev_info(&pdev->dev, "reset\n"); 1502 1503 if (pdev->is_physfn) 1504 timer_delete(&mhi_pdev->health_check_timer); 1505 1506 /* Clean up MHI state */ 1507 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1508 mhi_power_down(mhi_cntrl, false); 1509 mhi_unprepare_after_power_down(mhi_cntrl); 1510 } 1511 1512 /* cause internal device reset */ 1513 mhi_soc_reset(mhi_cntrl); 1514 1515 /* Be sure device reset has been executed */ 1516 msleep(MHI_POST_RESET_DELAY_MS); 1517 } 1518 1519 static void mhi_pci_reset_done(struct pci_dev *pdev) 1520 { 1521 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1522 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1523 int err; 1524 1525 /* Restore initial known working PCI state */ 1526 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1527 pci_restore_state(pdev); 1528 1529 /* Is device status available ? */ 1530 if (!mhi_pci_is_alive(mhi_cntrl)) { 1531 dev_err(&pdev->dev, "reset failed\n"); 1532 return; 1533 } 1534 1535 err = mhi_prepare_for_power_up(mhi_cntrl); 1536 if (err) { 1537 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1538 return; 1539 } 1540 1541 err = mhi_sync_power_up(mhi_cntrl); 1542 if (err) { 1543 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1544 mhi_unprepare_after_power_down(mhi_cntrl); 1545 return; 1546 } 1547 1548 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1549 if (pdev->is_physfn) 1550 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1551 } 1552 1553 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1554 pci_channel_state_t state) 1555 { 1556 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1557 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1558 1559 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1560 1561 if (state == pci_channel_io_perm_failure) 1562 return PCI_ERS_RESULT_DISCONNECT; 1563 1564 /* Clean up MHI state */ 1565 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1566 mhi_power_down(mhi_cntrl, false); 1567 mhi_unprepare_after_power_down(mhi_cntrl); 1568 } else { 1569 /* Nothing to do */ 1570 return PCI_ERS_RESULT_RECOVERED; 1571 } 1572 1573 pci_disable_device(pdev); 1574 1575 return PCI_ERS_RESULT_NEED_RESET; 1576 } 1577 1578 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1579 { 1580 if (pci_enable_device(pdev)) { 1581 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1582 return PCI_ERS_RESULT_DISCONNECT; 1583 } 1584 1585 return PCI_ERS_RESULT_RECOVERED; 1586 } 1587 1588 static void mhi_pci_io_resume(struct pci_dev *pdev) 1589 { 1590 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1591 1592 dev_err(&pdev->dev, "PCI slot reset done\n"); 1593 1594 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1595 } 1596 1597 static const struct pci_error_handlers mhi_pci_err_handler = { 1598 .error_detected = mhi_pci_error_detected, 1599 .slot_reset = mhi_pci_slot_reset, 1600 .resume = mhi_pci_io_resume, 1601 .reset_prepare = mhi_pci_reset_prepare, 1602 .reset_done = mhi_pci_reset_done, 1603 }; 1604 1605 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1606 { 1607 struct pci_dev *pdev = to_pci_dev(dev); 1608 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1609 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1610 int err; 1611 1612 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1613 return 0; 1614 1615 if (pdev->is_physfn) 1616 timer_delete(&mhi_pdev->health_check_timer); 1617 1618 cancel_work_sync(&mhi_pdev->recovery_work); 1619 1620 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1621 mhi_cntrl->ee != MHI_EE_AMSS) 1622 goto pci_suspend; /* Nothing to do at MHI level */ 1623 1624 /* Transition to M3 state */ 1625 err = mhi_pm_suspend(mhi_cntrl); 1626 if (err) { 1627 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1628 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1629 return -EBUSY; 1630 } 1631 1632 pci_suspend: 1633 pci_disable_device(pdev); 1634 pci_wake_from_d3(pdev, true); 1635 1636 return 0; 1637 } 1638 1639 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1640 { 1641 struct pci_dev *pdev = to_pci_dev(dev); 1642 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1643 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1644 int err; 1645 1646 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1647 return 0; 1648 1649 err = pci_enable_device(pdev); 1650 if (err) 1651 goto err_recovery; 1652 1653 pci_set_master(pdev); 1654 pci_wake_from_d3(pdev, false); 1655 1656 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1657 mhi_cntrl->ee != MHI_EE_AMSS) 1658 return 0; /* Nothing to do at MHI level */ 1659 1660 /* Exit M3, transition to M0 state */ 1661 err = mhi_pm_resume(mhi_cntrl); 1662 if (err) { 1663 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1664 goto err_recovery; 1665 } 1666 1667 /* Resume health check */ 1668 if (pdev->is_physfn) 1669 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1670 1671 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1672 pm_runtime_mark_last_busy(dev); 1673 1674 return 0; 1675 1676 err_recovery: 1677 /* Do not fail to not mess up our PCI device state, the device likely 1678 * lost power (d3cold) and we simply need to reset it from the recovery 1679 * procedure, trigger the recovery asynchronously to prevent system 1680 * suspend exit delaying. 1681 */ 1682 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1683 pm_runtime_mark_last_busy(dev); 1684 1685 return 0; 1686 } 1687 1688 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1689 { 1690 pm_runtime_disable(dev); 1691 return mhi_pci_runtime_suspend(dev); 1692 } 1693 1694 static int __maybe_unused mhi_pci_resume(struct device *dev) 1695 { 1696 int ret; 1697 1698 /* Depending the platform, device may have lost power (d3cold), we need 1699 * to resume it now to check its state and recover when necessary. 1700 */ 1701 ret = mhi_pci_runtime_resume(dev); 1702 pm_runtime_enable(dev); 1703 1704 return ret; 1705 } 1706 1707 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1708 { 1709 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1710 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1711 1712 /* We want to stop all operations, hibernation does not guarantee that 1713 * device will be in the same state as before freezing, especially if 1714 * the intermediate restore kernel reinitializes MHI device with new 1715 * context. 1716 */ 1717 flush_work(&mhi_pdev->recovery_work); 1718 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1719 mhi_power_down(mhi_cntrl, true); 1720 mhi_unprepare_after_power_down(mhi_cntrl); 1721 } 1722 1723 return 0; 1724 } 1725 1726 static int __maybe_unused mhi_pci_restore(struct device *dev) 1727 { 1728 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1729 1730 /* Reinitialize the device */ 1731 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1732 1733 return 0; 1734 } 1735 1736 static const struct dev_pm_ops mhi_pci_pm_ops = { 1737 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1738 #ifdef CONFIG_PM_SLEEP 1739 .suspend = mhi_pci_suspend, 1740 .resume = mhi_pci_resume, 1741 .freeze = mhi_pci_freeze, 1742 .thaw = mhi_pci_restore, 1743 .poweroff = mhi_pci_freeze, 1744 .restore = mhi_pci_restore, 1745 #endif 1746 }; 1747 1748 static struct pci_driver mhi_pci_driver = { 1749 .name = "mhi-pci-generic", 1750 .id_table = mhi_pci_id_table, 1751 .probe = mhi_pci_probe, 1752 .remove = mhi_pci_remove, 1753 .shutdown = mhi_pci_shutdown, 1754 .err_handler = &mhi_pci_err_handler, 1755 .driver.pm = &mhi_pci_pm_ops, 1756 .sriov_configure = pci_sriov_configure_simple, 1757 }; 1758 module_pci_driver(mhi_pci_driver); 1759 1760 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1761 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1762 MODULE_LICENSE("GPL"); 1763