1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timer.h> 18 #include <linux/workqueue.h> 19 20 #define MHI_PCI_DEFAULT_BAR_NUM 0 21 22 #define MHI_POST_RESET_DELAY_MS 2000 23 24 #define HEALTH_CHECK_PERIOD (HZ * 2) 25 26 /* PCI VID definitions */ 27 #define PCI_VENDOR_ID_THALES 0x1269 28 #define PCI_VENDOR_ID_QUECTEL 0x1eac 29 #define PCI_VENDOR_ID_NETPRISMA 0x203e 30 31 #define MHI_EDL_DB 91 32 #define MHI_EDL_COOKIE 0xEDEDEDED 33 34 /** 35 * struct mhi_pci_dev_info - MHI PCI device specific information 36 * @config: MHI controller configuration 37 * @vf_config: MHI controller configuration for Virtual function (optional) 38 * @name: name of the PCI module 39 * @fw: firmware path (if any) 40 * @edl: emergency download mode firmware path (if any) 41 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 42 * @bar_num: PCI base address register to use for MHI MMIO register space 43 * @dma_data_width: DMA transfer word size (32 or 64 bits) 44 * @vf_dma_data_width: DMA transfer word size for VF's (optional) 45 * @mru_default: default MRU size for MBIM network packets 46 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 47 * of inband wake support (such as sdx24) 48 * @no_m3: M3 not supported 49 * @reset_on_remove: Set true for devices that require SoC during driver removal 50 */ 51 struct mhi_pci_dev_info { 52 const struct mhi_controller_config *config; 53 const struct mhi_controller_config *vf_config; 54 const char *name; 55 const char *fw; 56 const char *edl; 57 bool edl_trigger; 58 unsigned int bar_num; 59 unsigned int dma_data_width; 60 unsigned int vf_dma_data_width; 61 unsigned int mru_default; 62 bool sideband_wake; 63 bool no_m3; 64 bool reset_on_remove; 65 }; 66 67 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 68 { \ 69 .num = ch_num, \ 70 .name = ch_name, \ 71 .num_elements = el_count, \ 72 .event_ring = ev_ring, \ 73 .dir = DMA_TO_DEVICE, \ 74 .ee_mask = BIT(MHI_EE_AMSS), \ 75 .pollcfg = 0, \ 76 .doorbell = MHI_DB_BRST_DISABLE, \ 77 .lpm_notify = false, \ 78 .offload_channel = false, \ 79 .doorbell_mode_switch = false, \ 80 } \ 81 82 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 83 { \ 84 .num = ch_num, \ 85 .name = ch_name, \ 86 .num_elements = el_count, \ 87 .event_ring = ev_ring, \ 88 .dir = DMA_FROM_DEVICE, \ 89 .ee_mask = BIT(MHI_EE_AMSS), \ 90 .pollcfg = 0, \ 91 .doorbell = MHI_DB_BRST_DISABLE, \ 92 .lpm_notify = false, \ 93 .offload_channel = false, \ 94 .doorbell_mode_switch = false, \ 95 } 96 97 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ 98 { \ 99 .num = ch_num, \ 100 .name = ch_name, \ 101 .num_elements = el_count, \ 102 .event_ring = ev_ring, \ 103 .dir = DMA_FROM_DEVICE, \ 104 .ee_mask = BIT(MHI_EE_AMSS), \ 105 .pollcfg = 0, \ 106 .doorbell = MHI_DB_BRST_DISABLE, \ 107 .lpm_notify = false, \ 108 .offload_channel = false, \ 109 .doorbell_mode_switch = false, \ 110 .auto_queue = true, \ 111 } 112 113 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 114 { \ 115 .num_elements = el_count, \ 116 .irq_moderation_ms = 0, \ 117 .irq = (ev_ring) + 1, \ 118 .priority = 1, \ 119 .mode = MHI_DB_BRST_DISABLE, \ 120 .data_type = MHI_ER_CTRL, \ 121 .hardware_event = false, \ 122 .client_managed = false, \ 123 .offload_channel = false, \ 124 } 125 126 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 127 { \ 128 .num = ch_num, \ 129 .name = ch_name, \ 130 .num_elements = el_count, \ 131 .event_ring = ev_ring, \ 132 .dir = DMA_TO_DEVICE, \ 133 .ee_mask = BIT(MHI_EE_AMSS), \ 134 .pollcfg = 0, \ 135 .doorbell = MHI_DB_BRST_ENABLE, \ 136 .lpm_notify = false, \ 137 .offload_channel = false, \ 138 .doorbell_mode_switch = true, \ 139 } \ 140 141 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 142 { \ 143 .num = ch_num, \ 144 .name = ch_name, \ 145 .num_elements = el_count, \ 146 .event_ring = ev_ring, \ 147 .dir = DMA_FROM_DEVICE, \ 148 .ee_mask = BIT(MHI_EE_AMSS), \ 149 .pollcfg = 0, \ 150 .doorbell = MHI_DB_BRST_ENABLE, \ 151 .lpm_notify = false, \ 152 .offload_channel = false, \ 153 .doorbell_mode_switch = true, \ 154 } 155 156 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 157 { \ 158 .num = ch_num, \ 159 .name = ch_name, \ 160 .num_elements = el_count, \ 161 .event_ring = ev_ring, \ 162 .dir = DMA_TO_DEVICE, \ 163 .ee_mask = BIT(MHI_EE_SBL), \ 164 .pollcfg = 0, \ 165 .doorbell = MHI_DB_BRST_DISABLE, \ 166 .lpm_notify = false, \ 167 .offload_channel = false, \ 168 .doorbell_mode_switch = false, \ 169 } \ 170 171 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 172 { \ 173 .num = ch_num, \ 174 .name = ch_name, \ 175 .num_elements = el_count, \ 176 .event_ring = ev_ring, \ 177 .dir = DMA_FROM_DEVICE, \ 178 .ee_mask = BIT(MHI_EE_SBL), \ 179 .pollcfg = 0, \ 180 .doorbell = MHI_DB_BRST_DISABLE, \ 181 .lpm_notify = false, \ 182 .offload_channel = false, \ 183 .doorbell_mode_switch = false, \ 184 } 185 186 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 187 { \ 188 .num = ch_num, \ 189 .name = ch_name, \ 190 .num_elements = el_count, \ 191 .event_ring = ev_ring, \ 192 .dir = DMA_TO_DEVICE, \ 193 .ee_mask = BIT(MHI_EE_FP), \ 194 .pollcfg = 0, \ 195 .doorbell = MHI_DB_BRST_DISABLE, \ 196 .lpm_notify = false, \ 197 .offload_channel = false, \ 198 .doorbell_mode_switch = false, \ 199 } \ 200 201 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 202 { \ 203 .num = ch_num, \ 204 .name = ch_name, \ 205 .num_elements = el_count, \ 206 .event_ring = ev_ring, \ 207 .dir = DMA_FROM_DEVICE, \ 208 .ee_mask = BIT(MHI_EE_FP), \ 209 .pollcfg = 0, \ 210 .doorbell = MHI_DB_BRST_DISABLE, \ 211 .lpm_notify = false, \ 212 .offload_channel = false, \ 213 .doorbell_mode_switch = false, \ 214 } 215 216 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 217 { \ 218 .num_elements = el_count, \ 219 .irq_moderation_ms = 5, \ 220 .irq = (ev_ring) + 1, \ 221 .priority = 1, \ 222 .mode = MHI_DB_BRST_DISABLE, \ 223 .data_type = MHI_ER_DATA, \ 224 .hardware_event = false, \ 225 .client_managed = false, \ 226 .offload_channel = false, \ 227 } 228 229 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 230 { \ 231 .num_elements = el_count, \ 232 .irq_moderation_ms = 0, \ 233 .irq = (ev_ring) + 1, \ 234 .priority = 1, \ 235 .mode = MHI_DB_BRST_DISABLE, \ 236 .data_type = MHI_ER_DATA, \ 237 .hardware_event = false, \ 238 .client_managed = false, \ 239 .offload_channel = false, \ 240 } 241 242 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 243 { \ 244 .num_elements = el_count, \ 245 .irq_moderation_ms = 1, \ 246 .irq = (ev_ring) + 1, \ 247 .priority = 1, \ 248 .mode = MHI_DB_BRST_DISABLE, \ 249 .data_type = MHI_ER_DATA, \ 250 .hardware_event = true, \ 251 .client_managed = false, \ 252 .offload_channel = false, \ 253 .channel = ch_num, \ 254 } 255 256 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { 257 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), 258 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), 259 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), 260 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), 261 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), 262 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), 263 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), 264 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), 265 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), 266 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), 267 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), 268 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), 269 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), 270 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), 271 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), 272 }; 273 274 static struct mhi_event_config mhi_qcom_qdu100_events[] = { 275 /* first ring is control+data ring */ 276 MHI_EVENT_CONFIG_CTRL(0, 64), 277 /* SAHARA dedicated event ring */ 278 MHI_EVENT_CONFIG_SW_DATA(1, 256), 279 /* Software channels dedicated event ring */ 280 MHI_EVENT_CONFIG_SW_DATA(2, 64), 281 MHI_EVENT_CONFIG_SW_DATA(3, 256), 282 MHI_EVENT_CONFIG_SW_DATA(4, 256), 283 /* Software IP channels dedicated event ring */ 284 MHI_EVENT_CONFIG_SW_DATA(5, 512), 285 MHI_EVENT_CONFIG_SW_DATA(6, 512), 286 MHI_EVENT_CONFIG_SW_DATA(7, 512), 287 }; 288 289 static const struct mhi_controller_config mhi_qcom_qdu100_config = { 290 .max_channels = 128, 291 .timeout_ms = 120000, 292 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), 293 .ch_cfg = mhi_qcom_qdu100_channels, 294 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), 295 .event_cfg = mhi_qcom_qdu100_events, 296 }; 297 298 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { 299 .name = "qcom-qdu100", 300 .fw = "qcom/qdu100/xbl_s.melf", 301 .edl_trigger = true, 302 .config = &mhi_qcom_qdu100_config, 303 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 304 .dma_data_width = 32, 305 .vf_dma_data_width = 40, 306 .sideband_wake = false, 307 .no_m3 = true, 308 .reset_on_remove = true, 309 }; 310 311 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { 312 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), 313 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), 314 }; 315 316 static struct mhi_event_config mhi_qcom_sa8775p_events[] = { 317 /* first ring is control+data ring */ 318 MHI_EVENT_CONFIG_CTRL(0, 64), 319 /* Software channels dedicated event ring */ 320 MHI_EVENT_CONFIG_SW_DATA(1, 64), 321 MHI_EVENT_CONFIG_SW_DATA(2, 64), 322 }; 323 324 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 325 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 326 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 327 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 328 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 329 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 330 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 331 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 332 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), 333 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 334 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 335 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 336 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 337 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 338 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 339 }; 340 341 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 342 /* first ring is control+data ring */ 343 MHI_EVENT_CONFIG_CTRL(0, 64), 344 /* DIAG dedicated event ring */ 345 MHI_EVENT_CONFIG_DATA(1, 128), 346 /* Software channels dedicated event ring */ 347 MHI_EVENT_CONFIG_SW_DATA(2, 64), 348 MHI_EVENT_CONFIG_SW_DATA(3, 64), 349 /* Hardware channels request dedicated hardware event rings */ 350 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 351 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 352 }; 353 354 static const struct mhi_controller_config mhi_qcom_sa8775p_config = { 355 .max_channels = 128, 356 .timeout_ms = 8000, 357 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels), 358 .ch_cfg = mhi_qcom_sa8775p_channels, 359 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events), 360 .event_cfg = mhi_qcom_sa8775p_events, 361 }; 362 363 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 364 .max_channels = 128, 365 .timeout_ms = 8000, 366 .ready_timeout_ms = 50000, 367 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 368 .ch_cfg = modem_qcom_v1_mhi_channels, 369 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 370 .event_cfg = modem_qcom_v1_mhi_events, 371 }; 372 373 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 374 .max_channels = 128, 375 .timeout_ms = 8000, 376 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 377 .ch_cfg = modem_qcom_v1_mhi_channels, 378 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 379 .event_cfg = modem_qcom_v1_mhi_events, 380 }; 381 382 static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { 383 .name = "qcom-sa8775p", 384 .edl_trigger = false, 385 .config = &mhi_qcom_sa8775p_config, 386 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 387 .dma_data_width = 32, 388 .mru_default = 32768, 389 .sideband_wake = false, 390 }; 391 392 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 393 .name = "qcom-sdx75m", 394 .fw = "qcom/sdx75m/xbl.elf", 395 .edl = "qcom/sdx75m/edl.mbn", 396 .edl_trigger = true, 397 .config = &modem_qcom_v2_mhiv_config, 398 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 399 .dma_data_width = 32, 400 .sideband_wake = false, 401 }; 402 403 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 404 .name = "qcom-sdx65m", 405 .fw = "qcom/sdx65m/xbl.elf", 406 .edl = "qcom/sdx65m/edl.mbn", 407 .edl_trigger = true, 408 .config = &modem_qcom_v1_mhiv_config, 409 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 410 .dma_data_width = 32, 411 .sideband_wake = false, 412 }; 413 414 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 415 .name = "qcom-sdx55m", 416 .fw = "qcom/sdx55m/sbl1.mbn", 417 .edl = "qcom/sdx55m/edl.mbn", 418 .edl_trigger = true, 419 .config = &modem_qcom_v1_mhiv_config, 420 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 421 .dma_data_width = 32, 422 .mru_default = 32768, 423 .sideband_wake = false, 424 }; 425 426 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 427 .name = "qcom-sdx24", 428 .edl = "qcom/prog_firehose_sdx24.mbn", 429 .config = &modem_qcom_v1_mhiv_config, 430 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 431 .dma_data_width = 32, 432 .sideband_wake = true, 433 }; 434 435 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 436 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 437 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 438 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 439 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 440 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 441 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 442 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 443 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 444 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 445 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 446 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 447 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 448 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 449 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 450 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 451 }; 452 453 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 454 MHI_EVENT_CONFIG_CTRL(0, 128), 455 MHI_EVENT_CONFIG_DATA(1, 128), 456 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 457 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 458 }; 459 460 static const struct mhi_controller_config modem_quectel_em1xx_config = { 461 .max_channels = 128, 462 .timeout_ms = 20000, 463 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 464 .ch_cfg = mhi_quectel_em1xx_channels, 465 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 466 .event_cfg = mhi_quectel_em1xx_events, 467 }; 468 469 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 470 .name = "quectel-em1xx", 471 .edl = "qcom/prog_firehose_sdx24.mbn", 472 .config = &modem_quectel_em1xx_config, 473 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 474 .dma_data_width = 32, 475 .mru_default = 32768, 476 .sideband_wake = true, 477 }; 478 479 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 480 .name = "quectel-rm5xx", 481 .edl = "qcom/prog_firehose_sdx6x.elf", 482 .config = &modem_quectel_em1xx_config, 483 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 484 .dma_data_width = 32, 485 .mru_default = 32768, 486 .sideband_wake = true, 487 }; 488 489 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 490 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 491 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 492 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 493 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 494 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 495 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 496 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 497 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 498 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 499 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 500 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 501 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 502 }; 503 504 static const struct mhi_channel_config mhi_foxconn_sdx61_channels[] = { 505 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 506 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 507 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 508 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 509 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 510 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 511 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 512 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 513 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 514 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 515 MHI_CHANNEL_CONFIG_UL(50, "NMEA", 32, 0), 516 MHI_CHANNEL_CONFIG_DL(51, "NMEA", 32, 0), 517 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 518 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 519 }; 520 521 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 522 MHI_EVENT_CONFIG_CTRL(0, 128), 523 MHI_EVENT_CONFIG_DATA(1, 128), 524 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 525 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 526 }; 527 528 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 529 .max_channels = 128, 530 .timeout_ms = 20000, 531 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 532 .ch_cfg = mhi_foxconn_sdx55_channels, 533 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 534 .event_cfg = mhi_foxconn_sdx55_events, 535 }; 536 537 static const struct mhi_controller_config modem_foxconn_sdx61_config = { 538 .max_channels = 128, 539 .timeout_ms = 20000, 540 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx61_channels), 541 .ch_cfg = mhi_foxconn_sdx61_channels, 542 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 543 .event_cfg = mhi_foxconn_sdx55_events, 544 }; 545 546 static const struct mhi_controller_config modem_foxconn_sdx72_config = { 547 .max_channels = 128, 548 .timeout_ms = 20000, 549 .ready_timeout_ms = 50000, 550 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 551 .ch_cfg = mhi_foxconn_sdx55_channels, 552 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 553 .event_cfg = mhi_foxconn_sdx55_events, 554 }; 555 556 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 557 .name = "foxconn-sdx55", 558 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 559 .edl_trigger = true, 560 .config = &modem_foxconn_sdx55_config, 561 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 562 .dma_data_width = 32, 563 .mru_default = 32768, 564 .sideband_wake = false, 565 }; 566 567 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 568 .name = "foxconn-t99w175", 569 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 570 .edl_trigger = true, 571 .config = &modem_foxconn_sdx55_config, 572 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 573 .dma_data_width = 32, 574 .mru_default = 32768, 575 .sideband_wake = false, 576 }; 577 578 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 579 .name = "foxconn-dw5930e", 580 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 581 .edl_trigger = true, 582 .config = &modem_foxconn_sdx55_config, 583 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 584 .dma_data_width = 32, 585 .mru_default = 32768, 586 .sideband_wake = false, 587 }; 588 589 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 590 .name = "foxconn-t99w368", 591 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 592 .edl_trigger = true, 593 .config = &modem_foxconn_sdx55_config, 594 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 595 .dma_data_width = 32, 596 .mru_default = 32768, 597 .sideband_wake = false, 598 }; 599 600 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 601 .name = "foxconn-t99w373", 602 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 603 .edl_trigger = true, 604 .config = &modem_foxconn_sdx55_config, 605 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 606 .dma_data_width = 32, 607 .mru_default = 32768, 608 .sideband_wake = false, 609 }; 610 611 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 612 .name = "foxconn-t99w510", 613 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn", 614 .edl_trigger = true, 615 .config = &modem_foxconn_sdx55_config, 616 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 617 .dma_data_width = 32, 618 .mru_default = 32768, 619 .sideband_wake = false, 620 }; 621 622 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 623 .name = "foxconn-dw5932e", 624 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 625 .edl_trigger = true, 626 .config = &modem_foxconn_sdx55_config, 627 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 628 .dma_data_width = 32, 629 .mru_default = 32768, 630 .sideband_wake = false, 631 }; 632 633 static const struct mhi_pci_dev_info mhi_foxconn_t99w640_info = { 634 .name = "foxconn-t99w640", 635 .edl = "qcom/sdx72m/foxconn/edl.mbn", 636 .edl_trigger = true, 637 .config = &modem_foxconn_sdx72_config, 638 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 639 .dma_data_width = 32, 640 .mru_default = 32768, 641 .sideband_wake = false, 642 }; 643 644 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 645 .name = "foxconn-dw5934e", 646 .edl = "qcom/sdx72m/foxconn/edl.mbn", 647 .edl_trigger = true, 648 .config = &modem_foxconn_sdx72_config, 649 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 650 .dma_data_width = 32, 651 .mru_default = 32768, 652 .sideband_wake = false, 653 }; 654 655 static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = { 656 .name = "foxconn-t99w696", 657 .edl = "qcom/sdx61/foxconn/prog_firehose_lite.elf", 658 .edl_trigger = true, 659 .config = &modem_foxconn_sdx61_config, 660 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 661 .dma_data_width = 32, 662 .mru_default = 32768, 663 .sideband_wake = false, 664 }; 665 666 static const struct mhi_pci_dev_info mhi_foxconn_t99w760_info = { 667 .name = "foxconn-t99w760", 668 .edl = "qcom/sdx35/foxconn/xbl_s_devprg_ns.melf", 669 .edl_trigger = true, 670 .config = &modem_foxconn_sdx61_config, 671 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 672 .dma_data_width = 32, 673 .mru_default = 32768, 674 .sideband_wake = false, 675 }; 676 677 static const struct mhi_channel_config mhi_mv3x_channels[] = { 678 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 679 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 680 /* MBIM Control Channel */ 681 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 682 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 683 /* MBIM Data Channel */ 684 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 685 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 686 }; 687 688 static struct mhi_event_config mhi_mv3x_events[] = { 689 MHI_EVENT_CONFIG_CTRL(0, 256), 690 MHI_EVENT_CONFIG_DATA(1, 256), 691 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 692 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 693 }; 694 695 static const struct mhi_controller_config modem_mv3x_config = { 696 .max_channels = 128, 697 .timeout_ms = 20000, 698 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 699 .ch_cfg = mhi_mv3x_channels, 700 .num_events = ARRAY_SIZE(mhi_mv3x_events), 701 .event_cfg = mhi_mv3x_events, 702 }; 703 704 static const struct mhi_pci_dev_info mhi_mv31_info = { 705 .name = "cinterion-mv31", 706 .config = &modem_mv3x_config, 707 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 708 .dma_data_width = 32, 709 .mru_default = 32768, 710 }; 711 712 static const struct mhi_pci_dev_info mhi_mv32_info = { 713 .name = "cinterion-mv32", 714 .config = &modem_mv3x_config, 715 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 716 .dma_data_width = 32, 717 .mru_default = 32768, 718 }; 719 720 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 721 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 722 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 723 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 724 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 725 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 726 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 727 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 728 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 729 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 730 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 731 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 732 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 733 }; 734 735 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 736 /* first ring is control+data and DIAG ring */ 737 MHI_EVENT_CONFIG_CTRL(0, 2048), 738 /* Hardware channels request dedicated hardware event rings */ 739 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 740 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 741 }; 742 743 static const struct mhi_controller_config modem_sierra_em919x_config = { 744 .max_channels = 128, 745 .timeout_ms = 24000, 746 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 747 .ch_cfg = mhi_sierra_em919x_channels, 748 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 749 .event_cfg = modem_sierra_em919x_mhi_events, 750 }; 751 752 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 753 .name = "sierra-em919x", 754 .config = &modem_sierra_em919x_config, 755 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 756 .dma_data_width = 32, 757 .mru_default = 32768, 758 .sideband_wake = false, 759 }; 760 761 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 762 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 763 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 764 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 765 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0), 766 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 767 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 768 }; 769 770 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 771 MHI_EVENT_CONFIG_CTRL(0, 128), 772 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 773 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 774 }; 775 776 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 777 .max_channels = 128, 778 .timeout_ms = 20000, 779 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 780 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 781 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 782 .event_cfg = mhi_telit_fn980_hw_v1_events, 783 }; 784 785 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 786 .name = "telit-fn980-hwv1", 787 .fw = "qcom/sdx55m/sbl1.mbn", 788 .edl = "qcom/sdx55m/edl.mbn", 789 .config = &modem_telit_fn980_hw_v1_config, 790 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 791 .dma_data_width = 32, 792 .mru_default = 32768, 793 .sideband_wake = false, 794 }; 795 796 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 797 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 798 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 799 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 800 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 801 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 802 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 803 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 804 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 805 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 806 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 807 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 808 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 809 }; 810 811 static struct mhi_event_config mhi_telit_fn990_events[] = { 812 MHI_EVENT_CONFIG_CTRL(0, 128), 813 MHI_EVENT_CONFIG_DATA(1, 128), 814 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 815 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 816 }; 817 818 static const struct mhi_controller_config modem_telit_fn990_config = { 819 .max_channels = 128, 820 .timeout_ms = 20000, 821 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 822 .ch_cfg = mhi_telit_fn990_channels, 823 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 824 .event_cfg = mhi_telit_fn990_events, 825 }; 826 827 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 828 .name = "telit-fn990", 829 .config = &modem_telit_fn990_config, 830 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 831 .dma_data_width = 32, 832 .sideband_wake = false, 833 .mru_default = 32768, 834 }; 835 836 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = { 837 .name = "telit-fe990a", 838 .config = &modem_telit_fn990_config, 839 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 840 .dma_data_width = 32, 841 .sideband_wake = false, 842 .mru_default = 32768, 843 }; 844 845 static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = { 846 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 847 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 848 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 849 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 850 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 851 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 852 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 853 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 854 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 855 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 856 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 857 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 858 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 859 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 860 }; 861 862 static const struct mhi_controller_config modem_telit_fn920c04_config = { 863 .max_channels = 128, 864 .timeout_ms = 50000, 865 .num_channels = ARRAY_SIZE(mhi_telit_fn920c04_channels), 866 .ch_cfg = mhi_telit_fn920c04_channels, 867 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 868 .event_cfg = mhi_telit_fn990_events, 869 }; 870 871 static const struct mhi_pci_dev_info mhi_telit_fn920c04_info = { 872 .name = "telit-fn920c04", 873 .config = &modem_telit_fn920c04_config, 874 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 875 .dma_data_width = 32, 876 .sideband_wake = false, 877 .mru_default = 32768, 878 .edl_trigger = true, 879 }; 880 881 static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = { 882 .name = "telit-fn990b40", 883 .config = &modem_telit_fn920c04_config, 884 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 885 .dma_data_width = 32, 886 .sideband_wake = false, 887 .mru_default = 32768, 888 .edl_trigger = true, 889 }; 890 891 static const struct mhi_pci_dev_info mhi_telit_fe990b40_info = { 892 .name = "telit-fe990b40", 893 .config = &modem_telit_fn920c04_config, 894 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 895 .dma_data_width = 32, 896 .sideband_wake = false, 897 .mru_default = 32768, 898 .edl_trigger = true, 899 }; 900 901 static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { 902 .name = "netprisma-lcur57", 903 .edl = "qcom/prog_firehose_sdx24.mbn", 904 .config = &modem_quectel_em1xx_config, 905 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 906 .dma_data_width = 32, 907 .mru_default = 32768, 908 .sideband_wake = true, 909 }; 910 911 static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { 912 .name = "netprisma-fcun69", 913 .edl = "qcom/prog_firehose_sdx6x.elf", 914 .config = &modem_quectel_em1xx_config, 915 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 916 .dma_data_width = 32, 917 .mru_default = 32768, 918 .sideband_wake = true, 919 }; 920 921 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 922 static const struct pci_device_id mhi_pci_id_table[] = { 923 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), 924 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, 925 /* Telit FN920C04 (sdx35) */ 926 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020), 927 .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info }, 928 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 929 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 930 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 931 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 932 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 933 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 934 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 935 /* EM929x (sdx65), use the same configuration as EM919x */ 936 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x18d7, 0x0301), 937 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 938 /* Telit FN980 hardware revision v1 */ 939 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 940 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 941 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 942 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 943 /* Telit FN990 */ 944 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 945 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 946 /* Telit FE990A */ 947 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 948 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info }, 949 /* Foxconn T99W696, all variants */ 950 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, PCI_ANY_ID), 951 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info }, 952 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 953 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 954 /* Telit FN990B40 (sdx72) */ 955 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a), 956 .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info }, 957 /* Telit FE990B40 (sdx72) */ 958 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x2025), 959 .driver_data = (kernel_ulong_t) &mhi_telit_fe990b40_info }, 960 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 961 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 962 /* QDU100, x100-DU */ 963 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), 964 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, 965 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 966 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 967 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 968 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 969 /* RM520N-GL (sdx6x), eSIM */ 970 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 971 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 972 /* RM520N-GL (sdx6x), Lenovo variant */ 973 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 974 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 975 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 976 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 977 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 978 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 979 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 980 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 981 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 982 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 983 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 984 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 985 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 986 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 987 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 988 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 989 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 990 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 991 /* T99W175 (sdx55) */ 992 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 993 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 994 /* T99W368 (sdx65) */ 995 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 996 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 997 /* T99W373 (sdx62) */ 998 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 999 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 1000 /* T99W510 (sdx24), variant 1 */ 1001 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 1002 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1003 /* T99W510 (sdx24), variant 2 */ 1004 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 1005 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1006 /* T99W510 (sdx24), variant 3 */ 1007 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 1008 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1009 /* DW5932e-eSIM (sdx62), With eSIM */ 1010 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 1011 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 1012 /* DW5932e (sdx62), Non-eSIM */ 1013 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 1014 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 1015 /* T99W640 (sdx72) */ 1016 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 1017 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w640_info }, 1018 /* DW5934e(sdx72), With eSIM */ 1019 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 1020 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1021 /* DW5934e(sdx72), Non-eSIM */ 1022 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 1023 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe123), 1025 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w760_info }, 1026 /* MV31-W (Cinterion) */ 1027 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 1028 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1029 /* MV31-W (Cinterion), based on new baseline */ 1030 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 1031 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1032 /* MV32-WA (Cinterion) */ 1033 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 1034 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1035 /* MV32-WB (Cinterion) */ 1036 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 1037 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1038 /* T99W175 (sdx55), HP variant */ 1039 { PCI_DEVICE(0x03f0, 0x0a6c), 1040 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1041 /* NETPRISMA LCUR57 (SDX24) */ 1042 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000), 1043 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info }, 1044 /* NETPRISMA FCUN69 (SDX6X) */ 1045 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), 1046 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, 1047 { } 1048 }; 1049 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 1050 1051 enum mhi_pci_device_status { 1052 MHI_PCI_DEV_STARTED, 1053 MHI_PCI_DEV_SUSPENDED, 1054 }; 1055 1056 struct mhi_pci_device { 1057 struct mhi_controller mhi_cntrl; 1058 struct pci_saved_state *pci_state; 1059 struct work_struct recovery_work; 1060 struct timer_list health_check_timer; 1061 unsigned long status; 1062 bool reset_on_remove; 1063 }; 1064 1065 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 1066 void __iomem *addr, u32 *out) 1067 { 1068 *out = readl(addr); 1069 return 0; 1070 } 1071 1072 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 1073 void __iomem *addr, u32 val) 1074 { 1075 writel(val, addr); 1076 } 1077 1078 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 1079 enum mhi_callback cb) 1080 { 1081 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1082 1083 /* Nothing to do for now */ 1084 switch (cb) { 1085 case MHI_CB_FATAL_ERROR: 1086 case MHI_CB_SYS_ERROR: 1087 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 1088 pm_runtime_forbid(&pdev->dev); 1089 break; 1090 case MHI_CB_EE_MISSION_MODE: 1091 pm_runtime_allow(&pdev->dev); 1092 break; 1093 default: 1094 break; 1095 } 1096 } 1097 1098 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 1099 { 1100 /* no-op */ 1101 } 1102 1103 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 1104 { 1105 /* no-op */ 1106 } 1107 1108 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 1109 { 1110 /* no-op */ 1111 } 1112 1113 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 1114 { 1115 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1116 u16 vendor = 0; 1117 1118 if (pci_read_config_word(pci_physfn(pdev), PCI_VENDOR_ID, &vendor)) 1119 return false; 1120 1121 if (vendor == (u16) ~0 || vendor == 0) 1122 return false; 1123 1124 return true; 1125 } 1126 1127 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 1128 unsigned int bar_num, u64 dma_mask) 1129 { 1130 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1131 int err; 1132 1133 err = pcim_enable_device(pdev); 1134 if (err) { 1135 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 1136 return err; 1137 } 1138 1139 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev)); 1140 if (IS_ERR(mhi_cntrl->regs)) { 1141 err = PTR_ERR(mhi_cntrl->regs); 1142 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 1143 return err; 1144 } 1145 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 1146 1147 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 1148 if (err) { 1149 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 1150 return err; 1151 } 1152 1153 pci_set_master(pdev); 1154 1155 return 0; 1156 } 1157 1158 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 1159 const struct mhi_controller_config *mhi_cntrl_config) 1160 { 1161 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1162 int nr_vectors, i; 1163 int *irq; 1164 1165 /* 1166 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 1167 * No explicit pci_free_irq_vectors required, done by pcim_release. 1168 */ 1169 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 1170 1171 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); 1172 if (nr_vectors < 0) { 1173 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 1174 nr_vectors); 1175 return nr_vectors; 1176 } 1177 1178 if (nr_vectors < mhi_cntrl->nr_irqs) { 1179 dev_warn(&pdev->dev, "using shared MSI\n"); 1180 1181 /* Patch msi vectors, use only one (shared) */ 1182 for (i = 0; i < mhi_cntrl_config->num_events; i++) 1183 mhi_cntrl_config->event_cfg[i].irq = 0; 1184 mhi_cntrl->nr_irqs = 1; 1185 } 1186 1187 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 1188 if (!irq) 1189 return -ENOMEM; 1190 1191 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 1192 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 1193 1194 irq[i] = pci_irq_vector(pdev, vector); 1195 } 1196 1197 mhi_cntrl->irq = irq; 1198 1199 return 0; 1200 } 1201 1202 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 1203 { 1204 /* The runtime_get() MHI callback means: 1205 * Do whatever is requested to leave M3. 1206 */ 1207 return pm_runtime_get(mhi_cntrl->cntrl_dev); 1208 } 1209 1210 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 1211 { 1212 /* The runtime_put() MHI callback means: 1213 * Device can be moved in M3 state. 1214 */ 1215 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 1216 pm_runtime_put(mhi_cntrl->cntrl_dev); 1217 } 1218 1219 static void mhi_pci_recovery_work(struct work_struct *work) 1220 { 1221 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 1222 recovery_work); 1223 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1224 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1225 int err; 1226 1227 dev_warn(&pdev->dev, "device recovery started\n"); 1228 1229 if (pdev->is_physfn) 1230 timer_delete(&mhi_pdev->health_check_timer); 1231 1232 pm_runtime_forbid(&pdev->dev); 1233 1234 /* Clean up MHI state */ 1235 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1236 mhi_power_down(mhi_cntrl, false); 1237 mhi_unprepare_after_power_down(mhi_cntrl); 1238 } 1239 1240 pci_set_power_state(pdev, PCI_D0); 1241 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1242 pci_restore_state(pdev); 1243 1244 if (!mhi_pci_is_alive(mhi_cntrl)) 1245 goto err_try_reset; 1246 1247 err = mhi_prepare_for_power_up(mhi_cntrl); 1248 if (err) 1249 goto err_try_reset; 1250 1251 err = mhi_sync_power_up(mhi_cntrl); 1252 if (err) 1253 goto err_unprepare; 1254 1255 dev_dbg(&pdev->dev, "Recovery completed\n"); 1256 1257 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1258 1259 if (pdev->is_physfn) 1260 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1261 1262 return; 1263 1264 err_unprepare: 1265 mhi_unprepare_after_power_down(mhi_cntrl); 1266 err_try_reset: 1267 err = pci_try_reset_function(pdev); 1268 if (err) 1269 dev_err(&pdev->dev, "Recovery failed: %d\n", err); 1270 } 1271 1272 static void health_check(struct timer_list *t) 1273 { 1274 struct mhi_pci_device *mhi_pdev = timer_container_of(mhi_pdev, t, 1275 health_check_timer); 1276 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1277 1278 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1279 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1280 return; 1281 1282 if (!mhi_pci_is_alive(mhi_cntrl)) { 1283 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1284 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1285 return; 1286 } 1287 1288 /* reschedule in two seconds */ 1289 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1290 } 1291 1292 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1293 { 1294 void __iomem *base = mhi_cntrl->regs; 1295 void __iomem *edl_db; 1296 int ret; 1297 u32 val; 1298 1299 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1300 if (ret) { 1301 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1302 return ret; 1303 } 1304 1305 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1306 mhi_cntrl->runtime_get(mhi_cntrl); 1307 1308 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1309 if (ret) 1310 goto err_get_chdb; 1311 1312 edl_db = base + val + (8 * MHI_EDL_DB); 1313 1314 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1315 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1316 1317 mhi_soc_reset(mhi_cntrl); 1318 1319 err_get_chdb: 1320 mhi_cntrl->runtime_put(mhi_cntrl); 1321 mhi_device_put(mhi_cntrl->mhi_dev); 1322 1323 return ret; 1324 } 1325 1326 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1327 { 1328 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1329 const struct mhi_controller_config *mhi_cntrl_config; 1330 struct mhi_pci_device *mhi_pdev; 1331 struct mhi_controller *mhi_cntrl; 1332 unsigned int dma_data_width; 1333 int err; 1334 1335 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1336 1337 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1338 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1339 if (!mhi_pdev) 1340 return -ENOMEM; 1341 1342 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1343 1344 if (pdev->is_virtfn && info->vf_config) 1345 mhi_cntrl_config = info->vf_config; 1346 else 1347 mhi_cntrl_config = info->config; 1348 1349 /* Initialize health check monitor only for Physical functions */ 1350 if (pdev->is_physfn) 1351 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1352 1353 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1354 1355 dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ? 1356 info->vf_dma_data_width : info->dma_data_width; 1357 1358 mhi_cntrl->cntrl_dev = &pdev->dev; 1359 mhi_cntrl->iova_start = 0; 1360 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width); 1361 mhi_cntrl->fw_image = info->fw; 1362 mhi_cntrl->edl_image = info->edl; 1363 1364 mhi_cntrl->read_reg = mhi_pci_read_reg; 1365 mhi_cntrl->write_reg = mhi_pci_write_reg; 1366 mhi_cntrl->status_cb = mhi_pci_status_cb; 1367 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1368 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1369 mhi_cntrl->mru = info->mru_default; 1370 mhi_cntrl->name = info->name; 1371 1372 if (pdev->is_physfn) 1373 mhi_pdev->reset_on_remove = info->reset_on_remove; 1374 1375 if (info->edl_trigger) 1376 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1377 1378 if (info->sideband_wake) { 1379 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1380 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1381 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1382 } 1383 1384 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_width)); 1385 if (err) 1386 return err; 1387 1388 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1389 if (err) 1390 return err; 1391 1392 pci_set_drvdata(pdev, mhi_pdev); 1393 1394 /* Have stored pci confspace at hand for restore in sudden PCI error. 1395 * cache the state locally and discard the PCI core one. 1396 */ 1397 pci_save_state(pdev); 1398 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1399 pci_load_saved_state(pdev, NULL); 1400 1401 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1402 if (err) 1403 return err; 1404 1405 /* MHI bus does not power up the controller by default */ 1406 err = mhi_prepare_for_power_up(mhi_cntrl); 1407 if (err) { 1408 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1409 goto err_unregister; 1410 } 1411 1412 err = mhi_sync_power_up(mhi_cntrl); 1413 if (err) { 1414 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1415 goto err_unprepare; 1416 } 1417 1418 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1419 1420 /* start health check */ 1421 if (pdev->is_physfn) 1422 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1423 1424 /* Allow runtime suspend only if both PME from D3Hot and M3 are supported */ 1425 if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) { 1426 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1427 pm_runtime_use_autosuspend(&pdev->dev); 1428 pm_runtime_mark_last_busy(&pdev->dev); 1429 pm_runtime_put_noidle(&pdev->dev); 1430 } 1431 1432 return 0; 1433 1434 err_unprepare: 1435 mhi_unprepare_after_power_down(mhi_cntrl); 1436 err_unregister: 1437 mhi_unregister_controller(mhi_cntrl); 1438 1439 return err; 1440 } 1441 1442 static void mhi_pci_remove(struct pci_dev *pdev) 1443 { 1444 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1445 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1446 1447 pci_disable_sriov(pdev); 1448 1449 if (pdev->is_physfn) 1450 timer_delete_sync(&mhi_pdev->health_check_timer); 1451 cancel_work_sync(&mhi_pdev->recovery_work); 1452 1453 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1454 mhi_power_down(mhi_cntrl, true); 1455 mhi_unprepare_after_power_down(mhi_cntrl); 1456 } 1457 1458 /* balancing probe put_noidle */ 1459 if (pci_pme_capable(pdev, PCI_D3hot)) 1460 pm_runtime_get_noresume(&pdev->dev); 1461 1462 if (mhi_pdev->reset_on_remove) 1463 mhi_soc_reset(mhi_cntrl); 1464 1465 mhi_unregister_controller(mhi_cntrl); 1466 } 1467 1468 static void mhi_pci_shutdown(struct pci_dev *pdev) 1469 { 1470 mhi_pci_remove(pdev); 1471 pci_set_power_state(pdev, PCI_D3hot); 1472 } 1473 1474 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1475 { 1476 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1477 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1478 1479 dev_info(&pdev->dev, "reset\n"); 1480 1481 if (pdev->is_physfn) 1482 timer_delete(&mhi_pdev->health_check_timer); 1483 1484 /* Clean up MHI state */ 1485 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1486 mhi_power_down(mhi_cntrl, false); 1487 mhi_unprepare_after_power_down(mhi_cntrl); 1488 } 1489 1490 /* cause internal device reset */ 1491 mhi_soc_reset(mhi_cntrl); 1492 1493 /* Be sure device reset has been executed */ 1494 msleep(MHI_POST_RESET_DELAY_MS); 1495 } 1496 1497 static void mhi_pci_reset_done(struct pci_dev *pdev) 1498 { 1499 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1500 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1501 int err; 1502 1503 /* Restore initial known working PCI state */ 1504 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1505 pci_restore_state(pdev); 1506 1507 /* Is device status available ? */ 1508 if (!mhi_pci_is_alive(mhi_cntrl)) { 1509 dev_err(&pdev->dev, "reset failed\n"); 1510 return; 1511 } 1512 1513 err = mhi_prepare_for_power_up(mhi_cntrl); 1514 if (err) { 1515 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1516 return; 1517 } 1518 1519 err = mhi_sync_power_up(mhi_cntrl); 1520 if (err) { 1521 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1522 mhi_unprepare_after_power_down(mhi_cntrl); 1523 return; 1524 } 1525 1526 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1527 if (pdev->is_physfn) 1528 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1529 } 1530 1531 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1532 pci_channel_state_t state) 1533 { 1534 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1535 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1536 1537 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1538 1539 if (state == pci_channel_io_perm_failure) 1540 return PCI_ERS_RESULT_DISCONNECT; 1541 1542 /* Clean up MHI state */ 1543 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1544 mhi_power_down(mhi_cntrl, false); 1545 mhi_unprepare_after_power_down(mhi_cntrl); 1546 } else { 1547 /* Nothing to do */ 1548 return PCI_ERS_RESULT_RECOVERED; 1549 } 1550 1551 pci_disable_device(pdev); 1552 1553 return PCI_ERS_RESULT_NEED_RESET; 1554 } 1555 1556 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1557 { 1558 if (pci_enable_device(pdev)) { 1559 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1560 return PCI_ERS_RESULT_DISCONNECT; 1561 } 1562 1563 return PCI_ERS_RESULT_RECOVERED; 1564 } 1565 1566 static void mhi_pci_io_resume(struct pci_dev *pdev) 1567 { 1568 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1569 1570 dev_err(&pdev->dev, "PCI slot reset done\n"); 1571 1572 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1573 } 1574 1575 static const struct pci_error_handlers mhi_pci_err_handler = { 1576 .error_detected = mhi_pci_error_detected, 1577 .slot_reset = mhi_pci_slot_reset, 1578 .resume = mhi_pci_io_resume, 1579 .reset_prepare = mhi_pci_reset_prepare, 1580 .reset_done = mhi_pci_reset_done, 1581 }; 1582 1583 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1584 { 1585 struct pci_dev *pdev = to_pci_dev(dev); 1586 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1587 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1588 int err; 1589 1590 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1591 return 0; 1592 1593 if (pdev->is_physfn) 1594 timer_delete(&mhi_pdev->health_check_timer); 1595 1596 cancel_work_sync(&mhi_pdev->recovery_work); 1597 1598 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1599 mhi_cntrl->ee != MHI_EE_AMSS) 1600 goto pci_suspend; /* Nothing to do at MHI level */ 1601 1602 /* Transition to M3 state */ 1603 err = mhi_pm_suspend(mhi_cntrl); 1604 if (err) { 1605 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1606 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1607 return -EBUSY; 1608 } 1609 1610 pci_suspend: 1611 pci_disable_device(pdev); 1612 pci_wake_from_d3(pdev, true); 1613 1614 return 0; 1615 } 1616 1617 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1618 { 1619 struct pci_dev *pdev = to_pci_dev(dev); 1620 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1621 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1622 int err; 1623 1624 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1625 return 0; 1626 1627 err = pci_enable_device(pdev); 1628 if (err) 1629 goto err_recovery; 1630 1631 pci_set_master(pdev); 1632 pci_wake_from_d3(pdev, false); 1633 1634 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1635 mhi_cntrl->ee != MHI_EE_AMSS) 1636 return 0; /* Nothing to do at MHI level */ 1637 1638 /* Exit M3, transition to M0 state */ 1639 err = mhi_pm_resume(mhi_cntrl); 1640 if (err) { 1641 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1642 goto err_recovery; 1643 } 1644 1645 /* Resume health check */ 1646 if (pdev->is_physfn) 1647 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1648 1649 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1650 pm_runtime_mark_last_busy(dev); 1651 1652 return 0; 1653 1654 err_recovery: 1655 /* Do not fail to not mess up our PCI device state, the device likely 1656 * lost power (d3cold) and we simply need to reset it from the recovery 1657 * procedure, trigger the recovery asynchronously to prevent system 1658 * suspend exit delaying. 1659 */ 1660 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1661 pm_runtime_mark_last_busy(dev); 1662 1663 return 0; 1664 } 1665 1666 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1667 { 1668 pm_runtime_disable(dev); 1669 return mhi_pci_runtime_suspend(dev); 1670 } 1671 1672 static int __maybe_unused mhi_pci_resume(struct device *dev) 1673 { 1674 int ret; 1675 1676 /* Depending the platform, device may have lost power (d3cold), we need 1677 * to resume it now to check its state and recover when necessary. 1678 */ 1679 ret = mhi_pci_runtime_resume(dev); 1680 pm_runtime_enable(dev); 1681 1682 return ret; 1683 } 1684 1685 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1686 { 1687 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1688 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1689 1690 /* We want to stop all operations, hibernation does not guarantee that 1691 * device will be in the same state as before freezing, especially if 1692 * the intermediate restore kernel reinitializes MHI device with new 1693 * context. 1694 */ 1695 flush_work(&mhi_pdev->recovery_work); 1696 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1697 mhi_power_down(mhi_cntrl, true); 1698 mhi_unprepare_after_power_down(mhi_cntrl); 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int __maybe_unused mhi_pci_restore(struct device *dev) 1705 { 1706 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1707 1708 /* Reinitialize the device */ 1709 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1710 1711 return 0; 1712 } 1713 1714 static const struct dev_pm_ops mhi_pci_pm_ops = { 1715 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1716 #ifdef CONFIG_PM_SLEEP 1717 .suspend = mhi_pci_suspend, 1718 .resume = mhi_pci_resume, 1719 .freeze = mhi_pci_freeze, 1720 .thaw = mhi_pci_restore, 1721 .poweroff = mhi_pci_freeze, 1722 .restore = mhi_pci_restore, 1723 #endif 1724 }; 1725 1726 static struct pci_driver mhi_pci_driver = { 1727 .name = "mhi-pci-generic", 1728 .id_table = mhi_pci_id_table, 1729 .probe = mhi_pci_probe, 1730 .remove = mhi_pci_remove, 1731 .shutdown = mhi_pci_shutdown, 1732 .err_handler = &mhi_pci_err_handler, 1733 .driver.pm = &mhi_pci_pm_ops, 1734 .sriov_configure = pci_sriov_configure_simple, 1735 }; 1736 module_pci_driver(mhi_pci_driver); 1737 1738 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1739 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1740 MODULE_LICENSE("GPL"); 1741