1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timer.h> 18 #include <linux/workqueue.h> 19 20 #define MHI_PCI_DEFAULT_BAR_NUM 0 21 22 #define MHI_POST_RESET_DELAY_MS 2000 23 24 #define HEALTH_CHECK_PERIOD (HZ * 2) 25 26 /* PCI VID definitions */ 27 #define PCI_VENDOR_ID_THALES 0x1269 28 #define PCI_VENDOR_ID_QUECTEL 0x1eac 29 30 #define MHI_EDL_DB 91 31 #define MHI_EDL_COOKIE 0xEDEDEDED 32 33 /** 34 * struct mhi_pci_dev_info - MHI PCI device specific information 35 * @config: MHI controller configuration 36 * @name: name of the PCI module 37 * @fw: firmware path (if any) 38 * @edl: emergency download mode firmware path (if any) 39 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 40 * @bar_num: PCI base address register to use for MHI MMIO register space 41 * @dma_data_width: DMA transfer word size (32 or 64 bits) 42 * @mru_default: default MRU size for MBIM network packets 43 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 44 * of inband wake support (such as sdx24) 45 */ 46 struct mhi_pci_dev_info { 47 const struct mhi_controller_config *config; 48 const char *name; 49 const char *fw; 50 const char *edl; 51 bool edl_trigger; 52 unsigned int bar_num; 53 unsigned int dma_data_width; 54 unsigned int mru_default; 55 bool sideband_wake; 56 }; 57 58 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 59 { \ 60 .num = ch_num, \ 61 .name = ch_name, \ 62 .num_elements = el_count, \ 63 .event_ring = ev_ring, \ 64 .dir = DMA_TO_DEVICE, \ 65 .ee_mask = BIT(MHI_EE_AMSS), \ 66 .pollcfg = 0, \ 67 .doorbell = MHI_DB_BRST_DISABLE, \ 68 .lpm_notify = false, \ 69 .offload_channel = false, \ 70 .doorbell_mode_switch = false, \ 71 } \ 72 73 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 74 { \ 75 .num = ch_num, \ 76 .name = ch_name, \ 77 .num_elements = el_count, \ 78 .event_ring = ev_ring, \ 79 .dir = DMA_FROM_DEVICE, \ 80 .ee_mask = BIT(MHI_EE_AMSS), \ 81 .pollcfg = 0, \ 82 .doorbell = MHI_DB_BRST_DISABLE, \ 83 .lpm_notify = false, \ 84 .offload_channel = false, \ 85 .doorbell_mode_switch = false, \ 86 } 87 88 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ 89 { \ 90 .num = ch_num, \ 91 .name = ch_name, \ 92 .num_elements = el_count, \ 93 .event_ring = ev_ring, \ 94 .dir = DMA_FROM_DEVICE, \ 95 .ee_mask = BIT(MHI_EE_AMSS), \ 96 .pollcfg = 0, \ 97 .doorbell = MHI_DB_BRST_DISABLE, \ 98 .lpm_notify = false, \ 99 .offload_channel = false, \ 100 .doorbell_mode_switch = false, \ 101 .auto_queue = true, \ 102 } 103 104 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 105 { \ 106 .num_elements = el_count, \ 107 .irq_moderation_ms = 0, \ 108 .irq = (ev_ring) + 1, \ 109 .priority = 1, \ 110 .mode = MHI_DB_BRST_DISABLE, \ 111 .data_type = MHI_ER_CTRL, \ 112 .hardware_event = false, \ 113 .client_managed = false, \ 114 .offload_channel = false, \ 115 } 116 117 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 118 { \ 119 .num = ch_num, \ 120 .name = ch_name, \ 121 .num_elements = el_count, \ 122 .event_ring = ev_ring, \ 123 .dir = DMA_TO_DEVICE, \ 124 .ee_mask = BIT(MHI_EE_AMSS), \ 125 .pollcfg = 0, \ 126 .doorbell = MHI_DB_BRST_ENABLE, \ 127 .lpm_notify = false, \ 128 .offload_channel = false, \ 129 .doorbell_mode_switch = true, \ 130 } \ 131 132 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 133 { \ 134 .num = ch_num, \ 135 .name = ch_name, \ 136 .num_elements = el_count, \ 137 .event_ring = ev_ring, \ 138 .dir = DMA_FROM_DEVICE, \ 139 .ee_mask = BIT(MHI_EE_AMSS), \ 140 .pollcfg = 0, \ 141 .doorbell = MHI_DB_BRST_ENABLE, \ 142 .lpm_notify = false, \ 143 .offload_channel = false, \ 144 .doorbell_mode_switch = true, \ 145 } 146 147 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 148 { \ 149 .num = ch_num, \ 150 .name = ch_name, \ 151 .num_elements = el_count, \ 152 .event_ring = ev_ring, \ 153 .dir = DMA_TO_DEVICE, \ 154 .ee_mask = BIT(MHI_EE_SBL), \ 155 .pollcfg = 0, \ 156 .doorbell = MHI_DB_BRST_DISABLE, \ 157 .lpm_notify = false, \ 158 .offload_channel = false, \ 159 .doorbell_mode_switch = false, \ 160 } \ 161 162 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 163 { \ 164 .num = ch_num, \ 165 .name = ch_name, \ 166 .num_elements = el_count, \ 167 .event_ring = ev_ring, \ 168 .dir = DMA_FROM_DEVICE, \ 169 .ee_mask = BIT(MHI_EE_SBL), \ 170 .pollcfg = 0, \ 171 .doorbell = MHI_DB_BRST_DISABLE, \ 172 .lpm_notify = false, \ 173 .offload_channel = false, \ 174 .doorbell_mode_switch = false, \ 175 } 176 177 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 178 { \ 179 .num = ch_num, \ 180 .name = ch_name, \ 181 .num_elements = el_count, \ 182 .event_ring = ev_ring, \ 183 .dir = DMA_TO_DEVICE, \ 184 .ee_mask = BIT(MHI_EE_FP), \ 185 .pollcfg = 0, \ 186 .doorbell = MHI_DB_BRST_DISABLE, \ 187 .lpm_notify = false, \ 188 .offload_channel = false, \ 189 .doorbell_mode_switch = false, \ 190 } \ 191 192 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 193 { \ 194 .num = ch_num, \ 195 .name = ch_name, \ 196 .num_elements = el_count, \ 197 .event_ring = ev_ring, \ 198 .dir = DMA_FROM_DEVICE, \ 199 .ee_mask = BIT(MHI_EE_FP), \ 200 .pollcfg = 0, \ 201 .doorbell = MHI_DB_BRST_DISABLE, \ 202 .lpm_notify = false, \ 203 .offload_channel = false, \ 204 .doorbell_mode_switch = false, \ 205 } 206 207 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 208 { \ 209 .num_elements = el_count, \ 210 .irq_moderation_ms = 5, \ 211 .irq = (ev_ring) + 1, \ 212 .priority = 1, \ 213 .mode = MHI_DB_BRST_DISABLE, \ 214 .data_type = MHI_ER_DATA, \ 215 .hardware_event = false, \ 216 .client_managed = false, \ 217 .offload_channel = false, \ 218 } 219 220 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 221 { \ 222 .num_elements = el_count, \ 223 .irq_moderation_ms = 0, \ 224 .irq = (ev_ring) + 1, \ 225 .priority = 1, \ 226 .mode = MHI_DB_BRST_DISABLE, \ 227 .data_type = MHI_ER_DATA, \ 228 .hardware_event = false, \ 229 .client_managed = false, \ 230 .offload_channel = false, \ 231 } 232 233 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 234 { \ 235 .num_elements = el_count, \ 236 .irq_moderation_ms = 1, \ 237 .irq = (ev_ring) + 1, \ 238 .priority = 1, \ 239 .mode = MHI_DB_BRST_DISABLE, \ 240 .data_type = MHI_ER_DATA, \ 241 .hardware_event = true, \ 242 .client_managed = false, \ 243 .offload_channel = false, \ 244 .channel = ch_num, \ 245 } 246 247 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 248 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 249 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 250 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 251 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 252 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 253 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 254 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 255 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), 256 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 257 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 258 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 259 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 260 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 261 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 262 }; 263 264 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 265 /* first ring is control+data ring */ 266 MHI_EVENT_CONFIG_CTRL(0, 64), 267 /* DIAG dedicated event ring */ 268 MHI_EVENT_CONFIG_DATA(1, 128), 269 /* Software channels dedicated event ring */ 270 MHI_EVENT_CONFIG_SW_DATA(2, 64), 271 MHI_EVENT_CONFIG_SW_DATA(3, 64), 272 /* Hardware channels request dedicated hardware event rings */ 273 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 274 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 275 }; 276 277 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 278 .max_channels = 128, 279 .timeout_ms = 8000, 280 .ready_timeout_ms = 50000, 281 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 282 .ch_cfg = modem_qcom_v1_mhi_channels, 283 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 284 .event_cfg = modem_qcom_v1_mhi_events, 285 }; 286 287 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 288 .max_channels = 128, 289 .timeout_ms = 8000, 290 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 291 .ch_cfg = modem_qcom_v1_mhi_channels, 292 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 293 .event_cfg = modem_qcom_v1_mhi_events, 294 }; 295 296 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 297 .name = "qcom-sdx75m", 298 .fw = "qcom/sdx75m/xbl.elf", 299 .edl = "qcom/sdx75m/edl.mbn", 300 .edl_trigger = true, 301 .config = &modem_qcom_v2_mhiv_config, 302 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 303 .dma_data_width = 32, 304 .sideband_wake = false, 305 }; 306 307 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 308 .name = "qcom-sdx65m", 309 .fw = "qcom/sdx65m/xbl.elf", 310 .edl = "qcom/sdx65m/edl.mbn", 311 .edl_trigger = true, 312 .config = &modem_qcom_v1_mhiv_config, 313 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 314 .dma_data_width = 32, 315 .sideband_wake = false, 316 }; 317 318 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 319 .name = "qcom-sdx55m", 320 .fw = "qcom/sdx55m/sbl1.mbn", 321 .edl = "qcom/sdx55m/edl.mbn", 322 .edl_trigger = true, 323 .config = &modem_qcom_v1_mhiv_config, 324 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 325 .dma_data_width = 32, 326 .mru_default = 32768, 327 .sideband_wake = false, 328 }; 329 330 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 331 .name = "qcom-sdx24", 332 .edl = "qcom/prog_firehose_sdx24.mbn", 333 .config = &modem_qcom_v1_mhiv_config, 334 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 335 .dma_data_width = 32, 336 .sideband_wake = true, 337 }; 338 339 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 340 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 341 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 342 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 343 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 344 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 345 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 346 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 347 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 348 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 349 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 350 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 351 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 352 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 353 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 354 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 355 }; 356 357 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 358 MHI_EVENT_CONFIG_CTRL(0, 128), 359 MHI_EVENT_CONFIG_DATA(1, 128), 360 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 361 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 362 }; 363 364 static const struct mhi_controller_config modem_quectel_em1xx_config = { 365 .max_channels = 128, 366 .timeout_ms = 20000, 367 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 368 .ch_cfg = mhi_quectel_em1xx_channels, 369 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 370 .event_cfg = mhi_quectel_em1xx_events, 371 }; 372 373 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 374 .name = "quectel-em1xx", 375 .edl = "qcom/prog_firehose_sdx24.mbn", 376 .config = &modem_quectel_em1xx_config, 377 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 378 .dma_data_width = 32, 379 .mru_default = 32768, 380 .sideband_wake = true, 381 }; 382 383 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 384 .name = "quectel-rm5xx", 385 .edl = "qcom/prog_firehose_sdx6x.elf", 386 .config = &modem_quectel_em1xx_config, 387 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 388 .dma_data_width = 32, 389 .mru_default = 32768, 390 .sideband_wake = true, 391 }; 392 393 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 394 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 395 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 396 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 397 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 398 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 399 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 400 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 401 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 402 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 403 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 404 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 405 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 406 }; 407 408 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 409 MHI_EVENT_CONFIG_CTRL(0, 128), 410 MHI_EVENT_CONFIG_DATA(1, 128), 411 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 412 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 413 }; 414 415 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 416 .max_channels = 128, 417 .timeout_ms = 20000, 418 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 419 .ch_cfg = mhi_foxconn_sdx55_channels, 420 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 421 .event_cfg = mhi_foxconn_sdx55_events, 422 }; 423 424 static const struct mhi_controller_config modem_foxconn_sdx72_config = { 425 .max_channels = 128, 426 .timeout_ms = 20000, 427 .ready_timeout_ms = 50000, 428 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 429 .ch_cfg = mhi_foxconn_sdx55_channels, 430 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 431 .event_cfg = mhi_foxconn_sdx55_events, 432 }; 433 434 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 435 .name = "foxconn-sdx55", 436 .fw = "qcom/sdx55m/sbl1.mbn", 437 .edl = "qcom/sdx55m/edl.mbn", 438 .config = &modem_foxconn_sdx55_config, 439 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 440 .dma_data_width = 32, 441 .mru_default = 32768, 442 .sideband_wake = false, 443 }; 444 445 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 446 .name = "foxconn-t99w175", 447 .fw = "qcom/sdx55m/sbl1.mbn", 448 .edl = "qcom/sdx55m/edl.mbn", 449 .config = &modem_foxconn_sdx55_config, 450 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 451 .dma_data_width = 32, 452 .mru_default = 32768, 453 .sideband_wake = false, 454 }; 455 456 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 457 .name = "foxconn-dw5930e", 458 .fw = "qcom/sdx55m/sbl1.mbn", 459 .edl = "qcom/sdx55m/edl.mbn", 460 .config = &modem_foxconn_sdx55_config, 461 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 462 .dma_data_width = 32, 463 .mru_default = 32768, 464 .sideband_wake = false, 465 }; 466 467 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 468 .name = "foxconn-t99w368", 469 .config = &modem_foxconn_sdx55_config, 470 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 471 .dma_data_width = 32, 472 .mru_default = 32768, 473 .sideband_wake = false, 474 }; 475 476 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 477 .name = "foxconn-t99w373", 478 .config = &modem_foxconn_sdx55_config, 479 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 480 .dma_data_width = 32, 481 .mru_default = 32768, 482 .sideband_wake = false, 483 }; 484 485 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 486 .name = "foxconn-t99w510", 487 .config = &modem_foxconn_sdx55_config, 488 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 489 .dma_data_width = 32, 490 .mru_default = 32768, 491 .sideband_wake = false, 492 }; 493 494 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 495 .name = "foxconn-dw5932e", 496 .config = &modem_foxconn_sdx55_config, 497 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 498 .dma_data_width = 32, 499 .mru_default = 32768, 500 .sideband_wake = false, 501 }; 502 503 static const struct mhi_pci_dev_info mhi_foxconn_t99w515_info = { 504 .name = "foxconn-t99w515", 505 .edl = "fox/sdx72m/edl.mbn", 506 .edl_trigger = true, 507 .config = &modem_foxconn_sdx72_config, 508 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 509 .dma_data_width = 32, 510 .mru_default = 32768, 511 .sideband_wake = false, 512 }; 513 514 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 515 .name = "foxconn-dw5934e", 516 .edl = "fox/sdx72m/edl.mbn", 517 .edl_trigger = true, 518 .config = &modem_foxconn_sdx72_config, 519 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 520 .dma_data_width = 32, 521 .mru_default = 32768, 522 .sideband_wake = false, 523 }; 524 525 static const struct mhi_channel_config mhi_mv3x_channels[] = { 526 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 527 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 528 /* MBIM Control Channel */ 529 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 530 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 531 /* MBIM Data Channel */ 532 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 533 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 534 }; 535 536 static struct mhi_event_config mhi_mv3x_events[] = { 537 MHI_EVENT_CONFIG_CTRL(0, 256), 538 MHI_EVENT_CONFIG_DATA(1, 256), 539 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 540 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 541 }; 542 543 static const struct mhi_controller_config modem_mv3x_config = { 544 .max_channels = 128, 545 .timeout_ms = 20000, 546 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 547 .ch_cfg = mhi_mv3x_channels, 548 .num_events = ARRAY_SIZE(mhi_mv3x_events), 549 .event_cfg = mhi_mv3x_events, 550 }; 551 552 static const struct mhi_pci_dev_info mhi_mv31_info = { 553 .name = "cinterion-mv31", 554 .config = &modem_mv3x_config, 555 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 556 .dma_data_width = 32, 557 .mru_default = 32768, 558 }; 559 560 static const struct mhi_pci_dev_info mhi_mv32_info = { 561 .name = "cinterion-mv32", 562 .config = &modem_mv3x_config, 563 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 564 .dma_data_width = 32, 565 .mru_default = 32768, 566 }; 567 568 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 569 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 570 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 571 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 572 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 573 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 574 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 575 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 576 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 577 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 578 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 579 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 580 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 581 }; 582 583 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 584 /* first ring is control+data and DIAG ring */ 585 MHI_EVENT_CONFIG_CTRL(0, 2048), 586 /* Hardware channels request dedicated hardware event rings */ 587 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 588 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 589 }; 590 591 static const struct mhi_controller_config modem_sierra_em919x_config = { 592 .max_channels = 128, 593 .timeout_ms = 24000, 594 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 595 .ch_cfg = mhi_sierra_em919x_channels, 596 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 597 .event_cfg = modem_sierra_em919x_mhi_events, 598 }; 599 600 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 601 .name = "sierra-em919x", 602 .config = &modem_sierra_em919x_config, 603 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 604 .dma_data_width = 32, 605 .sideband_wake = false, 606 }; 607 608 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 609 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 610 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 611 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 612 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0), 613 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 614 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 615 }; 616 617 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 618 MHI_EVENT_CONFIG_CTRL(0, 128), 619 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 620 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 621 }; 622 623 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 624 .max_channels = 128, 625 .timeout_ms = 20000, 626 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 627 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 628 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 629 .event_cfg = mhi_telit_fn980_hw_v1_events, 630 }; 631 632 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 633 .name = "telit-fn980-hwv1", 634 .fw = "qcom/sdx55m/sbl1.mbn", 635 .edl = "qcom/sdx55m/edl.mbn", 636 .config = &modem_telit_fn980_hw_v1_config, 637 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 638 .dma_data_width = 32, 639 .mru_default = 32768, 640 .sideband_wake = false, 641 }; 642 643 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 644 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 645 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 646 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 647 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 648 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 649 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 650 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 651 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 652 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 653 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 654 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 655 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 656 }; 657 658 static struct mhi_event_config mhi_telit_fn990_events[] = { 659 MHI_EVENT_CONFIG_CTRL(0, 128), 660 MHI_EVENT_CONFIG_DATA(1, 128), 661 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 662 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 663 }; 664 665 static const struct mhi_controller_config modem_telit_fn990_config = { 666 .max_channels = 128, 667 .timeout_ms = 20000, 668 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 669 .ch_cfg = mhi_telit_fn990_channels, 670 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 671 .event_cfg = mhi_telit_fn990_events, 672 }; 673 674 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 675 .name = "telit-fn990", 676 .config = &modem_telit_fn990_config, 677 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 678 .dma_data_width = 32, 679 .sideband_wake = false, 680 .mru_default = 32768, 681 }; 682 683 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 684 static const struct pci_device_id mhi_pci_id_table[] = { 685 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 686 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 687 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 688 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 689 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 690 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 691 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 692 /* Telit FN980 hardware revision v1 */ 693 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 694 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 695 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 696 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 697 /* Telit FN990 */ 698 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 699 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 700 /* Telit FE990 */ 701 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 702 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 703 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 704 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 705 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 706 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 707 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 708 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 709 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 710 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 711 /* RM520N-GL (sdx6x), eSIM */ 712 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 713 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 714 /* RM520N-GL (sdx6x), Lenovo variant */ 715 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 716 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 717 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 718 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 719 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 720 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 721 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 722 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 723 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 724 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 725 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 726 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 727 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 728 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 729 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 730 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 731 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 732 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 733 /* T99W175 (sdx55) */ 734 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 735 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 736 /* T99W368 (sdx65) */ 737 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 738 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 739 /* T99W373 (sdx62) */ 740 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 741 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 742 /* T99W510 (sdx24), variant 1 */ 743 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 744 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 745 /* T99W510 (sdx24), variant 2 */ 746 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 747 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 748 /* T99W510 (sdx24), variant 3 */ 749 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 750 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 751 /* DW5932e-eSIM (sdx62), With eSIM */ 752 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 753 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 754 /* DW5932e (sdx62), Non-eSIM */ 755 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 756 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 757 /* T99W515 (sdx72) */ 758 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 759 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w515_info }, 760 /* DW5934e(sdx72), With eSIM */ 761 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 762 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 763 /* DW5934e(sdx72), Non-eSIM */ 764 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 765 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 766 /* MV31-W (Cinterion) */ 767 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 768 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 769 /* MV31-W (Cinterion), based on new baseline */ 770 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 771 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 772 /* MV32-WA (Cinterion) */ 773 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 774 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 775 /* MV32-WB (Cinterion) */ 776 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 777 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 778 /* T99W175 (sdx55), HP variant */ 779 { PCI_DEVICE(0x03f0, 0x0a6c), 780 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 781 { } 782 }; 783 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 784 785 enum mhi_pci_device_status { 786 MHI_PCI_DEV_STARTED, 787 MHI_PCI_DEV_SUSPENDED, 788 }; 789 790 struct mhi_pci_device { 791 struct mhi_controller mhi_cntrl; 792 struct pci_saved_state *pci_state; 793 struct work_struct recovery_work; 794 struct timer_list health_check_timer; 795 unsigned long status; 796 }; 797 798 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 799 void __iomem *addr, u32 *out) 800 { 801 *out = readl(addr); 802 return 0; 803 } 804 805 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 806 void __iomem *addr, u32 val) 807 { 808 writel(val, addr); 809 } 810 811 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 812 enum mhi_callback cb) 813 { 814 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 815 816 /* Nothing to do for now */ 817 switch (cb) { 818 case MHI_CB_FATAL_ERROR: 819 case MHI_CB_SYS_ERROR: 820 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 821 pm_runtime_forbid(&pdev->dev); 822 break; 823 case MHI_CB_EE_MISSION_MODE: 824 pm_runtime_allow(&pdev->dev); 825 break; 826 default: 827 break; 828 } 829 } 830 831 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 832 { 833 /* no-op */ 834 } 835 836 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 837 { 838 /* no-op */ 839 } 840 841 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 842 { 843 /* no-op */ 844 } 845 846 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 847 { 848 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 849 u16 vendor = 0; 850 851 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) 852 return false; 853 854 if (vendor == (u16) ~0 || vendor == 0) 855 return false; 856 857 return true; 858 } 859 860 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 861 unsigned int bar_num, u64 dma_mask) 862 { 863 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 864 int err; 865 866 err = pci_assign_resource(pdev, bar_num); 867 if (err) 868 return err; 869 870 err = pcim_enable_device(pdev); 871 if (err) { 872 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 873 return err; 874 } 875 876 err = pcim_iomap_regions(pdev, 1 << bar_num, pci_name(pdev)); 877 if (err) { 878 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 879 return err; 880 } 881 mhi_cntrl->regs = pcim_iomap_table(pdev)[bar_num]; 882 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 883 884 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 885 if (err) { 886 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 887 return err; 888 } 889 890 pci_set_master(pdev); 891 892 return 0; 893 } 894 895 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 896 const struct mhi_controller_config *mhi_cntrl_config) 897 { 898 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 899 int nr_vectors, i; 900 int *irq; 901 902 /* 903 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 904 * No explicit pci_free_irq_vectors required, done by pcim_release. 905 */ 906 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 907 908 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSI); 909 if (nr_vectors < 0) { 910 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 911 nr_vectors); 912 return nr_vectors; 913 } 914 915 if (nr_vectors < mhi_cntrl->nr_irqs) { 916 dev_warn(&pdev->dev, "using shared MSI\n"); 917 918 /* Patch msi vectors, use only one (shared) */ 919 for (i = 0; i < mhi_cntrl_config->num_events; i++) 920 mhi_cntrl_config->event_cfg[i].irq = 0; 921 mhi_cntrl->nr_irqs = 1; 922 } 923 924 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 925 if (!irq) 926 return -ENOMEM; 927 928 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 929 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 930 931 irq[i] = pci_irq_vector(pdev, vector); 932 } 933 934 mhi_cntrl->irq = irq; 935 936 return 0; 937 } 938 939 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 940 { 941 /* The runtime_get() MHI callback means: 942 * Do whatever is requested to leave M3. 943 */ 944 return pm_runtime_get(mhi_cntrl->cntrl_dev); 945 } 946 947 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 948 { 949 /* The runtime_put() MHI callback means: 950 * Device can be moved in M3 state. 951 */ 952 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 953 pm_runtime_put(mhi_cntrl->cntrl_dev); 954 } 955 956 static void mhi_pci_recovery_work(struct work_struct *work) 957 { 958 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 959 recovery_work); 960 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 961 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 962 int err; 963 964 dev_warn(&pdev->dev, "device recovery started\n"); 965 966 del_timer(&mhi_pdev->health_check_timer); 967 pm_runtime_forbid(&pdev->dev); 968 969 /* Clean up MHI state */ 970 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 971 mhi_power_down(mhi_cntrl, false); 972 mhi_unprepare_after_power_down(mhi_cntrl); 973 } 974 975 pci_set_power_state(pdev, PCI_D0); 976 pci_load_saved_state(pdev, mhi_pdev->pci_state); 977 pci_restore_state(pdev); 978 979 if (!mhi_pci_is_alive(mhi_cntrl)) 980 goto err_try_reset; 981 982 err = mhi_prepare_for_power_up(mhi_cntrl); 983 if (err) 984 goto err_try_reset; 985 986 err = mhi_sync_power_up(mhi_cntrl); 987 if (err) 988 goto err_unprepare; 989 990 dev_dbg(&pdev->dev, "Recovery completed\n"); 991 992 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 993 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 994 return; 995 996 err_unprepare: 997 mhi_unprepare_after_power_down(mhi_cntrl); 998 err_try_reset: 999 if (pci_reset_function(pdev)) 1000 dev_err(&pdev->dev, "Recovery failed\n"); 1001 } 1002 1003 static void health_check(struct timer_list *t) 1004 { 1005 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); 1006 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1007 1008 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1009 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1010 return; 1011 1012 if (!mhi_pci_is_alive(mhi_cntrl)) { 1013 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1014 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1015 return; 1016 } 1017 1018 /* reschedule in two seconds */ 1019 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1020 } 1021 1022 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1023 { 1024 void __iomem *base = mhi_cntrl->regs; 1025 void __iomem *edl_db; 1026 int ret; 1027 u32 val; 1028 1029 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1030 if (ret) { 1031 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1032 return ret; 1033 } 1034 1035 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1036 mhi_cntrl->runtime_get(mhi_cntrl); 1037 1038 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1039 if (ret) 1040 goto err_get_chdb; 1041 1042 edl_db = base + val + (8 * MHI_EDL_DB); 1043 1044 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1045 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1046 1047 mhi_soc_reset(mhi_cntrl); 1048 1049 err_get_chdb: 1050 mhi_cntrl->runtime_put(mhi_cntrl); 1051 mhi_device_put(mhi_cntrl->mhi_dev); 1052 1053 return ret; 1054 } 1055 1056 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1057 { 1058 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1059 const struct mhi_controller_config *mhi_cntrl_config; 1060 struct mhi_pci_device *mhi_pdev; 1061 struct mhi_controller *mhi_cntrl; 1062 int err; 1063 1064 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1065 1066 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1067 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1068 if (!mhi_pdev) 1069 return -ENOMEM; 1070 1071 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1072 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1073 1074 mhi_cntrl_config = info->config; 1075 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1076 1077 mhi_cntrl->cntrl_dev = &pdev->dev; 1078 mhi_cntrl->iova_start = 0; 1079 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); 1080 mhi_cntrl->fw_image = info->fw; 1081 mhi_cntrl->edl_image = info->edl; 1082 1083 mhi_cntrl->read_reg = mhi_pci_read_reg; 1084 mhi_cntrl->write_reg = mhi_pci_write_reg; 1085 mhi_cntrl->status_cb = mhi_pci_status_cb; 1086 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1087 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1088 mhi_cntrl->mru = info->mru_default; 1089 mhi_cntrl->name = info->name; 1090 1091 if (info->edl_trigger) 1092 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1093 1094 if (info->sideband_wake) { 1095 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1096 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1097 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1098 } 1099 1100 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); 1101 if (err) 1102 return err; 1103 1104 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1105 if (err) 1106 return err; 1107 1108 pci_set_drvdata(pdev, mhi_pdev); 1109 1110 /* Have stored pci confspace at hand for restore in sudden PCI error. 1111 * cache the state locally and discard the PCI core one. 1112 */ 1113 pci_save_state(pdev); 1114 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1115 pci_load_saved_state(pdev, NULL); 1116 1117 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1118 if (err) 1119 return err; 1120 1121 /* MHI bus does not power up the controller by default */ 1122 err = mhi_prepare_for_power_up(mhi_cntrl); 1123 if (err) { 1124 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1125 goto err_unregister; 1126 } 1127 1128 err = mhi_sync_power_up(mhi_cntrl); 1129 if (err) { 1130 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1131 goto err_unprepare; 1132 } 1133 1134 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1135 1136 /* start health check */ 1137 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1138 1139 /* Only allow runtime-suspend if PME capable (for wakeup) */ 1140 if (pci_pme_capable(pdev, PCI_D3hot)) { 1141 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1142 pm_runtime_use_autosuspend(&pdev->dev); 1143 pm_runtime_mark_last_busy(&pdev->dev); 1144 pm_runtime_put_noidle(&pdev->dev); 1145 } 1146 1147 return 0; 1148 1149 err_unprepare: 1150 mhi_unprepare_after_power_down(mhi_cntrl); 1151 err_unregister: 1152 mhi_unregister_controller(mhi_cntrl); 1153 1154 return err; 1155 } 1156 1157 static void mhi_pci_remove(struct pci_dev *pdev) 1158 { 1159 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1160 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1161 1162 del_timer_sync(&mhi_pdev->health_check_timer); 1163 cancel_work_sync(&mhi_pdev->recovery_work); 1164 1165 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1166 mhi_power_down(mhi_cntrl, true); 1167 mhi_unprepare_after_power_down(mhi_cntrl); 1168 } 1169 1170 /* balancing probe put_noidle */ 1171 if (pci_pme_capable(pdev, PCI_D3hot)) 1172 pm_runtime_get_noresume(&pdev->dev); 1173 1174 mhi_unregister_controller(mhi_cntrl); 1175 } 1176 1177 static void mhi_pci_shutdown(struct pci_dev *pdev) 1178 { 1179 mhi_pci_remove(pdev); 1180 pci_set_power_state(pdev, PCI_D3hot); 1181 } 1182 1183 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1184 { 1185 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1186 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1187 1188 dev_info(&pdev->dev, "reset\n"); 1189 1190 del_timer(&mhi_pdev->health_check_timer); 1191 1192 /* Clean up MHI state */ 1193 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1194 mhi_power_down(mhi_cntrl, false); 1195 mhi_unprepare_after_power_down(mhi_cntrl); 1196 } 1197 1198 /* cause internal device reset */ 1199 mhi_soc_reset(mhi_cntrl); 1200 1201 /* Be sure device reset has been executed */ 1202 msleep(MHI_POST_RESET_DELAY_MS); 1203 } 1204 1205 static void mhi_pci_reset_done(struct pci_dev *pdev) 1206 { 1207 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1208 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1209 int err; 1210 1211 /* Restore initial known working PCI state */ 1212 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1213 pci_restore_state(pdev); 1214 1215 /* Is device status available ? */ 1216 if (!mhi_pci_is_alive(mhi_cntrl)) { 1217 dev_err(&pdev->dev, "reset failed\n"); 1218 return; 1219 } 1220 1221 err = mhi_prepare_for_power_up(mhi_cntrl); 1222 if (err) { 1223 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1224 return; 1225 } 1226 1227 err = mhi_sync_power_up(mhi_cntrl); 1228 if (err) { 1229 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1230 mhi_unprepare_after_power_down(mhi_cntrl); 1231 return; 1232 } 1233 1234 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1235 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1236 } 1237 1238 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1239 pci_channel_state_t state) 1240 { 1241 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1242 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1243 1244 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1245 1246 if (state == pci_channel_io_perm_failure) 1247 return PCI_ERS_RESULT_DISCONNECT; 1248 1249 /* Clean up MHI state */ 1250 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1251 mhi_power_down(mhi_cntrl, false); 1252 mhi_unprepare_after_power_down(mhi_cntrl); 1253 } else { 1254 /* Nothing to do */ 1255 return PCI_ERS_RESULT_RECOVERED; 1256 } 1257 1258 pci_disable_device(pdev); 1259 1260 return PCI_ERS_RESULT_NEED_RESET; 1261 } 1262 1263 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1264 { 1265 if (pci_enable_device(pdev)) { 1266 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1267 return PCI_ERS_RESULT_DISCONNECT; 1268 } 1269 1270 return PCI_ERS_RESULT_RECOVERED; 1271 } 1272 1273 static void mhi_pci_io_resume(struct pci_dev *pdev) 1274 { 1275 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1276 1277 dev_err(&pdev->dev, "PCI slot reset done\n"); 1278 1279 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1280 } 1281 1282 static const struct pci_error_handlers mhi_pci_err_handler = { 1283 .error_detected = mhi_pci_error_detected, 1284 .slot_reset = mhi_pci_slot_reset, 1285 .resume = mhi_pci_io_resume, 1286 .reset_prepare = mhi_pci_reset_prepare, 1287 .reset_done = mhi_pci_reset_done, 1288 }; 1289 1290 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1291 { 1292 struct pci_dev *pdev = to_pci_dev(dev); 1293 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1294 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1295 int err; 1296 1297 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1298 return 0; 1299 1300 del_timer(&mhi_pdev->health_check_timer); 1301 cancel_work_sync(&mhi_pdev->recovery_work); 1302 1303 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1304 mhi_cntrl->ee != MHI_EE_AMSS) 1305 goto pci_suspend; /* Nothing to do at MHI level */ 1306 1307 /* Transition to M3 state */ 1308 err = mhi_pm_suspend(mhi_cntrl); 1309 if (err) { 1310 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1311 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1312 return -EBUSY; 1313 } 1314 1315 pci_suspend: 1316 pci_disable_device(pdev); 1317 pci_wake_from_d3(pdev, true); 1318 1319 return 0; 1320 } 1321 1322 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1323 { 1324 struct pci_dev *pdev = to_pci_dev(dev); 1325 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1326 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1327 int err; 1328 1329 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1330 return 0; 1331 1332 err = pci_enable_device(pdev); 1333 if (err) 1334 goto err_recovery; 1335 1336 pci_set_master(pdev); 1337 pci_wake_from_d3(pdev, false); 1338 1339 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1340 mhi_cntrl->ee != MHI_EE_AMSS) 1341 return 0; /* Nothing to do at MHI level */ 1342 1343 /* Exit M3, transition to M0 state */ 1344 err = mhi_pm_resume(mhi_cntrl); 1345 if (err) { 1346 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1347 goto err_recovery; 1348 } 1349 1350 /* Resume health check */ 1351 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1352 1353 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1354 pm_runtime_mark_last_busy(dev); 1355 1356 return 0; 1357 1358 err_recovery: 1359 /* Do not fail to not mess up our PCI device state, the device likely 1360 * lost power (d3cold) and we simply need to reset it from the recovery 1361 * procedure, trigger the recovery asynchronously to prevent system 1362 * suspend exit delaying. 1363 */ 1364 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1365 pm_runtime_mark_last_busy(dev); 1366 1367 return 0; 1368 } 1369 1370 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1371 { 1372 pm_runtime_disable(dev); 1373 return mhi_pci_runtime_suspend(dev); 1374 } 1375 1376 static int __maybe_unused mhi_pci_resume(struct device *dev) 1377 { 1378 int ret; 1379 1380 /* Depending the platform, device may have lost power (d3cold), we need 1381 * to resume it now to check its state and recover when necessary. 1382 */ 1383 ret = mhi_pci_runtime_resume(dev); 1384 pm_runtime_enable(dev); 1385 1386 return ret; 1387 } 1388 1389 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1390 { 1391 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1392 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1393 1394 /* We want to stop all operations, hibernation does not guarantee that 1395 * device will be in the same state as before freezing, especially if 1396 * the intermediate restore kernel reinitializes MHI device with new 1397 * context. 1398 */ 1399 flush_work(&mhi_pdev->recovery_work); 1400 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1401 mhi_power_down(mhi_cntrl, true); 1402 mhi_unprepare_after_power_down(mhi_cntrl); 1403 } 1404 1405 return 0; 1406 } 1407 1408 static int __maybe_unused mhi_pci_restore(struct device *dev) 1409 { 1410 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1411 1412 /* Reinitialize the device */ 1413 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1414 1415 return 0; 1416 } 1417 1418 static const struct dev_pm_ops mhi_pci_pm_ops = { 1419 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1420 #ifdef CONFIG_PM_SLEEP 1421 .suspend = mhi_pci_suspend, 1422 .resume = mhi_pci_resume, 1423 .freeze = mhi_pci_freeze, 1424 .thaw = mhi_pci_restore, 1425 .poweroff = mhi_pci_freeze, 1426 .restore = mhi_pci_restore, 1427 #endif 1428 }; 1429 1430 static struct pci_driver mhi_pci_driver = { 1431 .name = "mhi-pci-generic", 1432 .id_table = mhi_pci_id_table, 1433 .probe = mhi_pci_probe, 1434 .remove = mhi_pci_remove, 1435 .shutdown = mhi_pci_shutdown, 1436 .err_handler = &mhi_pci_err_handler, 1437 .driver.pm = &mhi_pci_pm_ops 1438 }; 1439 module_pci_driver(mhi_pci_driver); 1440 1441 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1442 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1443 MODULE_LICENSE("GPL"); 1444