1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timer.h> 18 #include <linux/workqueue.h> 19 20 #define MHI_PCI_DEFAULT_BAR_NUM 0 21 22 #define MHI_POST_RESET_DELAY_MS 2000 23 24 #define HEALTH_CHECK_PERIOD (HZ * 2) 25 26 /* PCI VID definitions */ 27 #define PCI_VENDOR_ID_THALES 0x1269 28 #define PCI_VENDOR_ID_QUECTEL 0x1eac 29 #define PCI_VENDOR_ID_NETPRISMA 0x203e 30 31 #define MHI_EDL_DB 91 32 #define MHI_EDL_COOKIE 0xEDEDEDED 33 34 /** 35 * struct mhi_pci_dev_info - MHI PCI device specific information 36 * @config: MHI controller configuration 37 * @name: name of the PCI module 38 * @fw: firmware path (if any) 39 * @edl: emergency download mode firmware path (if any) 40 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 41 * @bar_num: PCI base address register to use for MHI MMIO register space 42 * @dma_data_width: DMA transfer word size (32 or 64 bits) 43 * @mru_default: default MRU size for MBIM network packets 44 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 45 * of inband wake support (such as sdx24) 46 */ 47 struct mhi_pci_dev_info { 48 const struct mhi_controller_config *config; 49 const char *name; 50 const char *fw; 51 const char *edl; 52 bool edl_trigger; 53 unsigned int bar_num; 54 unsigned int dma_data_width; 55 unsigned int mru_default; 56 bool sideband_wake; 57 }; 58 59 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 60 { \ 61 .num = ch_num, \ 62 .name = ch_name, \ 63 .num_elements = el_count, \ 64 .event_ring = ev_ring, \ 65 .dir = DMA_TO_DEVICE, \ 66 .ee_mask = BIT(MHI_EE_AMSS), \ 67 .pollcfg = 0, \ 68 .doorbell = MHI_DB_BRST_DISABLE, \ 69 .lpm_notify = false, \ 70 .offload_channel = false, \ 71 .doorbell_mode_switch = false, \ 72 } \ 73 74 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 75 { \ 76 .num = ch_num, \ 77 .name = ch_name, \ 78 .num_elements = el_count, \ 79 .event_ring = ev_ring, \ 80 .dir = DMA_FROM_DEVICE, \ 81 .ee_mask = BIT(MHI_EE_AMSS), \ 82 .pollcfg = 0, \ 83 .doorbell = MHI_DB_BRST_DISABLE, \ 84 .lpm_notify = false, \ 85 .offload_channel = false, \ 86 .doorbell_mode_switch = false, \ 87 } 88 89 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ 90 { \ 91 .num = ch_num, \ 92 .name = ch_name, \ 93 .num_elements = el_count, \ 94 .event_ring = ev_ring, \ 95 .dir = DMA_FROM_DEVICE, \ 96 .ee_mask = BIT(MHI_EE_AMSS), \ 97 .pollcfg = 0, \ 98 .doorbell = MHI_DB_BRST_DISABLE, \ 99 .lpm_notify = false, \ 100 .offload_channel = false, \ 101 .doorbell_mode_switch = false, \ 102 .auto_queue = true, \ 103 } 104 105 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 106 { \ 107 .num_elements = el_count, \ 108 .irq_moderation_ms = 0, \ 109 .irq = (ev_ring) + 1, \ 110 .priority = 1, \ 111 .mode = MHI_DB_BRST_DISABLE, \ 112 .data_type = MHI_ER_CTRL, \ 113 .hardware_event = false, \ 114 .client_managed = false, \ 115 .offload_channel = false, \ 116 } 117 118 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 119 { \ 120 .num = ch_num, \ 121 .name = ch_name, \ 122 .num_elements = el_count, \ 123 .event_ring = ev_ring, \ 124 .dir = DMA_TO_DEVICE, \ 125 .ee_mask = BIT(MHI_EE_AMSS), \ 126 .pollcfg = 0, \ 127 .doorbell = MHI_DB_BRST_ENABLE, \ 128 .lpm_notify = false, \ 129 .offload_channel = false, \ 130 .doorbell_mode_switch = true, \ 131 } \ 132 133 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 134 { \ 135 .num = ch_num, \ 136 .name = ch_name, \ 137 .num_elements = el_count, \ 138 .event_ring = ev_ring, \ 139 .dir = DMA_FROM_DEVICE, \ 140 .ee_mask = BIT(MHI_EE_AMSS), \ 141 .pollcfg = 0, \ 142 .doorbell = MHI_DB_BRST_ENABLE, \ 143 .lpm_notify = false, \ 144 .offload_channel = false, \ 145 .doorbell_mode_switch = true, \ 146 } 147 148 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 149 { \ 150 .num = ch_num, \ 151 .name = ch_name, \ 152 .num_elements = el_count, \ 153 .event_ring = ev_ring, \ 154 .dir = DMA_TO_DEVICE, \ 155 .ee_mask = BIT(MHI_EE_SBL), \ 156 .pollcfg = 0, \ 157 .doorbell = MHI_DB_BRST_DISABLE, \ 158 .lpm_notify = false, \ 159 .offload_channel = false, \ 160 .doorbell_mode_switch = false, \ 161 } \ 162 163 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 164 { \ 165 .num = ch_num, \ 166 .name = ch_name, \ 167 .num_elements = el_count, \ 168 .event_ring = ev_ring, \ 169 .dir = DMA_FROM_DEVICE, \ 170 .ee_mask = BIT(MHI_EE_SBL), \ 171 .pollcfg = 0, \ 172 .doorbell = MHI_DB_BRST_DISABLE, \ 173 .lpm_notify = false, \ 174 .offload_channel = false, \ 175 .doorbell_mode_switch = false, \ 176 } 177 178 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 179 { \ 180 .num = ch_num, \ 181 .name = ch_name, \ 182 .num_elements = el_count, \ 183 .event_ring = ev_ring, \ 184 .dir = DMA_TO_DEVICE, \ 185 .ee_mask = BIT(MHI_EE_FP), \ 186 .pollcfg = 0, \ 187 .doorbell = MHI_DB_BRST_DISABLE, \ 188 .lpm_notify = false, \ 189 .offload_channel = false, \ 190 .doorbell_mode_switch = false, \ 191 } \ 192 193 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 194 { \ 195 .num = ch_num, \ 196 .name = ch_name, \ 197 .num_elements = el_count, \ 198 .event_ring = ev_ring, \ 199 .dir = DMA_FROM_DEVICE, \ 200 .ee_mask = BIT(MHI_EE_FP), \ 201 .pollcfg = 0, \ 202 .doorbell = MHI_DB_BRST_DISABLE, \ 203 .lpm_notify = false, \ 204 .offload_channel = false, \ 205 .doorbell_mode_switch = false, \ 206 } 207 208 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 209 { \ 210 .num_elements = el_count, \ 211 .irq_moderation_ms = 5, \ 212 .irq = (ev_ring) + 1, \ 213 .priority = 1, \ 214 .mode = MHI_DB_BRST_DISABLE, \ 215 .data_type = MHI_ER_DATA, \ 216 .hardware_event = false, \ 217 .client_managed = false, \ 218 .offload_channel = false, \ 219 } 220 221 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 222 { \ 223 .num_elements = el_count, \ 224 .irq_moderation_ms = 0, \ 225 .irq = (ev_ring) + 1, \ 226 .priority = 1, \ 227 .mode = MHI_DB_BRST_DISABLE, \ 228 .data_type = MHI_ER_DATA, \ 229 .hardware_event = false, \ 230 .client_managed = false, \ 231 .offload_channel = false, \ 232 } 233 234 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 235 { \ 236 .num_elements = el_count, \ 237 .irq_moderation_ms = 1, \ 238 .irq = (ev_ring) + 1, \ 239 .priority = 1, \ 240 .mode = MHI_DB_BRST_DISABLE, \ 241 .data_type = MHI_ER_DATA, \ 242 .hardware_event = true, \ 243 .client_managed = false, \ 244 .offload_channel = false, \ 245 .channel = ch_num, \ 246 } 247 248 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { 249 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), 250 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), 251 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), 252 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), 253 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), 254 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), 255 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), 256 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), 257 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), 258 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), 259 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), 260 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), 261 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), 262 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), 263 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), 264 }; 265 266 static struct mhi_event_config mhi_qcom_qdu100_events[] = { 267 /* first ring is control+data ring */ 268 MHI_EVENT_CONFIG_CTRL(0, 64), 269 /* SAHARA dedicated event ring */ 270 MHI_EVENT_CONFIG_SW_DATA(1, 256), 271 /* Software channels dedicated event ring */ 272 MHI_EVENT_CONFIG_SW_DATA(2, 64), 273 MHI_EVENT_CONFIG_SW_DATA(3, 256), 274 MHI_EVENT_CONFIG_SW_DATA(4, 256), 275 /* Software IP channels dedicated event ring */ 276 MHI_EVENT_CONFIG_SW_DATA(5, 512), 277 MHI_EVENT_CONFIG_SW_DATA(6, 512), 278 MHI_EVENT_CONFIG_SW_DATA(7, 512), 279 }; 280 281 static const struct mhi_controller_config mhi_qcom_qdu100_config = { 282 .max_channels = 128, 283 .timeout_ms = 120000, 284 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), 285 .ch_cfg = mhi_qcom_qdu100_channels, 286 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), 287 .event_cfg = mhi_qcom_qdu100_events, 288 }; 289 290 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { 291 .name = "qcom-qdu100", 292 .fw = "qcom/qdu100/xbl_s.melf", 293 .edl_trigger = true, 294 .config = &mhi_qcom_qdu100_config, 295 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 296 .dma_data_width = 32, 297 .sideband_wake = false, 298 }; 299 300 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { 301 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), 302 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), 303 }; 304 305 static struct mhi_event_config mhi_qcom_sa8775p_events[] = { 306 /* first ring is control+data ring */ 307 MHI_EVENT_CONFIG_CTRL(0, 64), 308 /* Software channels dedicated event ring */ 309 MHI_EVENT_CONFIG_SW_DATA(1, 64), 310 MHI_EVENT_CONFIG_SW_DATA(2, 64), 311 }; 312 313 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 314 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 315 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 316 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 317 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 318 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 319 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 320 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 321 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), 322 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 323 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 324 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 325 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 326 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 327 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 328 }; 329 330 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 331 /* first ring is control+data ring */ 332 MHI_EVENT_CONFIG_CTRL(0, 64), 333 /* DIAG dedicated event ring */ 334 MHI_EVENT_CONFIG_DATA(1, 128), 335 /* Software channels dedicated event ring */ 336 MHI_EVENT_CONFIG_SW_DATA(2, 64), 337 MHI_EVENT_CONFIG_SW_DATA(3, 64), 338 /* Hardware channels request dedicated hardware event rings */ 339 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 340 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 341 }; 342 343 static const struct mhi_controller_config mhi_qcom_sa8775p_config = { 344 .max_channels = 128, 345 .timeout_ms = 8000, 346 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels), 347 .ch_cfg = mhi_qcom_sa8775p_channels, 348 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events), 349 .event_cfg = mhi_qcom_sa8775p_events, 350 }; 351 352 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 353 .max_channels = 128, 354 .timeout_ms = 8000, 355 .ready_timeout_ms = 50000, 356 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 357 .ch_cfg = modem_qcom_v1_mhi_channels, 358 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 359 .event_cfg = modem_qcom_v1_mhi_events, 360 }; 361 362 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 363 .max_channels = 128, 364 .timeout_ms = 8000, 365 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 366 .ch_cfg = modem_qcom_v1_mhi_channels, 367 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 368 .event_cfg = modem_qcom_v1_mhi_events, 369 }; 370 371 static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { 372 .name = "qcom-sa8775p", 373 .edl_trigger = false, 374 .config = &mhi_qcom_sa8775p_config, 375 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 376 .dma_data_width = 32, 377 .mru_default = 32768, 378 .sideband_wake = false, 379 }; 380 381 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 382 .name = "qcom-sdx75m", 383 .fw = "qcom/sdx75m/xbl.elf", 384 .edl = "qcom/sdx75m/edl.mbn", 385 .edl_trigger = true, 386 .config = &modem_qcom_v2_mhiv_config, 387 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 388 .dma_data_width = 32, 389 .sideband_wake = false, 390 }; 391 392 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 393 .name = "qcom-sdx65m", 394 .fw = "qcom/sdx65m/xbl.elf", 395 .edl = "qcom/sdx65m/edl.mbn", 396 .edl_trigger = true, 397 .config = &modem_qcom_v1_mhiv_config, 398 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 399 .dma_data_width = 32, 400 .sideband_wake = false, 401 }; 402 403 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 404 .name = "qcom-sdx55m", 405 .fw = "qcom/sdx55m/sbl1.mbn", 406 .edl = "qcom/sdx55m/edl.mbn", 407 .edl_trigger = true, 408 .config = &modem_qcom_v1_mhiv_config, 409 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 410 .dma_data_width = 32, 411 .mru_default = 32768, 412 .sideband_wake = false, 413 }; 414 415 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 416 .name = "qcom-sdx24", 417 .edl = "qcom/prog_firehose_sdx24.mbn", 418 .config = &modem_qcom_v1_mhiv_config, 419 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 420 .dma_data_width = 32, 421 .sideband_wake = true, 422 }; 423 424 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 425 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 426 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 427 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 428 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 429 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 430 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 431 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 432 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 433 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 434 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 435 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 436 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 437 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 438 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 439 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 440 }; 441 442 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 443 MHI_EVENT_CONFIG_CTRL(0, 128), 444 MHI_EVENT_CONFIG_DATA(1, 128), 445 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 446 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 447 }; 448 449 static const struct mhi_controller_config modem_quectel_em1xx_config = { 450 .max_channels = 128, 451 .timeout_ms = 20000, 452 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 453 .ch_cfg = mhi_quectel_em1xx_channels, 454 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 455 .event_cfg = mhi_quectel_em1xx_events, 456 }; 457 458 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 459 .name = "quectel-em1xx", 460 .edl = "qcom/prog_firehose_sdx24.mbn", 461 .config = &modem_quectel_em1xx_config, 462 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 463 .dma_data_width = 32, 464 .mru_default = 32768, 465 .sideband_wake = true, 466 }; 467 468 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 469 .name = "quectel-rm5xx", 470 .edl = "qcom/prog_firehose_sdx6x.elf", 471 .config = &modem_quectel_em1xx_config, 472 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 473 .dma_data_width = 32, 474 .mru_default = 32768, 475 .sideband_wake = true, 476 }; 477 478 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 479 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 480 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 481 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 482 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 483 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 484 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 485 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 486 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 487 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 488 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 489 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 490 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 491 }; 492 493 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 494 MHI_EVENT_CONFIG_CTRL(0, 128), 495 MHI_EVENT_CONFIG_DATA(1, 128), 496 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 497 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 498 }; 499 500 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 501 .max_channels = 128, 502 .timeout_ms = 20000, 503 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 504 .ch_cfg = mhi_foxconn_sdx55_channels, 505 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 506 .event_cfg = mhi_foxconn_sdx55_events, 507 }; 508 509 static const struct mhi_controller_config modem_foxconn_sdx72_config = { 510 .max_channels = 128, 511 .timeout_ms = 20000, 512 .ready_timeout_ms = 50000, 513 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 514 .ch_cfg = mhi_foxconn_sdx55_channels, 515 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 516 .event_cfg = mhi_foxconn_sdx55_events, 517 }; 518 519 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 520 .name = "foxconn-sdx55", 521 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 522 .edl_trigger = true, 523 .config = &modem_foxconn_sdx55_config, 524 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 525 .dma_data_width = 32, 526 .mru_default = 32768, 527 .sideband_wake = false, 528 }; 529 530 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 531 .name = "foxconn-t99w175", 532 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 533 .edl_trigger = true, 534 .config = &modem_foxconn_sdx55_config, 535 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 536 .dma_data_width = 32, 537 .mru_default = 32768, 538 .sideband_wake = false, 539 }; 540 541 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 542 .name = "foxconn-dw5930e", 543 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 544 .edl_trigger = true, 545 .config = &modem_foxconn_sdx55_config, 546 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 547 .dma_data_width = 32, 548 .mru_default = 32768, 549 .sideband_wake = false, 550 }; 551 552 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 553 .name = "foxconn-t99w368", 554 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 555 .edl_trigger = true, 556 .config = &modem_foxconn_sdx55_config, 557 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 558 .dma_data_width = 32, 559 .mru_default = 32768, 560 .sideband_wake = false, 561 }; 562 563 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 564 .name = "foxconn-t99w373", 565 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 566 .edl_trigger = true, 567 .config = &modem_foxconn_sdx55_config, 568 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 569 .dma_data_width = 32, 570 .mru_default = 32768, 571 .sideband_wake = false, 572 }; 573 574 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 575 .name = "foxconn-t99w510", 576 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn", 577 .edl_trigger = true, 578 .config = &modem_foxconn_sdx55_config, 579 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 580 .dma_data_width = 32, 581 .mru_default = 32768, 582 .sideband_wake = false, 583 }; 584 585 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 586 .name = "foxconn-dw5932e", 587 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 588 .edl_trigger = true, 589 .config = &modem_foxconn_sdx55_config, 590 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 591 .dma_data_width = 32, 592 .mru_default = 32768, 593 .sideband_wake = false, 594 }; 595 596 static const struct mhi_pci_dev_info mhi_foxconn_t99w515_info = { 597 .name = "foxconn-t99w515", 598 .edl = "qcom/sdx72m/foxconn/edl.mbn", 599 .edl_trigger = true, 600 .config = &modem_foxconn_sdx72_config, 601 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 602 .dma_data_width = 32, 603 .mru_default = 32768, 604 .sideband_wake = false, 605 }; 606 607 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 608 .name = "foxconn-dw5934e", 609 .edl = "qcom/sdx72m/foxconn/edl.mbn", 610 .edl_trigger = true, 611 .config = &modem_foxconn_sdx72_config, 612 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 613 .dma_data_width = 32, 614 .mru_default = 32768, 615 .sideband_wake = false, 616 }; 617 618 static const struct mhi_channel_config mhi_mv3x_channels[] = { 619 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 620 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 621 /* MBIM Control Channel */ 622 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 623 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 624 /* MBIM Data Channel */ 625 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 626 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 627 }; 628 629 static struct mhi_event_config mhi_mv3x_events[] = { 630 MHI_EVENT_CONFIG_CTRL(0, 256), 631 MHI_EVENT_CONFIG_DATA(1, 256), 632 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 633 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 634 }; 635 636 static const struct mhi_controller_config modem_mv3x_config = { 637 .max_channels = 128, 638 .timeout_ms = 20000, 639 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 640 .ch_cfg = mhi_mv3x_channels, 641 .num_events = ARRAY_SIZE(mhi_mv3x_events), 642 .event_cfg = mhi_mv3x_events, 643 }; 644 645 static const struct mhi_pci_dev_info mhi_mv31_info = { 646 .name = "cinterion-mv31", 647 .config = &modem_mv3x_config, 648 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 649 .dma_data_width = 32, 650 .mru_default = 32768, 651 }; 652 653 static const struct mhi_pci_dev_info mhi_mv32_info = { 654 .name = "cinterion-mv32", 655 .config = &modem_mv3x_config, 656 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 657 .dma_data_width = 32, 658 .mru_default = 32768, 659 }; 660 661 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 662 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 663 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 664 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 665 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 666 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 667 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 668 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 669 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 670 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 671 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 672 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 673 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 674 }; 675 676 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 677 /* first ring is control+data and DIAG ring */ 678 MHI_EVENT_CONFIG_CTRL(0, 2048), 679 /* Hardware channels request dedicated hardware event rings */ 680 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 681 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 682 }; 683 684 static const struct mhi_controller_config modem_sierra_em919x_config = { 685 .max_channels = 128, 686 .timeout_ms = 24000, 687 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 688 .ch_cfg = mhi_sierra_em919x_channels, 689 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 690 .event_cfg = modem_sierra_em919x_mhi_events, 691 }; 692 693 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 694 .name = "sierra-em919x", 695 .config = &modem_sierra_em919x_config, 696 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 697 .dma_data_width = 32, 698 .sideband_wake = false, 699 }; 700 701 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 702 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 703 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 704 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 705 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0), 706 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 707 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 708 }; 709 710 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 711 MHI_EVENT_CONFIG_CTRL(0, 128), 712 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 713 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 714 }; 715 716 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 717 .max_channels = 128, 718 .timeout_ms = 20000, 719 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 720 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 721 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 722 .event_cfg = mhi_telit_fn980_hw_v1_events, 723 }; 724 725 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 726 .name = "telit-fn980-hwv1", 727 .fw = "qcom/sdx55m/sbl1.mbn", 728 .edl = "qcom/sdx55m/edl.mbn", 729 .config = &modem_telit_fn980_hw_v1_config, 730 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 731 .dma_data_width = 32, 732 .mru_default = 32768, 733 .sideband_wake = false, 734 }; 735 736 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 737 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 738 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 739 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 740 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 741 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 742 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 743 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 744 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 745 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 746 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 747 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 748 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 749 }; 750 751 static struct mhi_event_config mhi_telit_fn990_events[] = { 752 MHI_EVENT_CONFIG_CTRL(0, 128), 753 MHI_EVENT_CONFIG_DATA(1, 128), 754 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 755 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 756 }; 757 758 static const struct mhi_controller_config modem_telit_fn990_config = { 759 .max_channels = 128, 760 .timeout_ms = 20000, 761 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 762 .ch_cfg = mhi_telit_fn990_channels, 763 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 764 .event_cfg = mhi_telit_fn990_events, 765 }; 766 767 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 768 .name = "telit-fn990", 769 .config = &modem_telit_fn990_config, 770 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 771 .dma_data_width = 32, 772 .sideband_wake = false, 773 .mru_default = 32768, 774 }; 775 776 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = { 777 .name = "telit-fe990a", 778 .config = &modem_telit_fn990_config, 779 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 780 .dma_data_width = 32, 781 .sideband_wake = false, 782 .mru_default = 32768, 783 }; 784 785 static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { 786 .name = "netprisma-lcur57", 787 .edl = "qcom/prog_firehose_sdx24.mbn", 788 .config = &modem_quectel_em1xx_config, 789 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 790 .dma_data_width = 32, 791 .mru_default = 32768, 792 .sideband_wake = true, 793 }; 794 795 static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { 796 .name = "netprisma-fcun69", 797 .edl = "qcom/prog_firehose_sdx6x.elf", 798 .config = &modem_quectel_em1xx_config, 799 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 800 .dma_data_width = 32, 801 .mru_default = 32768, 802 .sideband_wake = true, 803 }; 804 805 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 806 static const struct pci_device_id mhi_pci_id_table[] = { 807 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), 808 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, 809 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 810 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 811 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 812 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 813 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 814 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 815 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 816 /* Telit FN980 hardware revision v1 */ 817 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 818 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 819 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 820 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 821 /* Telit FN990 */ 822 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 823 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 824 /* Telit FE990A */ 825 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 826 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info }, 827 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 828 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 829 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 830 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 831 /* QDU100, x100-DU */ 832 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), 833 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, 834 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 835 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 836 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 837 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 838 /* RM520N-GL (sdx6x), eSIM */ 839 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 840 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 841 /* RM520N-GL (sdx6x), Lenovo variant */ 842 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 843 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 844 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 845 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 846 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 847 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 848 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 849 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 850 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 851 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 852 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 853 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 854 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 855 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 856 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 857 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 858 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 859 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 860 /* T99W175 (sdx55) */ 861 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 862 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 863 /* T99W368 (sdx65) */ 864 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 865 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 866 /* T99W373 (sdx62) */ 867 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 868 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 869 /* T99W510 (sdx24), variant 1 */ 870 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 871 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 872 /* T99W510 (sdx24), variant 2 */ 873 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 874 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 875 /* T99W510 (sdx24), variant 3 */ 876 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 877 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 878 /* DW5932e-eSIM (sdx62), With eSIM */ 879 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 880 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 881 /* DW5932e (sdx62), Non-eSIM */ 882 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 883 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 884 /* T99W515 (sdx72) */ 885 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 886 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w515_info }, 887 /* DW5934e(sdx72), With eSIM */ 888 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 889 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 890 /* DW5934e(sdx72), Non-eSIM */ 891 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 892 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 893 /* MV31-W (Cinterion) */ 894 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 895 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 896 /* MV31-W (Cinterion), based on new baseline */ 897 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 898 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 899 /* MV32-WA (Cinterion) */ 900 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 901 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 902 /* MV32-WB (Cinterion) */ 903 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 904 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 905 /* T99W175 (sdx55), HP variant */ 906 { PCI_DEVICE(0x03f0, 0x0a6c), 907 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 908 /* NETPRISMA LCUR57 (SDX24) */ 909 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000), 910 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info }, 911 /* NETPRISMA FCUN69 (SDX6X) */ 912 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), 913 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, 914 { } 915 }; 916 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 917 918 enum mhi_pci_device_status { 919 MHI_PCI_DEV_STARTED, 920 MHI_PCI_DEV_SUSPENDED, 921 }; 922 923 struct mhi_pci_device { 924 struct mhi_controller mhi_cntrl; 925 struct pci_saved_state *pci_state; 926 struct work_struct recovery_work; 927 struct timer_list health_check_timer; 928 unsigned long status; 929 }; 930 931 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 932 void __iomem *addr, u32 *out) 933 { 934 *out = readl(addr); 935 return 0; 936 } 937 938 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 939 void __iomem *addr, u32 val) 940 { 941 writel(val, addr); 942 } 943 944 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 945 enum mhi_callback cb) 946 { 947 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 948 949 /* Nothing to do for now */ 950 switch (cb) { 951 case MHI_CB_FATAL_ERROR: 952 case MHI_CB_SYS_ERROR: 953 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 954 pm_runtime_forbid(&pdev->dev); 955 break; 956 case MHI_CB_EE_MISSION_MODE: 957 pm_runtime_allow(&pdev->dev); 958 break; 959 default: 960 break; 961 } 962 } 963 964 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 965 { 966 /* no-op */ 967 } 968 969 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 970 { 971 /* no-op */ 972 } 973 974 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 975 { 976 /* no-op */ 977 } 978 979 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 980 { 981 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 982 u16 vendor = 0; 983 984 if (pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor)) 985 return false; 986 987 if (vendor == (u16) ~0 || vendor == 0) 988 return false; 989 990 return true; 991 } 992 993 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 994 unsigned int bar_num, u64 dma_mask) 995 { 996 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 997 int err; 998 999 err = pci_assign_resource(pdev, bar_num); 1000 if (err) 1001 return err; 1002 1003 err = pcim_enable_device(pdev); 1004 if (err) { 1005 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 1006 return err; 1007 } 1008 1009 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev)); 1010 if (IS_ERR(mhi_cntrl->regs)) { 1011 err = PTR_ERR(mhi_cntrl->regs); 1012 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 1013 return err; 1014 } 1015 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 1016 1017 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 1018 if (err) { 1019 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 1020 return err; 1021 } 1022 1023 pci_set_master(pdev); 1024 1025 return 0; 1026 } 1027 1028 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 1029 const struct mhi_controller_config *mhi_cntrl_config) 1030 { 1031 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1032 int nr_vectors, i; 1033 int *irq; 1034 1035 /* 1036 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 1037 * No explicit pci_free_irq_vectors required, done by pcim_release. 1038 */ 1039 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 1040 1041 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); 1042 if (nr_vectors < 0) { 1043 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 1044 nr_vectors); 1045 return nr_vectors; 1046 } 1047 1048 if (nr_vectors < mhi_cntrl->nr_irqs) { 1049 dev_warn(&pdev->dev, "using shared MSI\n"); 1050 1051 /* Patch msi vectors, use only one (shared) */ 1052 for (i = 0; i < mhi_cntrl_config->num_events; i++) 1053 mhi_cntrl_config->event_cfg[i].irq = 0; 1054 mhi_cntrl->nr_irqs = 1; 1055 } 1056 1057 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 1058 if (!irq) 1059 return -ENOMEM; 1060 1061 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 1062 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 1063 1064 irq[i] = pci_irq_vector(pdev, vector); 1065 } 1066 1067 mhi_cntrl->irq = irq; 1068 1069 return 0; 1070 } 1071 1072 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 1073 { 1074 /* The runtime_get() MHI callback means: 1075 * Do whatever is requested to leave M3. 1076 */ 1077 return pm_runtime_get(mhi_cntrl->cntrl_dev); 1078 } 1079 1080 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 1081 { 1082 /* The runtime_put() MHI callback means: 1083 * Device can be moved in M3 state. 1084 */ 1085 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 1086 pm_runtime_put(mhi_cntrl->cntrl_dev); 1087 } 1088 1089 static void mhi_pci_recovery_work(struct work_struct *work) 1090 { 1091 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 1092 recovery_work); 1093 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1094 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1095 int err; 1096 1097 dev_warn(&pdev->dev, "device recovery started\n"); 1098 1099 timer_delete(&mhi_pdev->health_check_timer); 1100 pm_runtime_forbid(&pdev->dev); 1101 1102 /* Clean up MHI state */ 1103 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1104 mhi_power_down(mhi_cntrl, false); 1105 mhi_unprepare_after_power_down(mhi_cntrl); 1106 } 1107 1108 pci_set_power_state(pdev, PCI_D0); 1109 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1110 pci_restore_state(pdev); 1111 1112 if (!mhi_pci_is_alive(mhi_cntrl)) 1113 goto err_try_reset; 1114 1115 err = mhi_prepare_for_power_up(mhi_cntrl); 1116 if (err) 1117 goto err_try_reset; 1118 1119 err = mhi_sync_power_up(mhi_cntrl); 1120 if (err) 1121 goto err_unprepare; 1122 1123 dev_dbg(&pdev->dev, "Recovery completed\n"); 1124 1125 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1126 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1127 return; 1128 1129 err_unprepare: 1130 mhi_unprepare_after_power_down(mhi_cntrl); 1131 err_try_reset: 1132 err = pci_try_reset_function(pdev); 1133 if (err) 1134 dev_err(&pdev->dev, "Recovery failed: %d\n", err); 1135 } 1136 1137 static void health_check(struct timer_list *t) 1138 { 1139 struct mhi_pci_device *mhi_pdev = from_timer(mhi_pdev, t, health_check_timer); 1140 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1141 1142 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1143 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1144 return; 1145 1146 if (!mhi_pci_is_alive(mhi_cntrl)) { 1147 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1148 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1149 return; 1150 } 1151 1152 /* reschedule in two seconds */ 1153 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1154 } 1155 1156 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1157 { 1158 void __iomem *base = mhi_cntrl->regs; 1159 void __iomem *edl_db; 1160 int ret; 1161 u32 val; 1162 1163 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1164 if (ret) { 1165 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1166 return ret; 1167 } 1168 1169 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1170 mhi_cntrl->runtime_get(mhi_cntrl); 1171 1172 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1173 if (ret) 1174 goto err_get_chdb; 1175 1176 edl_db = base + val + (8 * MHI_EDL_DB); 1177 1178 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1179 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1180 1181 mhi_soc_reset(mhi_cntrl); 1182 1183 err_get_chdb: 1184 mhi_cntrl->runtime_put(mhi_cntrl); 1185 mhi_device_put(mhi_cntrl->mhi_dev); 1186 1187 return ret; 1188 } 1189 1190 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1191 { 1192 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1193 const struct mhi_controller_config *mhi_cntrl_config; 1194 struct mhi_pci_device *mhi_pdev; 1195 struct mhi_controller *mhi_cntrl; 1196 int err; 1197 1198 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1199 1200 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1201 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1202 if (!mhi_pdev) 1203 return -ENOMEM; 1204 1205 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1206 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1207 1208 mhi_cntrl_config = info->config; 1209 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1210 1211 mhi_cntrl->cntrl_dev = &pdev->dev; 1212 mhi_cntrl->iova_start = 0; 1213 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); 1214 mhi_cntrl->fw_image = info->fw; 1215 mhi_cntrl->edl_image = info->edl; 1216 1217 mhi_cntrl->read_reg = mhi_pci_read_reg; 1218 mhi_cntrl->write_reg = mhi_pci_write_reg; 1219 mhi_cntrl->status_cb = mhi_pci_status_cb; 1220 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1221 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1222 mhi_cntrl->mru = info->mru_default; 1223 mhi_cntrl->name = info->name; 1224 1225 if (info->edl_trigger) 1226 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1227 1228 if (info->sideband_wake) { 1229 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1230 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1231 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1232 } 1233 1234 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width)); 1235 if (err) 1236 return err; 1237 1238 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1239 if (err) 1240 return err; 1241 1242 pci_set_drvdata(pdev, mhi_pdev); 1243 1244 /* Have stored pci confspace at hand for restore in sudden PCI error. 1245 * cache the state locally and discard the PCI core one. 1246 */ 1247 pci_save_state(pdev); 1248 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1249 pci_load_saved_state(pdev, NULL); 1250 1251 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1252 if (err) 1253 return err; 1254 1255 /* MHI bus does not power up the controller by default */ 1256 err = mhi_prepare_for_power_up(mhi_cntrl); 1257 if (err) { 1258 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1259 goto err_unregister; 1260 } 1261 1262 err = mhi_sync_power_up(mhi_cntrl); 1263 if (err) { 1264 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1265 goto err_unprepare; 1266 } 1267 1268 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1269 1270 /* start health check */ 1271 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1272 1273 /* Only allow runtime-suspend if PME capable (for wakeup) */ 1274 if (pci_pme_capable(pdev, PCI_D3hot)) { 1275 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1276 pm_runtime_use_autosuspend(&pdev->dev); 1277 pm_runtime_mark_last_busy(&pdev->dev); 1278 pm_runtime_put_noidle(&pdev->dev); 1279 } 1280 1281 return 0; 1282 1283 err_unprepare: 1284 mhi_unprepare_after_power_down(mhi_cntrl); 1285 err_unregister: 1286 mhi_unregister_controller(mhi_cntrl); 1287 1288 return err; 1289 } 1290 1291 static void mhi_pci_remove(struct pci_dev *pdev) 1292 { 1293 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1294 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1295 1296 timer_delete_sync(&mhi_pdev->health_check_timer); 1297 cancel_work_sync(&mhi_pdev->recovery_work); 1298 1299 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1300 mhi_power_down(mhi_cntrl, true); 1301 mhi_unprepare_after_power_down(mhi_cntrl); 1302 } 1303 1304 /* balancing probe put_noidle */ 1305 if (pci_pme_capable(pdev, PCI_D3hot)) 1306 pm_runtime_get_noresume(&pdev->dev); 1307 1308 mhi_unregister_controller(mhi_cntrl); 1309 } 1310 1311 static void mhi_pci_shutdown(struct pci_dev *pdev) 1312 { 1313 mhi_pci_remove(pdev); 1314 pci_set_power_state(pdev, PCI_D3hot); 1315 } 1316 1317 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1318 { 1319 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1320 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1321 1322 dev_info(&pdev->dev, "reset\n"); 1323 1324 timer_delete(&mhi_pdev->health_check_timer); 1325 1326 /* Clean up MHI state */ 1327 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1328 mhi_power_down(mhi_cntrl, false); 1329 mhi_unprepare_after_power_down(mhi_cntrl); 1330 } 1331 1332 /* cause internal device reset */ 1333 mhi_soc_reset(mhi_cntrl); 1334 1335 /* Be sure device reset has been executed */ 1336 msleep(MHI_POST_RESET_DELAY_MS); 1337 } 1338 1339 static void mhi_pci_reset_done(struct pci_dev *pdev) 1340 { 1341 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1342 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1343 int err; 1344 1345 /* Restore initial known working PCI state */ 1346 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1347 pci_restore_state(pdev); 1348 1349 /* Is device status available ? */ 1350 if (!mhi_pci_is_alive(mhi_cntrl)) { 1351 dev_err(&pdev->dev, "reset failed\n"); 1352 return; 1353 } 1354 1355 err = mhi_prepare_for_power_up(mhi_cntrl); 1356 if (err) { 1357 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1358 return; 1359 } 1360 1361 err = mhi_sync_power_up(mhi_cntrl); 1362 if (err) { 1363 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1364 mhi_unprepare_after_power_down(mhi_cntrl); 1365 return; 1366 } 1367 1368 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1369 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1370 } 1371 1372 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1373 pci_channel_state_t state) 1374 { 1375 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1376 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1377 1378 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1379 1380 if (state == pci_channel_io_perm_failure) 1381 return PCI_ERS_RESULT_DISCONNECT; 1382 1383 /* Clean up MHI state */ 1384 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1385 mhi_power_down(mhi_cntrl, false); 1386 mhi_unprepare_after_power_down(mhi_cntrl); 1387 } else { 1388 /* Nothing to do */ 1389 return PCI_ERS_RESULT_RECOVERED; 1390 } 1391 1392 pci_disable_device(pdev); 1393 1394 return PCI_ERS_RESULT_NEED_RESET; 1395 } 1396 1397 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1398 { 1399 if (pci_enable_device(pdev)) { 1400 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1401 return PCI_ERS_RESULT_DISCONNECT; 1402 } 1403 1404 return PCI_ERS_RESULT_RECOVERED; 1405 } 1406 1407 static void mhi_pci_io_resume(struct pci_dev *pdev) 1408 { 1409 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1410 1411 dev_err(&pdev->dev, "PCI slot reset done\n"); 1412 1413 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1414 } 1415 1416 static const struct pci_error_handlers mhi_pci_err_handler = { 1417 .error_detected = mhi_pci_error_detected, 1418 .slot_reset = mhi_pci_slot_reset, 1419 .resume = mhi_pci_io_resume, 1420 .reset_prepare = mhi_pci_reset_prepare, 1421 .reset_done = mhi_pci_reset_done, 1422 }; 1423 1424 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1425 { 1426 struct pci_dev *pdev = to_pci_dev(dev); 1427 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1428 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1429 int err; 1430 1431 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1432 return 0; 1433 1434 timer_delete(&mhi_pdev->health_check_timer); 1435 cancel_work_sync(&mhi_pdev->recovery_work); 1436 1437 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1438 mhi_cntrl->ee != MHI_EE_AMSS) 1439 goto pci_suspend; /* Nothing to do at MHI level */ 1440 1441 /* Transition to M3 state */ 1442 err = mhi_pm_suspend(mhi_cntrl); 1443 if (err) { 1444 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1445 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1446 return -EBUSY; 1447 } 1448 1449 pci_suspend: 1450 pci_disable_device(pdev); 1451 pci_wake_from_d3(pdev, true); 1452 1453 return 0; 1454 } 1455 1456 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1457 { 1458 struct pci_dev *pdev = to_pci_dev(dev); 1459 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1460 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1461 int err; 1462 1463 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1464 return 0; 1465 1466 err = pci_enable_device(pdev); 1467 if (err) 1468 goto err_recovery; 1469 1470 pci_set_master(pdev); 1471 pci_wake_from_d3(pdev, false); 1472 1473 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1474 mhi_cntrl->ee != MHI_EE_AMSS) 1475 return 0; /* Nothing to do at MHI level */ 1476 1477 /* Exit M3, transition to M0 state */ 1478 err = mhi_pm_resume(mhi_cntrl); 1479 if (err) { 1480 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1481 goto err_recovery; 1482 } 1483 1484 /* Resume health check */ 1485 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1486 1487 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1488 pm_runtime_mark_last_busy(dev); 1489 1490 return 0; 1491 1492 err_recovery: 1493 /* Do not fail to not mess up our PCI device state, the device likely 1494 * lost power (d3cold) and we simply need to reset it from the recovery 1495 * procedure, trigger the recovery asynchronously to prevent system 1496 * suspend exit delaying. 1497 */ 1498 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1499 pm_runtime_mark_last_busy(dev); 1500 1501 return 0; 1502 } 1503 1504 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1505 { 1506 pm_runtime_disable(dev); 1507 return mhi_pci_runtime_suspend(dev); 1508 } 1509 1510 static int __maybe_unused mhi_pci_resume(struct device *dev) 1511 { 1512 int ret; 1513 1514 /* Depending the platform, device may have lost power (d3cold), we need 1515 * to resume it now to check its state and recover when necessary. 1516 */ 1517 ret = mhi_pci_runtime_resume(dev); 1518 pm_runtime_enable(dev); 1519 1520 return ret; 1521 } 1522 1523 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1524 { 1525 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1526 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1527 1528 /* We want to stop all operations, hibernation does not guarantee that 1529 * device will be in the same state as before freezing, especially if 1530 * the intermediate restore kernel reinitializes MHI device with new 1531 * context. 1532 */ 1533 flush_work(&mhi_pdev->recovery_work); 1534 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1535 mhi_power_down(mhi_cntrl, true); 1536 mhi_unprepare_after_power_down(mhi_cntrl); 1537 } 1538 1539 return 0; 1540 } 1541 1542 static int __maybe_unused mhi_pci_restore(struct device *dev) 1543 { 1544 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1545 1546 /* Reinitialize the device */ 1547 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1548 1549 return 0; 1550 } 1551 1552 static const struct dev_pm_ops mhi_pci_pm_ops = { 1553 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1554 #ifdef CONFIG_PM_SLEEP 1555 .suspend = mhi_pci_suspend, 1556 .resume = mhi_pci_resume, 1557 .freeze = mhi_pci_freeze, 1558 .thaw = mhi_pci_restore, 1559 .poweroff = mhi_pci_freeze, 1560 .restore = mhi_pci_restore, 1561 #endif 1562 }; 1563 1564 static struct pci_driver mhi_pci_driver = { 1565 .name = "mhi-pci-generic", 1566 .id_table = mhi_pci_id_table, 1567 .probe = mhi_pci_probe, 1568 .remove = mhi_pci_remove, 1569 .shutdown = mhi_pci_shutdown, 1570 .err_handler = &mhi_pci_err_handler, 1571 .driver.pm = &mhi_pci_pm_ops 1572 }; 1573 module_pci_driver(mhi_pci_driver); 1574 1575 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1576 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1577 MODULE_LICENSE("GPL"); 1578