1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timer.h> 18 #include <linux/workqueue.h> 19 20 #define MHI_PCI_DEFAULT_BAR_NUM 0 21 22 #define MHI_POST_RESET_DELAY_MS 2000 23 24 #define HEALTH_CHECK_PERIOD (HZ * 2) 25 26 /* PCI VID definitions */ 27 #define PCI_VENDOR_ID_THALES 0x1269 28 #define PCI_VENDOR_ID_QUECTEL 0x1eac 29 #define PCI_VENDOR_ID_NETPRISMA 0x203e 30 31 #define MHI_EDL_DB 91 32 #define MHI_EDL_COOKIE 0xEDEDEDED 33 34 /** 35 * struct mhi_pci_dev_info - MHI PCI device specific information 36 * @config: MHI controller configuration 37 * @vf_config: MHI controller configuration for Virtual function (optional) 38 * @name: name of the PCI module 39 * @fw: firmware path (if any) 40 * @edl: emergency download mode firmware path (if any) 41 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 42 * @bar_num: PCI base address register to use for MHI MMIO register space 43 * @dma_data_width: DMA transfer word size (32 or 64 bits) 44 * @vf_dma_data_width: DMA transfer word size for VF's (optional) 45 * @mru_default: default MRU size for MBIM network packets 46 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 47 * of inband wake support (such as sdx24) 48 * @no_m3: M3 not supported 49 * @reset_on_remove: Set true for devices that require SoC during driver removal 50 */ 51 struct mhi_pci_dev_info { 52 const struct mhi_controller_config *config; 53 const struct mhi_controller_config *vf_config; 54 const char *name; 55 const char *fw; 56 const char *edl; 57 bool edl_trigger; 58 unsigned int bar_num; 59 unsigned int dma_data_width; 60 unsigned int vf_dma_data_width; 61 unsigned int mru_default; 62 bool sideband_wake; 63 bool no_m3; 64 bool reset_on_remove; 65 }; 66 67 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 68 { \ 69 .num = ch_num, \ 70 .name = ch_name, \ 71 .num_elements = el_count, \ 72 .event_ring = ev_ring, \ 73 .dir = DMA_TO_DEVICE, \ 74 .ee_mask = BIT(MHI_EE_AMSS), \ 75 .pollcfg = 0, \ 76 .doorbell = MHI_DB_BRST_DISABLE, \ 77 .lpm_notify = false, \ 78 .offload_channel = false, \ 79 .doorbell_mode_switch = false, \ 80 } \ 81 82 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 83 { \ 84 .num = ch_num, \ 85 .name = ch_name, \ 86 .num_elements = el_count, \ 87 .event_ring = ev_ring, \ 88 .dir = DMA_FROM_DEVICE, \ 89 .ee_mask = BIT(MHI_EE_AMSS), \ 90 .pollcfg = 0, \ 91 .doorbell = MHI_DB_BRST_DISABLE, \ 92 .lpm_notify = false, \ 93 .offload_channel = false, \ 94 .doorbell_mode_switch = false, \ 95 } 96 97 #define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \ 98 { \ 99 .num = ch_num, \ 100 .name = ch_name, \ 101 .num_elements = el_count, \ 102 .event_ring = ev_ring, \ 103 .dir = DMA_FROM_DEVICE, \ 104 .ee_mask = BIT(MHI_EE_AMSS), \ 105 .pollcfg = 0, \ 106 .doorbell = MHI_DB_BRST_DISABLE, \ 107 .lpm_notify = false, \ 108 .offload_channel = false, \ 109 .doorbell_mode_switch = false, \ 110 .auto_queue = true, \ 111 } 112 113 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 114 { \ 115 .num_elements = el_count, \ 116 .irq_moderation_ms = 0, \ 117 .irq = (ev_ring) + 1, \ 118 .priority = 1, \ 119 .mode = MHI_DB_BRST_DISABLE, \ 120 .data_type = MHI_ER_CTRL, \ 121 .hardware_event = false, \ 122 .client_managed = false, \ 123 .offload_channel = false, \ 124 } 125 126 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 127 { \ 128 .num = ch_num, \ 129 .name = ch_name, \ 130 .num_elements = el_count, \ 131 .event_ring = ev_ring, \ 132 .dir = DMA_TO_DEVICE, \ 133 .ee_mask = BIT(MHI_EE_AMSS), \ 134 .pollcfg = 0, \ 135 .doorbell = MHI_DB_BRST_ENABLE, \ 136 .lpm_notify = false, \ 137 .offload_channel = false, \ 138 .doorbell_mode_switch = true, \ 139 } \ 140 141 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 142 { \ 143 .num = ch_num, \ 144 .name = ch_name, \ 145 .num_elements = el_count, \ 146 .event_ring = ev_ring, \ 147 .dir = DMA_FROM_DEVICE, \ 148 .ee_mask = BIT(MHI_EE_AMSS), \ 149 .pollcfg = 0, \ 150 .doorbell = MHI_DB_BRST_ENABLE, \ 151 .lpm_notify = false, \ 152 .offload_channel = false, \ 153 .doorbell_mode_switch = true, \ 154 } 155 156 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 157 { \ 158 .num = ch_num, \ 159 .name = ch_name, \ 160 .num_elements = el_count, \ 161 .event_ring = ev_ring, \ 162 .dir = DMA_TO_DEVICE, \ 163 .ee_mask = BIT(MHI_EE_SBL), \ 164 .pollcfg = 0, \ 165 .doorbell = MHI_DB_BRST_DISABLE, \ 166 .lpm_notify = false, \ 167 .offload_channel = false, \ 168 .doorbell_mode_switch = false, \ 169 } \ 170 171 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 172 { \ 173 .num = ch_num, \ 174 .name = ch_name, \ 175 .num_elements = el_count, \ 176 .event_ring = ev_ring, \ 177 .dir = DMA_FROM_DEVICE, \ 178 .ee_mask = BIT(MHI_EE_SBL), \ 179 .pollcfg = 0, \ 180 .doorbell = MHI_DB_BRST_DISABLE, \ 181 .lpm_notify = false, \ 182 .offload_channel = false, \ 183 .doorbell_mode_switch = false, \ 184 } 185 186 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 187 { \ 188 .num = ch_num, \ 189 .name = ch_name, \ 190 .num_elements = el_count, \ 191 .event_ring = ev_ring, \ 192 .dir = DMA_TO_DEVICE, \ 193 .ee_mask = BIT(MHI_EE_FP), \ 194 .pollcfg = 0, \ 195 .doorbell = MHI_DB_BRST_DISABLE, \ 196 .lpm_notify = false, \ 197 .offload_channel = false, \ 198 .doorbell_mode_switch = false, \ 199 } \ 200 201 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 202 { \ 203 .num = ch_num, \ 204 .name = ch_name, \ 205 .num_elements = el_count, \ 206 .event_ring = ev_ring, \ 207 .dir = DMA_FROM_DEVICE, \ 208 .ee_mask = BIT(MHI_EE_FP), \ 209 .pollcfg = 0, \ 210 .doorbell = MHI_DB_BRST_DISABLE, \ 211 .lpm_notify = false, \ 212 .offload_channel = false, \ 213 .doorbell_mode_switch = false, \ 214 } 215 216 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 217 { \ 218 .num_elements = el_count, \ 219 .irq_moderation_ms = 5, \ 220 .irq = (ev_ring) + 1, \ 221 .priority = 1, \ 222 .mode = MHI_DB_BRST_DISABLE, \ 223 .data_type = MHI_ER_DATA, \ 224 .hardware_event = false, \ 225 .client_managed = false, \ 226 .offload_channel = false, \ 227 } 228 229 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 230 { \ 231 .num_elements = el_count, \ 232 .irq_moderation_ms = 0, \ 233 .irq = (ev_ring) + 1, \ 234 .priority = 1, \ 235 .mode = MHI_DB_BRST_DISABLE, \ 236 .data_type = MHI_ER_DATA, \ 237 .hardware_event = false, \ 238 .client_managed = false, \ 239 .offload_channel = false, \ 240 } 241 242 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 243 { \ 244 .num_elements = el_count, \ 245 .irq_moderation_ms = 1, \ 246 .irq = (ev_ring) + 1, \ 247 .priority = 1, \ 248 .mode = MHI_DB_BRST_DISABLE, \ 249 .data_type = MHI_ER_DATA, \ 250 .hardware_event = true, \ 251 .client_managed = false, \ 252 .offload_channel = false, \ 253 .channel = ch_num, \ 254 } 255 256 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { 257 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), 258 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), 259 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), 260 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), 261 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), 262 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), 263 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), 264 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), 265 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), 266 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), 267 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), 268 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), 269 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), 270 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), 271 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), 272 }; 273 274 static struct mhi_event_config mhi_qcom_qdu100_events[] = { 275 /* first ring is control+data ring */ 276 MHI_EVENT_CONFIG_CTRL(0, 64), 277 /* SAHARA dedicated event ring */ 278 MHI_EVENT_CONFIG_SW_DATA(1, 256), 279 /* Software channels dedicated event ring */ 280 MHI_EVENT_CONFIG_SW_DATA(2, 64), 281 MHI_EVENT_CONFIG_SW_DATA(3, 256), 282 MHI_EVENT_CONFIG_SW_DATA(4, 256), 283 /* Software IP channels dedicated event ring */ 284 MHI_EVENT_CONFIG_SW_DATA(5, 512), 285 MHI_EVENT_CONFIG_SW_DATA(6, 512), 286 MHI_EVENT_CONFIG_SW_DATA(7, 512), 287 }; 288 289 static const struct mhi_controller_config mhi_qcom_qdu100_config = { 290 .max_channels = 128, 291 .timeout_ms = 120000, 292 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), 293 .ch_cfg = mhi_qcom_qdu100_channels, 294 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), 295 .event_cfg = mhi_qcom_qdu100_events, 296 }; 297 298 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { 299 .name = "qcom-qdu100", 300 .fw = "qcom/qdu100/xbl_s.melf", 301 .edl_trigger = true, 302 .config = &mhi_qcom_qdu100_config, 303 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 304 .dma_data_width = 32, 305 .vf_dma_data_width = 40, 306 .sideband_wake = false, 307 .no_m3 = true, 308 .reset_on_remove = true, 309 }; 310 311 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { 312 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), 313 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), 314 }; 315 316 static struct mhi_event_config mhi_qcom_sa8775p_events[] = { 317 /* first ring is control+data ring */ 318 MHI_EVENT_CONFIG_CTRL(0, 64), 319 /* Software channels dedicated event ring */ 320 MHI_EVENT_CONFIG_SW_DATA(1, 64), 321 MHI_EVENT_CONFIG_SW_DATA(2, 64), 322 }; 323 324 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 325 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 326 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 327 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 328 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 329 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 330 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 331 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 332 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0), 333 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 334 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 335 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 336 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 337 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 338 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 339 }; 340 341 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 342 /* first ring is control+data ring */ 343 MHI_EVENT_CONFIG_CTRL(0, 64), 344 /* DIAG dedicated event ring */ 345 MHI_EVENT_CONFIG_DATA(1, 128), 346 /* Software channels dedicated event ring */ 347 MHI_EVENT_CONFIG_SW_DATA(2, 64), 348 MHI_EVENT_CONFIG_SW_DATA(3, 64), 349 /* Hardware channels request dedicated hardware event rings */ 350 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 351 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 352 }; 353 354 static const struct mhi_controller_config mhi_qcom_sa8775p_config = { 355 .max_channels = 128, 356 .timeout_ms = 8000, 357 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels), 358 .ch_cfg = mhi_qcom_sa8775p_channels, 359 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events), 360 .event_cfg = mhi_qcom_sa8775p_events, 361 }; 362 363 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 364 .max_channels = 128, 365 .timeout_ms = 8000, 366 .ready_timeout_ms = 50000, 367 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 368 .ch_cfg = modem_qcom_v1_mhi_channels, 369 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 370 .event_cfg = modem_qcom_v1_mhi_events, 371 }; 372 373 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 374 .max_channels = 128, 375 .timeout_ms = 8000, 376 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 377 .ch_cfg = modem_qcom_v1_mhi_channels, 378 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 379 .event_cfg = modem_qcom_v1_mhi_events, 380 }; 381 382 static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { 383 .name = "qcom-sa8775p", 384 .edl_trigger = false, 385 .config = &mhi_qcom_sa8775p_config, 386 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 387 .dma_data_width = 32, 388 .mru_default = 32768, 389 .sideband_wake = false, 390 }; 391 392 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 393 .name = "qcom-sdx75m", 394 .fw = "qcom/sdx75m/xbl.elf", 395 .edl = "qcom/sdx75m/edl.mbn", 396 .edl_trigger = true, 397 .config = &modem_qcom_v2_mhiv_config, 398 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 399 .dma_data_width = 32, 400 .sideband_wake = false, 401 }; 402 403 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 404 .name = "qcom-sdx65m", 405 .fw = "qcom/sdx65m/xbl.elf", 406 .edl = "qcom/sdx65m/edl.mbn", 407 .edl_trigger = true, 408 .config = &modem_qcom_v1_mhiv_config, 409 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 410 .dma_data_width = 32, 411 .sideband_wake = false, 412 }; 413 414 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 415 .name = "qcom-sdx55m", 416 .fw = "qcom/sdx55m/sbl1.mbn", 417 .edl = "qcom/sdx55m/edl.mbn", 418 .edl_trigger = true, 419 .config = &modem_qcom_v1_mhiv_config, 420 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 421 .dma_data_width = 32, 422 .mru_default = 32768, 423 .sideband_wake = false, 424 }; 425 426 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 427 .name = "qcom-sdx24", 428 .edl = "qcom/prog_firehose_sdx24.mbn", 429 .config = &modem_qcom_v1_mhiv_config, 430 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 431 .dma_data_width = 32, 432 .sideband_wake = true, 433 }; 434 435 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 436 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 437 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 438 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 439 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 440 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 441 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 442 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 443 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 444 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 445 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 446 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 447 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 448 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 449 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 450 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 451 }; 452 453 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 454 MHI_EVENT_CONFIG_CTRL(0, 128), 455 MHI_EVENT_CONFIG_DATA(1, 128), 456 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 457 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 458 }; 459 460 static const struct mhi_controller_config modem_quectel_em1xx_config = { 461 .max_channels = 128, 462 .timeout_ms = 20000, 463 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 464 .ch_cfg = mhi_quectel_em1xx_channels, 465 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 466 .event_cfg = mhi_quectel_em1xx_events, 467 }; 468 469 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 470 .name = "quectel-em1xx", 471 .edl = "qcom/prog_firehose_sdx24.mbn", 472 .config = &modem_quectel_em1xx_config, 473 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 474 .dma_data_width = 32, 475 .mru_default = 32768, 476 .sideband_wake = true, 477 }; 478 479 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 480 .name = "quectel-rm5xx", 481 .edl = "qcom/prog_firehose_sdx6x.elf", 482 .config = &modem_quectel_em1xx_config, 483 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 484 .dma_data_width = 32, 485 .mru_default = 32768, 486 .sideband_wake = true, 487 }; 488 489 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 490 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 491 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 492 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 493 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 494 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 495 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 496 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 497 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 498 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 499 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 500 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 501 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 502 }; 503 504 static const struct mhi_channel_config mhi_foxconn_sdx61_channels[] = { 505 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 506 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 507 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 508 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 509 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 510 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 511 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 512 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 513 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 514 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 515 MHI_CHANNEL_CONFIG_UL(50, "NMEA", 32, 0), 516 MHI_CHANNEL_CONFIG_DL(51, "NMEA", 32, 0), 517 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 518 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 519 }; 520 521 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 522 MHI_EVENT_CONFIG_CTRL(0, 128), 523 MHI_EVENT_CONFIG_DATA(1, 128), 524 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 525 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 526 }; 527 528 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 529 .max_channels = 128, 530 .timeout_ms = 20000, 531 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 532 .ch_cfg = mhi_foxconn_sdx55_channels, 533 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 534 .event_cfg = mhi_foxconn_sdx55_events, 535 }; 536 537 static const struct mhi_controller_config modem_foxconn_sdx61_config = { 538 .max_channels = 128, 539 .timeout_ms = 20000, 540 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx61_channels), 541 .ch_cfg = mhi_foxconn_sdx61_channels, 542 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 543 .event_cfg = mhi_foxconn_sdx55_events, 544 }; 545 546 static const struct mhi_controller_config modem_foxconn_sdx72_config = { 547 .max_channels = 128, 548 .timeout_ms = 20000, 549 .ready_timeout_ms = 50000, 550 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 551 .ch_cfg = mhi_foxconn_sdx55_channels, 552 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 553 .event_cfg = mhi_foxconn_sdx55_events, 554 }; 555 556 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 557 .name = "foxconn-sdx55", 558 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 559 .edl_trigger = true, 560 .config = &modem_foxconn_sdx55_config, 561 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 562 .dma_data_width = 32, 563 .mru_default = 32768, 564 .sideband_wake = false, 565 }; 566 567 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 568 .name = "foxconn-t99w175", 569 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 570 .edl_trigger = true, 571 .config = &modem_foxconn_sdx55_config, 572 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 573 .dma_data_width = 32, 574 .mru_default = 32768, 575 .sideband_wake = false, 576 }; 577 578 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 579 .name = "foxconn-dw5930e", 580 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 581 .edl_trigger = true, 582 .config = &modem_foxconn_sdx55_config, 583 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 584 .dma_data_width = 32, 585 .mru_default = 32768, 586 .sideband_wake = false, 587 }; 588 589 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 590 .name = "foxconn-t99w368", 591 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 592 .edl_trigger = true, 593 .config = &modem_foxconn_sdx55_config, 594 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 595 .dma_data_width = 32, 596 .mru_default = 32768, 597 .sideband_wake = false, 598 }; 599 600 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 601 .name = "foxconn-t99w373", 602 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 603 .edl_trigger = true, 604 .config = &modem_foxconn_sdx55_config, 605 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 606 .dma_data_width = 32, 607 .mru_default = 32768, 608 .sideband_wake = false, 609 }; 610 611 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 612 .name = "foxconn-t99w510", 613 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn", 614 .edl_trigger = true, 615 .config = &modem_foxconn_sdx55_config, 616 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 617 .dma_data_width = 32, 618 .mru_default = 32768, 619 .sideband_wake = false, 620 }; 621 622 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 623 .name = "foxconn-dw5932e", 624 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 625 .edl_trigger = true, 626 .config = &modem_foxconn_sdx55_config, 627 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 628 .dma_data_width = 32, 629 .mru_default = 32768, 630 .sideband_wake = false, 631 }; 632 633 static const struct mhi_pci_dev_info mhi_foxconn_t99w640_info = { 634 .name = "foxconn-t99w640", 635 .edl = "qcom/sdx72m/foxconn/edl.mbn", 636 .edl_trigger = true, 637 .config = &modem_foxconn_sdx72_config, 638 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 639 .dma_data_width = 32, 640 .mru_default = 32768, 641 .sideband_wake = false, 642 }; 643 644 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 645 .name = "foxconn-dw5934e", 646 .edl = "qcom/sdx72m/foxconn/edl.mbn", 647 .edl_trigger = true, 648 .config = &modem_foxconn_sdx72_config, 649 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 650 .dma_data_width = 32, 651 .mru_default = 32768, 652 .sideband_wake = false, 653 }; 654 655 static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = { 656 .name = "foxconn-t99w696", 657 .edl = "qcom/sdx61/foxconn/prog_firehose_lite.elf", 658 .edl_trigger = true, 659 .config = &modem_foxconn_sdx61_config, 660 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 661 .dma_data_width = 32, 662 .mru_default = 32768, 663 .sideband_wake = false, 664 }; 665 666 static const struct mhi_channel_config mhi_mv3x_channels[] = { 667 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 668 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 669 /* MBIM Control Channel */ 670 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 671 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 672 /* MBIM Data Channel */ 673 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 674 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 675 }; 676 677 static struct mhi_event_config mhi_mv3x_events[] = { 678 MHI_EVENT_CONFIG_CTRL(0, 256), 679 MHI_EVENT_CONFIG_DATA(1, 256), 680 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 681 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 682 }; 683 684 static const struct mhi_controller_config modem_mv3x_config = { 685 .max_channels = 128, 686 .timeout_ms = 20000, 687 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 688 .ch_cfg = mhi_mv3x_channels, 689 .num_events = ARRAY_SIZE(mhi_mv3x_events), 690 .event_cfg = mhi_mv3x_events, 691 }; 692 693 static const struct mhi_pci_dev_info mhi_mv31_info = { 694 .name = "cinterion-mv31", 695 .config = &modem_mv3x_config, 696 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 697 .dma_data_width = 32, 698 .mru_default = 32768, 699 }; 700 701 static const struct mhi_pci_dev_info mhi_mv32_info = { 702 .name = "cinterion-mv32", 703 .config = &modem_mv3x_config, 704 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 705 .dma_data_width = 32, 706 .mru_default = 32768, 707 }; 708 709 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 710 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 711 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 712 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 713 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 714 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 715 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 716 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 717 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 718 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 719 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 720 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 721 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 722 }; 723 724 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 725 /* first ring is control+data and DIAG ring */ 726 MHI_EVENT_CONFIG_CTRL(0, 2048), 727 /* Hardware channels request dedicated hardware event rings */ 728 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 729 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 730 }; 731 732 static const struct mhi_controller_config modem_sierra_em919x_config = { 733 .max_channels = 128, 734 .timeout_ms = 24000, 735 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 736 .ch_cfg = mhi_sierra_em919x_channels, 737 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 738 .event_cfg = modem_sierra_em919x_mhi_events, 739 }; 740 741 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 742 .name = "sierra-em919x", 743 .config = &modem_sierra_em919x_config, 744 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 745 .dma_data_width = 32, 746 .mru_default = 32768, 747 .sideband_wake = false, 748 }; 749 750 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 751 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 752 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 753 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 754 MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 16, 0), 755 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 756 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 757 }; 758 759 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 760 MHI_EVENT_CONFIG_CTRL(0, 128), 761 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 762 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 763 }; 764 765 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 766 .max_channels = 128, 767 .timeout_ms = 20000, 768 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 769 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 770 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 771 .event_cfg = mhi_telit_fn980_hw_v1_events, 772 }; 773 774 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 775 .name = "telit-fn980-hwv1", 776 .fw = "qcom/sdx55m/sbl1.mbn", 777 .edl = "qcom/sdx55m/edl.mbn", 778 .config = &modem_telit_fn980_hw_v1_config, 779 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 780 .dma_data_width = 32, 781 .mru_default = 32768, 782 .sideband_wake = false, 783 }; 784 785 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 786 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 787 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 788 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 789 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 790 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 791 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 792 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 793 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 794 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 795 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 796 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 797 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 798 }; 799 800 static struct mhi_event_config mhi_telit_fn990_events[] = { 801 MHI_EVENT_CONFIG_CTRL(0, 128), 802 MHI_EVENT_CONFIG_DATA(1, 128), 803 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 804 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 805 }; 806 807 static const struct mhi_controller_config modem_telit_fn990_config = { 808 .max_channels = 128, 809 .timeout_ms = 20000, 810 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 811 .ch_cfg = mhi_telit_fn990_channels, 812 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 813 .event_cfg = mhi_telit_fn990_events, 814 }; 815 816 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 817 .name = "telit-fn990", 818 .config = &modem_telit_fn990_config, 819 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 820 .dma_data_width = 32, 821 .sideband_wake = false, 822 .mru_default = 32768, 823 }; 824 825 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = { 826 .name = "telit-fe990a", 827 .config = &modem_telit_fn990_config, 828 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 829 .dma_data_width = 32, 830 .sideband_wake = false, 831 .mru_default = 32768, 832 }; 833 834 static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = { 835 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 836 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 837 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 838 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 839 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 840 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 841 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 842 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 843 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 844 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 845 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 846 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 847 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 848 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 849 }; 850 851 static const struct mhi_controller_config modem_telit_fn920c04_config = { 852 .max_channels = 128, 853 .timeout_ms = 50000, 854 .num_channels = ARRAY_SIZE(mhi_telit_fn920c04_channels), 855 .ch_cfg = mhi_telit_fn920c04_channels, 856 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 857 .event_cfg = mhi_telit_fn990_events, 858 }; 859 860 static const struct mhi_pci_dev_info mhi_telit_fn920c04_info = { 861 .name = "telit-fn920c04", 862 .config = &modem_telit_fn920c04_config, 863 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 864 .dma_data_width = 32, 865 .sideband_wake = false, 866 .mru_default = 32768, 867 .edl_trigger = true, 868 }; 869 870 static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = { 871 .name = "telit-fn990b40", 872 .config = &modem_telit_fn920c04_config, 873 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 874 .dma_data_width = 32, 875 .sideband_wake = false, 876 .mru_default = 32768, 877 .edl_trigger = true, 878 }; 879 880 static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { 881 .name = "netprisma-lcur57", 882 .edl = "qcom/prog_firehose_sdx24.mbn", 883 .config = &modem_quectel_em1xx_config, 884 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 885 .dma_data_width = 32, 886 .mru_default = 32768, 887 .sideband_wake = true, 888 }; 889 890 static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { 891 .name = "netprisma-fcun69", 892 .edl = "qcom/prog_firehose_sdx6x.elf", 893 .config = &modem_quectel_em1xx_config, 894 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 895 .dma_data_width = 32, 896 .mru_default = 32768, 897 .sideband_wake = true, 898 }; 899 900 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 901 static const struct pci_device_id mhi_pci_id_table[] = { 902 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), 903 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, 904 /* Telit FN920C04 (sdx35) */ 905 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020), 906 .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info }, 907 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 908 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 909 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 910 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 911 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 912 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 913 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 914 /* EM929x (sdx65), use the same configuration as EM919x */ 915 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x18d7, 0x0301), 916 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 917 /* Telit FN980 hardware revision v1 */ 918 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 919 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 920 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 921 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 922 /* Telit FN990 */ 923 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 924 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 925 /* Telit FE990A */ 926 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 927 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info }, 928 /* Foxconn T99W696, all variants */ 929 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, PCI_ANY_ID), 930 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info }, 931 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 932 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 933 /* Telit FN990B40 (sdx72) */ 934 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a), 935 .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info }, 936 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 937 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 938 /* QDU100, x100-DU */ 939 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), 940 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, 941 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 942 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 943 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 944 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 945 /* RM520N-GL (sdx6x), eSIM */ 946 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 947 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 948 /* RM520N-GL (sdx6x), Lenovo variant */ 949 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 950 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 951 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 952 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 953 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 954 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 955 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 956 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 957 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 958 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 959 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 960 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 961 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 962 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 963 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 964 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 965 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 966 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 967 /* T99W175 (sdx55) */ 968 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 969 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 970 /* T99W368 (sdx65) */ 971 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 972 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 973 /* T99W373 (sdx62) */ 974 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 975 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 976 /* T99W510 (sdx24), variant 1 */ 977 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 978 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 979 /* T99W510 (sdx24), variant 2 */ 980 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 981 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 982 /* T99W510 (sdx24), variant 3 */ 983 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 984 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 985 /* DW5932e-eSIM (sdx62), With eSIM */ 986 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 987 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 988 /* DW5932e (sdx62), Non-eSIM */ 989 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 990 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 991 /* T99W640 (sdx72) */ 992 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 993 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w640_info }, 994 /* DW5934e(sdx72), With eSIM */ 995 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 996 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 997 /* DW5934e(sdx72), Non-eSIM */ 998 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 999 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1000 /* MV31-W (Cinterion) */ 1001 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 1002 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1003 /* MV31-W (Cinterion), based on new baseline */ 1004 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 1005 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1006 /* MV32-WA (Cinterion) */ 1007 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 1008 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1009 /* MV32-WB (Cinterion) */ 1010 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 1011 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1012 /* T99W175 (sdx55), HP variant */ 1013 { PCI_DEVICE(0x03f0, 0x0a6c), 1014 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1015 /* NETPRISMA LCUR57 (SDX24) */ 1016 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000), 1017 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info }, 1018 /* NETPRISMA FCUN69 (SDX6X) */ 1019 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), 1020 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, 1021 { } 1022 }; 1023 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 1024 1025 enum mhi_pci_device_status { 1026 MHI_PCI_DEV_STARTED, 1027 MHI_PCI_DEV_SUSPENDED, 1028 }; 1029 1030 struct mhi_pci_device { 1031 struct mhi_controller mhi_cntrl; 1032 struct pci_saved_state *pci_state; 1033 struct work_struct recovery_work; 1034 struct timer_list health_check_timer; 1035 unsigned long status; 1036 bool reset_on_remove; 1037 }; 1038 1039 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 1040 void __iomem *addr, u32 *out) 1041 { 1042 *out = readl(addr); 1043 return 0; 1044 } 1045 1046 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 1047 void __iomem *addr, u32 val) 1048 { 1049 writel(val, addr); 1050 } 1051 1052 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 1053 enum mhi_callback cb) 1054 { 1055 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1056 1057 /* Nothing to do for now */ 1058 switch (cb) { 1059 case MHI_CB_FATAL_ERROR: 1060 case MHI_CB_SYS_ERROR: 1061 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 1062 pm_runtime_forbid(&pdev->dev); 1063 break; 1064 case MHI_CB_EE_MISSION_MODE: 1065 pm_runtime_allow(&pdev->dev); 1066 break; 1067 default: 1068 break; 1069 } 1070 } 1071 1072 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 1073 { 1074 /* no-op */ 1075 } 1076 1077 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 1078 { 1079 /* no-op */ 1080 } 1081 1082 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 1083 { 1084 /* no-op */ 1085 } 1086 1087 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 1088 { 1089 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1090 u16 vendor = 0; 1091 1092 if (pci_read_config_word(pci_physfn(pdev), PCI_VENDOR_ID, &vendor)) 1093 return false; 1094 1095 if (vendor == (u16) ~0 || vendor == 0) 1096 return false; 1097 1098 return true; 1099 } 1100 1101 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 1102 unsigned int bar_num, u64 dma_mask) 1103 { 1104 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1105 int err; 1106 1107 err = pcim_enable_device(pdev); 1108 if (err) { 1109 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 1110 return err; 1111 } 1112 1113 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev)); 1114 if (IS_ERR(mhi_cntrl->regs)) { 1115 err = PTR_ERR(mhi_cntrl->regs); 1116 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 1117 return err; 1118 } 1119 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 1120 1121 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 1122 if (err) { 1123 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 1124 return err; 1125 } 1126 1127 pci_set_master(pdev); 1128 1129 return 0; 1130 } 1131 1132 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 1133 const struct mhi_controller_config *mhi_cntrl_config) 1134 { 1135 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1136 int nr_vectors, i; 1137 int *irq; 1138 1139 /* 1140 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 1141 * No explicit pci_free_irq_vectors required, done by pcim_release. 1142 */ 1143 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 1144 1145 nr_vectors = pci_alloc_irq_vectors(pdev, 1, mhi_cntrl->nr_irqs, PCI_IRQ_MSIX | PCI_IRQ_MSI); 1146 if (nr_vectors < 0) { 1147 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 1148 nr_vectors); 1149 return nr_vectors; 1150 } 1151 1152 if (nr_vectors < mhi_cntrl->nr_irqs) { 1153 dev_warn(&pdev->dev, "using shared MSI\n"); 1154 1155 /* Patch msi vectors, use only one (shared) */ 1156 for (i = 0; i < mhi_cntrl_config->num_events; i++) 1157 mhi_cntrl_config->event_cfg[i].irq = 0; 1158 mhi_cntrl->nr_irqs = 1; 1159 } 1160 1161 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 1162 if (!irq) 1163 return -ENOMEM; 1164 1165 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 1166 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 1167 1168 irq[i] = pci_irq_vector(pdev, vector); 1169 } 1170 1171 mhi_cntrl->irq = irq; 1172 1173 return 0; 1174 } 1175 1176 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 1177 { 1178 /* The runtime_get() MHI callback means: 1179 * Do whatever is requested to leave M3. 1180 */ 1181 return pm_runtime_get(mhi_cntrl->cntrl_dev); 1182 } 1183 1184 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 1185 { 1186 /* The runtime_put() MHI callback means: 1187 * Device can be moved in M3 state. 1188 */ 1189 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 1190 pm_runtime_put(mhi_cntrl->cntrl_dev); 1191 } 1192 1193 static void mhi_pci_recovery_work(struct work_struct *work) 1194 { 1195 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 1196 recovery_work); 1197 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1198 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1199 int err; 1200 1201 dev_warn(&pdev->dev, "device recovery started\n"); 1202 1203 if (pdev->is_physfn) 1204 timer_delete(&mhi_pdev->health_check_timer); 1205 1206 pm_runtime_forbid(&pdev->dev); 1207 1208 /* Clean up MHI state */ 1209 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1210 mhi_power_down(mhi_cntrl, false); 1211 mhi_unprepare_after_power_down(mhi_cntrl); 1212 } 1213 1214 pci_set_power_state(pdev, PCI_D0); 1215 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1216 pci_restore_state(pdev); 1217 1218 if (!mhi_pci_is_alive(mhi_cntrl)) 1219 goto err_try_reset; 1220 1221 err = mhi_prepare_for_power_up(mhi_cntrl); 1222 if (err) 1223 goto err_try_reset; 1224 1225 err = mhi_sync_power_up(mhi_cntrl); 1226 if (err) 1227 goto err_unprepare; 1228 1229 dev_dbg(&pdev->dev, "Recovery completed\n"); 1230 1231 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1232 1233 if (pdev->is_physfn) 1234 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1235 1236 return; 1237 1238 err_unprepare: 1239 mhi_unprepare_after_power_down(mhi_cntrl); 1240 err_try_reset: 1241 err = pci_try_reset_function(pdev); 1242 if (err) 1243 dev_err(&pdev->dev, "Recovery failed: %d\n", err); 1244 } 1245 1246 static void health_check(struct timer_list *t) 1247 { 1248 struct mhi_pci_device *mhi_pdev = timer_container_of(mhi_pdev, t, 1249 health_check_timer); 1250 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1251 1252 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1253 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1254 return; 1255 1256 if (!mhi_pci_is_alive(mhi_cntrl)) { 1257 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1258 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1259 return; 1260 } 1261 1262 /* reschedule in two seconds */ 1263 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1264 } 1265 1266 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1267 { 1268 void __iomem *base = mhi_cntrl->regs; 1269 void __iomem *edl_db; 1270 int ret; 1271 u32 val; 1272 1273 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1274 if (ret) { 1275 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1276 return ret; 1277 } 1278 1279 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1280 mhi_cntrl->runtime_get(mhi_cntrl); 1281 1282 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1283 if (ret) 1284 goto err_get_chdb; 1285 1286 edl_db = base + val + (8 * MHI_EDL_DB); 1287 1288 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1289 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1290 1291 mhi_soc_reset(mhi_cntrl); 1292 1293 err_get_chdb: 1294 mhi_cntrl->runtime_put(mhi_cntrl); 1295 mhi_device_put(mhi_cntrl->mhi_dev); 1296 1297 return ret; 1298 } 1299 1300 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1301 { 1302 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1303 const struct mhi_controller_config *mhi_cntrl_config; 1304 struct mhi_pci_device *mhi_pdev; 1305 struct mhi_controller *mhi_cntrl; 1306 unsigned int dma_data_width; 1307 int err; 1308 1309 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1310 1311 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1312 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1313 if (!mhi_pdev) 1314 return -ENOMEM; 1315 1316 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1317 1318 if (pdev->is_virtfn && info->vf_config) 1319 mhi_cntrl_config = info->vf_config; 1320 else 1321 mhi_cntrl_config = info->config; 1322 1323 /* Initialize health check monitor only for Physical functions */ 1324 if (pdev->is_physfn) 1325 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1326 1327 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1328 1329 dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ? 1330 info->vf_dma_data_width : info->dma_data_width; 1331 1332 mhi_cntrl->cntrl_dev = &pdev->dev; 1333 mhi_cntrl->iova_start = 0; 1334 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width); 1335 mhi_cntrl->fw_image = info->fw; 1336 mhi_cntrl->edl_image = info->edl; 1337 1338 mhi_cntrl->read_reg = mhi_pci_read_reg; 1339 mhi_cntrl->write_reg = mhi_pci_write_reg; 1340 mhi_cntrl->status_cb = mhi_pci_status_cb; 1341 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1342 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1343 mhi_cntrl->mru = info->mru_default; 1344 mhi_cntrl->name = info->name; 1345 1346 if (pdev->is_physfn) 1347 mhi_pdev->reset_on_remove = info->reset_on_remove; 1348 1349 if (info->edl_trigger) 1350 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1351 1352 if (info->sideband_wake) { 1353 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1354 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1355 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1356 } 1357 1358 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_width)); 1359 if (err) 1360 return err; 1361 1362 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1363 if (err) 1364 return err; 1365 1366 pci_set_drvdata(pdev, mhi_pdev); 1367 1368 /* Have stored pci confspace at hand for restore in sudden PCI error. 1369 * cache the state locally and discard the PCI core one. 1370 */ 1371 pci_save_state(pdev); 1372 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1373 pci_load_saved_state(pdev, NULL); 1374 1375 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1376 if (err) 1377 return err; 1378 1379 /* MHI bus does not power up the controller by default */ 1380 err = mhi_prepare_for_power_up(mhi_cntrl); 1381 if (err) { 1382 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1383 goto err_unregister; 1384 } 1385 1386 err = mhi_sync_power_up(mhi_cntrl); 1387 if (err) { 1388 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1389 goto err_unprepare; 1390 } 1391 1392 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1393 1394 /* start health check */ 1395 if (pdev->is_physfn) 1396 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1397 1398 /* Allow runtime suspend only if both PME from D3Hot and M3 are supported */ 1399 if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) { 1400 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1401 pm_runtime_use_autosuspend(&pdev->dev); 1402 pm_runtime_mark_last_busy(&pdev->dev); 1403 pm_runtime_put_noidle(&pdev->dev); 1404 } 1405 1406 return 0; 1407 1408 err_unprepare: 1409 mhi_unprepare_after_power_down(mhi_cntrl); 1410 err_unregister: 1411 mhi_unregister_controller(mhi_cntrl); 1412 1413 return err; 1414 } 1415 1416 static void mhi_pci_remove(struct pci_dev *pdev) 1417 { 1418 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1419 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1420 1421 pci_disable_sriov(pdev); 1422 1423 if (pdev->is_physfn) 1424 timer_delete_sync(&mhi_pdev->health_check_timer); 1425 cancel_work_sync(&mhi_pdev->recovery_work); 1426 1427 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1428 mhi_power_down(mhi_cntrl, true); 1429 mhi_unprepare_after_power_down(mhi_cntrl); 1430 } 1431 1432 /* balancing probe put_noidle */ 1433 if (pci_pme_capable(pdev, PCI_D3hot)) 1434 pm_runtime_get_noresume(&pdev->dev); 1435 1436 if (mhi_pdev->reset_on_remove) 1437 mhi_soc_reset(mhi_cntrl); 1438 1439 mhi_unregister_controller(mhi_cntrl); 1440 } 1441 1442 static void mhi_pci_shutdown(struct pci_dev *pdev) 1443 { 1444 mhi_pci_remove(pdev); 1445 pci_set_power_state(pdev, PCI_D3hot); 1446 } 1447 1448 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1449 { 1450 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1451 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1452 1453 dev_info(&pdev->dev, "reset\n"); 1454 1455 if (pdev->is_physfn) 1456 timer_delete(&mhi_pdev->health_check_timer); 1457 1458 /* Clean up MHI state */ 1459 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1460 mhi_power_down(mhi_cntrl, false); 1461 mhi_unprepare_after_power_down(mhi_cntrl); 1462 } 1463 1464 /* cause internal device reset */ 1465 mhi_soc_reset(mhi_cntrl); 1466 1467 /* Be sure device reset has been executed */ 1468 msleep(MHI_POST_RESET_DELAY_MS); 1469 } 1470 1471 static void mhi_pci_reset_done(struct pci_dev *pdev) 1472 { 1473 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1474 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1475 int err; 1476 1477 /* Restore initial known working PCI state */ 1478 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1479 pci_restore_state(pdev); 1480 1481 /* Is device status available ? */ 1482 if (!mhi_pci_is_alive(mhi_cntrl)) { 1483 dev_err(&pdev->dev, "reset failed\n"); 1484 return; 1485 } 1486 1487 err = mhi_prepare_for_power_up(mhi_cntrl); 1488 if (err) { 1489 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1490 return; 1491 } 1492 1493 err = mhi_sync_power_up(mhi_cntrl); 1494 if (err) { 1495 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1496 mhi_unprepare_after_power_down(mhi_cntrl); 1497 return; 1498 } 1499 1500 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1501 if (pdev->is_physfn) 1502 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1503 } 1504 1505 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1506 pci_channel_state_t state) 1507 { 1508 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1509 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1510 1511 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1512 1513 if (state == pci_channel_io_perm_failure) 1514 return PCI_ERS_RESULT_DISCONNECT; 1515 1516 /* Clean up MHI state */ 1517 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1518 mhi_power_down(mhi_cntrl, false); 1519 mhi_unprepare_after_power_down(mhi_cntrl); 1520 } else { 1521 /* Nothing to do */ 1522 return PCI_ERS_RESULT_RECOVERED; 1523 } 1524 1525 pci_disable_device(pdev); 1526 1527 return PCI_ERS_RESULT_NEED_RESET; 1528 } 1529 1530 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1531 { 1532 if (pci_enable_device(pdev)) { 1533 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1534 return PCI_ERS_RESULT_DISCONNECT; 1535 } 1536 1537 return PCI_ERS_RESULT_RECOVERED; 1538 } 1539 1540 static void mhi_pci_io_resume(struct pci_dev *pdev) 1541 { 1542 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1543 1544 dev_err(&pdev->dev, "PCI slot reset done\n"); 1545 1546 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1547 } 1548 1549 static const struct pci_error_handlers mhi_pci_err_handler = { 1550 .error_detected = mhi_pci_error_detected, 1551 .slot_reset = mhi_pci_slot_reset, 1552 .resume = mhi_pci_io_resume, 1553 .reset_prepare = mhi_pci_reset_prepare, 1554 .reset_done = mhi_pci_reset_done, 1555 }; 1556 1557 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1558 { 1559 struct pci_dev *pdev = to_pci_dev(dev); 1560 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1561 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1562 int err; 1563 1564 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1565 return 0; 1566 1567 if (pdev->is_physfn) 1568 timer_delete(&mhi_pdev->health_check_timer); 1569 1570 cancel_work_sync(&mhi_pdev->recovery_work); 1571 1572 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1573 mhi_cntrl->ee != MHI_EE_AMSS) 1574 goto pci_suspend; /* Nothing to do at MHI level */ 1575 1576 /* Transition to M3 state */ 1577 err = mhi_pm_suspend(mhi_cntrl); 1578 if (err) { 1579 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1580 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1581 return -EBUSY; 1582 } 1583 1584 pci_suspend: 1585 pci_disable_device(pdev); 1586 pci_wake_from_d3(pdev, true); 1587 1588 return 0; 1589 } 1590 1591 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1592 { 1593 struct pci_dev *pdev = to_pci_dev(dev); 1594 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1595 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1596 int err; 1597 1598 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1599 return 0; 1600 1601 err = pci_enable_device(pdev); 1602 if (err) 1603 goto err_recovery; 1604 1605 pci_set_master(pdev); 1606 pci_wake_from_d3(pdev, false); 1607 1608 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1609 mhi_cntrl->ee != MHI_EE_AMSS) 1610 return 0; /* Nothing to do at MHI level */ 1611 1612 /* Exit M3, transition to M0 state */ 1613 err = mhi_pm_resume(mhi_cntrl); 1614 if (err) { 1615 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1616 goto err_recovery; 1617 } 1618 1619 /* Resume health check */ 1620 if (pdev->is_physfn) 1621 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1622 1623 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1624 pm_runtime_mark_last_busy(dev); 1625 1626 return 0; 1627 1628 err_recovery: 1629 /* Do not fail to not mess up our PCI device state, the device likely 1630 * lost power (d3cold) and we simply need to reset it from the recovery 1631 * procedure, trigger the recovery asynchronously to prevent system 1632 * suspend exit delaying. 1633 */ 1634 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1635 pm_runtime_mark_last_busy(dev); 1636 1637 return 0; 1638 } 1639 1640 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1641 { 1642 pm_runtime_disable(dev); 1643 return mhi_pci_runtime_suspend(dev); 1644 } 1645 1646 static int __maybe_unused mhi_pci_resume(struct device *dev) 1647 { 1648 int ret; 1649 1650 /* Depending the platform, device may have lost power (d3cold), we need 1651 * to resume it now to check its state and recover when necessary. 1652 */ 1653 ret = mhi_pci_runtime_resume(dev); 1654 pm_runtime_enable(dev); 1655 1656 return ret; 1657 } 1658 1659 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1660 { 1661 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1662 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1663 1664 /* We want to stop all operations, hibernation does not guarantee that 1665 * device will be in the same state as before freezing, especially if 1666 * the intermediate restore kernel reinitializes MHI device with new 1667 * context. 1668 */ 1669 flush_work(&mhi_pdev->recovery_work); 1670 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1671 mhi_power_down(mhi_cntrl, true); 1672 mhi_unprepare_after_power_down(mhi_cntrl); 1673 } 1674 1675 return 0; 1676 } 1677 1678 static int __maybe_unused mhi_pci_restore(struct device *dev) 1679 { 1680 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1681 1682 /* Reinitialize the device */ 1683 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1684 1685 return 0; 1686 } 1687 1688 static const struct dev_pm_ops mhi_pci_pm_ops = { 1689 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1690 #ifdef CONFIG_PM_SLEEP 1691 .suspend = mhi_pci_suspend, 1692 .resume = mhi_pci_resume, 1693 .freeze = mhi_pci_freeze, 1694 .thaw = mhi_pci_restore, 1695 .poweroff = mhi_pci_freeze, 1696 .restore = mhi_pci_restore, 1697 #endif 1698 }; 1699 1700 static struct pci_driver mhi_pci_driver = { 1701 .name = "mhi-pci-generic", 1702 .id_table = mhi_pci_id_table, 1703 .probe = mhi_pci_probe, 1704 .remove = mhi_pci_remove, 1705 .shutdown = mhi_pci_shutdown, 1706 .err_handler = &mhi_pci_err_handler, 1707 .driver.pm = &mhi_pci_pm_ops, 1708 .sriov_configure = pci_sriov_configure_simple, 1709 }; 1710 module_pci_driver(mhi_pci_driver); 1711 1712 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1713 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1714 MODULE_LICENSE("GPL"); 1715