1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * MHI PCI driver - MHI over PCI controller driver 4 * 5 * This module is a generic driver for registering MHI-over-PCI devices, 6 * such as PCIe QCOM modems. 7 * 8 * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org> 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/timer.h> 18 #include <linux/workqueue.h> 19 20 #define MHI_PCI_DEFAULT_BAR_NUM 0 21 22 #define MHI_POST_RESET_DELAY_MS 2000 23 24 #define HEALTH_CHECK_PERIOD (HZ * 2) 25 26 /* PCI VID definitions */ 27 #define PCI_VENDOR_ID_THALES 0x1269 28 #define PCI_VENDOR_ID_QUECTEL 0x1eac 29 #define PCI_VENDOR_ID_NETPRISMA 0x203e 30 31 #define MHI_EDL_DB 91 32 #define MHI_EDL_COOKIE 0xEDEDEDED 33 34 /** 35 * struct mhi_pci_dev_info - MHI PCI device specific information 36 * @config: MHI controller configuration 37 * @vf_config: MHI controller configuration for Virtual function (optional) 38 * @name: name of the PCI module 39 * @fw: firmware path (if any) 40 * @edl: emergency download mode firmware path (if any) 41 * @edl_trigger: capable of triggering EDL mode in the device (if supported) 42 * @bar_num: PCI base address register to use for MHI MMIO register space 43 * @dma_data_width: DMA transfer word size (32 or 64 bits) 44 * @vf_dma_data_width: DMA transfer word size for VF's (optional) 45 * @mru_default: default MRU size for MBIM network packets 46 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead 47 * of inband wake support (such as sdx24) 48 * @no_m3: M3 not supported 49 * @reset_on_remove: Set true for devices that require SoC during driver removal 50 */ 51 struct mhi_pci_dev_info { 52 const struct mhi_controller_config *config; 53 const struct mhi_controller_config *vf_config; 54 const char *name; 55 const char *fw; 56 const char *edl; 57 bool edl_trigger; 58 unsigned int bar_num; 59 unsigned int dma_data_width; 60 unsigned int vf_dma_data_width; 61 unsigned int mru_default; 62 bool sideband_wake; 63 bool no_m3; 64 bool reset_on_remove; 65 }; 66 67 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ 68 { \ 69 .num = ch_num, \ 70 .name = ch_name, \ 71 .num_elements = el_count, \ 72 .event_ring = ev_ring, \ 73 .dir = DMA_TO_DEVICE, \ 74 .ee_mask = BIT(MHI_EE_AMSS), \ 75 .pollcfg = 0, \ 76 .doorbell = MHI_DB_BRST_DISABLE, \ 77 .lpm_notify = false, \ 78 .offload_channel = false, \ 79 .doorbell_mode_switch = false, \ 80 } \ 81 82 #define MHI_CHANNEL_CONFIG_DL(ch_num, ch_name, el_count, ev_ring) \ 83 { \ 84 .num = ch_num, \ 85 .name = ch_name, \ 86 .num_elements = el_count, \ 87 .event_ring = ev_ring, \ 88 .dir = DMA_FROM_DEVICE, \ 89 .ee_mask = BIT(MHI_EE_AMSS), \ 90 .pollcfg = 0, \ 91 .doorbell = MHI_DB_BRST_DISABLE, \ 92 .lpm_notify = false, \ 93 .offload_channel = false, \ 94 .doorbell_mode_switch = false, \ 95 } 96 97 #define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \ 98 { \ 99 .num_elements = el_count, \ 100 .irq_moderation_ms = 0, \ 101 .irq = (ev_ring) + 1, \ 102 .priority = 1, \ 103 .mode = MHI_DB_BRST_DISABLE, \ 104 .data_type = MHI_ER_CTRL, \ 105 .hardware_event = false, \ 106 .client_managed = false, \ 107 .offload_channel = false, \ 108 } 109 110 #define MHI_CHANNEL_CONFIG_HW_UL(ch_num, ch_name, el_count, ev_ring) \ 111 { \ 112 .num = ch_num, \ 113 .name = ch_name, \ 114 .num_elements = el_count, \ 115 .event_ring = ev_ring, \ 116 .dir = DMA_TO_DEVICE, \ 117 .ee_mask = BIT(MHI_EE_AMSS), \ 118 .pollcfg = 0, \ 119 .doorbell = MHI_DB_BRST_ENABLE, \ 120 .lpm_notify = false, \ 121 .offload_channel = false, \ 122 .doorbell_mode_switch = true, \ 123 } \ 124 125 #define MHI_CHANNEL_CONFIG_HW_DL(ch_num, ch_name, el_count, ev_ring) \ 126 { \ 127 .num = ch_num, \ 128 .name = ch_name, \ 129 .num_elements = el_count, \ 130 .event_ring = ev_ring, \ 131 .dir = DMA_FROM_DEVICE, \ 132 .ee_mask = BIT(MHI_EE_AMSS), \ 133 .pollcfg = 0, \ 134 .doorbell = MHI_DB_BRST_ENABLE, \ 135 .lpm_notify = false, \ 136 .offload_channel = false, \ 137 .doorbell_mode_switch = true, \ 138 } 139 140 #define MHI_CHANNEL_CONFIG_UL_SBL(ch_num, ch_name, el_count, ev_ring) \ 141 { \ 142 .num = ch_num, \ 143 .name = ch_name, \ 144 .num_elements = el_count, \ 145 .event_ring = ev_ring, \ 146 .dir = DMA_TO_DEVICE, \ 147 .ee_mask = BIT(MHI_EE_SBL), \ 148 .pollcfg = 0, \ 149 .doorbell = MHI_DB_BRST_DISABLE, \ 150 .lpm_notify = false, \ 151 .offload_channel = false, \ 152 .doorbell_mode_switch = false, \ 153 } \ 154 155 #define MHI_CHANNEL_CONFIG_DL_SBL(ch_num, ch_name, el_count, ev_ring) \ 156 { \ 157 .num = ch_num, \ 158 .name = ch_name, \ 159 .num_elements = el_count, \ 160 .event_ring = ev_ring, \ 161 .dir = DMA_FROM_DEVICE, \ 162 .ee_mask = BIT(MHI_EE_SBL), \ 163 .pollcfg = 0, \ 164 .doorbell = MHI_DB_BRST_DISABLE, \ 165 .lpm_notify = false, \ 166 .offload_channel = false, \ 167 .doorbell_mode_switch = false, \ 168 } 169 170 #define MHI_CHANNEL_CONFIG_UL_FP(ch_num, ch_name, el_count, ev_ring) \ 171 { \ 172 .num = ch_num, \ 173 .name = ch_name, \ 174 .num_elements = el_count, \ 175 .event_ring = ev_ring, \ 176 .dir = DMA_TO_DEVICE, \ 177 .ee_mask = BIT(MHI_EE_FP), \ 178 .pollcfg = 0, \ 179 .doorbell = MHI_DB_BRST_DISABLE, \ 180 .lpm_notify = false, \ 181 .offload_channel = false, \ 182 .doorbell_mode_switch = false, \ 183 } \ 184 185 #define MHI_CHANNEL_CONFIG_DL_FP(ch_num, ch_name, el_count, ev_ring) \ 186 { \ 187 .num = ch_num, \ 188 .name = ch_name, \ 189 .num_elements = el_count, \ 190 .event_ring = ev_ring, \ 191 .dir = DMA_FROM_DEVICE, \ 192 .ee_mask = BIT(MHI_EE_FP), \ 193 .pollcfg = 0, \ 194 .doorbell = MHI_DB_BRST_DISABLE, \ 195 .lpm_notify = false, \ 196 .offload_channel = false, \ 197 .doorbell_mode_switch = false, \ 198 } 199 200 #define MHI_EVENT_CONFIG_DATA(ev_ring, el_count) \ 201 { \ 202 .num_elements = el_count, \ 203 .irq_moderation_ms = 5, \ 204 .irq = (ev_ring) + 1, \ 205 .priority = 1, \ 206 .mode = MHI_DB_BRST_DISABLE, \ 207 .data_type = MHI_ER_DATA, \ 208 .hardware_event = false, \ 209 .client_managed = false, \ 210 .offload_channel = false, \ 211 } 212 213 #define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \ 214 { \ 215 .num_elements = el_count, \ 216 .irq_moderation_ms = 0, \ 217 .irq = (ev_ring) + 1, \ 218 .priority = 1, \ 219 .mode = MHI_DB_BRST_DISABLE, \ 220 .data_type = MHI_ER_DATA, \ 221 .hardware_event = false, \ 222 .client_managed = false, \ 223 .offload_channel = false, \ 224 } 225 226 #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \ 227 { \ 228 .num_elements = el_count, \ 229 .irq_moderation_ms = 1, \ 230 .irq = (ev_ring) + 1, \ 231 .priority = 1, \ 232 .mode = MHI_DB_BRST_DISABLE, \ 233 .data_type = MHI_ER_DATA, \ 234 .hardware_event = true, \ 235 .client_managed = false, \ 236 .offload_channel = false, \ 237 .channel = ch_num, \ 238 } 239 240 static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { 241 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), 242 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), 243 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), 244 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), 245 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), 246 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), 247 MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), 248 MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), 249 MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), 250 MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), 251 MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), 252 MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), 253 MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), 254 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), 255 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), 256 MHI_CHANNEL_CONFIG_UL(48, "IP_SW1", 256, 6), 257 MHI_CHANNEL_CONFIG_DL(49, "IP_SW1", 256, 6), 258 MHI_CHANNEL_CONFIG_UL(50, "IP_ETH0", 256, 7), 259 MHI_CHANNEL_CONFIG_DL(51, "IP_ETH0", 256, 7), 260 MHI_CHANNEL_CONFIG_UL(52, "IP_ETH1", 256, 8), 261 MHI_CHANNEL_CONFIG_DL(53, "IP_ETH1", 256, 8), 262 263 }; 264 265 static struct mhi_event_config mhi_qcom_qdu100_events[] = { 266 /* first ring is control+data ring */ 267 MHI_EVENT_CONFIG_CTRL(0, 64), 268 /* SAHARA dedicated event ring */ 269 MHI_EVENT_CONFIG_SW_DATA(1, 256), 270 /* Software channels dedicated event ring */ 271 MHI_EVENT_CONFIG_SW_DATA(2, 64), 272 MHI_EVENT_CONFIG_SW_DATA(3, 256), 273 MHI_EVENT_CONFIG_SW_DATA(4, 256), 274 /* Software IP channels dedicated event ring */ 275 MHI_EVENT_CONFIG_SW_DATA(5, 512), 276 MHI_EVENT_CONFIG_SW_DATA(6, 512), 277 MHI_EVENT_CONFIG_SW_DATA(7, 512), 278 MHI_EVENT_CONFIG_SW_DATA(8, 512), 279 }; 280 281 static const struct mhi_controller_config mhi_qcom_qdu100_config = { 282 .max_channels = 128, 283 .timeout_ms = 120000, 284 .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), 285 .ch_cfg = mhi_qcom_qdu100_channels, 286 .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), 287 .event_cfg = mhi_qcom_qdu100_events, 288 }; 289 290 static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { 291 .name = "qcom-qdu100", 292 .fw = "qcom/qdu100/xbl_s.melf", 293 .edl_trigger = true, 294 .config = &mhi_qcom_qdu100_config, 295 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 296 .dma_data_width = 32, 297 .vf_dma_data_width = 40, 298 .sideband_wake = false, 299 .no_m3 = true, 300 .reset_on_remove = true, 301 }; 302 303 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] = { 304 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 2048, 1), 305 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 2048, 2), 306 }; 307 308 static struct mhi_event_config mhi_qcom_sa8775p_events[] = { 309 /* first ring is control+data ring */ 310 MHI_EVENT_CONFIG_CTRL(0, 64), 311 /* Software channels dedicated event ring */ 312 MHI_EVENT_CONFIG_SW_DATA(1, 64), 313 MHI_EVENT_CONFIG_SW_DATA(2, 64), 314 }; 315 316 static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { 317 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), 318 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), 319 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 4, 0), 320 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 4, 0), 321 MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0), 322 MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0), 323 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0), 324 MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0), 325 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 326 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 327 MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2), 328 MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3), 329 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4), 330 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5), 331 }; 332 333 static struct mhi_event_config modem_qcom_v1_mhi_events[] = { 334 /* first ring is control+data ring */ 335 MHI_EVENT_CONFIG_CTRL(0, 64), 336 /* DIAG dedicated event ring */ 337 MHI_EVENT_CONFIG_DATA(1, 128), 338 /* Software channels dedicated event ring */ 339 MHI_EVENT_CONFIG_SW_DATA(2, 64), 340 MHI_EVENT_CONFIG_SW_DATA(3, 64), 341 /* Hardware channels request dedicated hardware event rings */ 342 MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100), 343 MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101) 344 }; 345 346 static const struct mhi_controller_config mhi_qcom_sa8775p_config = { 347 .max_channels = 128, 348 .timeout_ms = 8000, 349 .num_channels = ARRAY_SIZE(mhi_qcom_sa8775p_channels), 350 .ch_cfg = mhi_qcom_sa8775p_channels, 351 .num_events = ARRAY_SIZE(mhi_qcom_sa8775p_events), 352 .event_cfg = mhi_qcom_sa8775p_events, 353 }; 354 355 static const struct mhi_controller_config modem_qcom_v2_mhiv_config = { 356 .max_channels = 128, 357 .timeout_ms = 8000, 358 .ready_timeout_ms = 50000, 359 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 360 .ch_cfg = modem_qcom_v1_mhi_channels, 361 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 362 .event_cfg = modem_qcom_v1_mhi_events, 363 }; 364 365 static const struct mhi_controller_config modem_qcom_v1_mhiv_config = { 366 .max_channels = 128, 367 .timeout_ms = 8000, 368 .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels), 369 .ch_cfg = modem_qcom_v1_mhi_channels, 370 .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events), 371 .event_cfg = modem_qcom_v1_mhi_events, 372 }; 373 374 static const struct mhi_pci_dev_info mhi_qcom_sa8775p_info = { 375 .name = "qcom-sa8775p", 376 .edl_trigger = false, 377 .config = &mhi_qcom_sa8775p_config, 378 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 379 .dma_data_width = 32, 380 .mru_default = 32768, 381 .sideband_wake = false, 382 }; 383 384 static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = { 385 .name = "qcom-sdx75m", 386 .fw = "qcom/sdx75m/xbl.elf", 387 .edl = "qcom/sdx75m/edl.mbn", 388 .edl_trigger = true, 389 .config = &modem_qcom_v2_mhiv_config, 390 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 391 .dma_data_width = 32, 392 .sideband_wake = false, 393 }; 394 395 static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = { 396 .name = "qcom-sdx65m", 397 .fw = "qcom/sdx65m/xbl.elf", 398 .edl = "qcom/sdx65m/edl.mbn", 399 .edl_trigger = true, 400 .config = &modem_qcom_v1_mhiv_config, 401 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 402 .dma_data_width = 32, 403 .sideband_wake = false, 404 }; 405 406 static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = { 407 .name = "qcom-sdx55m", 408 .fw = "qcom/sdx55m/sbl1.mbn", 409 .edl = "qcom/sdx55m/edl.mbn", 410 .edl_trigger = true, 411 .config = &modem_qcom_v1_mhiv_config, 412 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 413 .dma_data_width = 32, 414 .mru_default = 32768, 415 .sideband_wake = false, 416 }; 417 418 static const struct mhi_pci_dev_info mhi_qcom_sdx35_info = { 419 .name = "qcom-sdx35m", 420 .config = &modem_qcom_v2_mhiv_config, 421 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 422 .dma_data_width = 32, 423 .mru_default = 32768, 424 .sideband_wake = false, 425 .edl_trigger = true, 426 }; 427 428 static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = { 429 .name = "qcom-sdx24", 430 .edl = "qcom/prog_firehose_sdx24.mbn", 431 .config = &modem_qcom_v1_mhiv_config, 432 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 433 .dma_data_width = 32, 434 .sideband_wake = true, 435 }; 436 437 static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = { 438 MHI_CHANNEL_CONFIG_UL(0, "NMEA", 32, 0), 439 MHI_CHANNEL_CONFIG_DL(1, "NMEA", 32, 0), 440 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 441 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 442 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 443 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 444 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 445 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 446 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 447 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 448 /* The EDL firmware is a flash-programmer exposing firehose protocol */ 449 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 450 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 451 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 452 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 453 }; 454 455 static struct mhi_event_config mhi_quectel_em1xx_events[] = { 456 MHI_EVENT_CONFIG_CTRL(0, 128), 457 MHI_EVENT_CONFIG_DATA(1, 128), 458 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 459 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 460 }; 461 462 static const struct mhi_controller_config modem_quectel_em1xx_config = { 463 .max_channels = 128, 464 .timeout_ms = 20000, 465 .num_channels = ARRAY_SIZE(mhi_quectel_em1xx_channels), 466 .ch_cfg = mhi_quectel_em1xx_channels, 467 .num_events = ARRAY_SIZE(mhi_quectel_em1xx_events), 468 .event_cfg = mhi_quectel_em1xx_events, 469 }; 470 471 static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = { 472 .name = "quectel-em1xx", 473 .edl = "qcom/prog_firehose_sdx24.mbn", 474 .config = &modem_quectel_em1xx_config, 475 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 476 .dma_data_width = 32, 477 .mru_default = 32768, 478 .sideband_wake = true, 479 }; 480 481 static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = { 482 .name = "quectel-rm5xx", 483 .edl = "qcom/prog_firehose_sdx6x.elf", 484 .config = &modem_quectel_em1xx_config, 485 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 486 .dma_data_width = 32, 487 .mru_default = 32768, 488 .sideband_wake = true, 489 }; 490 491 static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = { 492 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 493 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 494 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 495 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 496 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 497 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 498 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 499 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 500 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 501 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 502 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 503 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 504 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 505 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 506 }; 507 508 static const struct mhi_channel_config mhi_foxconn_sdx61_channels[] = { 509 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0), 510 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0), 511 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 512 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 513 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 1), 514 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 1), 515 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 516 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 517 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 518 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 519 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 520 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 521 MHI_CHANNEL_CONFIG_UL(50, "NMEA", 32, 0), 522 MHI_CHANNEL_CONFIG_DL(51, "NMEA", 32, 0), 523 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 524 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 525 }; 526 527 static struct mhi_event_config mhi_foxconn_sdx55_events[] = { 528 MHI_EVENT_CONFIG_CTRL(0, 128), 529 MHI_EVENT_CONFIG_DATA(1, 128), 530 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 531 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101) 532 }; 533 534 static const struct mhi_controller_config modem_foxconn_sdx55_config = { 535 .max_channels = 128, 536 .timeout_ms = 20000, 537 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 538 .ch_cfg = mhi_foxconn_sdx55_channels, 539 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 540 .event_cfg = mhi_foxconn_sdx55_events, 541 }; 542 543 static const struct mhi_controller_config modem_foxconn_sdx61_config = { 544 .max_channels = 128, 545 .timeout_ms = 20000, 546 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx61_channels), 547 .ch_cfg = mhi_foxconn_sdx61_channels, 548 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 549 .event_cfg = mhi_foxconn_sdx55_events, 550 }; 551 552 static const struct mhi_controller_config modem_foxconn_sdx72_config = { 553 .max_channels = 128, 554 .timeout_ms = 20000, 555 .ready_timeout_ms = 50000, 556 .num_channels = ARRAY_SIZE(mhi_foxconn_sdx55_channels), 557 .ch_cfg = mhi_foxconn_sdx55_channels, 558 .num_events = ARRAY_SIZE(mhi_foxconn_sdx55_events), 559 .event_cfg = mhi_foxconn_sdx55_events, 560 }; 561 562 static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = { 563 .name = "foxconn-sdx55", 564 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 565 .edl_trigger = true, 566 .config = &modem_foxconn_sdx55_config, 567 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 568 .dma_data_width = 32, 569 .mru_default = 32768, 570 .sideband_wake = false, 571 }; 572 573 static const struct mhi_pci_dev_info mhi_foxconn_t99w175_info = { 574 .name = "foxconn-t99w175", 575 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 576 .edl_trigger = true, 577 .config = &modem_foxconn_sdx55_config, 578 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 579 .dma_data_width = 32, 580 .mru_default = 32768, 581 .sideband_wake = false, 582 }; 583 584 static const struct mhi_pci_dev_info mhi_foxconn_dw5930e_info = { 585 .name = "foxconn-dw5930e", 586 .edl = "qcom/sdx55m/foxconn/prog_firehose_sdx55.mbn", 587 .edl_trigger = true, 588 .config = &modem_foxconn_sdx55_config, 589 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 590 .dma_data_width = 32, 591 .mru_default = 32768, 592 .sideband_wake = false, 593 }; 594 595 static const struct mhi_pci_dev_info mhi_foxconn_t99w368_info = { 596 .name = "foxconn-t99w368", 597 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 598 .edl_trigger = true, 599 .config = &modem_foxconn_sdx55_config, 600 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 601 .dma_data_width = 32, 602 .mru_default = 32768, 603 .sideband_wake = false, 604 }; 605 606 static const struct mhi_pci_dev_info mhi_foxconn_t99w373_info = { 607 .name = "foxconn-t99w373", 608 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 609 .edl_trigger = true, 610 .config = &modem_foxconn_sdx55_config, 611 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 612 .dma_data_width = 32, 613 .mru_default = 32768, 614 .sideband_wake = false, 615 }; 616 617 static const struct mhi_pci_dev_info mhi_foxconn_t99w510_info = { 618 .name = "foxconn-t99w510", 619 .edl = "qcom/sdx24m/foxconn/prog_firehose_sdx24.mbn", 620 .edl_trigger = true, 621 .config = &modem_foxconn_sdx55_config, 622 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 623 .dma_data_width = 32, 624 .mru_default = 32768, 625 .sideband_wake = false, 626 }; 627 628 static const struct mhi_pci_dev_info mhi_foxconn_dw5932e_info = { 629 .name = "foxconn-dw5932e", 630 .edl = "qcom/sdx65m/foxconn/prog_firehose_lite.elf", 631 .edl_trigger = true, 632 .config = &modem_foxconn_sdx55_config, 633 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 634 .dma_data_width = 32, 635 .mru_default = 32768, 636 .sideband_wake = false, 637 }; 638 639 static const struct mhi_pci_dev_info mhi_foxconn_t99w640_info = { 640 .name = "foxconn-t99w640", 641 .edl = "qcom/sdx72m/foxconn/edl.mbn", 642 .edl_trigger = true, 643 .config = &modem_foxconn_sdx72_config, 644 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 645 .dma_data_width = 32, 646 .mru_default = 32768, 647 .sideband_wake = false, 648 }; 649 650 static const struct mhi_pci_dev_info mhi_foxconn_dw5934e_info = { 651 .name = "foxconn-dw5934e", 652 .edl = "qcom/sdx72m/foxconn/edl.mbn", 653 .edl_trigger = true, 654 .config = &modem_foxconn_sdx72_config, 655 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 656 .dma_data_width = 32, 657 .mru_default = 32768, 658 .sideband_wake = false, 659 }; 660 661 static const struct mhi_pci_dev_info mhi_foxconn_t99w696_info = { 662 .name = "foxconn-t99w696", 663 .edl = "qcom/sdx61/foxconn/prog_firehose_lite.elf", 664 .edl_trigger = true, 665 .config = &modem_foxconn_sdx61_config, 666 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 667 .dma_data_width = 32, 668 .mru_default = 32768, 669 .sideband_wake = false, 670 }; 671 672 static const struct mhi_pci_dev_info mhi_foxconn_t99w760_info = { 673 .name = "foxconn-t99w760", 674 .edl = "qcom/sdx35/foxconn/xbl_s_devprg_ns.melf", 675 .edl_trigger = true, 676 .config = &modem_foxconn_sdx61_config, 677 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 678 .dma_data_width = 32, 679 .mru_default = 32768, 680 .sideband_wake = false, 681 }; 682 683 static const struct mhi_channel_config mhi_mv3x_channels[] = { 684 MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 64, 0), 685 MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 64, 0), 686 /* MBIM Control Channel */ 687 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 64, 0), 688 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 64, 0), 689 /* MBIM Data Channel */ 690 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 512, 2), 691 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 512, 3), 692 }; 693 694 static struct mhi_event_config mhi_mv3x_events[] = { 695 MHI_EVENT_CONFIG_CTRL(0, 256), 696 MHI_EVENT_CONFIG_DATA(1, 256), 697 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 698 MHI_EVENT_CONFIG_HW_DATA(3, 1024, 101), 699 }; 700 701 static const struct mhi_controller_config modem_mv3x_config = { 702 .max_channels = 128, 703 .timeout_ms = 20000, 704 .num_channels = ARRAY_SIZE(mhi_mv3x_channels), 705 .ch_cfg = mhi_mv3x_channels, 706 .num_events = ARRAY_SIZE(mhi_mv3x_events), 707 .event_cfg = mhi_mv3x_events, 708 }; 709 710 static const struct mhi_pci_dev_info mhi_mv31_info = { 711 .name = "cinterion-mv31", 712 .config = &modem_mv3x_config, 713 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 714 .dma_data_width = 32, 715 .mru_default = 32768, 716 }; 717 718 static const struct mhi_pci_dev_info mhi_mv32_info = { 719 .name = "cinterion-mv32", 720 .config = &modem_mv3x_config, 721 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 722 .dma_data_width = 32, 723 .mru_default = 32768, 724 }; 725 726 static const struct mhi_channel_config mhi_sierra_em919x_channels[] = { 727 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 728 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 256, 0), 729 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 32, 0), 730 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 32, 0), 731 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 128, 0), 732 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 128, 0), 733 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 734 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 735 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 736 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 737 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 512, 1), 738 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 512, 2), 739 }; 740 741 static struct mhi_event_config modem_sierra_em919x_mhi_events[] = { 742 /* first ring is control+data and DIAG ring */ 743 MHI_EVENT_CONFIG_CTRL(0, 2048), 744 /* Hardware channels request dedicated hardware event rings */ 745 MHI_EVENT_CONFIG_HW_DATA(1, 2048, 100), 746 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 747 }; 748 749 static const struct mhi_controller_config modem_sierra_em919x_config = { 750 .max_channels = 128, 751 .timeout_ms = 24000, 752 .num_channels = ARRAY_SIZE(mhi_sierra_em919x_channels), 753 .ch_cfg = mhi_sierra_em919x_channels, 754 .num_events = ARRAY_SIZE(modem_sierra_em919x_mhi_events), 755 .event_cfg = modem_sierra_em919x_mhi_events, 756 }; 757 758 static const struct mhi_pci_dev_info mhi_sierra_em919x_info = { 759 .name = "sierra-em919x", 760 .config = &modem_sierra_em919x_config, 761 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 762 .dma_data_width = 32, 763 .mru_default = 32768, 764 .sideband_wake = false, 765 }; 766 767 static const struct mhi_channel_config mhi_telit_fn980_hw_v1_channels[] = { 768 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 769 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 770 MHI_CHANNEL_CONFIG_UL(20, "IPCR", 16, 0), 771 MHI_CHANNEL_CONFIG_DL(21, "IPCR", 16, 0), 772 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 1), 773 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 2), 774 }; 775 776 static struct mhi_event_config mhi_telit_fn980_hw_v1_events[] = { 777 MHI_EVENT_CONFIG_CTRL(0, 128), 778 MHI_EVENT_CONFIG_HW_DATA(1, 1024, 100), 779 MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101) 780 }; 781 782 static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = { 783 .max_channels = 128, 784 .timeout_ms = 20000, 785 .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels), 786 .ch_cfg = mhi_telit_fn980_hw_v1_channels, 787 .num_events = ARRAY_SIZE(mhi_telit_fn980_hw_v1_events), 788 .event_cfg = mhi_telit_fn980_hw_v1_events, 789 }; 790 791 static const struct mhi_pci_dev_info mhi_telit_fn980_hw_v1_info = { 792 .name = "telit-fn980-hwv1", 793 .fw = "qcom/sdx55m/sbl1.mbn", 794 .edl = "qcom/sdx55m/edl.mbn", 795 .config = &modem_telit_fn980_hw_v1_config, 796 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 797 .dma_data_width = 32, 798 .mru_default = 32768, 799 .sideband_wake = false, 800 }; 801 802 static const struct mhi_channel_config mhi_telit_fn990_channels[] = { 803 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 804 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 805 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 806 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 807 MHI_CHANNEL_CONFIG_UL(12, "MBIM", 32, 0), 808 MHI_CHANNEL_CONFIG_DL(13, "MBIM", 32, 0), 809 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 810 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 811 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 812 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 813 MHI_CHANNEL_CONFIG_UL(94, "NMEA", 32, 1), 814 MHI_CHANNEL_CONFIG_DL(95, "NMEA", 32, 1), 815 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0_MBIM", 128, 2), 816 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0_MBIM", 128, 3), 817 }; 818 819 static struct mhi_event_config mhi_telit_fn990_events[] = { 820 MHI_EVENT_CONFIG_CTRL(0, 128), 821 MHI_EVENT_CONFIG_DATA(1, 128), 822 MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100), 823 MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101) 824 }; 825 826 static const struct mhi_controller_config modem_telit_fn990_config = { 827 .max_channels = 128, 828 .timeout_ms = 20000, 829 .num_channels = ARRAY_SIZE(mhi_telit_fn990_channels), 830 .ch_cfg = mhi_telit_fn990_channels, 831 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 832 .event_cfg = mhi_telit_fn990_events, 833 }; 834 835 static const struct mhi_pci_dev_info mhi_telit_fn990_info = { 836 .name = "telit-fn990", 837 .config = &modem_telit_fn990_config, 838 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 839 .dma_data_width = 32, 840 .sideband_wake = false, 841 .mru_default = 32768, 842 }; 843 844 static const struct mhi_pci_dev_info mhi_telit_fe990a_info = { 845 .name = "telit-fe990a", 846 .config = &modem_telit_fn990_config, 847 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 848 .dma_data_width = 32, 849 .sideband_wake = false, 850 .mru_default = 32768, 851 }; 852 853 static const struct mhi_channel_config mhi_telit_fn920c04_channels[] = { 854 MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 32, 0), 855 MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 32, 0), 856 MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 1), 857 MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 1), 858 MHI_CHANNEL_CONFIG_UL(14, "QMI", 32, 0), 859 MHI_CHANNEL_CONFIG_DL(15, "QMI", 32, 0), 860 MHI_CHANNEL_CONFIG_UL(32, "DUN", 32, 0), 861 MHI_CHANNEL_CONFIG_DL(33, "DUN", 32, 0), 862 MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0), 863 MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0), 864 MHI_CHANNEL_CONFIG_UL(92, "DUN2", 32, 1), 865 MHI_CHANNEL_CONFIG_DL(93, "DUN2", 32, 1), 866 MHI_CHANNEL_CONFIG_UL(94, "NMEA", 32, 1), 867 MHI_CHANNEL_CONFIG_DL(95, "NMEA", 32, 1), 868 MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2), 869 MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3), 870 }; 871 872 static const struct mhi_controller_config modem_telit_fn920c04_config = { 873 .max_channels = 128, 874 .timeout_ms = 50000, 875 .num_channels = ARRAY_SIZE(mhi_telit_fn920c04_channels), 876 .ch_cfg = mhi_telit_fn920c04_channels, 877 .num_events = ARRAY_SIZE(mhi_telit_fn990_events), 878 .event_cfg = mhi_telit_fn990_events, 879 }; 880 881 static const struct mhi_pci_dev_info mhi_telit_fn920c04_info = { 882 .name = "telit-fn920c04", 883 .config = &modem_telit_fn920c04_config, 884 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 885 .dma_data_width = 32, 886 .sideband_wake = false, 887 .mru_default = 32768, 888 .edl_trigger = true, 889 }; 890 891 static const struct mhi_pci_dev_info mhi_telit_fn990b40_info = { 892 .name = "telit-fn990b40", 893 .config = &modem_telit_fn920c04_config, 894 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 895 .dma_data_width = 32, 896 .sideband_wake = false, 897 .mru_default = 32768, 898 .edl_trigger = true, 899 }; 900 901 static const struct mhi_pci_dev_info mhi_telit_fe990b40_info = { 902 .name = "telit-fe990b40", 903 .config = &modem_telit_fn920c04_config, 904 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 905 .dma_data_width = 32, 906 .sideband_wake = false, 907 .mru_default = 32768, 908 .edl_trigger = true, 909 }; 910 911 static const struct mhi_pci_dev_info mhi_telit_fe912c04_info = { 912 .name = "telit-fe912c04", 913 .config = &modem_telit_fn920c04_config, 914 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 915 .dma_data_width = 32, 916 .sideband_wake = false, 917 .mru_default = 32768, 918 .edl_trigger = true, 919 }; 920 921 static const struct mhi_pci_dev_info mhi_telit_fe910c04_info = { 922 .name = "telit-fe910c04", 923 .config = &modem_telit_fn920c04_config, 924 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 925 .dma_data_width = 32, 926 .sideband_wake = false, 927 .mru_default = 32768, 928 .edl_trigger = true, 929 }; 930 931 static const struct mhi_pci_dev_info mhi_netprisma_lcur57_info = { 932 .name = "netprisma-lcur57", 933 .edl = "qcom/prog_firehose_sdx24.mbn", 934 .config = &modem_quectel_em1xx_config, 935 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 936 .dma_data_width = 32, 937 .mru_default = 32768, 938 .sideband_wake = true, 939 }; 940 941 static const struct mhi_pci_dev_info mhi_netprisma_fcun69_info = { 942 .name = "netprisma-fcun69", 943 .edl = "qcom/prog_firehose_sdx6x.elf", 944 .config = &modem_quectel_em1xx_config, 945 .bar_num = MHI_PCI_DEFAULT_BAR_NUM, 946 .dma_data_width = 32, 947 .mru_default = 32768, 948 .sideband_wake = true, 949 }; 950 951 /* Keep the list sorted based on the PID. New VID should be added as the last entry */ 952 static const struct pci_device_id mhi_pci_id_table[] = { 953 {PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0116), 954 .driver_data = (kernel_ulong_t) &mhi_qcom_sa8775p_info }, 955 /* Telit FN920C04 (sdx35) */ 956 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2020), 957 .driver_data = (kernel_ulong_t) &mhi_telit_fn920c04_info }, 958 /* Telit FE910C04 (sdx35) */ 959 {PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x202a), 960 .driver_data = (kernel_ulong_t) &mhi_telit_fe910c04_info }, 961 /* Telit FE912C04 (sdx35) */ 962 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x011a, 0x1c5d, 0x2045), 963 .driver_data = (kernel_ulong_t) &mhi_telit_fe912c04_info }, 964 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x011a), 965 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx35_info }, 966 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304), 967 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info }, 968 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c), 969 .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info }, 970 /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */ 971 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200), 972 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 973 /* EM929x (sdx65), use the same configuration as EM919x */ 974 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x18d7, 0x0301), 975 .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info }, 976 /* Telit FN980 hardware revision v1 */ 977 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x1C5D, 0x2000), 978 .driver_data = (kernel_ulong_t) &mhi_telit_fn980_hw_v1_info }, 979 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0306), 980 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx55_info }, 981 /* Telit FN990 */ 982 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010), 983 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info }, 984 /* Telit FE990A */ 985 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015), 986 .driver_data = (kernel_ulong_t) &mhi_telit_fe990a_info }, 987 /* Foxconn T99W696, all variants */ 988 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, PCI_VENDOR_ID_FOXCONN, PCI_ANY_ID), 989 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w696_info }, 990 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308), 991 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, 992 /* Telit FN990B40 (sdx72) */ 993 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x201a), 994 .driver_data = (kernel_ulong_t) &mhi_telit_fn990b40_info }, 995 /* Telit FE990B40 (sdx72) */ 996 { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0309, 0x1c5d, 0x2025), 997 .driver_data = (kernel_ulong_t) &mhi_telit_fe990b40_info }, 998 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), 999 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, 1000 /* QDU100, x100-DU */ 1001 { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), 1002 .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, 1003 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ 1004 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 1005 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ 1006 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 1007 /* RM520N-GL (sdx6x), eSIM */ 1008 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004), 1009 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 1010 /* RM520N-GL (sdx6x), Lenovo variant */ 1011 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007), 1012 .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info }, 1013 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */ 1014 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 1015 { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */ 1016 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, 1017 /* T99W175 (sdx55), Both for eSIM and Non-eSIM */ 1018 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab), 1019 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1020 /* DW5930e (sdx55), With eSIM, It's also T99W175 */ 1021 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b0), 1022 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 1023 /* DW5930e (sdx55), Non-eSIM, It's also T99W175 */ 1024 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0b1), 1025 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5930e_info }, 1026 /* T99W175 (sdx55), Based on Qualcomm new baseline */ 1027 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0bf), 1028 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1029 /* T99W175 (sdx55) */ 1030 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0c3), 1031 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1032 /* T99W368 (sdx65) */ 1033 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d8), 1034 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w368_info }, 1035 /* T99W373 (sdx62) */ 1036 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9), 1037 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w373_info }, 1038 /* T99W510 (sdx24), variant 1 */ 1039 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0), 1040 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1041 /* T99W510 (sdx24), variant 2 */ 1042 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1), 1043 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1044 /* T99W510 (sdx24), variant 3 */ 1045 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2), 1046 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w510_info }, 1047 /* DW5932e-eSIM (sdx62), With eSIM */ 1048 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5), 1049 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 1050 /* DW5932e (sdx62), Non-eSIM */ 1051 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9), 1052 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5932e_info }, 1053 /* T99W640 (sdx72) */ 1054 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe118), 1055 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w640_info }, 1056 /* DW5934e(sdx72), With eSIM */ 1057 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11d), 1058 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1059 /* DW5934e(sdx72), Non-eSIM */ 1060 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe11e), 1061 .driver_data = (kernel_ulong_t) &mhi_foxconn_dw5934e_info }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe123), 1063 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w760_info }, 1064 /* MV31-W (Cinterion) */ 1065 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3), 1066 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1067 /* MV31-W (Cinterion), based on new baseline */ 1068 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4), 1069 .driver_data = (kernel_ulong_t) &mhi_mv31_info }, 1070 /* MV32-WA (Cinterion) */ 1071 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba), 1072 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1073 /* MV32-WB (Cinterion) */ 1074 { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb), 1075 .driver_data = (kernel_ulong_t) &mhi_mv32_info }, 1076 /* T99W175 (sdx55), HP variant */ 1077 { PCI_DEVICE(0x03f0, 0x0a6c), 1078 .driver_data = (kernel_ulong_t) &mhi_foxconn_t99w175_info }, 1079 /* NETPRISMA LCUR57 (SDX24) */ 1080 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1000), 1081 .driver_data = (kernel_ulong_t) &mhi_netprisma_lcur57_info }, 1082 /* NETPRISMA FCUN69 (SDX6X) */ 1083 { PCI_DEVICE(PCI_VENDOR_ID_NETPRISMA, 0x1001), 1084 .driver_data = (kernel_ulong_t) &mhi_netprisma_fcun69_info }, 1085 { } 1086 }; 1087 MODULE_DEVICE_TABLE(pci, mhi_pci_id_table); 1088 1089 enum mhi_pci_device_status { 1090 MHI_PCI_DEV_STARTED, 1091 MHI_PCI_DEV_SUSPENDED, 1092 }; 1093 1094 struct mhi_pci_device { 1095 struct mhi_controller mhi_cntrl; 1096 struct pci_saved_state *pci_state; 1097 struct work_struct recovery_work; 1098 struct timer_list health_check_timer; 1099 unsigned long status; 1100 bool reset_on_remove; 1101 }; 1102 1103 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, 1104 void __iomem *addr, u32 *out) 1105 { 1106 *out = readl(addr); 1107 return 0; 1108 } 1109 1110 static void mhi_pci_write_reg(struct mhi_controller *mhi_cntrl, 1111 void __iomem *addr, u32 val) 1112 { 1113 writel(val, addr); 1114 } 1115 1116 static void mhi_pci_status_cb(struct mhi_controller *mhi_cntrl, 1117 enum mhi_callback cb) 1118 { 1119 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1120 1121 /* Nothing to do for now */ 1122 switch (cb) { 1123 case MHI_CB_FATAL_ERROR: 1124 case MHI_CB_SYS_ERROR: 1125 dev_warn(&pdev->dev, "firmware crashed (%u)\n", cb); 1126 pm_runtime_forbid(&pdev->dev); 1127 break; 1128 case MHI_CB_EE_MISSION_MODE: 1129 pm_runtime_allow(&pdev->dev); 1130 break; 1131 default: 1132 break; 1133 } 1134 } 1135 1136 static void mhi_pci_wake_get_nop(struct mhi_controller *mhi_cntrl, bool force) 1137 { 1138 /* no-op */ 1139 } 1140 1141 static void mhi_pci_wake_put_nop(struct mhi_controller *mhi_cntrl, bool override) 1142 { 1143 /* no-op */ 1144 } 1145 1146 static void mhi_pci_wake_toggle_nop(struct mhi_controller *mhi_cntrl) 1147 { 1148 /* no-op */ 1149 } 1150 1151 static bool mhi_pci_is_alive(struct mhi_controller *mhi_cntrl) 1152 { 1153 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1154 u16 vendor = 0; 1155 1156 if (pci_read_config_word(pci_physfn(pdev), PCI_VENDOR_ID, &vendor)) 1157 return false; 1158 1159 if (vendor == (u16) ~0 || vendor == 0) 1160 return false; 1161 1162 return true; 1163 } 1164 1165 static int mhi_pci_claim(struct mhi_controller *mhi_cntrl, 1166 unsigned int bar_num, u64 dma_mask) 1167 { 1168 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1169 int err; 1170 1171 err = pcim_enable_device(pdev); 1172 if (err) { 1173 dev_err(&pdev->dev, "failed to enable pci device: %d\n", err); 1174 return err; 1175 } 1176 1177 mhi_cntrl->regs = pcim_iomap_region(pdev, bar_num, pci_name(pdev)); 1178 if (IS_ERR(mhi_cntrl->regs)) { 1179 err = PTR_ERR(mhi_cntrl->regs); 1180 dev_err(&pdev->dev, "failed to map pci region: %d\n", err); 1181 return err; 1182 } 1183 mhi_cntrl->reg_len = pci_resource_len(pdev, bar_num); 1184 1185 err = dma_set_mask_and_coherent(&pdev->dev, dma_mask); 1186 if (err) { 1187 dev_err(&pdev->dev, "Cannot set proper DMA mask\n"); 1188 return err; 1189 } 1190 1191 pci_set_master(pdev); 1192 1193 return 0; 1194 } 1195 1196 static int mhi_pci_get_irqs(struct mhi_controller *mhi_cntrl, 1197 const struct mhi_controller_config *mhi_cntrl_config) 1198 { 1199 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1200 int nr_vectors, i; 1201 int *irq; 1202 1203 /* 1204 * Alloc one MSI vector for BHI + one vector per event ring, ideally... 1205 * No explicit pci_free_irq_vectors required, done by pcim_release. 1206 */ 1207 mhi_cntrl->nr_irqs = 1 + mhi_cntrl_config->num_events; 1208 1209 nr_vectors = pci_alloc_irq_vectors(pdev, 1, roundup_pow_of_two(mhi_cntrl->nr_irqs), 1210 PCI_IRQ_MSIX | PCI_IRQ_MSI); 1211 if (nr_vectors < 0) { 1212 dev_err(&pdev->dev, "Error allocating MSI vectors %d\n", 1213 nr_vectors); 1214 return nr_vectors; 1215 } 1216 1217 if (nr_vectors < mhi_cntrl->nr_irqs) { 1218 dev_warn(&pdev->dev, "using shared MSI\n"); 1219 1220 /* Patch msi vectors, use only one (shared) */ 1221 for (i = 0; i < mhi_cntrl_config->num_events; i++) 1222 mhi_cntrl_config->event_cfg[i].irq = 0; 1223 mhi_cntrl->nr_irqs = 1; 1224 } 1225 1226 irq = devm_kcalloc(&pdev->dev, mhi_cntrl->nr_irqs, sizeof(int), GFP_KERNEL); 1227 if (!irq) 1228 return -ENOMEM; 1229 1230 for (i = 0; i < mhi_cntrl->nr_irqs; i++) { 1231 int vector = i >= nr_vectors ? (nr_vectors - 1) : i; 1232 1233 irq[i] = pci_irq_vector(pdev, vector); 1234 } 1235 1236 mhi_cntrl->irq = irq; 1237 1238 return 0; 1239 } 1240 1241 static int mhi_pci_runtime_get(struct mhi_controller *mhi_cntrl) 1242 { 1243 /* The runtime_get() MHI callback means: 1244 * Do whatever is requested to leave M3. 1245 */ 1246 return pm_runtime_get(mhi_cntrl->cntrl_dev); 1247 } 1248 1249 static void mhi_pci_runtime_put(struct mhi_controller *mhi_cntrl) 1250 { 1251 /* The runtime_put() MHI callback means: 1252 * Device can be moved in M3 state. 1253 */ 1254 pm_runtime_mark_last_busy(mhi_cntrl->cntrl_dev); 1255 pm_runtime_put(mhi_cntrl->cntrl_dev); 1256 } 1257 1258 static void mhi_pci_recovery_work(struct work_struct *work) 1259 { 1260 struct mhi_pci_device *mhi_pdev = container_of(work, struct mhi_pci_device, 1261 recovery_work); 1262 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1263 struct pci_dev *pdev = to_pci_dev(mhi_cntrl->cntrl_dev); 1264 int err; 1265 1266 dev_warn(&pdev->dev, "device recovery started\n"); 1267 1268 if (!pdev->is_virtfn) 1269 timer_delete(&mhi_pdev->health_check_timer); 1270 1271 pm_runtime_forbid(&pdev->dev); 1272 1273 /* Clean up MHI state */ 1274 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1275 mhi_power_down(mhi_cntrl, false); 1276 mhi_unprepare_after_power_down(mhi_cntrl); 1277 } 1278 1279 pci_set_power_state(pdev, PCI_D0); 1280 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1281 pci_restore_state(pdev); 1282 1283 if (!mhi_pci_is_alive(mhi_cntrl)) 1284 goto err_try_reset; 1285 1286 err = mhi_prepare_for_power_up(mhi_cntrl); 1287 if (err) 1288 goto err_try_reset; 1289 1290 err = mhi_sync_power_up(mhi_cntrl); 1291 if (err) 1292 goto err_unprepare; 1293 1294 dev_dbg(&pdev->dev, "Recovery completed\n"); 1295 1296 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1297 1298 if (!pdev->is_virtfn) 1299 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1300 1301 return; 1302 1303 err_unprepare: 1304 mhi_unprepare_after_power_down(mhi_cntrl); 1305 err_try_reset: 1306 err = pci_try_reset_function(pdev); 1307 if (err) 1308 dev_err(&pdev->dev, "Recovery failed: %d\n", err); 1309 } 1310 1311 static void health_check(struct timer_list *t) 1312 { 1313 struct mhi_pci_device *mhi_pdev = timer_container_of(mhi_pdev, t, 1314 health_check_timer); 1315 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1316 1317 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1318 test_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1319 return; 1320 1321 if (!mhi_pci_is_alive(mhi_cntrl)) { 1322 dev_err(mhi_cntrl->cntrl_dev, "Device died\n"); 1323 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1324 return; 1325 } 1326 1327 /* reschedule in two seconds */ 1328 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1329 } 1330 1331 static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl) 1332 { 1333 void __iomem *base = mhi_cntrl->regs; 1334 void __iomem *edl_db; 1335 int ret; 1336 u32 val; 1337 1338 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1339 if (ret) { 1340 dev_err(mhi_cntrl->cntrl_dev, "Failed to wakeup the device\n"); 1341 return ret; 1342 } 1343 1344 pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); 1345 mhi_cntrl->runtime_get(mhi_cntrl); 1346 1347 ret = mhi_get_channel_doorbell_offset(mhi_cntrl, &val); 1348 if (ret) 1349 goto err_get_chdb; 1350 1351 edl_db = base + val + (8 * MHI_EDL_DB); 1352 1353 mhi_cntrl->write_reg(mhi_cntrl, edl_db + 4, upper_32_bits(MHI_EDL_COOKIE)); 1354 mhi_cntrl->write_reg(mhi_cntrl, edl_db, lower_32_bits(MHI_EDL_COOKIE)); 1355 1356 mhi_soc_reset(mhi_cntrl); 1357 1358 err_get_chdb: 1359 mhi_cntrl->runtime_put(mhi_cntrl); 1360 mhi_device_put(mhi_cntrl->mhi_dev); 1361 1362 return ret; 1363 } 1364 1365 static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1366 { 1367 const struct mhi_pci_dev_info *info = (struct mhi_pci_dev_info *) id->driver_data; 1368 const struct mhi_controller_config *mhi_cntrl_config; 1369 struct mhi_pci_device *mhi_pdev; 1370 struct mhi_controller *mhi_cntrl; 1371 unsigned int dma_data_width; 1372 int err; 1373 1374 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); 1375 1376 /* mhi_pdev.mhi_cntrl must be zero-initialized */ 1377 mhi_pdev = devm_kzalloc(&pdev->dev, sizeof(*mhi_pdev), GFP_KERNEL); 1378 if (!mhi_pdev) 1379 return -ENOMEM; 1380 1381 INIT_WORK(&mhi_pdev->recovery_work, mhi_pci_recovery_work); 1382 1383 if (pdev->is_virtfn && info->vf_config) 1384 mhi_cntrl_config = info->vf_config; 1385 else 1386 mhi_cntrl_config = info->config; 1387 1388 /* Initialize health check monitor only for Physical functions */ 1389 if (!pdev->is_virtfn) 1390 timer_setup(&mhi_pdev->health_check_timer, health_check, 0); 1391 1392 mhi_cntrl = &mhi_pdev->mhi_cntrl; 1393 1394 dma_data_width = (pdev->is_virtfn && info->vf_dma_data_width) ? 1395 info->vf_dma_data_width : info->dma_data_width; 1396 1397 mhi_cntrl->cntrl_dev = &pdev->dev; 1398 mhi_cntrl->iova_start = 0; 1399 mhi_cntrl->iova_stop = (dma_addr_t)DMA_BIT_MASK(dma_data_width); 1400 mhi_cntrl->fw_image = info->fw; 1401 mhi_cntrl->edl_image = info->edl; 1402 mhi_cntrl->no_m3 = info->no_m3; 1403 1404 mhi_cntrl->read_reg = mhi_pci_read_reg; 1405 mhi_cntrl->write_reg = mhi_pci_write_reg; 1406 mhi_cntrl->status_cb = mhi_pci_status_cb; 1407 mhi_cntrl->runtime_get = mhi_pci_runtime_get; 1408 mhi_cntrl->runtime_put = mhi_pci_runtime_put; 1409 mhi_cntrl->mru = info->mru_default; 1410 mhi_cntrl->name = info->name; 1411 1412 if (!pdev->is_virtfn) 1413 mhi_pdev->reset_on_remove = info->reset_on_remove; 1414 1415 if (info->edl_trigger) 1416 mhi_cntrl->edl_trigger = mhi_pci_generic_edl_trigger; 1417 1418 if (info->sideband_wake) { 1419 mhi_cntrl->wake_get = mhi_pci_wake_get_nop; 1420 mhi_cntrl->wake_put = mhi_pci_wake_put_nop; 1421 mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop; 1422 } 1423 1424 err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_width)); 1425 if (err) 1426 return err; 1427 1428 err = mhi_pci_get_irqs(mhi_cntrl, mhi_cntrl_config); 1429 if (err) 1430 return err; 1431 1432 pci_set_drvdata(pdev, mhi_pdev); 1433 1434 /* Have stored pci confspace at hand for restore in sudden PCI error. 1435 * cache the state locally and discard the PCI core one. 1436 */ 1437 pci_save_state(pdev); 1438 mhi_pdev->pci_state = pci_store_saved_state(pdev); 1439 pci_load_saved_state(pdev, NULL); 1440 1441 err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config); 1442 if (err) 1443 return err; 1444 1445 /* MHI bus does not power up the controller by default */ 1446 err = mhi_prepare_for_power_up(mhi_cntrl); 1447 if (err) { 1448 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1449 goto err_unregister; 1450 } 1451 1452 err = mhi_async_power_up(mhi_cntrl); 1453 if (err) { 1454 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1455 goto err_unprepare; 1456 } 1457 1458 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1459 1460 /* start health check */ 1461 if (!pdev->is_virtfn) 1462 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1463 1464 /* Allow runtime suspend only if both PME from D3Hot and M3 are supported */ 1465 if (pci_pme_capable(pdev, PCI_D3hot) && !(info->no_m3)) { 1466 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000); 1467 pm_runtime_use_autosuspend(&pdev->dev); 1468 pm_runtime_mark_last_busy(&pdev->dev); 1469 pm_runtime_put_noidle(&pdev->dev); 1470 } 1471 1472 return 0; 1473 1474 err_unprepare: 1475 mhi_unprepare_after_power_down(mhi_cntrl); 1476 err_unregister: 1477 mhi_unregister_controller(mhi_cntrl); 1478 1479 return err; 1480 } 1481 1482 static void mhi_pci_remove(struct pci_dev *pdev) 1483 { 1484 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1485 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1486 1487 pm_runtime_forbid(&pdev->dev); 1488 pci_disable_sriov(pdev); 1489 1490 if (!pdev->is_virtfn) 1491 timer_delete_sync(&mhi_pdev->health_check_timer); 1492 cancel_work_sync(&mhi_pdev->recovery_work); 1493 1494 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1495 mhi_power_down(mhi_cntrl, true); 1496 mhi_unprepare_after_power_down(mhi_cntrl); 1497 } 1498 1499 /* balancing probe put_noidle */ 1500 if (pci_pme_capable(pdev, PCI_D3hot)) 1501 pm_runtime_get_noresume(&pdev->dev); 1502 1503 if (mhi_pdev->reset_on_remove) 1504 mhi_soc_reset(mhi_cntrl); 1505 1506 mhi_unregister_controller(mhi_cntrl); 1507 } 1508 1509 static void mhi_pci_shutdown(struct pci_dev *pdev) 1510 { 1511 mhi_pci_remove(pdev); 1512 pci_set_power_state(pdev, PCI_D3hot); 1513 } 1514 1515 static void mhi_pci_reset_prepare(struct pci_dev *pdev) 1516 { 1517 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1518 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1519 1520 dev_info(&pdev->dev, "reset\n"); 1521 1522 if (!pdev->is_virtfn) 1523 timer_delete(&mhi_pdev->health_check_timer); 1524 1525 /* Clean up MHI state */ 1526 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1527 mhi_power_down(mhi_cntrl, false); 1528 mhi_unprepare_after_power_down(mhi_cntrl); 1529 } 1530 1531 /* cause internal device reset */ 1532 mhi_soc_reset(mhi_cntrl); 1533 1534 /* Be sure device reset has been executed */ 1535 msleep(MHI_POST_RESET_DELAY_MS); 1536 } 1537 1538 static void mhi_pci_reset_done(struct pci_dev *pdev) 1539 { 1540 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1541 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1542 int err; 1543 1544 /* Restore initial known working PCI state */ 1545 pci_load_saved_state(pdev, mhi_pdev->pci_state); 1546 pci_restore_state(pdev); 1547 1548 /* Is device status available ? */ 1549 if (!mhi_pci_is_alive(mhi_cntrl)) { 1550 dev_err(&pdev->dev, "reset failed\n"); 1551 return; 1552 } 1553 1554 err = mhi_prepare_for_power_up(mhi_cntrl); 1555 if (err) { 1556 dev_err(&pdev->dev, "failed to prepare MHI controller\n"); 1557 return; 1558 } 1559 1560 err = mhi_sync_power_up(mhi_cntrl); 1561 if (err) { 1562 dev_err(&pdev->dev, "failed to power up MHI controller\n"); 1563 mhi_unprepare_after_power_down(mhi_cntrl); 1564 return; 1565 } 1566 1567 set_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status); 1568 if (!pdev->is_virtfn) 1569 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1570 } 1571 1572 static pci_ers_result_t mhi_pci_error_detected(struct pci_dev *pdev, 1573 pci_channel_state_t state) 1574 { 1575 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1576 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1577 1578 dev_err(&pdev->dev, "PCI error detected, state = %u\n", state); 1579 1580 if (state == pci_channel_io_perm_failure) 1581 return PCI_ERS_RESULT_DISCONNECT; 1582 1583 /* Clean up MHI state */ 1584 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1585 mhi_power_down(mhi_cntrl, false); 1586 mhi_unprepare_after_power_down(mhi_cntrl); 1587 } else { 1588 /* Nothing to do */ 1589 return PCI_ERS_RESULT_RECOVERED; 1590 } 1591 1592 pci_disable_device(pdev); 1593 1594 return PCI_ERS_RESULT_NEED_RESET; 1595 } 1596 1597 static pci_ers_result_t mhi_pci_slot_reset(struct pci_dev *pdev) 1598 { 1599 if (pci_enable_device(pdev)) { 1600 dev_err(&pdev->dev, "Cannot re-enable PCI device after reset.\n"); 1601 return PCI_ERS_RESULT_DISCONNECT; 1602 } 1603 1604 return PCI_ERS_RESULT_RECOVERED; 1605 } 1606 1607 static void mhi_pci_io_resume(struct pci_dev *pdev) 1608 { 1609 struct mhi_pci_device *mhi_pdev = pci_get_drvdata(pdev); 1610 1611 dev_err(&pdev->dev, "PCI slot reset done\n"); 1612 1613 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1614 } 1615 1616 static const struct pci_error_handlers mhi_pci_err_handler = { 1617 .error_detected = mhi_pci_error_detected, 1618 .slot_reset = mhi_pci_slot_reset, 1619 .resume = mhi_pci_io_resume, 1620 .reset_prepare = mhi_pci_reset_prepare, 1621 .reset_done = mhi_pci_reset_done, 1622 }; 1623 1624 static int __maybe_unused mhi_pci_runtime_suspend(struct device *dev) 1625 { 1626 struct pci_dev *pdev = to_pci_dev(dev); 1627 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1628 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1629 int err; 1630 1631 if (test_and_set_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1632 return 0; 1633 1634 if (!pdev->is_virtfn) 1635 timer_delete(&mhi_pdev->health_check_timer); 1636 1637 cancel_work_sync(&mhi_pdev->recovery_work); 1638 1639 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1640 mhi_cntrl->ee != MHI_EE_AMSS) 1641 goto pci_suspend; /* Nothing to do at MHI level */ 1642 1643 /* Transition to M3 state */ 1644 err = mhi_pm_suspend(mhi_cntrl); 1645 if (err) { 1646 dev_err(&pdev->dev, "failed to suspend device: %d\n", err); 1647 clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status); 1648 return -EBUSY; 1649 } 1650 1651 pci_suspend: 1652 pci_disable_device(pdev); 1653 pci_wake_from_d3(pdev, true); 1654 1655 return 0; 1656 } 1657 1658 static int __maybe_unused mhi_pci_runtime_resume(struct device *dev) 1659 { 1660 struct pci_dev *pdev = to_pci_dev(dev); 1661 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1662 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1663 int err; 1664 1665 if (!test_and_clear_bit(MHI_PCI_DEV_SUSPENDED, &mhi_pdev->status)) 1666 return 0; 1667 1668 err = pci_enable_device(pdev); 1669 if (err) 1670 goto err_recovery; 1671 1672 pci_set_master(pdev); 1673 pci_wake_from_d3(pdev, false); 1674 1675 if (!test_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status) || 1676 mhi_cntrl->ee != MHI_EE_AMSS) 1677 return 0; /* Nothing to do at MHI level */ 1678 1679 /* Exit M3, transition to M0 state */ 1680 err = mhi_pm_resume(mhi_cntrl); 1681 if (err) { 1682 dev_err(&pdev->dev, "failed to resume device: %d\n", err); 1683 goto err_recovery; 1684 } 1685 1686 /* Resume health check */ 1687 if (!pdev->is_virtfn) 1688 mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD); 1689 1690 /* It can be a remote wakeup (no mhi runtime_get), update access time */ 1691 pm_runtime_mark_last_busy(dev); 1692 1693 return 0; 1694 1695 err_recovery: 1696 /* Do not fail to not mess up our PCI device state, the device likely 1697 * lost power (d3cold) and we simply need to reset it from the recovery 1698 * procedure, trigger the recovery asynchronously to prevent system 1699 * suspend exit delaying. 1700 */ 1701 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1702 pm_runtime_mark_last_busy(dev); 1703 1704 return 0; 1705 } 1706 1707 static int __maybe_unused mhi_pci_suspend(struct device *dev) 1708 { 1709 pm_runtime_disable(dev); 1710 return mhi_pci_runtime_suspend(dev); 1711 } 1712 1713 static int __maybe_unused mhi_pci_resume(struct device *dev) 1714 { 1715 int ret; 1716 1717 /* Depending the platform, device may have lost power (d3cold), we need 1718 * to resume it now to check its state and recover when necessary. 1719 */ 1720 ret = mhi_pci_runtime_resume(dev); 1721 pm_runtime_enable(dev); 1722 1723 return ret; 1724 } 1725 1726 static int __maybe_unused mhi_pci_freeze(struct device *dev) 1727 { 1728 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1729 struct mhi_controller *mhi_cntrl = &mhi_pdev->mhi_cntrl; 1730 1731 /* We want to stop all operations, hibernation does not guarantee that 1732 * device will be in the same state as before freezing, especially if 1733 * the intermediate restore kernel reinitializes MHI device with new 1734 * context. 1735 */ 1736 flush_work(&mhi_pdev->recovery_work); 1737 if (test_and_clear_bit(MHI_PCI_DEV_STARTED, &mhi_pdev->status)) { 1738 mhi_power_down(mhi_cntrl, true); 1739 mhi_unprepare_after_power_down(mhi_cntrl); 1740 } 1741 1742 return 0; 1743 } 1744 1745 static int __maybe_unused mhi_pci_restore(struct device *dev) 1746 { 1747 struct mhi_pci_device *mhi_pdev = dev_get_drvdata(dev); 1748 1749 /* Reinitialize the device */ 1750 queue_work(system_long_wq, &mhi_pdev->recovery_work); 1751 1752 return 0; 1753 } 1754 1755 static const struct dev_pm_ops mhi_pci_pm_ops = { 1756 SET_RUNTIME_PM_OPS(mhi_pci_runtime_suspend, mhi_pci_runtime_resume, NULL) 1757 #ifdef CONFIG_PM_SLEEP 1758 .suspend = mhi_pci_suspend, 1759 .resume = mhi_pci_resume, 1760 .freeze = mhi_pci_freeze, 1761 .thaw = mhi_pci_restore, 1762 .poweroff = mhi_pci_freeze, 1763 .restore = mhi_pci_restore, 1764 #endif 1765 }; 1766 1767 static struct pci_driver mhi_pci_driver = { 1768 .name = "mhi-pci-generic", 1769 .id_table = mhi_pci_id_table, 1770 .probe = mhi_pci_probe, 1771 .remove = mhi_pci_remove, 1772 .shutdown = mhi_pci_shutdown, 1773 .err_handler = &mhi_pci_err_handler, 1774 .driver.pm = &mhi_pci_pm_ops, 1775 .sriov_configure = pci_sriov_configure_simple, 1776 }; 1777 module_pci_driver(mhi_pci_driver); 1778 1779 MODULE_AUTHOR("Loic Poulain <loic.poulain@linaro.org>"); 1780 MODULE_DESCRIPTION("Modem Host Interface (MHI) PCI controller driver"); 1781 MODULE_LICENSE("GPL"); 1782