1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/dma-direction.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/list.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/skbuff.h> 16 #include <linux/slab.h> 17 #include "internal.h" 18 #include "trace.h" 19 20 int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, 21 void __iomem *base, u32 offset, u32 *out) 22 { 23 return mhi_cntrl->read_reg(mhi_cntrl, base + offset, out); 24 } 25 26 int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, 27 void __iomem *base, u32 offset, 28 u32 mask, u32 *out) 29 { 30 u32 tmp; 31 int ret; 32 33 ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); 34 if (ret) 35 return ret; 36 37 *out = (tmp & mask) >> __ffs(mask); 38 39 return 0; 40 } 41 42 int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl, 43 void __iomem *base, u32 offset, 44 u32 mask, u32 val, u32 delayus, 45 u32 timeout_ms) 46 { 47 int ret; 48 u32 out, retry = (timeout_ms * 1000) / delayus; 49 50 while (retry--) { 51 ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out); 52 if (ret) 53 return ret; 54 55 if (out == val) 56 return 0; 57 58 fsleep(delayus); 59 } 60 61 return -ETIMEDOUT; 62 } 63 64 void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, 65 u32 offset, u32 val) 66 { 67 mhi_cntrl->write_reg(mhi_cntrl, base + offset, val); 68 } 69 70 int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl, 71 void __iomem *base, u32 offset, u32 mask, 72 u32 val) 73 { 74 int ret; 75 u32 tmp; 76 77 ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); 78 if (ret) 79 return ret; 80 81 tmp &= ~mask; 82 tmp |= (val << __ffs(mask)); 83 mhi_write_reg(mhi_cntrl, base, offset, tmp); 84 85 return 0; 86 } 87 88 void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, 89 dma_addr_t db_val) 90 { 91 mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(db_val)); 92 mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(db_val)); 93 } 94 95 void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, 96 struct db_cfg *db_cfg, 97 void __iomem *db_addr, 98 dma_addr_t db_val) 99 { 100 if (db_cfg->db_mode) { 101 db_cfg->db_val = db_val; 102 mhi_write_db(mhi_cntrl, db_addr, db_val); 103 db_cfg->db_mode = 0; 104 } 105 } 106 107 void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, 108 struct db_cfg *db_cfg, 109 void __iomem *db_addr, 110 dma_addr_t db_val) 111 { 112 db_cfg->db_val = db_val; 113 mhi_write_db(mhi_cntrl, db_addr, db_val); 114 } 115 116 void mhi_ring_er_db(struct mhi_event *mhi_event) 117 { 118 struct mhi_ring *ring = &mhi_event->ring; 119 120 mhi_event->db_cfg.process_db(mhi_event->mhi_cntrl, &mhi_event->db_cfg, 121 ring->db_addr, le64_to_cpu(*ring->ctxt_wp)); 122 } 123 124 void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd) 125 { 126 dma_addr_t db; 127 struct mhi_ring *ring = &mhi_cmd->ring; 128 129 db = ring->iommu_base + (ring->wp - ring->base); 130 *ring->ctxt_wp = cpu_to_le64(db); 131 mhi_write_db(mhi_cntrl, ring->db_addr, db); 132 } 133 134 void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, 135 struct mhi_chan *mhi_chan) 136 { 137 struct mhi_ring *ring = &mhi_chan->tre_ring; 138 dma_addr_t db; 139 140 db = ring->iommu_base + (ring->wp - ring->base); 141 142 /* 143 * Writes to the new ring element must be visible to the hardware 144 * before letting h/w know there is new element to fetch. 145 */ 146 dma_wmb(); 147 *ring->ctxt_wp = cpu_to_le64(db); 148 149 mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg, 150 ring->db_addr, db); 151 } 152 153 enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl) 154 { 155 u32 exec; 156 int ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_EXECENV, &exec); 157 158 return (ret) ? MHI_EE_MAX : exec; 159 } 160 EXPORT_SYMBOL_GPL(mhi_get_exec_env); 161 162 enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) 163 { 164 u32 state; 165 int ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS, 166 MHISTATUS_MHISTATE_MASK, &state); 167 return ret ? MHI_STATE_MAX : state; 168 } 169 EXPORT_SYMBOL_GPL(mhi_get_mhi_state); 170 171 void mhi_soc_reset(struct mhi_controller *mhi_cntrl) 172 { 173 if (mhi_cntrl->reset) { 174 mhi_cntrl->reset(mhi_cntrl); 175 return; 176 } 177 178 /* Generic MHI SoC reset */ 179 mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, 180 MHI_SOC_RESET_REQ); 181 } 182 EXPORT_SYMBOL_GPL(mhi_soc_reset); 183 184 int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, 185 struct mhi_buf_info *buf_info) 186 { 187 buf_info->p_addr = dma_map_single(mhi_cntrl->cntrl_dev, 188 buf_info->v_addr, buf_info->len, 189 buf_info->dir); 190 if (dma_mapping_error(mhi_cntrl->cntrl_dev, buf_info->p_addr)) 191 return -ENOMEM; 192 193 return 0; 194 } 195 196 int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, 197 struct mhi_buf_info *buf_info) 198 { 199 void *buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, buf_info->len, 200 &buf_info->p_addr, GFP_ATOMIC); 201 202 if (!buf) 203 return -ENOMEM; 204 205 if (buf_info->dir == DMA_TO_DEVICE) 206 memcpy(buf, buf_info->v_addr, buf_info->len); 207 208 buf_info->bb_addr = buf; 209 210 return 0; 211 } 212 213 void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, 214 struct mhi_buf_info *buf_info) 215 { 216 dma_unmap_single(mhi_cntrl->cntrl_dev, buf_info->p_addr, buf_info->len, 217 buf_info->dir); 218 } 219 220 void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, 221 struct mhi_buf_info *buf_info) 222 { 223 if (buf_info->dir == DMA_FROM_DEVICE) 224 memcpy(buf_info->v_addr, buf_info->bb_addr, buf_info->len); 225 226 dma_free_coherent(mhi_cntrl->cntrl_dev, buf_info->len, 227 buf_info->bb_addr, buf_info->p_addr); 228 } 229 230 static int get_nr_avail_ring_elements(struct mhi_controller *mhi_cntrl, 231 struct mhi_ring *ring) 232 { 233 int nr_el; 234 235 if (ring->wp < ring->rp) { 236 nr_el = ((ring->rp - ring->wp) / ring->el_size) - 1; 237 } else { 238 nr_el = (ring->rp - ring->base) / ring->el_size; 239 nr_el += ((ring->base + ring->len - ring->wp) / 240 ring->el_size) - 1; 241 } 242 243 return nr_el; 244 } 245 246 static void *mhi_to_virtual(struct mhi_ring *ring, dma_addr_t addr) 247 { 248 return (addr - ring->iommu_base) + ring->base; 249 } 250 251 static void mhi_add_ring_element(struct mhi_controller *mhi_cntrl, 252 struct mhi_ring *ring) 253 { 254 ring->wp += ring->el_size; 255 if (ring->wp >= (ring->base + ring->len)) 256 ring->wp = ring->base; 257 /* smp update */ 258 smp_wmb(); 259 } 260 261 static void mhi_del_ring_element(struct mhi_controller *mhi_cntrl, 262 struct mhi_ring *ring) 263 { 264 ring->rp += ring->el_size; 265 if (ring->rp >= (ring->base + ring->len)) 266 ring->rp = ring->base; 267 /* smp update */ 268 smp_wmb(); 269 } 270 271 static bool is_valid_ring_ptr(struct mhi_ring *ring, dma_addr_t addr) 272 { 273 return addr >= ring->iommu_base && addr < ring->iommu_base + ring->len && 274 !(addr & (sizeof(struct mhi_ring_element) - 1)); 275 } 276 277 int mhi_destroy_device(struct device *dev, void *data) 278 { 279 struct mhi_chan *ul_chan, *dl_chan; 280 struct mhi_device *mhi_dev; 281 struct mhi_controller *mhi_cntrl; 282 enum mhi_ee_type ee = MHI_EE_MAX; 283 284 if (dev->bus != &mhi_bus_type) 285 return 0; 286 287 mhi_dev = to_mhi_device(dev); 288 mhi_cntrl = mhi_dev->mhi_cntrl; 289 290 /* Only destroy virtual devices thats attached to bus */ 291 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) 292 return 0; 293 294 ul_chan = mhi_dev->ul_chan; 295 dl_chan = mhi_dev->dl_chan; 296 297 /* 298 * If execution environment is specified, remove only those devices that 299 * started in them based on ee_mask for the channels as we move on to a 300 * different execution environment 301 */ 302 if (data) 303 ee = *(enum mhi_ee_type *)data; 304 305 /* 306 * For the suspend and resume case, this function will get called 307 * without mhi_unregister_controller(). Hence, we need to drop the 308 * references to mhi_dev created for ul and dl channels. We can 309 * be sure that there will be no instances of mhi_dev left after 310 * this. 311 */ 312 if (ul_chan) { 313 if (ee != MHI_EE_MAX && !(ul_chan->ee_mask & BIT(ee))) 314 return 0; 315 316 put_device(&ul_chan->mhi_dev->dev); 317 } 318 319 if (dl_chan) { 320 if (ee != MHI_EE_MAX && !(dl_chan->ee_mask & BIT(ee))) 321 return 0; 322 323 put_device(&dl_chan->mhi_dev->dev); 324 } 325 326 dev_dbg(&mhi_cntrl->mhi_dev->dev, "destroy device for chan:%s\n", 327 mhi_dev->name); 328 329 /* Notify the client and remove the device from MHI bus */ 330 device_del(dev); 331 put_device(dev); 332 333 return 0; 334 } 335 336 int mhi_get_free_desc_count(struct mhi_device *mhi_dev, 337 enum dma_data_direction dir) 338 { 339 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 340 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? 341 mhi_dev->ul_chan : mhi_dev->dl_chan; 342 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 343 344 return get_nr_avail_ring_elements(mhi_cntrl, tre_ring); 345 } 346 EXPORT_SYMBOL_GPL(mhi_get_free_desc_count); 347 348 void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) 349 { 350 struct mhi_driver *mhi_drv; 351 352 if (!mhi_dev->dev.driver) 353 return; 354 355 mhi_drv = to_mhi_driver(mhi_dev->dev.driver); 356 357 if (mhi_drv->status_cb) 358 mhi_drv->status_cb(mhi_dev, cb_reason); 359 } 360 EXPORT_SYMBOL_GPL(mhi_notify); 361 362 /* Bind MHI channels to MHI devices */ 363 void mhi_create_devices(struct mhi_controller *mhi_cntrl) 364 { 365 struct mhi_chan *mhi_chan; 366 struct mhi_device *mhi_dev; 367 struct device *dev = &mhi_cntrl->mhi_dev->dev; 368 int i, ret; 369 370 mhi_chan = mhi_cntrl->mhi_chan; 371 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 372 if (!mhi_chan->configured || mhi_chan->mhi_dev || 373 !(mhi_chan->ee_mask & BIT(mhi_cntrl->ee))) 374 continue; 375 mhi_dev = mhi_alloc_device(mhi_cntrl); 376 if (IS_ERR(mhi_dev)) 377 return; 378 379 mhi_dev->dev_type = MHI_DEVICE_XFER; 380 switch (mhi_chan->dir) { 381 case DMA_TO_DEVICE: 382 mhi_dev->ul_chan = mhi_chan; 383 mhi_dev->ul_chan_id = mhi_chan->chan; 384 break; 385 case DMA_FROM_DEVICE: 386 /* We use dl_chan as offload channels */ 387 mhi_dev->dl_chan = mhi_chan; 388 mhi_dev->dl_chan_id = mhi_chan->chan; 389 break; 390 default: 391 dev_err(dev, "Direction not supported\n"); 392 put_device(&mhi_dev->dev); 393 return; 394 } 395 396 get_device(&mhi_dev->dev); 397 mhi_chan->mhi_dev = mhi_dev; 398 399 /* Check next channel if it matches */ 400 if ((i + 1) < mhi_cntrl->max_chan && mhi_chan[1].configured) { 401 if (!strcmp(mhi_chan[1].name, mhi_chan->name)) { 402 i++; 403 mhi_chan++; 404 if (mhi_chan->dir == DMA_TO_DEVICE) { 405 mhi_dev->ul_chan = mhi_chan; 406 mhi_dev->ul_chan_id = mhi_chan->chan; 407 } else { 408 mhi_dev->dl_chan = mhi_chan; 409 mhi_dev->dl_chan_id = mhi_chan->chan; 410 } 411 get_device(&mhi_dev->dev); 412 mhi_chan->mhi_dev = mhi_dev; 413 } 414 } 415 416 /* Channel name is same for both UL and DL */ 417 mhi_dev->name = mhi_chan->name; 418 dev_set_name(&mhi_dev->dev, "%s_%s", 419 dev_name(&mhi_cntrl->mhi_dev->dev), 420 mhi_dev->name); 421 422 /* Init wakeup source if available */ 423 if (mhi_dev->dl_chan && mhi_dev->dl_chan->wake_capable) 424 device_init_wakeup(&mhi_dev->dev, true); 425 426 ret = device_add(&mhi_dev->dev); 427 if (ret) 428 put_device(&mhi_dev->dev); 429 } 430 } 431 432 irqreturn_t mhi_irq_handler(int irq_number, void *dev) 433 { 434 struct mhi_event *mhi_event = dev; 435 struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; 436 struct mhi_event_ctxt *er_ctxt; 437 struct mhi_ring *ev_ring = &mhi_event->ring; 438 dma_addr_t ptr; 439 void *dev_rp; 440 441 /* 442 * If CONFIG_DEBUG_SHIRQ is set, the IRQ handler will get invoked during __free_irq() 443 * and by that time mhi_ctxt() would've freed. So check for the existence of mhi_ctxt 444 * before handling the IRQs. 445 */ 446 if (!mhi_cntrl->mhi_ctxt) { 447 dev_dbg(&mhi_cntrl->mhi_dev->dev, 448 "mhi_ctxt has been freed\n"); 449 return IRQ_HANDLED; 450 } 451 452 er_ctxt = &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; 453 ptr = le64_to_cpu(er_ctxt->rp); 454 455 if (!is_valid_ring_ptr(ev_ring, ptr)) { 456 dev_err(&mhi_cntrl->mhi_dev->dev, 457 "Event ring rp points outside of the event ring\n"); 458 return IRQ_HANDLED; 459 } 460 461 dev_rp = mhi_to_virtual(ev_ring, ptr); 462 463 /* Only proceed if event ring has pending events */ 464 if (ev_ring->rp == dev_rp) 465 return IRQ_HANDLED; 466 467 /* For client managed event ring, notify pending data */ 468 if (mhi_event->cl_manage) { 469 struct mhi_chan *mhi_chan = mhi_event->mhi_chan; 470 struct mhi_device *mhi_dev = mhi_chan->mhi_dev; 471 472 if (mhi_dev) 473 mhi_notify(mhi_dev, MHI_CB_PENDING_DATA); 474 } else { 475 tasklet_schedule(&mhi_event->task); 476 } 477 478 return IRQ_HANDLED; 479 } 480 481 irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv) 482 { 483 struct mhi_controller *mhi_cntrl = priv; 484 struct device *dev = &mhi_cntrl->mhi_dev->dev; 485 enum mhi_state state; 486 enum mhi_pm_state pm_state = 0; 487 enum mhi_ee_type ee; 488 489 write_lock_irq(&mhi_cntrl->pm_lock); 490 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { 491 write_unlock_irq(&mhi_cntrl->pm_lock); 492 goto exit_intvec; 493 } 494 495 state = mhi_get_mhi_state(mhi_cntrl); 496 ee = mhi_get_exec_env(mhi_cntrl); 497 498 trace_mhi_intvec_states(mhi_cntrl, ee, state); 499 if (state == MHI_STATE_SYS_ERR) { 500 dev_dbg(dev, "System error detected\n"); 501 pm_state = mhi_tryset_pm_state(mhi_cntrl, 502 MHI_PM_SYS_ERR_DETECT); 503 } 504 write_unlock_irq(&mhi_cntrl->pm_lock); 505 506 if (pm_state != MHI_PM_SYS_ERR_DETECT) 507 goto exit_intvec; 508 509 switch (ee) { 510 case MHI_EE_RDDM: 511 /* proceed if power down is not already in progress */ 512 if (mhi_cntrl->rddm_image && mhi_is_active(mhi_cntrl)) { 513 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); 514 mhi_cntrl->ee = ee; 515 wake_up_all(&mhi_cntrl->state_event); 516 } 517 break; 518 case MHI_EE_PBL: 519 case MHI_EE_EDL: 520 case MHI_EE_PTHRU: 521 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_FATAL_ERROR); 522 mhi_cntrl->ee = ee; 523 wake_up_all(&mhi_cntrl->state_event); 524 mhi_pm_sys_err_handler(mhi_cntrl); 525 break; 526 default: 527 wake_up_all(&mhi_cntrl->state_event); 528 mhi_pm_sys_err_handler(mhi_cntrl); 529 break; 530 } 531 532 exit_intvec: 533 534 return IRQ_HANDLED; 535 } 536 537 irqreturn_t mhi_intvec_handler(int irq_number, void *dev) 538 { 539 struct mhi_controller *mhi_cntrl = dev; 540 541 /* Wake up events waiting for state change */ 542 wake_up_all(&mhi_cntrl->state_event); 543 544 return IRQ_WAKE_THREAD; 545 } 546 547 static void mhi_recycle_ev_ring_element(struct mhi_controller *mhi_cntrl, 548 struct mhi_ring *ring) 549 { 550 /* Update the WP */ 551 ring->wp += ring->el_size; 552 553 if (ring->wp >= (ring->base + ring->len)) 554 ring->wp = ring->base; 555 556 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + (ring->wp - ring->base)); 557 558 /* Update the RP */ 559 ring->rp += ring->el_size; 560 if (ring->rp >= (ring->base + ring->len)) 561 ring->rp = ring->base; 562 563 /* Update to all cores */ 564 smp_wmb(); 565 } 566 567 static int parse_xfer_event(struct mhi_controller *mhi_cntrl, 568 struct mhi_ring_element *event, 569 struct mhi_chan *mhi_chan) 570 { 571 struct mhi_ring *buf_ring, *tre_ring; 572 struct device *dev = &mhi_cntrl->mhi_dev->dev; 573 struct mhi_result result; 574 unsigned long flags = 0; 575 u32 ev_code; 576 577 ev_code = MHI_TRE_GET_EV_CODE(event); 578 buf_ring = &mhi_chan->buf_ring; 579 tre_ring = &mhi_chan->tre_ring; 580 581 result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? 582 -EOVERFLOW : 0; 583 584 /* 585 * If it's a DB Event then we need to grab the lock 586 * with preemption disabled and as a write because we 587 * have to update db register and there are chances that 588 * another thread could be doing the same. 589 */ 590 if (ev_code >= MHI_EV_CC_OOB) 591 write_lock_irqsave(&mhi_chan->lock, flags); 592 else 593 read_lock_bh(&mhi_chan->lock); 594 595 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) 596 goto end_process_tx_event; 597 598 switch (ev_code) { 599 case MHI_EV_CC_OVERFLOW: 600 case MHI_EV_CC_EOB: 601 case MHI_EV_CC_EOT: 602 { 603 dma_addr_t ptr = MHI_TRE_GET_EV_PTR(event); 604 struct mhi_ring_element *local_rp, *ev_tre; 605 void *dev_rp, *next_rp; 606 struct mhi_buf_info *buf_info; 607 u16 xfer_len; 608 609 if (!is_valid_ring_ptr(tre_ring, ptr)) { 610 dev_err(&mhi_cntrl->mhi_dev->dev, 611 "Event element points outside of the tre ring\n"); 612 break; 613 } 614 /* Get the TRB this event points to */ 615 ev_tre = mhi_to_virtual(tre_ring, ptr); 616 617 dev_rp = ev_tre + 1; 618 if (dev_rp >= (tre_ring->base + tre_ring->len)) 619 dev_rp = tre_ring->base; 620 621 result.dir = mhi_chan->dir; 622 623 local_rp = tre_ring->rp; 624 625 next_rp = local_rp + 1; 626 if (next_rp >= tre_ring->base + tre_ring->len) 627 next_rp = tre_ring->base; 628 if (dev_rp != next_rp && !MHI_TRE_DATA_GET_CHAIN(local_rp)) { 629 dev_err(&mhi_cntrl->mhi_dev->dev, 630 "Event element points to an unexpected TRE\n"); 631 break; 632 } 633 634 while (local_rp != dev_rp) { 635 buf_info = buf_ring->rp; 636 /* If it's the last TRE, get length from the event */ 637 if (local_rp == ev_tre) 638 xfer_len = MHI_TRE_GET_EV_LEN(event); 639 else 640 xfer_len = buf_info->len; 641 642 /* Unmap if it's not pre-mapped by client */ 643 if (likely(!buf_info->pre_mapped)) 644 mhi_cntrl->unmap_single(mhi_cntrl, buf_info); 645 646 result.buf_addr = buf_info->cb_buf; 647 648 /* truncate to buf len if xfer_len is larger */ 649 result.bytes_xferd = 650 min_t(u16, xfer_len, buf_info->len); 651 mhi_del_ring_element(mhi_cntrl, buf_ring); 652 mhi_del_ring_element(mhi_cntrl, tre_ring); 653 local_rp = tre_ring->rp; 654 655 read_unlock_bh(&mhi_chan->lock); 656 657 /* notify client */ 658 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); 659 660 if (mhi_chan->dir == DMA_TO_DEVICE) { 661 atomic_dec(&mhi_cntrl->pending_pkts); 662 /* Release the reference got from mhi_queue() */ 663 mhi_cntrl->runtime_put(mhi_cntrl); 664 } 665 666 /* 667 * Recycle the buffer if buffer is pre-allocated, 668 * if there is an error, not much we can do apart 669 * from dropping the packet 670 */ 671 if (mhi_chan->pre_alloc) { 672 if (mhi_queue_buf(mhi_chan->mhi_dev, 673 mhi_chan->dir, 674 buf_info->cb_buf, 675 buf_info->len, MHI_EOT)) { 676 dev_err(dev, 677 "Error recycling buffer for chan:%d\n", 678 mhi_chan->chan); 679 kfree(buf_info->cb_buf); 680 } 681 } 682 683 read_lock_bh(&mhi_chan->lock); 684 } 685 break; 686 } /* CC_EOT */ 687 case MHI_EV_CC_OOB: 688 case MHI_EV_CC_DB_MODE: 689 { 690 unsigned long pm_lock_flags; 691 692 mhi_chan->db_cfg.db_mode = 1; 693 read_lock_irqsave(&mhi_cntrl->pm_lock, pm_lock_flags); 694 if (tre_ring->wp != tre_ring->rp && 695 MHI_DB_ACCESS_VALID(mhi_cntrl)) { 696 mhi_ring_chan_db(mhi_cntrl, mhi_chan); 697 } 698 read_unlock_irqrestore(&mhi_cntrl->pm_lock, pm_lock_flags); 699 break; 700 } 701 case MHI_EV_CC_BAD_TRE: 702 default: 703 dev_err(dev, "Unknown event 0x%x\n", ev_code); 704 break; 705 } /* switch(MHI_EV_READ_CODE(EV_TRB_CODE,event)) */ 706 707 end_process_tx_event: 708 if (ev_code >= MHI_EV_CC_OOB) 709 write_unlock_irqrestore(&mhi_chan->lock, flags); 710 else 711 read_unlock_bh(&mhi_chan->lock); 712 713 return 0; 714 } 715 716 static int parse_rsc_event(struct mhi_controller *mhi_cntrl, 717 struct mhi_ring_element *event, 718 struct mhi_chan *mhi_chan) 719 { 720 struct mhi_ring *buf_ring, *tre_ring; 721 struct mhi_buf_info *buf_info; 722 struct mhi_result result; 723 int ev_code; 724 u32 cookie; /* offset to local descriptor */ 725 u16 xfer_len; 726 727 buf_ring = &mhi_chan->buf_ring; 728 tre_ring = &mhi_chan->tre_ring; 729 730 ev_code = MHI_TRE_GET_EV_CODE(event); 731 cookie = MHI_TRE_GET_EV_COOKIE(event); 732 xfer_len = MHI_TRE_GET_EV_LEN(event); 733 734 /* Received out of bound cookie */ 735 WARN_ON(cookie >= buf_ring->len); 736 737 buf_info = buf_ring->base + cookie; 738 739 result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? 740 -EOVERFLOW : 0; 741 742 /* truncate to buf len if xfer_len is larger */ 743 result.bytes_xferd = min_t(u16, xfer_len, buf_info->len); 744 result.buf_addr = buf_info->cb_buf; 745 result.dir = mhi_chan->dir; 746 747 read_lock_bh(&mhi_chan->lock); 748 749 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) 750 goto end_process_rsc_event; 751 752 WARN_ON(!buf_info->used); 753 754 /* notify the client */ 755 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); 756 757 /* 758 * Note: We're arbitrarily incrementing RP even though, completion 759 * packet we processed might not be the same one, reason we can do this 760 * is because device guaranteed to cache descriptors in order it 761 * receive, so even though completion event is different we can re-use 762 * all descriptors in between. 763 * Example: 764 * Transfer Ring has descriptors: A, B, C, D 765 * Last descriptor host queue is D (WP) and first descriptor 766 * host queue is A (RP). 767 * The completion event we just serviced is descriptor C. 768 * Then we can safely queue descriptors to replace A, B, and C 769 * even though host did not receive any completions. 770 */ 771 mhi_del_ring_element(mhi_cntrl, tre_ring); 772 buf_info->used = false; 773 774 end_process_rsc_event: 775 read_unlock_bh(&mhi_chan->lock); 776 777 return 0; 778 } 779 780 static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, 781 struct mhi_ring_element *tre) 782 { 783 dma_addr_t ptr = MHI_TRE_GET_EV_PTR(tre); 784 struct mhi_cmd *cmd_ring = &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; 785 struct mhi_ring *mhi_ring = &cmd_ring->ring; 786 struct mhi_ring_element *cmd_pkt; 787 struct mhi_chan *mhi_chan; 788 u32 chan; 789 790 if (!is_valid_ring_ptr(mhi_ring, ptr)) { 791 dev_err(&mhi_cntrl->mhi_dev->dev, 792 "Event element points outside of the cmd ring\n"); 793 return; 794 } 795 796 cmd_pkt = mhi_to_virtual(mhi_ring, ptr); 797 798 chan = MHI_TRE_GET_CMD_CHID(cmd_pkt); 799 800 if (chan < mhi_cntrl->max_chan && 801 mhi_cntrl->mhi_chan[chan].configured) { 802 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 803 write_lock_bh(&mhi_chan->lock); 804 mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); 805 complete(&mhi_chan->completion); 806 write_unlock_bh(&mhi_chan->lock); 807 } else { 808 dev_err(&mhi_cntrl->mhi_dev->dev, 809 "Completion packet for invalid channel ID: %d\n", chan); 810 } 811 812 mhi_del_ring_element(mhi_cntrl, mhi_ring); 813 } 814 815 int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, 816 struct mhi_event *mhi_event, 817 u32 event_quota) 818 { 819 struct mhi_ring_element *dev_rp, *local_rp; 820 struct mhi_ring *ev_ring = &mhi_event->ring; 821 struct mhi_event_ctxt *er_ctxt = 822 &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; 823 struct mhi_chan *mhi_chan; 824 struct device *dev = &mhi_cntrl->mhi_dev->dev; 825 u32 chan; 826 int count = 0; 827 dma_addr_t ptr = le64_to_cpu(er_ctxt->rp); 828 829 /* 830 * This is a quick check to avoid unnecessary event processing 831 * in case MHI is already in error state, but it's still possible 832 * to transition to error state while processing events 833 */ 834 if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) 835 return -EIO; 836 837 if (!is_valid_ring_ptr(ev_ring, ptr)) { 838 dev_err(&mhi_cntrl->mhi_dev->dev, 839 "Event ring rp points outside of the event ring\n"); 840 return -EIO; 841 } 842 843 dev_rp = mhi_to_virtual(ev_ring, ptr); 844 local_rp = ev_ring->rp; 845 846 while (dev_rp != local_rp) { 847 enum mhi_pkt_type type = MHI_TRE_GET_EV_TYPE(local_rp); 848 849 trace_mhi_ctrl_event(mhi_cntrl, local_rp); 850 851 switch (type) { 852 case MHI_PKT_TYPE_BW_REQ_EVENT: 853 { 854 struct mhi_link_info *link_info; 855 856 link_info = &mhi_cntrl->mhi_link_info; 857 write_lock_irq(&mhi_cntrl->pm_lock); 858 link_info->target_link_speed = 859 MHI_TRE_GET_EV_LINKSPEED(local_rp); 860 link_info->target_link_width = 861 MHI_TRE_GET_EV_LINKWIDTH(local_rp); 862 write_unlock_irq(&mhi_cntrl->pm_lock); 863 dev_dbg(dev, "Received BW_REQ event\n"); 864 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_BW_REQ); 865 break; 866 } 867 case MHI_PKT_TYPE_STATE_CHANGE_EVENT: 868 { 869 enum mhi_state new_state; 870 871 new_state = MHI_TRE_GET_EV_STATE(local_rp); 872 873 dev_dbg(dev, "State change event to state: %s\n", 874 mhi_state_str(new_state)); 875 876 switch (new_state) { 877 case MHI_STATE_M0: 878 mhi_pm_m0_transition(mhi_cntrl); 879 break; 880 case MHI_STATE_M1: 881 mhi_pm_m1_transition(mhi_cntrl); 882 break; 883 case MHI_STATE_M3: 884 mhi_pm_m3_transition(mhi_cntrl); 885 break; 886 case MHI_STATE_SYS_ERR: 887 { 888 enum mhi_pm_state pm_state; 889 890 dev_dbg(dev, "System error detected\n"); 891 write_lock_irq(&mhi_cntrl->pm_lock); 892 pm_state = mhi_tryset_pm_state(mhi_cntrl, 893 MHI_PM_SYS_ERR_DETECT); 894 write_unlock_irq(&mhi_cntrl->pm_lock); 895 if (pm_state == MHI_PM_SYS_ERR_DETECT) 896 mhi_pm_sys_err_handler(mhi_cntrl); 897 break; 898 } 899 default: 900 dev_err(dev, "Invalid state: %s\n", 901 mhi_state_str(new_state)); 902 } 903 904 break; 905 } 906 case MHI_PKT_TYPE_CMD_COMPLETION_EVENT: 907 mhi_process_cmd_completion(mhi_cntrl, local_rp); 908 break; 909 case MHI_PKT_TYPE_EE_EVENT: 910 { 911 enum dev_st_transition st = DEV_ST_TRANSITION_MAX; 912 enum mhi_ee_type event = MHI_TRE_GET_EV_EXECENV(local_rp); 913 914 dev_dbg(dev, "Received EE event: %s\n", 915 TO_MHI_EXEC_STR(event)); 916 switch (event) { 917 case MHI_EE_SBL: 918 st = DEV_ST_TRANSITION_SBL; 919 break; 920 case MHI_EE_WFW: 921 case MHI_EE_AMSS: 922 st = DEV_ST_TRANSITION_MISSION_MODE; 923 break; 924 case MHI_EE_FP: 925 st = DEV_ST_TRANSITION_FP; 926 break; 927 case MHI_EE_RDDM: 928 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); 929 write_lock_irq(&mhi_cntrl->pm_lock); 930 mhi_cntrl->ee = event; 931 write_unlock_irq(&mhi_cntrl->pm_lock); 932 wake_up_all(&mhi_cntrl->state_event); 933 break; 934 default: 935 dev_err(dev, 936 "Unhandled EE event: 0x%x\n", type); 937 } 938 if (st != DEV_ST_TRANSITION_MAX) 939 mhi_queue_state_transition(mhi_cntrl, st); 940 941 break; 942 } 943 case MHI_PKT_TYPE_TX_EVENT: 944 chan = MHI_TRE_GET_EV_CHID(local_rp); 945 946 WARN_ON(chan >= mhi_cntrl->max_chan); 947 948 /* 949 * Only process the event ring elements whose channel 950 * ID is within the maximum supported range. 951 */ 952 if (chan < mhi_cntrl->max_chan) { 953 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 954 if (!mhi_chan->configured) 955 break; 956 parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); 957 } 958 break; 959 default: 960 dev_err(dev, "Unhandled event type: %d\n", type); 961 break; 962 } 963 964 mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); 965 local_rp = ev_ring->rp; 966 967 ptr = le64_to_cpu(er_ctxt->rp); 968 if (!is_valid_ring_ptr(ev_ring, ptr)) { 969 dev_err(&mhi_cntrl->mhi_dev->dev, 970 "Event ring rp points outside of the event ring\n"); 971 return -EIO; 972 } 973 974 dev_rp = mhi_to_virtual(ev_ring, ptr); 975 count++; 976 } 977 978 read_lock_bh(&mhi_cntrl->pm_lock); 979 980 /* Ring EV DB only if there is any pending element to process */ 981 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && count) 982 mhi_ring_er_db(mhi_event); 983 read_unlock_bh(&mhi_cntrl->pm_lock); 984 985 return count; 986 } 987 988 int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, 989 struct mhi_event *mhi_event, 990 u32 event_quota) 991 { 992 struct mhi_ring_element *dev_rp, *local_rp; 993 struct mhi_ring *ev_ring = &mhi_event->ring; 994 struct mhi_event_ctxt *er_ctxt = 995 &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; 996 int count = 0; 997 u32 chan; 998 struct mhi_chan *mhi_chan; 999 dma_addr_t ptr = le64_to_cpu(er_ctxt->rp); 1000 1001 if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) 1002 return -EIO; 1003 1004 if (!is_valid_ring_ptr(ev_ring, ptr)) { 1005 dev_err(&mhi_cntrl->mhi_dev->dev, 1006 "Event ring rp points outside of the event ring\n"); 1007 return -EIO; 1008 } 1009 1010 dev_rp = mhi_to_virtual(ev_ring, ptr); 1011 local_rp = ev_ring->rp; 1012 1013 while (dev_rp != local_rp && event_quota > 0) { 1014 enum mhi_pkt_type type = MHI_TRE_GET_EV_TYPE(local_rp); 1015 1016 trace_mhi_data_event(mhi_cntrl, local_rp); 1017 1018 chan = MHI_TRE_GET_EV_CHID(local_rp); 1019 1020 WARN_ON(chan >= mhi_cntrl->max_chan); 1021 1022 /* 1023 * Only process the event ring elements whose channel 1024 * ID is within the maximum supported range. 1025 */ 1026 if (chan < mhi_cntrl->max_chan && 1027 mhi_cntrl->mhi_chan[chan].configured) { 1028 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 1029 1030 if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { 1031 parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); 1032 event_quota--; 1033 } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { 1034 parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); 1035 event_quota--; 1036 } 1037 } 1038 1039 mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); 1040 local_rp = ev_ring->rp; 1041 1042 ptr = le64_to_cpu(er_ctxt->rp); 1043 if (!is_valid_ring_ptr(ev_ring, ptr)) { 1044 dev_err(&mhi_cntrl->mhi_dev->dev, 1045 "Event ring rp points outside of the event ring\n"); 1046 return -EIO; 1047 } 1048 1049 dev_rp = mhi_to_virtual(ev_ring, ptr); 1050 count++; 1051 } 1052 read_lock_bh(&mhi_cntrl->pm_lock); 1053 1054 /* Ring EV DB only if there is any pending element to process */ 1055 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && count) 1056 mhi_ring_er_db(mhi_event); 1057 read_unlock_bh(&mhi_cntrl->pm_lock); 1058 1059 return count; 1060 } 1061 1062 void mhi_ev_task(unsigned long data) 1063 { 1064 struct mhi_event *mhi_event = (struct mhi_event *)data; 1065 struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; 1066 1067 /* process all pending events */ 1068 spin_lock_bh(&mhi_event->lock); 1069 mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); 1070 spin_unlock_bh(&mhi_event->lock); 1071 } 1072 1073 void mhi_ctrl_ev_task(unsigned long data) 1074 { 1075 struct mhi_event *mhi_event = (struct mhi_event *)data; 1076 struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; 1077 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1078 enum mhi_state state; 1079 enum mhi_pm_state pm_state = 0; 1080 int ret; 1081 1082 /* 1083 * We can check PM state w/o a lock here because there is no way 1084 * PM state can change from reg access valid to no access while this 1085 * thread being executed. 1086 */ 1087 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { 1088 /* 1089 * We may have a pending event but not allowed to 1090 * process it since we are probably in a suspended state, 1091 * so trigger a resume. 1092 */ 1093 mhi_trigger_resume(mhi_cntrl); 1094 1095 return; 1096 } 1097 1098 /* Process ctrl events */ 1099 ret = mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); 1100 1101 /* 1102 * We received an IRQ but no events to process, maybe device went to 1103 * SYS_ERR state? Check the state to confirm. 1104 */ 1105 if (!ret) { 1106 write_lock_irq(&mhi_cntrl->pm_lock); 1107 state = mhi_get_mhi_state(mhi_cntrl); 1108 if (state == MHI_STATE_SYS_ERR) { 1109 dev_dbg(dev, "System error detected\n"); 1110 pm_state = mhi_tryset_pm_state(mhi_cntrl, 1111 MHI_PM_SYS_ERR_DETECT); 1112 } 1113 write_unlock_irq(&mhi_cntrl->pm_lock); 1114 if (pm_state == MHI_PM_SYS_ERR_DETECT) 1115 mhi_pm_sys_err_handler(mhi_cntrl); 1116 } 1117 } 1118 1119 static bool mhi_is_ring_full(struct mhi_controller *mhi_cntrl, 1120 struct mhi_ring *ring) 1121 { 1122 void *tmp = ring->wp + ring->el_size; 1123 1124 if (tmp >= (ring->base + ring->len)) 1125 tmp = ring->base; 1126 1127 return (tmp == ring->rp); 1128 } 1129 1130 static int mhi_queue(struct mhi_device *mhi_dev, struct mhi_buf_info *buf_info, 1131 enum dma_data_direction dir, enum mhi_flags mflags) 1132 { 1133 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1134 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : 1135 mhi_dev->dl_chan; 1136 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 1137 unsigned long flags; 1138 int ret; 1139 1140 if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) 1141 return -EIO; 1142 1143 ret = mhi_is_ring_full(mhi_cntrl, tre_ring); 1144 if (unlikely(ret)) 1145 return -EAGAIN; 1146 1147 ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf_info, mflags); 1148 if (unlikely(ret)) 1149 return ret; 1150 1151 read_lock_irqsave(&mhi_cntrl->pm_lock, flags); 1152 1153 /* Packet is queued, take a usage ref to exit M3 if necessary 1154 * for host->device buffer, balanced put is done on buffer completion 1155 * for device->host buffer, balanced put is after ringing the DB 1156 */ 1157 mhi_cntrl->runtime_get(mhi_cntrl); 1158 1159 /* Assert dev_wake (to exit/prevent M1/M2)*/ 1160 mhi_cntrl->wake_toggle(mhi_cntrl); 1161 1162 if (mhi_chan->dir == DMA_TO_DEVICE) 1163 atomic_inc(&mhi_cntrl->pending_pkts); 1164 1165 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) 1166 mhi_ring_chan_db(mhi_cntrl, mhi_chan); 1167 1168 if (dir == DMA_FROM_DEVICE) 1169 mhi_cntrl->runtime_put(mhi_cntrl); 1170 1171 read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); 1172 1173 return ret; 1174 } 1175 1176 int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, 1177 struct sk_buff *skb, size_t len, enum mhi_flags mflags) 1178 { 1179 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : 1180 mhi_dev->dl_chan; 1181 struct mhi_buf_info buf_info = { }; 1182 1183 buf_info.v_addr = skb->data; 1184 buf_info.cb_buf = skb; 1185 buf_info.len = len; 1186 1187 if (unlikely(mhi_chan->pre_alloc)) 1188 return -EINVAL; 1189 1190 return mhi_queue(mhi_dev, &buf_info, dir, mflags); 1191 } 1192 EXPORT_SYMBOL_GPL(mhi_queue_skb); 1193 1194 int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, 1195 struct mhi_buf_info *info, enum mhi_flags flags) 1196 { 1197 struct mhi_ring *buf_ring, *tre_ring; 1198 struct mhi_ring_element *mhi_tre; 1199 struct mhi_buf_info *buf_info; 1200 int eot, eob, chain, bei; 1201 int ret = 0; 1202 1203 /* Protect accesses for reading and incrementing WP */ 1204 write_lock_bh(&mhi_chan->lock); 1205 1206 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) { 1207 ret = -ENODEV; 1208 goto out; 1209 } 1210 1211 buf_ring = &mhi_chan->buf_ring; 1212 tre_ring = &mhi_chan->tre_ring; 1213 1214 buf_info = buf_ring->wp; 1215 WARN_ON(buf_info->used); 1216 buf_info->pre_mapped = info->pre_mapped; 1217 if (info->pre_mapped) 1218 buf_info->p_addr = info->p_addr; 1219 else 1220 buf_info->v_addr = info->v_addr; 1221 buf_info->cb_buf = info->cb_buf; 1222 buf_info->wp = tre_ring->wp; 1223 buf_info->dir = mhi_chan->dir; 1224 buf_info->len = info->len; 1225 1226 if (!info->pre_mapped) { 1227 ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); 1228 if (ret) 1229 goto out; 1230 } 1231 1232 eob = !!(flags & MHI_EOB); 1233 eot = !!(flags & MHI_EOT); 1234 chain = !!(flags & MHI_CHAIN); 1235 bei = !!(mhi_chan->intmod); 1236 1237 mhi_tre = tre_ring->wp; 1238 mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); 1239 mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(info->len); 1240 mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(bei, eot, eob, chain); 1241 1242 trace_mhi_gen_tre(mhi_cntrl, mhi_chan, mhi_tre); 1243 /* increment WP */ 1244 mhi_add_ring_element(mhi_cntrl, tre_ring); 1245 mhi_add_ring_element(mhi_cntrl, buf_ring); 1246 1247 out: 1248 write_unlock_bh(&mhi_chan->lock); 1249 1250 return ret; 1251 } 1252 1253 int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, 1254 void *buf, size_t len, enum mhi_flags mflags) 1255 { 1256 struct mhi_buf_info buf_info = { }; 1257 1258 buf_info.v_addr = buf; 1259 buf_info.cb_buf = buf; 1260 buf_info.len = len; 1261 1262 return mhi_queue(mhi_dev, &buf_info, dir, mflags); 1263 } 1264 EXPORT_SYMBOL_GPL(mhi_queue_buf); 1265 1266 bool mhi_queue_is_full(struct mhi_device *mhi_dev, enum dma_data_direction dir) 1267 { 1268 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1269 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? 1270 mhi_dev->ul_chan : mhi_dev->dl_chan; 1271 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 1272 1273 return mhi_is_ring_full(mhi_cntrl, tre_ring); 1274 } 1275 EXPORT_SYMBOL_GPL(mhi_queue_is_full); 1276 1277 int mhi_send_cmd(struct mhi_controller *mhi_cntrl, 1278 struct mhi_chan *mhi_chan, 1279 enum mhi_cmd_type cmd) 1280 { 1281 struct mhi_ring_element *cmd_tre = NULL; 1282 struct mhi_cmd *mhi_cmd = &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; 1283 struct mhi_ring *ring = &mhi_cmd->ring; 1284 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1285 int chan = 0; 1286 1287 if (mhi_chan) 1288 chan = mhi_chan->chan; 1289 1290 spin_lock_bh(&mhi_cmd->lock); 1291 if (!get_nr_avail_ring_elements(mhi_cntrl, ring)) { 1292 spin_unlock_bh(&mhi_cmd->lock); 1293 return -ENOMEM; 1294 } 1295 1296 /* prepare the cmd tre */ 1297 cmd_tre = ring->wp; 1298 switch (cmd) { 1299 case MHI_CMD_RESET_CHAN: 1300 cmd_tre->ptr = MHI_TRE_CMD_RESET_PTR; 1301 cmd_tre->dword[0] = MHI_TRE_CMD_RESET_DWORD0; 1302 cmd_tre->dword[1] = MHI_TRE_CMD_RESET_DWORD1(chan); 1303 break; 1304 case MHI_CMD_STOP_CHAN: 1305 cmd_tre->ptr = MHI_TRE_CMD_STOP_PTR; 1306 cmd_tre->dword[0] = MHI_TRE_CMD_STOP_DWORD0; 1307 cmd_tre->dword[1] = MHI_TRE_CMD_STOP_DWORD1(chan); 1308 break; 1309 case MHI_CMD_START_CHAN: 1310 cmd_tre->ptr = MHI_TRE_CMD_START_PTR; 1311 cmd_tre->dword[0] = MHI_TRE_CMD_START_DWORD0; 1312 cmd_tre->dword[1] = MHI_TRE_CMD_START_DWORD1(chan); 1313 break; 1314 default: 1315 dev_err(dev, "Command not supported\n"); 1316 break; 1317 } 1318 1319 /* queue to hardware */ 1320 mhi_add_ring_element(mhi_cntrl, ring); 1321 read_lock_bh(&mhi_cntrl->pm_lock); 1322 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) 1323 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd); 1324 read_unlock_bh(&mhi_cntrl->pm_lock); 1325 spin_unlock_bh(&mhi_cmd->lock); 1326 1327 return 0; 1328 } 1329 1330 static int mhi_update_channel_state(struct mhi_controller *mhi_cntrl, 1331 struct mhi_chan *mhi_chan, 1332 enum mhi_ch_state_type to_state) 1333 { 1334 struct device *dev = &mhi_chan->mhi_dev->dev; 1335 enum mhi_cmd_type cmd = MHI_CMD_NOP; 1336 int ret; 1337 1338 trace_mhi_channel_command_start(mhi_cntrl, mhi_chan, to_state, TPS("Updating")); 1339 switch (to_state) { 1340 case MHI_CH_STATE_TYPE_RESET: 1341 write_lock_irq(&mhi_chan->lock); 1342 if (mhi_chan->ch_state != MHI_CH_STATE_STOP && 1343 mhi_chan->ch_state != MHI_CH_STATE_ENABLED && 1344 mhi_chan->ch_state != MHI_CH_STATE_SUSPENDED) { 1345 write_unlock_irq(&mhi_chan->lock); 1346 return -EINVAL; 1347 } 1348 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 1349 write_unlock_irq(&mhi_chan->lock); 1350 1351 cmd = MHI_CMD_RESET_CHAN; 1352 break; 1353 case MHI_CH_STATE_TYPE_STOP: 1354 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) 1355 return -EINVAL; 1356 1357 cmd = MHI_CMD_STOP_CHAN; 1358 break; 1359 case MHI_CH_STATE_TYPE_START: 1360 if (mhi_chan->ch_state != MHI_CH_STATE_STOP && 1361 mhi_chan->ch_state != MHI_CH_STATE_DISABLED) 1362 return -EINVAL; 1363 1364 cmd = MHI_CMD_START_CHAN; 1365 break; 1366 default: 1367 dev_err(dev, "%d: Channel state update to %s not allowed\n", 1368 mhi_chan->chan, TO_CH_STATE_TYPE_STR(to_state)); 1369 return -EINVAL; 1370 } 1371 1372 /* bring host and device out of suspended states */ 1373 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1374 if (ret) 1375 return ret; 1376 mhi_cntrl->runtime_get(mhi_cntrl); 1377 1378 reinit_completion(&mhi_chan->completion); 1379 ret = mhi_send_cmd(mhi_cntrl, mhi_chan, cmd); 1380 if (ret) { 1381 dev_err(dev, "%d: Failed to send %s channel command\n", 1382 mhi_chan->chan, TO_CH_STATE_TYPE_STR(to_state)); 1383 goto exit_channel_update; 1384 } 1385 1386 ret = wait_for_completion_timeout(&mhi_chan->completion, 1387 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 1388 if (!ret || mhi_chan->ccs != MHI_EV_CC_SUCCESS) { 1389 dev_err(dev, 1390 "%d: Failed to receive %s channel command completion\n", 1391 mhi_chan->chan, TO_CH_STATE_TYPE_STR(to_state)); 1392 ret = -EIO; 1393 goto exit_channel_update; 1394 } 1395 1396 ret = 0; 1397 1398 if (to_state != MHI_CH_STATE_TYPE_RESET) { 1399 write_lock_irq(&mhi_chan->lock); 1400 mhi_chan->ch_state = (to_state == MHI_CH_STATE_TYPE_START) ? 1401 MHI_CH_STATE_ENABLED : MHI_CH_STATE_STOP; 1402 write_unlock_irq(&mhi_chan->lock); 1403 } 1404 1405 trace_mhi_channel_command_end(mhi_cntrl, mhi_chan, to_state, TPS("Updated")); 1406 exit_channel_update: 1407 mhi_cntrl->runtime_put(mhi_cntrl); 1408 mhi_device_put(mhi_cntrl->mhi_dev); 1409 1410 return ret; 1411 } 1412 1413 static void mhi_unprepare_channel(struct mhi_controller *mhi_cntrl, 1414 struct mhi_chan *mhi_chan) 1415 { 1416 int ret; 1417 struct device *dev = &mhi_chan->mhi_dev->dev; 1418 1419 mutex_lock(&mhi_chan->mutex); 1420 1421 if (!(BIT(mhi_cntrl->ee) & mhi_chan->ee_mask)) { 1422 dev_dbg(dev, "Current EE: %s Required EE Mask: 0x%x\n", 1423 TO_MHI_EXEC_STR(mhi_cntrl->ee), mhi_chan->ee_mask); 1424 goto exit_unprepare_channel; 1425 } 1426 1427 /* no more processing events for this channel */ 1428 ret = mhi_update_channel_state(mhi_cntrl, mhi_chan, 1429 MHI_CH_STATE_TYPE_RESET); 1430 if (ret) 1431 dev_err(dev, "%d: Failed to reset channel, still resetting\n", 1432 mhi_chan->chan); 1433 1434 exit_unprepare_channel: 1435 write_lock_irq(&mhi_chan->lock); 1436 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 1437 write_unlock_irq(&mhi_chan->lock); 1438 1439 if (!mhi_chan->offload_ch) { 1440 mhi_reset_chan(mhi_cntrl, mhi_chan); 1441 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); 1442 } 1443 dev_dbg(dev, "%d: successfully reset\n", mhi_chan->chan); 1444 1445 mutex_unlock(&mhi_chan->mutex); 1446 } 1447 1448 static int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, 1449 struct mhi_chan *mhi_chan, unsigned int flags) 1450 { 1451 int ret = 0; 1452 struct device *dev = &mhi_chan->mhi_dev->dev; 1453 1454 if (!(BIT(mhi_cntrl->ee) & mhi_chan->ee_mask)) { 1455 dev_err(dev, "Current EE: %s Required EE Mask: 0x%x\n", 1456 TO_MHI_EXEC_STR(mhi_cntrl->ee), mhi_chan->ee_mask); 1457 return -ENOTCONN; 1458 } 1459 1460 mutex_lock(&mhi_chan->mutex); 1461 1462 /* Check of client manages channel context for offload channels */ 1463 if (!mhi_chan->offload_ch) { 1464 ret = mhi_init_chan_ctxt(mhi_cntrl, mhi_chan); 1465 if (ret) 1466 goto error_init_chan; 1467 } 1468 1469 ret = mhi_update_channel_state(mhi_cntrl, mhi_chan, 1470 MHI_CH_STATE_TYPE_START); 1471 if (ret) 1472 goto error_pm_state; 1473 1474 if (mhi_chan->dir == DMA_FROM_DEVICE) 1475 mhi_chan->pre_alloc = !!(flags & MHI_CH_INBOUND_ALLOC_BUFS); 1476 1477 /* Pre-allocate buffer for xfer ring */ 1478 if (mhi_chan->pre_alloc) { 1479 int nr_el = get_nr_avail_ring_elements(mhi_cntrl, 1480 &mhi_chan->tre_ring); 1481 size_t len = mhi_cntrl->buffer_len; 1482 1483 while (nr_el--) { 1484 void *buf; 1485 struct mhi_buf_info info = { }; 1486 1487 buf = kmalloc(len, GFP_KERNEL); 1488 if (!buf) { 1489 ret = -ENOMEM; 1490 goto error_pre_alloc; 1491 } 1492 1493 /* Prepare transfer descriptors */ 1494 info.v_addr = buf; 1495 info.cb_buf = buf; 1496 info.len = len; 1497 ret = mhi_gen_tre(mhi_cntrl, mhi_chan, &info, MHI_EOT); 1498 if (ret) { 1499 kfree(buf); 1500 goto error_pre_alloc; 1501 } 1502 } 1503 1504 read_lock_bh(&mhi_cntrl->pm_lock); 1505 if (MHI_DB_ACCESS_VALID(mhi_cntrl)) { 1506 read_lock_irq(&mhi_chan->lock); 1507 mhi_ring_chan_db(mhi_cntrl, mhi_chan); 1508 read_unlock_irq(&mhi_chan->lock); 1509 } 1510 read_unlock_bh(&mhi_cntrl->pm_lock); 1511 } 1512 1513 mutex_unlock(&mhi_chan->mutex); 1514 1515 return 0; 1516 1517 error_pm_state: 1518 if (!mhi_chan->offload_ch) 1519 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); 1520 1521 error_init_chan: 1522 mutex_unlock(&mhi_chan->mutex); 1523 1524 return ret; 1525 1526 error_pre_alloc: 1527 mutex_unlock(&mhi_chan->mutex); 1528 mhi_unprepare_channel(mhi_cntrl, mhi_chan); 1529 1530 return ret; 1531 } 1532 1533 static void mhi_mark_stale_events(struct mhi_controller *mhi_cntrl, 1534 struct mhi_event *mhi_event, 1535 struct mhi_event_ctxt *er_ctxt, 1536 int chan) 1537 1538 { 1539 struct mhi_ring_element *dev_rp, *local_rp; 1540 struct mhi_ring *ev_ring; 1541 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1542 unsigned long flags; 1543 dma_addr_t ptr; 1544 1545 dev_dbg(dev, "Marking all events for chan: %d as stale\n", chan); 1546 1547 ev_ring = &mhi_event->ring; 1548 1549 /* mark all stale events related to channel as STALE event */ 1550 spin_lock_irqsave(&mhi_event->lock, flags); 1551 1552 ptr = le64_to_cpu(er_ctxt->rp); 1553 if (!is_valid_ring_ptr(ev_ring, ptr)) { 1554 dev_err(&mhi_cntrl->mhi_dev->dev, 1555 "Event ring rp points outside of the event ring\n"); 1556 dev_rp = ev_ring->rp; 1557 } else { 1558 dev_rp = mhi_to_virtual(ev_ring, ptr); 1559 } 1560 1561 local_rp = ev_ring->rp; 1562 while (dev_rp != local_rp) { 1563 if (MHI_TRE_GET_EV_TYPE(local_rp) == MHI_PKT_TYPE_TX_EVENT && 1564 chan == MHI_TRE_GET_EV_CHID(local_rp)) 1565 local_rp->dword[1] = MHI_TRE_EV_DWORD1(chan, 1566 MHI_PKT_TYPE_STALE_EVENT); 1567 local_rp++; 1568 if (local_rp == (ev_ring->base + ev_ring->len)) 1569 local_rp = ev_ring->base; 1570 } 1571 1572 dev_dbg(dev, "Finished marking events as stale events\n"); 1573 spin_unlock_irqrestore(&mhi_event->lock, flags); 1574 } 1575 1576 static void mhi_reset_data_chan(struct mhi_controller *mhi_cntrl, 1577 struct mhi_chan *mhi_chan) 1578 { 1579 struct mhi_ring *buf_ring, *tre_ring; 1580 struct mhi_result result; 1581 1582 /* Reset any pending buffers */ 1583 buf_ring = &mhi_chan->buf_ring; 1584 tre_ring = &mhi_chan->tre_ring; 1585 result.transaction_status = -ENOTCONN; 1586 result.bytes_xferd = 0; 1587 while (tre_ring->rp != tre_ring->wp) { 1588 struct mhi_buf_info *buf_info = buf_ring->rp; 1589 1590 if (mhi_chan->dir == DMA_TO_DEVICE) { 1591 atomic_dec(&mhi_cntrl->pending_pkts); 1592 /* Release the reference got from mhi_queue() */ 1593 mhi_cntrl->runtime_put(mhi_cntrl); 1594 } 1595 1596 if (!buf_info->pre_mapped) 1597 mhi_cntrl->unmap_single(mhi_cntrl, buf_info); 1598 1599 mhi_del_ring_element(mhi_cntrl, buf_ring); 1600 mhi_del_ring_element(mhi_cntrl, tre_ring); 1601 1602 if (mhi_chan->pre_alloc) { 1603 kfree(buf_info->cb_buf); 1604 } else { 1605 result.buf_addr = buf_info->cb_buf; 1606 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); 1607 } 1608 } 1609 } 1610 1611 void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan) 1612 { 1613 struct mhi_event *mhi_event; 1614 struct mhi_event_ctxt *er_ctxt; 1615 int chan = mhi_chan->chan; 1616 1617 /* Nothing to reset, client doesn't queue buffers */ 1618 if (mhi_chan->offload_ch) 1619 return; 1620 1621 read_lock_bh(&mhi_cntrl->pm_lock); 1622 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; 1623 er_ctxt = &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_chan->er_index]; 1624 1625 mhi_mark_stale_events(mhi_cntrl, mhi_event, er_ctxt, chan); 1626 1627 mhi_reset_data_chan(mhi_cntrl, mhi_chan); 1628 1629 read_unlock_bh(&mhi_cntrl->pm_lock); 1630 } 1631 1632 static int __mhi_prepare_for_transfer(struct mhi_device *mhi_dev, unsigned int flags) 1633 { 1634 int ret, dir; 1635 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1636 struct mhi_chan *mhi_chan; 1637 1638 for (dir = 0; dir < 2; dir++) { 1639 mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; 1640 if (!mhi_chan) 1641 continue; 1642 1643 ret = mhi_prepare_channel(mhi_cntrl, mhi_chan, flags); 1644 if (ret) 1645 goto error_open_chan; 1646 } 1647 1648 return 0; 1649 1650 error_open_chan: 1651 for (--dir; dir >= 0; dir--) { 1652 mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; 1653 if (!mhi_chan) 1654 continue; 1655 1656 mhi_unprepare_channel(mhi_cntrl, mhi_chan); 1657 } 1658 1659 return ret; 1660 } 1661 1662 int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) 1663 { 1664 return __mhi_prepare_for_transfer(mhi_dev, 0); 1665 } 1666 EXPORT_SYMBOL_GPL(mhi_prepare_for_transfer); 1667 1668 int mhi_prepare_for_transfer_autoqueue(struct mhi_device *mhi_dev) 1669 { 1670 return __mhi_prepare_for_transfer(mhi_dev, MHI_CH_INBOUND_ALLOC_BUFS); 1671 } 1672 EXPORT_SYMBOL_GPL(mhi_prepare_for_transfer_autoqueue); 1673 1674 void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev) 1675 { 1676 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1677 struct mhi_chan *mhi_chan; 1678 int dir; 1679 1680 for (dir = 0; dir < 2; dir++) { 1681 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; 1682 if (!mhi_chan) 1683 continue; 1684 1685 mhi_unprepare_channel(mhi_cntrl, mhi_chan); 1686 } 1687 } 1688 EXPORT_SYMBOL_GPL(mhi_unprepare_from_transfer); 1689 1690 int mhi_get_channel_doorbell_offset(struct mhi_controller *mhi_cntrl, u32 *chdb_offset) 1691 { 1692 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1693 void __iomem *base = mhi_cntrl->regs; 1694 int ret; 1695 1696 ret = mhi_read_reg(mhi_cntrl, base, CHDBOFF, chdb_offset); 1697 if (ret) { 1698 dev_err(dev, "Unable to read CHDBOFF register\n"); 1699 return -EIO; 1700 } 1701 1702 return 0; 1703 } 1704 EXPORT_SYMBOL_GPL(mhi_get_channel_doorbell_offset); 1705