1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/device.h> 9 #include <linux/dma-direction.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/interrupt.h> 12 #include <linux/list.h> 13 #include <linux/mhi.h> 14 #include <linux/module.h> 15 #include <linux/skbuff.h> 16 #include <linux/slab.h> 17 #include "internal.h" 18 #include "trace.h" 19 20 int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, 21 void __iomem *base, u32 offset, u32 *out) 22 { 23 return mhi_cntrl->read_reg(mhi_cntrl, base + offset, out); 24 } 25 26 int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, 27 void __iomem *base, u32 offset, 28 u32 mask, u32 *out) 29 { 30 u32 tmp; 31 int ret; 32 33 ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); 34 if (ret) 35 return ret; 36 37 *out = (tmp & mask) >> __ffs(mask); 38 39 return 0; 40 } 41 42 int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl, 43 void __iomem *base, u32 offset, 44 u32 mask, u32 val, u32 delayus, 45 u32 timeout_ms) 46 { 47 int ret; 48 u32 out, retry = (timeout_ms * 1000) / delayus; 49 50 while (retry--) { 51 ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out); 52 if (ret) 53 return ret; 54 55 if (out == val) 56 return 0; 57 58 fsleep(delayus); 59 } 60 61 return -ETIMEDOUT; 62 } 63 64 void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, 65 u32 offset, u32 val) 66 { 67 mhi_cntrl->write_reg(mhi_cntrl, base + offset, val); 68 } 69 70 int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl, 71 void __iomem *base, u32 offset, u32 mask, 72 u32 val) 73 { 74 int ret; 75 u32 tmp; 76 77 ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); 78 if (ret) 79 return ret; 80 81 tmp &= ~mask; 82 tmp |= (val << __ffs(mask)); 83 mhi_write_reg(mhi_cntrl, base, offset, tmp); 84 85 return 0; 86 } 87 88 void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, 89 dma_addr_t db_val) 90 { 91 mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(db_val)); 92 mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(db_val)); 93 } 94 95 void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, 96 struct db_cfg *db_cfg, 97 void __iomem *db_addr, 98 dma_addr_t db_val) 99 { 100 if (db_cfg->db_mode) { 101 db_cfg->db_val = db_val; 102 mhi_write_db(mhi_cntrl, db_addr, db_val); 103 db_cfg->db_mode = 0; 104 } 105 } 106 107 void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, 108 struct db_cfg *db_cfg, 109 void __iomem *db_addr, 110 dma_addr_t db_val) 111 { 112 db_cfg->db_val = db_val; 113 mhi_write_db(mhi_cntrl, db_addr, db_val); 114 } 115 116 void mhi_ring_er_db(struct mhi_event *mhi_event) 117 { 118 struct mhi_ring *ring = &mhi_event->ring; 119 120 mhi_event->db_cfg.process_db(mhi_event->mhi_cntrl, &mhi_event->db_cfg, 121 ring->db_addr, le64_to_cpu(*ring->ctxt_wp)); 122 } 123 124 void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd) 125 { 126 dma_addr_t db; 127 struct mhi_ring *ring = &mhi_cmd->ring; 128 129 db = ring->iommu_base + (ring->wp - ring->base); 130 *ring->ctxt_wp = cpu_to_le64(db); 131 mhi_write_db(mhi_cntrl, ring->db_addr, db); 132 } 133 134 void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, 135 struct mhi_chan *mhi_chan) 136 { 137 struct mhi_ring *ring = &mhi_chan->tre_ring; 138 dma_addr_t db; 139 140 db = ring->iommu_base + (ring->wp - ring->base); 141 142 /* 143 * Writes to the new ring element must be visible to the hardware 144 * before letting h/w know there is new element to fetch. 145 */ 146 dma_wmb(); 147 *ring->ctxt_wp = cpu_to_le64(db); 148 149 mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg, 150 ring->db_addr, db); 151 } 152 153 enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl) 154 { 155 u32 exec; 156 int ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_EXECENV, &exec); 157 158 return (ret) ? MHI_EE_MAX : exec; 159 } 160 EXPORT_SYMBOL_GPL(mhi_get_exec_env); 161 162 enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) 163 { 164 u32 state; 165 int ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS, 166 MHISTATUS_MHISTATE_MASK, &state); 167 return ret ? MHI_STATE_MAX : state; 168 } 169 EXPORT_SYMBOL_GPL(mhi_get_mhi_state); 170 171 void mhi_soc_reset(struct mhi_controller *mhi_cntrl) 172 { 173 int __maybe_unused ret; 174 u32 tmp; 175 176 if (mhi_cntrl->reset) { 177 mhi_cntrl->reset(mhi_cntrl); 178 return; 179 } 180 181 /* Generic MHI SoC reset */ 182 mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, 183 MHI_SOC_RESET_REQ); 184 /* Flush the posted write to the device (ignore return value) */ 185 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, MHI_SOC_RESET_REQ_OFFSET, 186 &tmp); 187 } 188 EXPORT_SYMBOL_GPL(mhi_soc_reset); 189 190 int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, 191 struct mhi_buf_info *buf_info) 192 { 193 buf_info->p_addr = dma_map_single(mhi_cntrl->cntrl_dev, 194 buf_info->v_addr, buf_info->len, 195 buf_info->dir); 196 if (dma_mapping_error(mhi_cntrl->cntrl_dev, buf_info->p_addr)) 197 return -ENOMEM; 198 199 return 0; 200 } 201 202 int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, 203 struct mhi_buf_info *buf_info) 204 { 205 void *buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, buf_info->len, 206 &buf_info->p_addr, GFP_ATOMIC); 207 208 if (!buf) 209 return -ENOMEM; 210 211 if (buf_info->dir == DMA_TO_DEVICE) 212 memcpy(buf, buf_info->v_addr, buf_info->len); 213 214 buf_info->bb_addr = buf; 215 216 return 0; 217 } 218 219 void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, 220 struct mhi_buf_info *buf_info) 221 { 222 dma_unmap_single(mhi_cntrl->cntrl_dev, buf_info->p_addr, buf_info->len, 223 buf_info->dir); 224 } 225 226 void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, 227 struct mhi_buf_info *buf_info) 228 { 229 if (buf_info->dir == DMA_FROM_DEVICE) 230 memcpy(buf_info->v_addr, buf_info->bb_addr, buf_info->len); 231 232 dma_free_coherent(mhi_cntrl->cntrl_dev, buf_info->len, 233 buf_info->bb_addr, buf_info->p_addr); 234 } 235 236 static int get_nr_avail_ring_elements(struct mhi_controller *mhi_cntrl, 237 struct mhi_ring *ring) 238 { 239 int nr_el; 240 241 if (ring->wp < ring->rp) { 242 nr_el = ((ring->rp - ring->wp) / ring->el_size) - 1; 243 } else { 244 nr_el = (ring->rp - ring->base) / ring->el_size; 245 nr_el += ((ring->base + ring->len - ring->wp) / 246 ring->el_size) - 1; 247 } 248 249 return nr_el; 250 } 251 252 static void *mhi_to_virtual(struct mhi_ring *ring, dma_addr_t addr) 253 { 254 return (addr - ring->iommu_base) + ring->base; 255 } 256 257 static void mhi_add_ring_element(struct mhi_controller *mhi_cntrl, 258 struct mhi_ring *ring) 259 { 260 ring->wp += ring->el_size; 261 if (ring->wp >= (ring->base + ring->len)) 262 ring->wp = ring->base; 263 /* smp update */ 264 smp_wmb(); 265 } 266 267 static void mhi_del_ring_element(struct mhi_controller *mhi_cntrl, 268 struct mhi_ring *ring) 269 { 270 ring->rp += ring->el_size; 271 if (ring->rp >= (ring->base + ring->len)) 272 ring->rp = ring->base; 273 /* smp update */ 274 smp_wmb(); 275 } 276 277 static bool is_valid_ring_ptr(struct mhi_ring *ring, dma_addr_t addr) 278 { 279 return addr >= ring->iommu_base && addr < ring->iommu_base + ring->len && 280 !(addr & (sizeof(struct mhi_ring_element) - 1)); 281 } 282 283 int mhi_destroy_device(struct device *dev, void *data) 284 { 285 struct mhi_chan *ul_chan, *dl_chan; 286 struct mhi_device *mhi_dev; 287 struct mhi_controller *mhi_cntrl; 288 enum mhi_ee_type ee = MHI_EE_MAX; 289 290 if (dev->bus != &mhi_bus_type) 291 return 0; 292 293 mhi_dev = to_mhi_device(dev); 294 mhi_cntrl = mhi_dev->mhi_cntrl; 295 296 /* Only destroy virtual devices thats attached to bus */ 297 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) 298 return 0; 299 300 ul_chan = mhi_dev->ul_chan; 301 dl_chan = mhi_dev->dl_chan; 302 303 /* 304 * If execution environment is specified, remove only those devices that 305 * started in them based on ee_mask for the channels as we move on to a 306 * different execution environment 307 */ 308 if (data) 309 ee = *(enum mhi_ee_type *)data; 310 311 /* 312 * For the suspend and resume case, this function will get called 313 * without mhi_unregister_controller(). Hence, we need to drop the 314 * references to mhi_dev created for ul and dl channels. We can 315 * be sure that there will be no instances of mhi_dev left after 316 * this. 317 */ 318 if (ul_chan) { 319 if (ee != MHI_EE_MAX && !(ul_chan->ee_mask & BIT(ee))) 320 return 0; 321 322 put_device(&ul_chan->mhi_dev->dev); 323 } 324 325 if (dl_chan) { 326 if (ee != MHI_EE_MAX && !(dl_chan->ee_mask & BIT(ee))) 327 return 0; 328 329 put_device(&dl_chan->mhi_dev->dev); 330 } 331 332 dev_dbg(&mhi_cntrl->mhi_dev->dev, "destroy device for chan:%s\n", 333 mhi_dev->name); 334 335 /* Notify the client and remove the device from MHI bus */ 336 device_del(dev); 337 put_device(dev); 338 339 return 0; 340 } 341 342 int mhi_get_free_desc_count(struct mhi_device *mhi_dev, 343 enum dma_data_direction dir) 344 { 345 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 346 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? 347 mhi_dev->ul_chan : mhi_dev->dl_chan; 348 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 349 350 return get_nr_avail_ring_elements(mhi_cntrl, tre_ring); 351 } 352 EXPORT_SYMBOL_GPL(mhi_get_free_desc_count); 353 354 void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) 355 { 356 struct mhi_driver *mhi_drv; 357 358 if (!mhi_dev->dev.driver) 359 return; 360 361 mhi_drv = to_mhi_driver(mhi_dev->dev.driver); 362 363 if (mhi_drv->status_cb) 364 mhi_drv->status_cb(mhi_dev, cb_reason); 365 } 366 EXPORT_SYMBOL_GPL(mhi_notify); 367 368 /* Bind MHI channels to MHI devices */ 369 void mhi_create_devices(struct mhi_controller *mhi_cntrl) 370 { 371 struct mhi_chan *mhi_chan; 372 struct mhi_device *mhi_dev; 373 struct device *dev = &mhi_cntrl->mhi_dev->dev; 374 int i, ret; 375 376 mhi_chan = mhi_cntrl->mhi_chan; 377 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 378 if (!mhi_chan->configured || mhi_chan->mhi_dev || 379 !(mhi_chan->ee_mask & BIT(mhi_cntrl->ee))) 380 continue; 381 mhi_dev = mhi_alloc_device(mhi_cntrl); 382 if (IS_ERR(mhi_dev)) 383 return; 384 385 mhi_dev->dev_type = MHI_DEVICE_XFER; 386 switch (mhi_chan->dir) { 387 case DMA_TO_DEVICE: 388 mhi_dev->ul_chan = mhi_chan; 389 mhi_dev->ul_chan_id = mhi_chan->chan; 390 break; 391 case DMA_FROM_DEVICE: 392 /* We use dl_chan as offload channels */ 393 mhi_dev->dl_chan = mhi_chan; 394 mhi_dev->dl_chan_id = mhi_chan->chan; 395 break; 396 default: 397 dev_err(dev, "Direction not supported\n"); 398 put_device(&mhi_dev->dev); 399 return; 400 } 401 402 get_device(&mhi_dev->dev); 403 mhi_chan->mhi_dev = mhi_dev; 404 405 /* Check next channel if it matches */ 406 if ((i + 1) < mhi_cntrl->max_chan && mhi_chan[1].configured) { 407 if (!strcmp(mhi_chan[1].name, mhi_chan->name)) { 408 i++; 409 mhi_chan++; 410 if (mhi_chan->dir == DMA_TO_DEVICE) { 411 mhi_dev->ul_chan = mhi_chan; 412 mhi_dev->ul_chan_id = mhi_chan->chan; 413 } else { 414 mhi_dev->dl_chan = mhi_chan; 415 mhi_dev->dl_chan_id = mhi_chan->chan; 416 } 417 get_device(&mhi_dev->dev); 418 mhi_chan->mhi_dev = mhi_dev; 419 } 420 } 421 422 /* Channel name is same for both UL and DL */ 423 mhi_dev->name = mhi_chan->name; 424 dev_set_name(&mhi_dev->dev, "%s_%s", 425 dev_name(&mhi_cntrl->mhi_dev->dev), 426 mhi_dev->name); 427 428 /* Init wakeup source if available */ 429 if (mhi_dev->dl_chan && mhi_dev->dl_chan->wake_capable) 430 device_init_wakeup(&mhi_dev->dev, true); 431 432 ret = device_add(&mhi_dev->dev); 433 if (ret) 434 put_device(&mhi_dev->dev); 435 } 436 } 437 438 irqreturn_t mhi_irq_handler(int irq_number, void *dev) 439 { 440 struct mhi_event *mhi_event = dev; 441 struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; 442 struct mhi_event_ctxt *er_ctxt; 443 struct mhi_ring *ev_ring = &mhi_event->ring; 444 dma_addr_t ptr; 445 void *dev_rp; 446 447 /* 448 * If CONFIG_DEBUG_SHIRQ is set, the IRQ handler will get invoked during __free_irq() 449 * and by that time mhi_ctxt() would've freed. So check for the existence of mhi_ctxt 450 * before handling the IRQs. 451 */ 452 if (!mhi_cntrl->mhi_ctxt) { 453 dev_dbg(&mhi_cntrl->mhi_dev->dev, 454 "mhi_ctxt has been freed\n"); 455 return IRQ_HANDLED; 456 } 457 458 er_ctxt = &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; 459 ptr = le64_to_cpu(er_ctxt->rp); 460 461 if (!is_valid_ring_ptr(ev_ring, ptr)) { 462 dev_err(&mhi_cntrl->mhi_dev->dev, 463 "Event ring rp points outside of the event ring\n"); 464 return IRQ_HANDLED; 465 } 466 467 dev_rp = mhi_to_virtual(ev_ring, ptr); 468 469 /* Only proceed if event ring has pending events */ 470 if (ev_ring->rp == dev_rp) 471 return IRQ_HANDLED; 472 473 /* For client managed event ring, notify pending data */ 474 if (mhi_event->cl_manage) { 475 struct mhi_chan *mhi_chan = mhi_event->mhi_chan; 476 struct mhi_device *mhi_dev = mhi_chan->mhi_dev; 477 478 if (mhi_dev) 479 mhi_notify(mhi_dev, MHI_CB_PENDING_DATA); 480 } else { 481 tasklet_schedule(&mhi_event->task); 482 } 483 484 return IRQ_HANDLED; 485 } 486 487 irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *priv) 488 { 489 struct mhi_controller *mhi_cntrl = priv; 490 struct device *dev = &mhi_cntrl->mhi_dev->dev; 491 enum mhi_state state; 492 enum mhi_pm_state pm_state = 0; 493 enum mhi_ee_type ee; 494 495 write_lock_irq(&mhi_cntrl->pm_lock); 496 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { 497 write_unlock_irq(&mhi_cntrl->pm_lock); 498 goto exit_intvec; 499 } 500 501 state = mhi_get_mhi_state(mhi_cntrl); 502 ee = mhi_get_exec_env(mhi_cntrl); 503 504 trace_mhi_intvec_states(mhi_cntrl, ee, state); 505 if (state == MHI_STATE_SYS_ERR) { 506 dev_dbg(dev, "System error detected\n"); 507 pm_state = mhi_tryset_pm_state(mhi_cntrl, 508 MHI_PM_SYS_ERR_DETECT); 509 } 510 write_unlock_irq(&mhi_cntrl->pm_lock); 511 512 if (pm_state != MHI_PM_SYS_ERR_DETECT) 513 goto exit_intvec; 514 515 switch (ee) { 516 case MHI_EE_RDDM: 517 /* proceed if power down is not already in progress */ 518 if (mhi_cntrl->rddm_image && mhi_is_active(mhi_cntrl)) { 519 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); 520 mhi_cntrl->ee = ee; 521 mhi_uevent_notify(mhi_cntrl, mhi_cntrl->ee); 522 wake_up_all(&mhi_cntrl->state_event); 523 } 524 break; 525 case MHI_EE_PBL: 526 case MHI_EE_EDL: 527 case MHI_EE_PTHRU: 528 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_FATAL_ERROR); 529 mhi_cntrl->ee = ee; 530 wake_up_all(&mhi_cntrl->state_event); 531 mhi_pm_sys_err_handler(mhi_cntrl); 532 break; 533 default: 534 wake_up_all(&mhi_cntrl->state_event); 535 mhi_pm_sys_err_handler(mhi_cntrl); 536 break; 537 } 538 539 exit_intvec: 540 541 return IRQ_HANDLED; 542 } 543 544 irqreturn_t mhi_intvec_handler(int irq_number, void *dev) 545 { 546 struct mhi_controller *mhi_cntrl = dev; 547 548 /* Wake up events waiting for state change */ 549 wake_up_all(&mhi_cntrl->state_event); 550 551 return IRQ_WAKE_THREAD; 552 } 553 554 static void mhi_recycle_ev_ring_element(struct mhi_controller *mhi_cntrl, 555 struct mhi_ring *ring) 556 { 557 /* Update the WP */ 558 ring->wp += ring->el_size; 559 560 if (ring->wp >= (ring->base + ring->len)) 561 ring->wp = ring->base; 562 563 *ring->ctxt_wp = cpu_to_le64(ring->iommu_base + (ring->wp - ring->base)); 564 565 /* Update the RP */ 566 ring->rp += ring->el_size; 567 if (ring->rp >= (ring->base + ring->len)) 568 ring->rp = ring->base; 569 570 /* Update to all cores */ 571 smp_wmb(); 572 } 573 574 static int parse_xfer_event(struct mhi_controller *mhi_cntrl, 575 struct mhi_ring_element *event, 576 struct mhi_chan *mhi_chan) 577 { 578 struct mhi_ring *buf_ring, *tre_ring; 579 struct device *dev = &mhi_cntrl->mhi_dev->dev; 580 struct mhi_result result; 581 unsigned long flags = 0; 582 u32 ev_code; 583 584 ev_code = MHI_TRE_GET_EV_CODE(event); 585 buf_ring = &mhi_chan->buf_ring; 586 tre_ring = &mhi_chan->tre_ring; 587 588 result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? 589 -EOVERFLOW : 0; 590 591 /* 592 * If it's a DB Event then we need to grab the lock 593 * with preemption disabled and as a write because we 594 * have to update db register and there are chances that 595 * another thread could be doing the same. 596 */ 597 if (ev_code >= MHI_EV_CC_OOB) 598 write_lock_irqsave(&mhi_chan->lock, flags); 599 else 600 read_lock_bh(&mhi_chan->lock); 601 602 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) 603 goto end_process_tx_event; 604 605 switch (ev_code) { 606 case MHI_EV_CC_OVERFLOW: 607 case MHI_EV_CC_EOB: 608 case MHI_EV_CC_EOT: 609 { 610 dma_addr_t ptr = MHI_TRE_GET_EV_PTR(event); 611 struct mhi_ring_element *local_rp, *ev_tre; 612 void *dev_rp, *next_rp; 613 struct mhi_buf_info *buf_info; 614 u16 xfer_len; 615 616 if (!is_valid_ring_ptr(tre_ring, ptr)) { 617 dev_err(&mhi_cntrl->mhi_dev->dev, 618 "Event element points outside of the tre ring\n"); 619 break; 620 } 621 /* Get the TRB this event points to */ 622 ev_tre = mhi_to_virtual(tre_ring, ptr); 623 624 dev_rp = ev_tre + 1; 625 if (dev_rp >= (tre_ring->base + tre_ring->len)) 626 dev_rp = tre_ring->base; 627 628 result.dir = mhi_chan->dir; 629 630 local_rp = tre_ring->rp; 631 632 next_rp = local_rp + 1; 633 if (next_rp >= tre_ring->base + tre_ring->len) 634 next_rp = tre_ring->base; 635 if (dev_rp != next_rp && !MHI_TRE_DATA_GET_CHAIN(local_rp)) { 636 dev_err(&mhi_cntrl->mhi_dev->dev, 637 "Event element points to an unexpected TRE\n"); 638 break; 639 } 640 641 while (local_rp != dev_rp) { 642 buf_info = buf_ring->rp; 643 /* If it's the last TRE, get length from the event */ 644 if (local_rp == ev_tre) 645 xfer_len = MHI_TRE_GET_EV_LEN(event); 646 else 647 xfer_len = buf_info->len; 648 649 /* Unmap if it's not pre-mapped by client */ 650 if (likely(!buf_info->pre_mapped)) 651 mhi_cntrl->unmap_single(mhi_cntrl, buf_info); 652 653 result.buf_addr = buf_info->cb_buf; 654 655 /* truncate to buf len if xfer_len is larger */ 656 result.bytes_xferd = 657 min_t(u16, xfer_len, buf_info->len); 658 mhi_del_ring_element(mhi_cntrl, buf_ring); 659 mhi_del_ring_element(mhi_cntrl, tre_ring); 660 local_rp = tre_ring->rp; 661 662 read_unlock_bh(&mhi_chan->lock); 663 664 /* notify client */ 665 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); 666 667 if (mhi_chan->dir == DMA_TO_DEVICE) { 668 atomic_dec(&mhi_cntrl->pending_pkts); 669 /* Release the reference got from mhi_queue() */ 670 mhi_cntrl->runtime_put(mhi_cntrl); 671 } 672 673 read_lock_bh(&mhi_chan->lock); 674 } 675 break; 676 } /* CC_EOT */ 677 case MHI_EV_CC_OOB: 678 case MHI_EV_CC_DB_MODE: 679 { 680 unsigned long pm_lock_flags; 681 682 mhi_chan->db_cfg.db_mode = 1; 683 read_lock_irqsave(&mhi_cntrl->pm_lock, pm_lock_flags); 684 if (tre_ring->wp != tre_ring->rp && 685 MHI_DB_ACCESS_VALID(mhi_cntrl)) { 686 mhi_ring_chan_db(mhi_cntrl, mhi_chan); 687 } 688 read_unlock_irqrestore(&mhi_cntrl->pm_lock, pm_lock_flags); 689 break; 690 } 691 case MHI_EV_CC_BAD_TRE: 692 default: 693 dev_err(dev, "Unknown event 0x%x\n", ev_code); 694 break; 695 } /* switch(MHI_EV_READ_CODE(EV_TRB_CODE,event)) */ 696 697 end_process_tx_event: 698 if (ev_code >= MHI_EV_CC_OOB) 699 write_unlock_irqrestore(&mhi_chan->lock, flags); 700 else 701 read_unlock_bh(&mhi_chan->lock); 702 703 return 0; 704 } 705 706 static int parse_rsc_event(struct mhi_controller *mhi_cntrl, 707 struct mhi_ring_element *event, 708 struct mhi_chan *mhi_chan) 709 { 710 struct mhi_ring *buf_ring, *tre_ring; 711 struct mhi_buf_info *buf_info; 712 struct mhi_result result; 713 int ev_code; 714 u32 cookie; /* offset to local descriptor */ 715 u16 xfer_len; 716 717 buf_ring = &mhi_chan->buf_ring; 718 tre_ring = &mhi_chan->tre_ring; 719 720 ev_code = MHI_TRE_GET_EV_CODE(event); 721 cookie = MHI_TRE_GET_EV_COOKIE(event); 722 xfer_len = MHI_TRE_GET_EV_LEN(event); 723 724 /* Received out of bound cookie */ 725 WARN_ON(cookie >= buf_ring->len); 726 727 buf_info = buf_ring->base + cookie; 728 729 result.transaction_status = (ev_code == MHI_EV_CC_OVERFLOW) ? 730 -EOVERFLOW : 0; 731 732 /* truncate to buf len if xfer_len is larger */ 733 result.bytes_xferd = min_t(u16, xfer_len, buf_info->len); 734 result.buf_addr = buf_info->cb_buf; 735 result.dir = mhi_chan->dir; 736 737 read_lock_bh(&mhi_chan->lock); 738 739 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) 740 goto end_process_rsc_event; 741 742 WARN_ON(!buf_info->used); 743 744 /* notify the client */ 745 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); 746 747 /* 748 * Note: We're arbitrarily incrementing RP even though, completion 749 * packet we processed might not be the same one, reason we can do this 750 * is because device guaranteed to cache descriptors in order it 751 * receive, so even though completion event is different we can re-use 752 * all descriptors in between. 753 * Example: 754 * Transfer Ring has descriptors: A, B, C, D 755 * Last descriptor host queue is D (WP) and first descriptor 756 * host queue is A (RP). 757 * The completion event we just serviced is descriptor C. 758 * Then we can safely queue descriptors to replace A, B, and C 759 * even though host did not receive any completions. 760 */ 761 mhi_del_ring_element(mhi_cntrl, tre_ring); 762 buf_info->used = false; 763 764 end_process_rsc_event: 765 read_unlock_bh(&mhi_chan->lock); 766 767 return 0; 768 } 769 770 static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, 771 struct mhi_ring_element *tre) 772 { 773 dma_addr_t ptr = MHI_TRE_GET_EV_PTR(tre); 774 struct mhi_cmd *cmd_ring = &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; 775 struct mhi_ring *mhi_ring = &cmd_ring->ring; 776 struct mhi_ring_element *cmd_pkt; 777 struct mhi_chan *mhi_chan; 778 u32 chan; 779 780 if (!is_valid_ring_ptr(mhi_ring, ptr)) { 781 dev_err(&mhi_cntrl->mhi_dev->dev, 782 "Event element points outside of the cmd ring\n"); 783 return; 784 } 785 786 cmd_pkt = mhi_to_virtual(mhi_ring, ptr); 787 788 chan = MHI_TRE_GET_CMD_CHID(cmd_pkt); 789 790 if (chan < mhi_cntrl->max_chan && 791 mhi_cntrl->mhi_chan[chan].configured) { 792 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 793 write_lock_bh(&mhi_chan->lock); 794 mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre); 795 complete(&mhi_chan->completion); 796 write_unlock_bh(&mhi_chan->lock); 797 } else { 798 dev_err(&mhi_cntrl->mhi_dev->dev, 799 "Completion packet for invalid channel ID: %d\n", chan); 800 } 801 802 mhi_del_ring_element(mhi_cntrl, mhi_ring); 803 } 804 805 int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, 806 struct mhi_event *mhi_event, 807 u32 event_quota) 808 { 809 struct mhi_ring_element *dev_rp, *local_rp; 810 struct mhi_ring *ev_ring = &mhi_event->ring; 811 struct mhi_event_ctxt *er_ctxt = 812 &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; 813 struct mhi_chan *mhi_chan; 814 struct device *dev = &mhi_cntrl->mhi_dev->dev; 815 u32 chan; 816 int count = 0; 817 dma_addr_t ptr = le64_to_cpu(er_ctxt->rp); 818 819 /* 820 * This is a quick check to avoid unnecessary event processing 821 * in case MHI is already in error state, but it's still possible 822 * to transition to error state while processing events 823 */ 824 if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) 825 return -EIO; 826 827 if (!is_valid_ring_ptr(ev_ring, ptr)) { 828 dev_err(&mhi_cntrl->mhi_dev->dev, 829 "Event ring rp points outside of the event ring\n"); 830 return -EIO; 831 } 832 833 dev_rp = mhi_to_virtual(ev_ring, ptr); 834 local_rp = ev_ring->rp; 835 836 while (dev_rp != local_rp) { 837 enum mhi_pkt_type type = MHI_TRE_GET_EV_TYPE(local_rp); 838 839 trace_mhi_ctrl_event(mhi_cntrl, local_rp); 840 841 switch (type) { 842 case MHI_PKT_TYPE_BW_REQ_EVENT: 843 { 844 struct mhi_link_info *link_info; 845 846 link_info = &mhi_cntrl->mhi_link_info; 847 write_lock_irq(&mhi_cntrl->pm_lock); 848 link_info->target_link_speed = 849 MHI_TRE_GET_EV_LINKSPEED(local_rp); 850 link_info->target_link_width = 851 MHI_TRE_GET_EV_LINKWIDTH(local_rp); 852 write_unlock_irq(&mhi_cntrl->pm_lock); 853 dev_dbg(dev, "Received BW_REQ event\n"); 854 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_BW_REQ); 855 break; 856 } 857 case MHI_PKT_TYPE_STATE_CHANGE_EVENT: 858 { 859 enum mhi_state new_state; 860 861 new_state = MHI_TRE_GET_EV_STATE(local_rp); 862 863 dev_dbg(dev, "State change event to state: %s\n", 864 mhi_state_str(new_state)); 865 866 switch (new_state) { 867 case MHI_STATE_M0: 868 mhi_pm_m0_transition(mhi_cntrl); 869 break; 870 case MHI_STATE_M1: 871 mhi_pm_m1_transition(mhi_cntrl); 872 break; 873 case MHI_STATE_M3: 874 mhi_pm_m3_transition(mhi_cntrl); 875 break; 876 case MHI_STATE_SYS_ERR: 877 { 878 enum mhi_pm_state pm_state; 879 880 dev_dbg(dev, "System error detected\n"); 881 write_lock_irq(&mhi_cntrl->pm_lock); 882 pm_state = mhi_tryset_pm_state(mhi_cntrl, 883 MHI_PM_SYS_ERR_DETECT); 884 write_unlock_irq(&mhi_cntrl->pm_lock); 885 if (pm_state == MHI_PM_SYS_ERR_DETECT) 886 mhi_pm_sys_err_handler(mhi_cntrl); 887 break; 888 } 889 default: 890 dev_err(dev, "Invalid state: %s\n", 891 mhi_state_str(new_state)); 892 } 893 894 break; 895 } 896 case MHI_PKT_TYPE_CMD_COMPLETION_EVENT: 897 mhi_process_cmd_completion(mhi_cntrl, local_rp); 898 break; 899 case MHI_PKT_TYPE_EE_EVENT: 900 { 901 enum dev_st_transition st = DEV_ST_TRANSITION_MAX; 902 enum mhi_ee_type event = MHI_TRE_GET_EV_EXECENV(local_rp); 903 904 dev_dbg(dev, "Received EE event: %s\n", 905 TO_MHI_EXEC_STR(event)); 906 switch (event) { 907 case MHI_EE_SBL: 908 st = DEV_ST_TRANSITION_SBL; 909 break; 910 case MHI_EE_WFW: 911 case MHI_EE_AMSS: 912 st = DEV_ST_TRANSITION_MISSION_MODE; 913 break; 914 case MHI_EE_FP: 915 st = DEV_ST_TRANSITION_FP; 916 break; 917 case MHI_EE_RDDM: 918 mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_RDDM); 919 write_lock_irq(&mhi_cntrl->pm_lock); 920 mhi_cntrl->ee = event; 921 write_unlock_irq(&mhi_cntrl->pm_lock); 922 wake_up_all(&mhi_cntrl->state_event); 923 break; 924 default: 925 dev_err(dev, 926 "Unhandled EE event: 0x%x\n", type); 927 } 928 if (st != DEV_ST_TRANSITION_MAX) 929 mhi_queue_state_transition(mhi_cntrl, st); 930 931 break; 932 } 933 case MHI_PKT_TYPE_TX_EVENT: 934 chan = MHI_TRE_GET_EV_CHID(local_rp); 935 936 WARN_ON(chan >= mhi_cntrl->max_chan); 937 938 /* 939 * Only process the event ring elements whose channel 940 * ID is within the maximum supported range. 941 */ 942 if (chan < mhi_cntrl->max_chan) { 943 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 944 if (!mhi_chan->configured) 945 break; 946 parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); 947 } 948 break; 949 default: 950 dev_err(dev, "Unhandled event type: %d\n", type); 951 break; 952 } 953 954 mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); 955 local_rp = ev_ring->rp; 956 957 ptr = le64_to_cpu(er_ctxt->rp); 958 if (!is_valid_ring_ptr(ev_ring, ptr)) { 959 dev_err(&mhi_cntrl->mhi_dev->dev, 960 "Event ring rp points outside of the event ring\n"); 961 return -EIO; 962 } 963 964 dev_rp = mhi_to_virtual(ev_ring, ptr); 965 count++; 966 } 967 968 read_lock_bh(&mhi_cntrl->pm_lock); 969 970 /* Ring EV DB only if there is any pending element to process */ 971 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && count) 972 mhi_ring_er_db(mhi_event); 973 read_unlock_bh(&mhi_cntrl->pm_lock); 974 975 return count; 976 } 977 978 int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, 979 struct mhi_event *mhi_event, 980 u32 event_quota) 981 { 982 struct mhi_ring_element *dev_rp, *local_rp; 983 struct mhi_ring *ev_ring = &mhi_event->ring; 984 struct mhi_event_ctxt *er_ctxt = 985 &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; 986 int count = 0; 987 u32 chan; 988 struct mhi_chan *mhi_chan; 989 dma_addr_t ptr = le64_to_cpu(er_ctxt->rp); 990 991 if (unlikely(MHI_EVENT_ACCESS_INVALID(mhi_cntrl->pm_state))) 992 return -EIO; 993 994 if (!is_valid_ring_ptr(ev_ring, ptr)) { 995 dev_err(&mhi_cntrl->mhi_dev->dev, 996 "Event ring rp points outside of the event ring\n"); 997 return -EIO; 998 } 999 1000 dev_rp = mhi_to_virtual(ev_ring, ptr); 1001 local_rp = ev_ring->rp; 1002 1003 while (dev_rp != local_rp && event_quota > 0) { 1004 enum mhi_pkt_type type = MHI_TRE_GET_EV_TYPE(local_rp); 1005 1006 trace_mhi_data_event(mhi_cntrl, local_rp); 1007 1008 chan = MHI_TRE_GET_EV_CHID(local_rp); 1009 1010 WARN_ON(chan >= mhi_cntrl->max_chan); 1011 1012 /* 1013 * Only process the event ring elements whose channel 1014 * ID is within the maximum supported range. 1015 */ 1016 if (chan < mhi_cntrl->max_chan && 1017 mhi_cntrl->mhi_chan[chan].configured) { 1018 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 1019 1020 if (likely(type == MHI_PKT_TYPE_TX_EVENT)) { 1021 parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); 1022 event_quota--; 1023 } else if (type == MHI_PKT_TYPE_RSC_TX_EVENT) { 1024 parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); 1025 event_quota--; 1026 } 1027 } 1028 1029 mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); 1030 local_rp = ev_ring->rp; 1031 1032 ptr = le64_to_cpu(er_ctxt->rp); 1033 if (!is_valid_ring_ptr(ev_ring, ptr)) { 1034 dev_err(&mhi_cntrl->mhi_dev->dev, 1035 "Event ring rp points outside of the event ring\n"); 1036 return -EIO; 1037 } 1038 1039 dev_rp = mhi_to_virtual(ev_ring, ptr); 1040 count++; 1041 } 1042 read_lock_bh(&mhi_cntrl->pm_lock); 1043 1044 /* Ring EV DB only if there is any pending element to process */ 1045 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)) && count) 1046 mhi_ring_er_db(mhi_event); 1047 read_unlock_bh(&mhi_cntrl->pm_lock); 1048 1049 return count; 1050 } 1051 1052 void mhi_ev_task(unsigned long data) 1053 { 1054 struct mhi_event *mhi_event = (struct mhi_event *)data; 1055 struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; 1056 1057 /* process all pending events */ 1058 spin_lock_bh(&mhi_event->lock); 1059 mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); 1060 spin_unlock_bh(&mhi_event->lock); 1061 } 1062 1063 void mhi_ctrl_ev_task(unsigned long data) 1064 { 1065 struct mhi_event *mhi_event = (struct mhi_event *)data; 1066 struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; 1067 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1068 enum mhi_state state; 1069 enum mhi_pm_state pm_state = 0; 1070 int ret; 1071 1072 /* 1073 * We can check PM state w/o a lock here because there is no way 1074 * PM state can change from reg access valid to no access while this 1075 * thread being executed. 1076 */ 1077 if (!MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state)) { 1078 /* 1079 * We may have a pending event but not allowed to 1080 * process it since we are probably in a suspended state, 1081 * so trigger a resume. 1082 */ 1083 mhi_trigger_resume(mhi_cntrl); 1084 1085 return; 1086 } 1087 1088 /* Process ctrl events */ 1089 ret = mhi_event->process_event(mhi_cntrl, mhi_event, U32_MAX); 1090 1091 /* 1092 * We received an IRQ but no events to process, maybe device went to 1093 * SYS_ERR state? Check the state to confirm. 1094 */ 1095 if (!ret) { 1096 write_lock_irq(&mhi_cntrl->pm_lock); 1097 state = mhi_get_mhi_state(mhi_cntrl); 1098 if (state == MHI_STATE_SYS_ERR) { 1099 dev_dbg(dev, "System error detected\n"); 1100 pm_state = mhi_tryset_pm_state(mhi_cntrl, 1101 MHI_PM_SYS_ERR_DETECT); 1102 } 1103 write_unlock_irq(&mhi_cntrl->pm_lock); 1104 if (pm_state == MHI_PM_SYS_ERR_DETECT) 1105 mhi_pm_sys_err_handler(mhi_cntrl); 1106 } 1107 } 1108 1109 static bool mhi_is_ring_full(struct mhi_controller *mhi_cntrl, 1110 struct mhi_ring *ring) 1111 { 1112 void *tmp = ring->wp + ring->el_size; 1113 1114 if (tmp >= (ring->base + ring->len)) 1115 tmp = ring->base; 1116 1117 return (tmp == ring->rp); 1118 } 1119 1120 static int mhi_queue(struct mhi_device *mhi_dev, struct mhi_buf_info *buf_info, 1121 enum dma_data_direction dir, enum mhi_flags mflags) 1122 { 1123 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1124 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? mhi_dev->ul_chan : 1125 mhi_dev->dl_chan; 1126 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 1127 unsigned long flags; 1128 int ret; 1129 1130 if (unlikely(MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))) 1131 return -EIO; 1132 1133 ret = mhi_is_ring_full(mhi_cntrl, tre_ring); 1134 if (unlikely(ret)) 1135 return -EAGAIN; 1136 1137 ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf_info, mflags); 1138 if (unlikely(ret)) 1139 return ret; 1140 1141 read_lock_irqsave(&mhi_cntrl->pm_lock, flags); 1142 1143 /* Packet is queued, take a usage ref to exit M3 if necessary 1144 * for host->device buffer, balanced put is done on buffer completion 1145 * for device->host buffer, balanced put is after ringing the DB 1146 */ 1147 mhi_cntrl->runtime_get(mhi_cntrl); 1148 1149 /* Assert dev_wake (to exit/prevent M1/M2)*/ 1150 mhi_cntrl->wake_toggle(mhi_cntrl); 1151 1152 if (mhi_chan->dir == DMA_TO_DEVICE) 1153 atomic_inc(&mhi_cntrl->pending_pkts); 1154 1155 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) 1156 mhi_ring_chan_db(mhi_cntrl, mhi_chan); 1157 1158 if (dir == DMA_FROM_DEVICE) 1159 mhi_cntrl->runtime_put(mhi_cntrl); 1160 1161 read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); 1162 1163 return ret; 1164 } 1165 1166 int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, 1167 struct sk_buff *skb, size_t len, enum mhi_flags mflags) 1168 { 1169 struct mhi_buf_info buf_info = { }; 1170 1171 buf_info.v_addr = skb->data; 1172 buf_info.cb_buf = skb; 1173 buf_info.len = len; 1174 1175 return mhi_queue(mhi_dev, &buf_info, dir, mflags); 1176 } 1177 EXPORT_SYMBOL_GPL(mhi_queue_skb); 1178 1179 int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, 1180 struct mhi_buf_info *info, enum mhi_flags flags) 1181 { 1182 struct mhi_ring *buf_ring, *tre_ring; 1183 struct mhi_ring_element *mhi_tre; 1184 struct mhi_buf_info *buf_info; 1185 int eot, eob, chain, bei; 1186 int ret = 0; 1187 1188 /* Protect accesses for reading and incrementing WP */ 1189 write_lock_bh(&mhi_chan->lock); 1190 1191 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) { 1192 ret = -ENODEV; 1193 goto out; 1194 } 1195 1196 buf_ring = &mhi_chan->buf_ring; 1197 tre_ring = &mhi_chan->tre_ring; 1198 1199 buf_info = buf_ring->wp; 1200 WARN_ON(buf_info->used); 1201 buf_info->pre_mapped = info->pre_mapped; 1202 if (info->pre_mapped) 1203 buf_info->p_addr = info->p_addr; 1204 else 1205 buf_info->v_addr = info->v_addr; 1206 buf_info->cb_buf = info->cb_buf; 1207 buf_info->wp = tre_ring->wp; 1208 buf_info->dir = mhi_chan->dir; 1209 buf_info->len = info->len; 1210 1211 if (!info->pre_mapped) { 1212 ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); 1213 if (ret) 1214 goto out; 1215 } 1216 1217 eob = !!(flags & MHI_EOB); 1218 eot = !!(flags & MHI_EOT); 1219 chain = !!(flags & MHI_CHAIN); 1220 bei = !!(mhi_chan->intmod); 1221 1222 mhi_tre = tre_ring->wp; 1223 mhi_tre->ptr = MHI_TRE_DATA_PTR(buf_info->p_addr); 1224 mhi_tre->dword[0] = MHI_TRE_DATA_DWORD0(info->len); 1225 mhi_tre->dword[1] = MHI_TRE_DATA_DWORD1(bei, eot, eob, chain); 1226 1227 trace_mhi_gen_tre(mhi_cntrl, mhi_chan, mhi_tre); 1228 /* increment WP */ 1229 mhi_add_ring_element(mhi_cntrl, tre_ring); 1230 mhi_add_ring_element(mhi_cntrl, buf_ring); 1231 1232 out: 1233 write_unlock_bh(&mhi_chan->lock); 1234 1235 return ret; 1236 } 1237 1238 int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, 1239 void *buf, size_t len, enum mhi_flags mflags) 1240 { 1241 struct mhi_buf_info buf_info = { }; 1242 1243 buf_info.v_addr = buf; 1244 buf_info.cb_buf = buf; 1245 buf_info.len = len; 1246 1247 return mhi_queue(mhi_dev, &buf_info, dir, mflags); 1248 } 1249 EXPORT_SYMBOL_GPL(mhi_queue_buf); 1250 1251 bool mhi_queue_is_full(struct mhi_device *mhi_dev, enum dma_data_direction dir) 1252 { 1253 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1254 struct mhi_chan *mhi_chan = (dir == DMA_TO_DEVICE) ? 1255 mhi_dev->ul_chan : mhi_dev->dl_chan; 1256 struct mhi_ring *tre_ring = &mhi_chan->tre_ring; 1257 1258 return mhi_is_ring_full(mhi_cntrl, tre_ring); 1259 } 1260 EXPORT_SYMBOL_GPL(mhi_queue_is_full); 1261 1262 int mhi_send_cmd(struct mhi_controller *mhi_cntrl, 1263 struct mhi_chan *mhi_chan, 1264 enum mhi_cmd_type cmd) 1265 { 1266 struct mhi_ring_element *cmd_tre = NULL; 1267 struct mhi_cmd *mhi_cmd = &mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING]; 1268 struct mhi_ring *ring = &mhi_cmd->ring; 1269 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1270 int chan = 0; 1271 1272 if (mhi_chan) 1273 chan = mhi_chan->chan; 1274 1275 spin_lock_bh(&mhi_cmd->lock); 1276 if (!get_nr_avail_ring_elements(mhi_cntrl, ring)) { 1277 spin_unlock_bh(&mhi_cmd->lock); 1278 return -ENOMEM; 1279 } 1280 1281 /* prepare the cmd tre */ 1282 cmd_tre = ring->wp; 1283 switch (cmd) { 1284 case MHI_CMD_RESET_CHAN: 1285 cmd_tre->ptr = MHI_TRE_CMD_RESET_PTR; 1286 cmd_tre->dword[0] = MHI_TRE_CMD_RESET_DWORD0; 1287 cmd_tre->dword[1] = MHI_TRE_CMD_RESET_DWORD1(chan); 1288 break; 1289 case MHI_CMD_STOP_CHAN: 1290 cmd_tre->ptr = MHI_TRE_CMD_STOP_PTR; 1291 cmd_tre->dword[0] = MHI_TRE_CMD_STOP_DWORD0; 1292 cmd_tre->dword[1] = MHI_TRE_CMD_STOP_DWORD1(chan); 1293 break; 1294 case MHI_CMD_START_CHAN: 1295 cmd_tre->ptr = MHI_TRE_CMD_START_PTR; 1296 cmd_tre->dword[0] = MHI_TRE_CMD_START_DWORD0; 1297 cmd_tre->dword[1] = MHI_TRE_CMD_START_DWORD1(chan); 1298 break; 1299 default: 1300 dev_err(dev, "Command not supported\n"); 1301 break; 1302 } 1303 1304 /* queue to hardware */ 1305 mhi_add_ring_element(mhi_cntrl, ring); 1306 read_lock_bh(&mhi_cntrl->pm_lock); 1307 if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl))) 1308 mhi_ring_cmd_db(mhi_cntrl, mhi_cmd); 1309 read_unlock_bh(&mhi_cntrl->pm_lock); 1310 spin_unlock_bh(&mhi_cmd->lock); 1311 1312 return 0; 1313 } 1314 1315 static int mhi_update_channel_state(struct mhi_controller *mhi_cntrl, 1316 struct mhi_chan *mhi_chan, 1317 enum mhi_ch_state_type to_state) 1318 { 1319 struct device *dev = &mhi_chan->mhi_dev->dev; 1320 enum mhi_cmd_type cmd = MHI_CMD_NOP; 1321 int ret; 1322 1323 trace_mhi_channel_command_start(mhi_cntrl, mhi_chan, to_state, TPS("Updating")); 1324 switch (to_state) { 1325 case MHI_CH_STATE_TYPE_RESET: 1326 write_lock_irq(&mhi_chan->lock); 1327 if (mhi_chan->ch_state != MHI_CH_STATE_STOP && 1328 mhi_chan->ch_state != MHI_CH_STATE_ENABLED && 1329 mhi_chan->ch_state != MHI_CH_STATE_SUSPENDED) { 1330 write_unlock_irq(&mhi_chan->lock); 1331 return -EINVAL; 1332 } 1333 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 1334 write_unlock_irq(&mhi_chan->lock); 1335 1336 cmd = MHI_CMD_RESET_CHAN; 1337 break; 1338 case MHI_CH_STATE_TYPE_STOP: 1339 if (mhi_chan->ch_state != MHI_CH_STATE_ENABLED) 1340 return -EINVAL; 1341 1342 cmd = MHI_CMD_STOP_CHAN; 1343 break; 1344 case MHI_CH_STATE_TYPE_START: 1345 if (mhi_chan->ch_state != MHI_CH_STATE_STOP && 1346 mhi_chan->ch_state != MHI_CH_STATE_DISABLED) 1347 return -EINVAL; 1348 1349 cmd = MHI_CMD_START_CHAN; 1350 break; 1351 default: 1352 dev_err(dev, "%d: Channel state update to %s not allowed\n", 1353 mhi_chan->chan, TO_CH_STATE_TYPE_STR(to_state)); 1354 return -EINVAL; 1355 } 1356 1357 /* bring host and device out of suspended states */ 1358 ret = mhi_device_get_sync(mhi_cntrl->mhi_dev); 1359 if (ret) 1360 return ret; 1361 mhi_cntrl->runtime_get(mhi_cntrl); 1362 1363 reinit_completion(&mhi_chan->completion); 1364 ret = mhi_send_cmd(mhi_cntrl, mhi_chan, cmd); 1365 if (ret) { 1366 dev_err(dev, "%d: Failed to send %s channel command\n", 1367 mhi_chan->chan, TO_CH_STATE_TYPE_STR(to_state)); 1368 goto exit_channel_update; 1369 } 1370 1371 ret = wait_for_completion_timeout(&mhi_chan->completion, 1372 msecs_to_jiffies(mhi_cntrl->timeout_ms)); 1373 if (!ret || mhi_chan->ccs != MHI_EV_CC_SUCCESS) { 1374 dev_err(dev, 1375 "%d: Failed to receive %s channel command completion\n", 1376 mhi_chan->chan, TO_CH_STATE_TYPE_STR(to_state)); 1377 ret = -EIO; 1378 goto exit_channel_update; 1379 } 1380 1381 ret = 0; 1382 1383 if (to_state != MHI_CH_STATE_TYPE_RESET) { 1384 write_lock_irq(&mhi_chan->lock); 1385 mhi_chan->ch_state = (to_state == MHI_CH_STATE_TYPE_START) ? 1386 MHI_CH_STATE_ENABLED : MHI_CH_STATE_STOP; 1387 write_unlock_irq(&mhi_chan->lock); 1388 } 1389 1390 trace_mhi_channel_command_end(mhi_cntrl, mhi_chan, to_state, TPS("Updated")); 1391 exit_channel_update: 1392 mhi_cntrl->runtime_put(mhi_cntrl); 1393 mhi_device_put(mhi_cntrl->mhi_dev); 1394 1395 return ret; 1396 } 1397 1398 static void mhi_unprepare_channel(struct mhi_controller *mhi_cntrl, 1399 struct mhi_chan *mhi_chan) 1400 { 1401 int ret; 1402 struct device *dev = &mhi_chan->mhi_dev->dev; 1403 1404 mutex_lock(&mhi_chan->mutex); 1405 1406 if (!(BIT(mhi_cntrl->ee) & mhi_chan->ee_mask)) { 1407 dev_dbg(dev, "Current EE: %s Required EE Mask: 0x%x\n", 1408 TO_MHI_EXEC_STR(mhi_cntrl->ee), mhi_chan->ee_mask); 1409 goto exit_unprepare_channel; 1410 } 1411 1412 /* no more processing events for this channel */ 1413 ret = mhi_update_channel_state(mhi_cntrl, mhi_chan, 1414 MHI_CH_STATE_TYPE_RESET); 1415 if (ret) 1416 dev_err(dev, "%d: Failed to reset channel, still resetting\n", 1417 mhi_chan->chan); 1418 1419 exit_unprepare_channel: 1420 write_lock_irq(&mhi_chan->lock); 1421 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 1422 write_unlock_irq(&mhi_chan->lock); 1423 1424 if (!mhi_chan->offload_ch) { 1425 mhi_reset_chan(mhi_cntrl, mhi_chan); 1426 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); 1427 } 1428 dev_dbg(dev, "%d: successfully reset\n", mhi_chan->chan); 1429 1430 mutex_unlock(&mhi_chan->mutex); 1431 } 1432 1433 static int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, 1434 struct mhi_chan *mhi_chan, unsigned int flags) 1435 { 1436 int ret = 0; 1437 struct device *dev = &mhi_chan->mhi_dev->dev; 1438 1439 if (!(BIT(mhi_cntrl->ee) & mhi_chan->ee_mask)) { 1440 dev_err(dev, "Current EE: %s Required EE Mask: 0x%x\n", 1441 TO_MHI_EXEC_STR(mhi_cntrl->ee), mhi_chan->ee_mask); 1442 return -ENOTCONN; 1443 } 1444 1445 mutex_lock(&mhi_chan->mutex); 1446 1447 /* Check of client manages channel context for offload channels */ 1448 if (!mhi_chan->offload_ch) { 1449 ret = mhi_init_chan_ctxt(mhi_cntrl, mhi_chan); 1450 if (ret) 1451 goto error_init_chan; 1452 } 1453 1454 ret = mhi_update_channel_state(mhi_cntrl, mhi_chan, 1455 MHI_CH_STATE_TYPE_START); 1456 if (ret) 1457 goto error_pm_state; 1458 1459 mutex_unlock(&mhi_chan->mutex); 1460 1461 return 0; 1462 1463 error_pm_state: 1464 if (!mhi_chan->offload_ch) 1465 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); 1466 1467 error_init_chan: 1468 mutex_unlock(&mhi_chan->mutex); 1469 1470 return ret; 1471 } 1472 1473 static void mhi_mark_stale_events(struct mhi_controller *mhi_cntrl, 1474 struct mhi_event *mhi_event, 1475 struct mhi_event_ctxt *er_ctxt, 1476 int chan) 1477 1478 { 1479 struct mhi_ring_element *dev_rp, *local_rp; 1480 struct mhi_ring *ev_ring; 1481 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1482 unsigned long flags; 1483 dma_addr_t ptr; 1484 1485 dev_dbg(dev, "Marking all events for chan: %d as stale\n", chan); 1486 1487 ev_ring = &mhi_event->ring; 1488 1489 /* mark all stale events related to channel as STALE event */ 1490 spin_lock_irqsave(&mhi_event->lock, flags); 1491 1492 ptr = le64_to_cpu(er_ctxt->rp); 1493 if (!is_valid_ring_ptr(ev_ring, ptr)) { 1494 dev_err(&mhi_cntrl->mhi_dev->dev, 1495 "Event ring rp points outside of the event ring\n"); 1496 dev_rp = ev_ring->rp; 1497 } else { 1498 dev_rp = mhi_to_virtual(ev_ring, ptr); 1499 } 1500 1501 local_rp = ev_ring->rp; 1502 while (dev_rp != local_rp) { 1503 if (MHI_TRE_GET_EV_TYPE(local_rp) == MHI_PKT_TYPE_TX_EVENT && 1504 chan == MHI_TRE_GET_EV_CHID(local_rp)) 1505 local_rp->dword[1] = MHI_TRE_EV_DWORD1(chan, 1506 MHI_PKT_TYPE_STALE_EVENT); 1507 local_rp++; 1508 if (local_rp == (ev_ring->base + ev_ring->len)) 1509 local_rp = ev_ring->base; 1510 } 1511 1512 dev_dbg(dev, "Finished marking events as stale events\n"); 1513 spin_unlock_irqrestore(&mhi_event->lock, flags); 1514 } 1515 1516 static void mhi_reset_data_chan(struct mhi_controller *mhi_cntrl, 1517 struct mhi_chan *mhi_chan) 1518 { 1519 struct mhi_ring *buf_ring, *tre_ring; 1520 struct mhi_result result; 1521 1522 /* Reset any pending buffers */ 1523 buf_ring = &mhi_chan->buf_ring; 1524 tre_ring = &mhi_chan->tre_ring; 1525 result.transaction_status = -ENOTCONN; 1526 result.bytes_xferd = 0; 1527 while (tre_ring->rp != tre_ring->wp) { 1528 struct mhi_buf_info *buf_info = buf_ring->rp; 1529 1530 if (mhi_chan->dir == DMA_TO_DEVICE) { 1531 atomic_dec(&mhi_cntrl->pending_pkts); 1532 /* Release the reference got from mhi_queue() */ 1533 mhi_cntrl->runtime_put(mhi_cntrl); 1534 } 1535 1536 if (!buf_info->pre_mapped) 1537 mhi_cntrl->unmap_single(mhi_cntrl, buf_info); 1538 1539 mhi_del_ring_element(mhi_cntrl, buf_ring); 1540 mhi_del_ring_element(mhi_cntrl, tre_ring); 1541 1542 result.buf_addr = buf_info->cb_buf; 1543 mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); 1544 } 1545 } 1546 1547 void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan) 1548 { 1549 struct mhi_event *mhi_event; 1550 struct mhi_event_ctxt *er_ctxt; 1551 int chan = mhi_chan->chan; 1552 1553 /* Nothing to reset, client doesn't queue buffers */ 1554 if (mhi_chan->offload_ch) 1555 return; 1556 1557 read_lock_bh(&mhi_cntrl->pm_lock); 1558 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; 1559 er_ctxt = &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_chan->er_index]; 1560 1561 mhi_mark_stale_events(mhi_cntrl, mhi_event, er_ctxt, chan); 1562 1563 mhi_reset_data_chan(mhi_cntrl, mhi_chan); 1564 1565 read_unlock_bh(&mhi_cntrl->pm_lock); 1566 } 1567 1568 static int __mhi_prepare_for_transfer(struct mhi_device *mhi_dev, unsigned int flags) 1569 { 1570 int ret, dir; 1571 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1572 struct mhi_chan *mhi_chan; 1573 1574 for (dir = 0; dir < 2; dir++) { 1575 mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; 1576 if (!mhi_chan) 1577 continue; 1578 1579 ret = mhi_prepare_channel(mhi_cntrl, mhi_chan, flags); 1580 if (ret) 1581 goto error_open_chan; 1582 } 1583 1584 return 0; 1585 1586 error_open_chan: 1587 for (--dir; dir >= 0; dir--) { 1588 mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; 1589 if (!mhi_chan) 1590 continue; 1591 1592 mhi_unprepare_channel(mhi_cntrl, mhi_chan); 1593 } 1594 1595 return ret; 1596 } 1597 1598 int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) 1599 { 1600 return __mhi_prepare_for_transfer(mhi_dev, 0); 1601 } 1602 EXPORT_SYMBOL_GPL(mhi_prepare_for_transfer); 1603 1604 void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev) 1605 { 1606 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1607 struct mhi_chan *mhi_chan; 1608 int dir; 1609 1610 for (dir = 0; dir < 2; dir++) { 1611 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; 1612 if (!mhi_chan) 1613 continue; 1614 1615 mhi_unprepare_channel(mhi_cntrl, mhi_chan); 1616 } 1617 } 1618 EXPORT_SYMBOL_GPL(mhi_unprepare_from_transfer); 1619 1620 int mhi_get_channel_doorbell_offset(struct mhi_controller *mhi_cntrl, u32 *chdb_offset) 1621 { 1622 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1623 void __iomem *base = mhi_cntrl->regs; 1624 int ret; 1625 1626 ret = mhi_read_reg(mhi_cntrl, base, CHDBOFF, chdb_offset); 1627 if (ret) { 1628 dev_err(dev, "Unable to read CHDBOFF register\n"); 1629 return -EIO; 1630 } 1631 1632 return 0; 1633 } 1634 EXPORT_SYMBOL_GPL(mhi_get_channel_doorbell_offset); 1635