1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/debugfs.h> 9 #include <linux/device.h> 10 #include <linux/dma-direction.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/idr.h> 13 #include <linux/interrupt.h> 14 #include <linux/list.h> 15 #include <linux/mhi.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/vmalloc.h> 20 #include <linux/wait.h> 21 #include "internal.h" 22 23 static DEFINE_IDA(mhi_controller_ida); 24 25 const char * const mhi_ee_str[MHI_EE_MAX] = { 26 [MHI_EE_PBL] = "PRIMARY BOOTLOADER", 27 [MHI_EE_SBL] = "SECONDARY BOOTLOADER", 28 [MHI_EE_AMSS] = "MISSION MODE", 29 [MHI_EE_RDDM] = "RAMDUMP DOWNLOAD MODE", 30 [MHI_EE_WFW] = "WLAN FIRMWARE", 31 [MHI_EE_PTHRU] = "PASS THROUGH", 32 [MHI_EE_EDL] = "EMERGENCY DOWNLOAD", 33 [MHI_EE_FP] = "FLASH PROGRAMMER", 34 [MHI_EE_DISABLE_TRANSITION] = "DISABLE", 35 [MHI_EE_NOT_SUPPORTED] = "NOT SUPPORTED", 36 }; 37 38 const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = { 39 [DEV_ST_TRANSITION_PBL] = "PBL", 40 [DEV_ST_TRANSITION_READY] = "READY", 41 [DEV_ST_TRANSITION_SBL] = "SBL", 42 [DEV_ST_TRANSITION_MISSION_MODE] = "MISSION MODE", 43 [DEV_ST_TRANSITION_FP] = "FLASH PROGRAMMER", 44 [DEV_ST_TRANSITION_SYS_ERR] = "SYS ERROR", 45 [DEV_ST_TRANSITION_DISABLE] = "DISABLE", 46 }; 47 48 const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = { 49 [MHI_CH_STATE_TYPE_RESET] = "RESET", 50 [MHI_CH_STATE_TYPE_STOP] = "STOP", 51 [MHI_CH_STATE_TYPE_START] = "START", 52 }; 53 54 static const char * const mhi_pm_state_str[] = { 55 [MHI_PM_STATE_DISABLE] = "DISABLE", 56 [MHI_PM_STATE_POR] = "POWER ON RESET", 57 [MHI_PM_STATE_M0] = "M0", 58 [MHI_PM_STATE_M2] = "M2", 59 [MHI_PM_STATE_M3_ENTER] = "M?->M3", 60 [MHI_PM_STATE_M3] = "M3", 61 [MHI_PM_STATE_M3_EXIT] = "M3->M0", 62 [MHI_PM_STATE_FW_DL_ERR] = "Firmware Download Error", 63 [MHI_PM_STATE_SYS_ERR_DETECT] = "SYS ERROR Detect", 64 [MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS ERROR Process", 65 [MHI_PM_STATE_SHUTDOWN_PROCESS] = "SHUTDOWN Process", 66 [MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "Linkdown or Error Fatal Detect", 67 }; 68 69 const char *to_mhi_pm_state_str(u32 state) 70 { 71 int index; 72 73 if (state) 74 index = __fls(state); 75 76 if (!state || index >= ARRAY_SIZE(mhi_pm_state_str)) 77 return "Invalid State"; 78 79 return mhi_pm_state_str[index]; 80 } 81 82 static ssize_t serial_number_show(struct device *dev, 83 struct device_attribute *attr, 84 char *buf) 85 { 86 struct mhi_device *mhi_dev = to_mhi_device(dev); 87 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 88 89 return sysfs_emit(buf, "Serial Number: %u\n", 90 mhi_cntrl->serial_number); 91 } 92 static DEVICE_ATTR_RO(serial_number); 93 94 static ssize_t oem_pk_hash_show(struct device *dev, 95 struct device_attribute *attr, 96 char *buf) 97 { 98 struct mhi_device *mhi_dev = to_mhi_device(dev); 99 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 100 int i, cnt = 0; 101 102 for (i = 0; i < ARRAY_SIZE(mhi_cntrl->oem_pk_hash); i++) 103 cnt += sysfs_emit_at(buf, cnt, "OEMPKHASH[%d]: 0x%x\n", 104 i, mhi_cntrl->oem_pk_hash[i]); 105 106 return cnt; 107 } 108 static DEVICE_ATTR_RO(oem_pk_hash); 109 110 static ssize_t soc_reset_store(struct device *dev, 111 struct device_attribute *attr, 112 const char *buf, 113 size_t count) 114 { 115 struct mhi_device *mhi_dev = to_mhi_device(dev); 116 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 117 118 mhi_soc_reset(mhi_cntrl); 119 return count; 120 } 121 static DEVICE_ATTR_WO(soc_reset); 122 123 static struct attribute *mhi_dev_attrs[] = { 124 &dev_attr_serial_number.attr, 125 &dev_attr_oem_pk_hash.attr, 126 &dev_attr_soc_reset.attr, 127 NULL, 128 }; 129 ATTRIBUTE_GROUPS(mhi_dev); 130 131 /* MHI protocol requires the transfer ring to be aligned with ring length */ 132 static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl, 133 struct mhi_ring *ring, 134 u64 len) 135 { 136 ring->alloc_size = len + (len - 1); 137 ring->pre_aligned = dma_alloc_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 138 &ring->dma_handle, GFP_KERNEL); 139 if (!ring->pre_aligned) 140 return -ENOMEM; 141 142 ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1); 143 ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle); 144 145 return 0; 146 } 147 148 void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl) 149 { 150 int i; 151 struct mhi_event *mhi_event = mhi_cntrl->mhi_event; 152 153 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 154 if (mhi_event->offload_ev) 155 continue; 156 157 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); 158 } 159 160 free_irq(mhi_cntrl->irq[0], mhi_cntrl); 161 } 162 163 int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl) 164 { 165 struct mhi_event *mhi_event = mhi_cntrl->mhi_event; 166 struct device *dev = &mhi_cntrl->mhi_dev->dev; 167 unsigned long irq_flags = IRQF_SHARED | IRQF_NO_SUSPEND; 168 int i, ret; 169 170 /* if controller driver has set irq_flags, use it */ 171 if (mhi_cntrl->irq_flags) 172 irq_flags = mhi_cntrl->irq_flags; 173 174 /* Setup BHI_INTVEC IRQ */ 175 ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler, 176 mhi_intvec_threaded_handler, 177 irq_flags, 178 "bhi", mhi_cntrl); 179 if (ret) 180 return ret; 181 /* 182 * IRQs should be enabled during mhi_async_power_up(), so disable them explicitly here. 183 * Due to the use of IRQF_SHARED flag as default while requesting IRQs, we assume that 184 * IRQ_NOAUTOEN is not applicable. 185 */ 186 disable_irq(mhi_cntrl->irq[0]); 187 188 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 189 if (mhi_event->offload_ev) 190 continue; 191 192 if (mhi_event->irq >= mhi_cntrl->nr_irqs) { 193 dev_err(dev, "irq %d not available for event ring\n", 194 mhi_event->irq); 195 ret = -EINVAL; 196 goto error_request; 197 } 198 199 ret = request_irq(mhi_cntrl->irq[mhi_event->irq], 200 mhi_irq_handler, 201 irq_flags, 202 "mhi", mhi_event); 203 if (ret) { 204 dev_err(dev, "Error requesting irq:%d for ev:%d\n", 205 mhi_cntrl->irq[mhi_event->irq], i); 206 goto error_request; 207 } 208 209 disable_irq(mhi_cntrl->irq[mhi_event->irq]); 210 } 211 212 return 0; 213 214 error_request: 215 for (--i, --mhi_event; i >= 0; i--, mhi_event--) { 216 if (mhi_event->offload_ev) 217 continue; 218 219 free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); 220 } 221 free_irq(mhi_cntrl->irq[0], mhi_cntrl); 222 223 return ret; 224 } 225 226 void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl) 227 { 228 int i; 229 struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt; 230 struct mhi_cmd *mhi_cmd; 231 struct mhi_event *mhi_event; 232 struct mhi_ring *ring; 233 234 mhi_cmd = mhi_cntrl->mhi_cmd; 235 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) { 236 ring = &mhi_cmd->ring; 237 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 238 ring->pre_aligned, ring->dma_handle); 239 ring->base = NULL; 240 ring->iommu_base = 0; 241 } 242 243 dma_free_coherent(mhi_cntrl->cntrl_dev, 244 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS, 245 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr); 246 247 mhi_event = mhi_cntrl->mhi_event; 248 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 249 if (mhi_event->offload_ev) 250 continue; 251 252 ring = &mhi_event->ring; 253 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 254 ring->pre_aligned, ring->dma_handle); 255 ring->base = NULL; 256 ring->iommu_base = 0; 257 } 258 259 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) * 260 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt, 261 mhi_ctxt->er_ctxt_addr); 262 263 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) * 264 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt, 265 mhi_ctxt->chan_ctxt_addr); 266 267 kfree(mhi_ctxt); 268 mhi_cntrl->mhi_ctxt = NULL; 269 } 270 271 int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) 272 { 273 struct mhi_ctxt *mhi_ctxt; 274 struct mhi_chan_ctxt *chan_ctxt; 275 struct mhi_event_ctxt *er_ctxt; 276 struct mhi_cmd_ctxt *cmd_ctxt; 277 struct mhi_chan *mhi_chan; 278 struct mhi_event *mhi_event; 279 struct mhi_cmd *mhi_cmd; 280 u32 tmp; 281 int ret = -ENOMEM, i; 282 283 atomic_set(&mhi_cntrl->dev_wake, 0); 284 atomic_set(&mhi_cntrl->pending_pkts, 0); 285 286 mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), GFP_KERNEL); 287 if (!mhi_ctxt) 288 return -ENOMEM; 289 290 /* Setup channel ctxt */ 291 mhi_ctxt->chan_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev, 292 sizeof(*mhi_ctxt->chan_ctxt) * 293 mhi_cntrl->max_chan, 294 &mhi_ctxt->chan_ctxt_addr, 295 GFP_KERNEL); 296 if (!mhi_ctxt->chan_ctxt) 297 goto error_alloc_chan_ctxt; 298 299 mhi_chan = mhi_cntrl->mhi_chan; 300 chan_ctxt = mhi_ctxt->chan_ctxt; 301 for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) { 302 /* Skip if it is an offload channel */ 303 if (mhi_chan->offload_ch) 304 continue; 305 306 tmp = le32_to_cpu(chan_ctxt->chcfg); 307 tmp &= ~CHAN_CTX_CHSTATE_MASK; 308 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED); 309 tmp &= ~CHAN_CTX_BRSTMODE_MASK; 310 tmp |= FIELD_PREP(CHAN_CTX_BRSTMODE_MASK, mhi_chan->db_cfg.brstmode); 311 tmp &= ~CHAN_CTX_POLLCFG_MASK; 312 tmp |= FIELD_PREP(CHAN_CTX_POLLCFG_MASK, mhi_chan->db_cfg.pollcfg); 313 chan_ctxt->chcfg = cpu_to_le32(tmp); 314 315 chan_ctxt->chtype = cpu_to_le32(mhi_chan->type); 316 chan_ctxt->erindex = cpu_to_le32(mhi_chan->er_index); 317 318 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 319 mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp; 320 } 321 322 /* Setup event context */ 323 mhi_ctxt->er_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev, 324 sizeof(*mhi_ctxt->er_ctxt) * 325 mhi_cntrl->total_ev_rings, 326 &mhi_ctxt->er_ctxt_addr, 327 GFP_KERNEL); 328 if (!mhi_ctxt->er_ctxt) 329 goto error_alloc_er_ctxt; 330 331 er_ctxt = mhi_ctxt->er_ctxt; 332 mhi_event = mhi_cntrl->mhi_event; 333 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, 334 mhi_event++) { 335 struct mhi_ring *ring = &mhi_event->ring; 336 337 /* Skip if it is an offload event */ 338 if (mhi_event->offload_ev) 339 continue; 340 341 tmp = le32_to_cpu(er_ctxt->intmod); 342 tmp &= ~EV_CTX_INTMODC_MASK; 343 tmp &= ~EV_CTX_INTMODT_MASK; 344 tmp |= FIELD_PREP(EV_CTX_INTMODT_MASK, mhi_event->intmod); 345 er_ctxt->intmod = cpu_to_le32(tmp); 346 347 er_ctxt->ertype = cpu_to_le32(MHI_ER_TYPE_VALID); 348 er_ctxt->msivec = cpu_to_le32(mhi_event->irq); 349 mhi_event->db_cfg.db_mode = true; 350 351 ring->el_size = sizeof(struct mhi_ring_element); 352 ring->len = ring->el_size * ring->elements; 353 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len); 354 if (ret) 355 goto error_alloc_er; 356 357 /* 358 * If the read pointer equals to the write pointer, then the 359 * ring is empty 360 */ 361 ring->rp = ring->wp = ring->base; 362 er_ctxt->rbase = cpu_to_le64(ring->iommu_base); 363 er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase; 364 er_ctxt->rlen = cpu_to_le64(ring->len); 365 ring->ctxt_wp = &er_ctxt->wp; 366 } 367 368 /* Setup cmd context */ 369 ret = -ENOMEM; 370 mhi_ctxt->cmd_ctxt = dma_alloc_coherent(mhi_cntrl->cntrl_dev, 371 sizeof(*mhi_ctxt->cmd_ctxt) * 372 NR_OF_CMD_RINGS, 373 &mhi_ctxt->cmd_ctxt_addr, 374 GFP_KERNEL); 375 if (!mhi_ctxt->cmd_ctxt) 376 goto error_alloc_er; 377 378 mhi_cmd = mhi_cntrl->mhi_cmd; 379 cmd_ctxt = mhi_ctxt->cmd_ctxt; 380 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++, cmd_ctxt++) { 381 struct mhi_ring *ring = &mhi_cmd->ring; 382 383 ring->el_size = sizeof(struct mhi_ring_element); 384 ring->elements = CMD_EL_PER_RING; 385 ring->len = ring->el_size * ring->elements; 386 ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len); 387 if (ret) 388 goto error_alloc_cmd; 389 390 ring->rp = ring->wp = ring->base; 391 cmd_ctxt->rbase = cpu_to_le64(ring->iommu_base); 392 cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase; 393 cmd_ctxt->rlen = cpu_to_le64(ring->len); 394 ring->ctxt_wp = &cmd_ctxt->wp; 395 } 396 397 mhi_cntrl->mhi_ctxt = mhi_ctxt; 398 399 return 0; 400 401 error_alloc_cmd: 402 for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) { 403 struct mhi_ring *ring = &mhi_cmd->ring; 404 405 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 406 ring->pre_aligned, ring->dma_handle); 407 } 408 dma_free_coherent(mhi_cntrl->cntrl_dev, 409 sizeof(*mhi_ctxt->cmd_ctxt) * NR_OF_CMD_RINGS, 410 mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr); 411 i = mhi_cntrl->total_ev_rings; 412 mhi_event = mhi_cntrl->mhi_event + i; 413 414 error_alloc_er: 415 for (--i, --mhi_event; i >= 0; i--, mhi_event--) { 416 struct mhi_ring *ring = &mhi_event->ring; 417 418 if (mhi_event->offload_ev) 419 continue; 420 421 dma_free_coherent(mhi_cntrl->cntrl_dev, ring->alloc_size, 422 ring->pre_aligned, ring->dma_handle); 423 } 424 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->er_ctxt) * 425 mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt, 426 mhi_ctxt->er_ctxt_addr); 427 428 error_alloc_er_ctxt: 429 dma_free_coherent(mhi_cntrl->cntrl_dev, sizeof(*mhi_ctxt->chan_ctxt) * 430 mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt, 431 mhi_ctxt->chan_ctxt_addr); 432 433 error_alloc_chan_ctxt: 434 kfree(mhi_ctxt); 435 436 return ret; 437 } 438 439 int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 440 { 441 u32 val; 442 int i, ret; 443 struct mhi_chan *mhi_chan; 444 struct mhi_event *mhi_event; 445 void __iomem *base = mhi_cntrl->regs; 446 struct device *dev = &mhi_cntrl->mhi_dev->dev; 447 struct { 448 u32 offset; 449 u32 val; 450 } reg_info[] = { 451 { 452 CCABAP_HIGHER, 453 upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr), 454 }, 455 { 456 CCABAP_LOWER, 457 lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr), 458 }, 459 { 460 ECABAP_HIGHER, 461 upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr), 462 }, 463 { 464 ECABAP_LOWER, 465 lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr), 466 }, 467 { 468 CRCBAP_HIGHER, 469 upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr), 470 }, 471 { 472 CRCBAP_LOWER, 473 lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr), 474 }, 475 { 476 MHICTRLBASE_HIGHER, 477 upper_32_bits(mhi_cntrl->iova_start), 478 }, 479 { 480 MHICTRLBASE_LOWER, 481 lower_32_bits(mhi_cntrl->iova_start), 482 }, 483 { 484 MHIDATABASE_HIGHER, 485 upper_32_bits(mhi_cntrl->iova_start), 486 }, 487 { 488 MHIDATABASE_LOWER, 489 lower_32_bits(mhi_cntrl->iova_start), 490 }, 491 { 492 MHICTRLLIMIT_HIGHER, 493 upper_32_bits(mhi_cntrl->iova_stop), 494 }, 495 { 496 MHICTRLLIMIT_LOWER, 497 lower_32_bits(mhi_cntrl->iova_stop), 498 }, 499 { 500 MHIDATALIMIT_HIGHER, 501 upper_32_bits(mhi_cntrl->iova_stop), 502 }, 503 { 504 MHIDATALIMIT_LOWER, 505 lower_32_bits(mhi_cntrl->iova_stop), 506 }, 507 {0, 0} 508 }; 509 510 dev_dbg(dev, "Initializing MHI registers\n"); 511 512 /* Read channel db offset */ 513 ret = mhi_read_reg(mhi_cntrl, base, CHDBOFF, &val); 514 if (ret) { 515 dev_err(dev, "Unable to read CHDBOFF register\n"); 516 return -EIO; 517 } 518 519 if (val >= mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)) { 520 dev_err(dev, "CHDB offset: 0x%x is out of range: 0x%zx\n", 521 val, mhi_cntrl->reg_len - (8 * MHI_DEV_WAKE_DB)); 522 return -ERANGE; 523 } 524 525 /* Setup wake db */ 526 mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB); 527 mhi_cntrl->wake_set = false; 528 529 /* Setup channel db address for each channel in tre_ring */ 530 mhi_chan = mhi_cntrl->mhi_chan; 531 for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++) 532 mhi_chan->tre_ring.db_addr = base + val; 533 534 /* Read event ring db offset */ 535 ret = mhi_read_reg(mhi_cntrl, base, ERDBOFF, &val); 536 if (ret) { 537 dev_err(dev, "Unable to read ERDBOFF register\n"); 538 return -EIO; 539 } 540 541 if (val >= mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)) { 542 dev_err(dev, "ERDB offset: 0x%x is out of range: 0x%zx\n", 543 val, mhi_cntrl->reg_len - (8 * mhi_cntrl->total_ev_rings)); 544 return -ERANGE; 545 } 546 547 /* Setup event db address for each ev_ring */ 548 mhi_event = mhi_cntrl->mhi_event; 549 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) { 550 if (mhi_event->offload_ev) 551 continue; 552 553 mhi_event->ring.db_addr = base + val; 554 } 555 556 /* Setup DB register for primary CMD rings */ 557 mhi_cntrl->mhi_cmd[PRIMARY_CMD_RING].ring.db_addr = base + CRDB_LOWER; 558 559 /* Write to MMIO registers */ 560 for (i = 0; reg_info[i].offset; i++) 561 mhi_write_reg(mhi_cntrl, base, reg_info[i].offset, 562 reg_info[i].val); 563 564 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NER_MASK, 565 mhi_cntrl->total_ev_rings); 566 if (ret) { 567 dev_err(dev, "Unable to write MHICFG register\n"); 568 return ret; 569 } 570 571 ret = mhi_write_reg_field(mhi_cntrl, base, MHICFG, MHICFG_NHWER_MASK, 572 mhi_cntrl->hw_ev_rings); 573 if (ret) { 574 dev_err(dev, "Unable to write MHICFG register\n"); 575 return ret; 576 } 577 578 return 0; 579 } 580 581 void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, 582 struct mhi_chan *mhi_chan) 583 { 584 struct mhi_ring *buf_ring; 585 struct mhi_ring *tre_ring; 586 struct mhi_chan_ctxt *chan_ctxt; 587 u32 tmp; 588 589 buf_ring = &mhi_chan->buf_ring; 590 tre_ring = &mhi_chan->tre_ring; 591 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan]; 592 593 if (!chan_ctxt->rbase) /* Already uninitialized */ 594 return; 595 596 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size, 597 tre_ring->pre_aligned, tre_ring->dma_handle); 598 vfree(buf_ring->base); 599 600 buf_ring->base = tre_ring->base = NULL; 601 tre_ring->ctxt_wp = NULL; 602 chan_ctxt->rbase = 0; 603 chan_ctxt->rlen = 0; 604 chan_ctxt->rp = 0; 605 chan_ctxt->wp = 0; 606 607 tmp = le32_to_cpu(chan_ctxt->chcfg); 608 tmp &= ~CHAN_CTX_CHSTATE_MASK; 609 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_DISABLED); 610 chan_ctxt->chcfg = cpu_to_le32(tmp); 611 612 /* Update to all cores */ 613 smp_wmb(); 614 } 615 616 int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, 617 struct mhi_chan *mhi_chan) 618 { 619 struct mhi_ring *buf_ring; 620 struct mhi_ring *tre_ring; 621 struct mhi_chan_ctxt *chan_ctxt; 622 u32 tmp; 623 int ret; 624 625 buf_ring = &mhi_chan->buf_ring; 626 tre_ring = &mhi_chan->tre_ring; 627 tre_ring->el_size = sizeof(struct mhi_ring_element); 628 tre_ring->len = tre_ring->el_size * tre_ring->elements; 629 chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan]; 630 ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len); 631 if (ret) 632 return -ENOMEM; 633 634 buf_ring->el_size = sizeof(struct mhi_buf_info); 635 buf_ring->len = buf_ring->el_size * buf_ring->elements; 636 buf_ring->base = vzalloc(buf_ring->len); 637 638 if (!buf_ring->base) { 639 dma_free_coherent(mhi_cntrl->cntrl_dev, tre_ring->alloc_size, 640 tre_ring->pre_aligned, tre_ring->dma_handle); 641 return -ENOMEM; 642 } 643 644 tmp = le32_to_cpu(chan_ctxt->chcfg); 645 tmp &= ~CHAN_CTX_CHSTATE_MASK; 646 tmp |= FIELD_PREP(CHAN_CTX_CHSTATE_MASK, MHI_CH_STATE_ENABLED); 647 chan_ctxt->chcfg = cpu_to_le32(tmp); 648 649 chan_ctxt->rbase = cpu_to_le64(tre_ring->iommu_base); 650 chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase; 651 chan_ctxt->rlen = cpu_to_le64(tre_ring->len); 652 tre_ring->ctxt_wp = &chan_ctxt->wp; 653 654 tre_ring->rp = tre_ring->wp = tre_ring->base; 655 buf_ring->rp = buf_ring->wp = buf_ring->base; 656 mhi_chan->db_cfg.db_mode = 1; 657 658 /* Update to all cores */ 659 smp_wmb(); 660 661 return 0; 662 } 663 664 static int parse_ev_cfg(struct mhi_controller *mhi_cntrl, 665 const struct mhi_controller_config *config) 666 { 667 struct mhi_event *mhi_event; 668 const struct mhi_event_config *event_cfg; 669 struct device *dev = mhi_cntrl->cntrl_dev; 670 int i, num; 671 672 num = config->num_events; 673 mhi_cntrl->total_ev_rings = num; 674 mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event), 675 GFP_KERNEL); 676 if (!mhi_cntrl->mhi_event) 677 return -ENOMEM; 678 679 /* Populate event ring */ 680 mhi_event = mhi_cntrl->mhi_event; 681 for (i = 0; i < num; i++) { 682 event_cfg = &config->event_cfg[i]; 683 684 mhi_event->er_index = i; 685 mhi_event->ring.elements = event_cfg->num_elements; 686 mhi_event->intmod = event_cfg->irq_moderation_ms; 687 mhi_event->irq = event_cfg->irq; 688 689 if (event_cfg->channel != U32_MAX) { 690 /* This event ring has a dedicated channel */ 691 mhi_event->chan = event_cfg->channel; 692 if (mhi_event->chan >= mhi_cntrl->max_chan) { 693 dev_err(dev, 694 "Event Ring channel not available\n"); 695 goto error_ev_cfg; 696 } 697 698 mhi_event->mhi_chan = 699 &mhi_cntrl->mhi_chan[mhi_event->chan]; 700 } 701 702 /* Priority is fixed to 1 for now */ 703 mhi_event->priority = 1; 704 705 mhi_event->db_cfg.brstmode = event_cfg->mode; 706 if (MHI_INVALID_BRSTMODE(mhi_event->db_cfg.brstmode)) 707 goto error_ev_cfg; 708 709 if (mhi_event->db_cfg.brstmode == MHI_DB_BRST_ENABLE) 710 mhi_event->db_cfg.process_db = mhi_db_brstmode; 711 else 712 mhi_event->db_cfg.process_db = mhi_db_brstmode_disable; 713 714 mhi_event->data_type = event_cfg->data_type; 715 716 switch (mhi_event->data_type) { 717 case MHI_ER_DATA: 718 mhi_event->process_event = mhi_process_data_event_ring; 719 break; 720 case MHI_ER_CTRL: 721 mhi_event->process_event = mhi_process_ctrl_ev_ring; 722 break; 723 default: 724 dev_err(dev, "Event Ring type not supported\n"); 725 goto error_ev_cfg; 726 } 727 728 mhi_event->hw_ring = event_cfg->hardware_event; 729 if (mhi_event->hw_ring) 730 mhi_cntrl->hw_ev_rings++; 731 else 732 mhi_cntrl->sw_ev_rings++; 733 734 mhi_event->cl_manage = event_cfg->client_managed; 735 mhi_event->offload_ev = event_cfg->offload_channel; 736 mhi_event++; 737 } 738 739 return 0; 740 741 error_ev_cfg: 742 743 kfree(mhi_cntrl->mhi_event); 744 return -EINVAL; 745 } 746 747 static int parse_ch_cfg(struct mhi_controller *mhi_cntrl, 748 const struct mhi_controller_config *config) 749 { 750 const struct mhi_channel_config *ch_cfg; 751 struct device *dev = mhi_cntrl->cntrl_dev; 752 int i; 753 u32 chan; 754 755 mhi_cntrl->max_chan = config->max_channels; 756 757 /* 758 * The allocation of MHI channels can exceed 32KB in some scenarios, 759 * so to avoid any memory possible allocation failures, vzalloc is 760 * used here 761 */ 762 mhi_cntrl->mhi_chan = vcalloc(mhi_cntrl->max_chan, 763 sizeof(*mhi_cntrl->mhi_chan)); 764 if (!mhi_cntrl->mhi_chan) 765 return -ENOMEM; 766 767 INIT_LIST_HEAD(&mhi_cntrl->lpm_chans); 768 769 /* Populate channel configurations */ 770 for (i = 0; i < config->num_channels; i++) { 771 struct mhi_chan *mhi_chan; 772 773 ch_cfg = &config->ch_cfg[i]; 774 775 chan = ch_cfg->num; 776 if (chan >= mhi_cntrl->max_chan) { 777 dev_err(dev, "Channel %d not available\n", chan); 778 goto error_chan_cfg; 779 } 780 781 mhi_chan = &mhi_cntrl->mhi_chan[chan]; 782 mhi_chan->name = ch_cfg->name; 783 mhi_chan->chan = chan; 784 785 mhi_chan->tre_ring.elements = ch_cfg->num_elements; 786 if (!mhi_chan->tre_ring.elements) 787 goto error_chan_cfg; 788 789 /* 790 * For some channels, local ring length should be bigger than 791 * the transfer ring length due to internal logical channels 792 * in device. So host can queue much more buffers than transfer 793 * ring length. Example, RSC channels should have a larger local 794 * channel length than transfer ring length. 795 */ 796 mhi_chan->buf_ring.elements = ch_cfg->local_elements; 797 if (!mhi_chan->buf_ring.elements) 798 mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements; 799 mhi_chan->er_index = ch_cfg->event_ring; 800 mhi_chan->dir = ch_cfg->dir; 801 802 /* 803 * For most channels, chtype is identical to channel directions. 804 * So, if it is not defined then assign channel direction to 805 * chtype 806 */ 807 mhi_chan->type = ch_cfg->type; 808 if (!mhi_chan->type) 809 mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir; 810 811 mhi_chan->ee_mask = ch_cfg->ee_mask; 812 mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg; 813 mhi_chan->lpm_notify = ch_cfg->lpm_notify; 814 mhi_chan->offload_ch = ch_cfg->offload_channel; 815 mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch; 816 mhi_chan->pre_alloc = ch_cfg->auto_queue; 817 mhi_chan->wake_capable = ch_cfg->wake_capable; 818 819 /* 820 * If MHI host allocates buffers, then the channel direction 821 * should be DMA_FROM_DEVICE 822 */ 823 if (mhi_chan->pre_alloc && mhi_chan->dir != DMA_FROM_DEVICE) { 824 dev_err(dev, "Invalid channel configuration\n"); 825 goto error_chan_cfg; 826 } 827 828 /* 829 * Bi-directional and direction less channel must be an 830 * offload channel 831 */ 832 if ((mhi_chan->dir == DMA_BIDIRECTIONAL || 833 mhi_chan->dir == DMA_NONE) && !mhi_chan->offload_ch) { 834 dev_err(dev, "Invalid channel configuration\n"); 835 goto error_chan_cfg; 836 } 837 838 if (!mhi_chan->offload_ch) { 839 mhi_chan->db_cfg.brstmode = ch_cfg->doorbell; 840 if (MHI_INVALID_BRSTMODE(mhi_chan->db_cfg.brstmode)) { 841 dev_err(dev, "Invalid Door bell mode\n"); 842 goto error_chan_cfg; 843 } 844 } 845 846 if (mhi_chan->db_cfg.brstmode == MHI_DB_BRST_ENABLE) 847 mhi_chan->db_cfg.process_db = mhi_db_brstmode; 848 else 849 mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable; 850 851 mhi_chan->configured = true; 852 853 if (mhi_chan->lpm_notify) 854 list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans); 855 } 856 857 return 0; 858 859 error_chan_cfg: 860 vfree(mhi_cntrl->mhi_chan); 861 862 return -EINVAL; 863 } 864 865 static int parse_config(struct mhi_controller *mhi_cntrl, 866 const struct mhi_controller_config *config) 867 { 868 int ret; 869 870 /* Parse MHI channel configuration */ 871 ret = parse_ch_cfg(mhi_cntrl, config); 872 if (ret) 873 return ret; 874 875 /* Parse MHI event configuration */ 876 ret = parse_ev_cfg(mhi_cntrl, config); 877 if (ret) 878 goto error_ev_cfg; 879 880 mhi_cntrl->timeout_ms = config->timeout_ms; 881 if (!mhi_cntrl->timeout_ms) 882 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS; 883 884 mhi_cntrl->ready_timeout_ms = config->ready_timeout_ms; 885 mhi_cntrl->bounce_buf = config->use_bounce_buf; 886 mhi_cntrl->buffer_len = config->buf_len; 887 if (!mhi_cntrl->buffer_len) 888 mhi_cntrl->buffer_len = MHI_MAX_MTU; 889 890 /* By default, host is allowed to ring DB in both M0 and M2 states */ 891 mhi_cntrl->db_access = MHI_PM_M0 | MHI_PM_M2; 892 if (config->m2_no_db) 893 mhi_cntrl->db_access &= ~MHI_PM_M2; 894 895 return 0; 896 897 error_ev_cfg: 898 vfree(mhi_cntrl->mhi_chan); 899 900 return ret; 901 } 902 903 int mhi_register_controller(struct mhi_controller *mhi_cntrl, 904 const struct mhi_controller_config *config) 905 { 906 struct mhi_event *mhi_event; 907 struct mhi_chan *mhi_chan; 908 struct mhi_cmd *mhi_cmd; 909 struct mhi_device *mhi_dev; 910 u32 soc_info; 911 int ret, i; 912 913 if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs || 914 !mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put || 915 !mhi_cntrl->status_cb || !mhi_cntrl->read_reg || 916 !mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || 917 !mhi_cntrl->irq || !mhi_cntrl->reg_len) 918 return -EINVAL; 919 920 ret = parse_config(mhi_cntrl, config); 921 if (ret) 922 return -EINVAL; 923 924 mhi_cntrl->mhi_cmd = kcalloc(NR_OF_CMD_RINGS, 925 sizeof(*mhi_cntrl->mhi_cmd), GFP_KERNEL); 926 if (!mhi_cntrl->mhi_cmd) { 927 ret = -ENOMEM; 928 goto err_free_event; 929 } 930 931 INIT_LIST_HEAD(&mhi_cntrl->transition_list); 932 mutex_init(&mhi_cntrl->pm_mutex); 933 rwlock_init(&mhi_cntrl->pm_lock); 934 spin_lock_init(&mhi_cntrl->transition_lock); 935 spin_lock_init(&mhi_cntrl->wlock); 936 INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker); 937 init_waitqueue_head(&mhi_cntrl->state_event); 938 939 mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI); 940 if (!mhi_cntrl->hiprio_wq) { 941 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n"); 942 ret = -ENOMEM; 943 goto err_free_cmd; 944 } 945 946 mhi_cmd = mhi_cntrl->mhi_cmd; 947 for (i = 0; i < NR_OF_CMD_RINGS; i++, mhi_cmd++) 948 spin_lock_init(&mhi_cmd->lock); 949 950 mhi_event = mhi_cntrl->mhi_event; 951 for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { 952 /* Skip for offload events */ 953 if (mhi_event->offload_ev) 954 continue; 955 956 mhi_event->mhi_cntrl = mhi_cntrl; 957 spin_lock_init(&mhi_event->lock); 958 if (mhi_event->data_type == MHI_ER_CTRL) 959 tasklet_init(&mhi_event->task, mhi_ctrl_ev_task, 960 (ulong)mhi_event); 961 else 962 tasklet_init(&mhi_event->task, mhi_ev_task, 963 (ulong)mhi_event); 964 } 965 966 mhi_chan = mhi_cntrl->mhi_chan; 967 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 968 mutex_init(&mhi_chan->mutex); 969 init_completion(&mhi_chan->completion); 970 rwlock_init(&mhi_chan->lock); 971 972 /* used in setting bei field of TRE */ 973 mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; 974 mhi_chan->intmod = mhi_event->intmod; 975 } 976 977 if (mhi_cntrl->bounce_buf) { 978 mhi_cntrl->map_single = mhi_map_single_use_bb; 979 mhi_cntrl->unmap_single = mhi_unmap_single_use_bb; 980 } else { 981 mhi_cntrl->map_single = mhi_map_single_no_bb; 982 mhi_cntrl->unmap_single = mhi_unmap_single_no_bb; 983 } 984 985 /* Read the MHI device info */ 986 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, 987 SOC_HW_VERSION_OFFS, &soc_info); 988 if (ret) 989 goto err_destroy_wq; 990 991 mhi_cntrl->family_number = FIELD_GET(SOC_HW_VERSION_FAM_NUM_BMSK, soc_info); 992 mhi_cntrl->device_number = FIELD_GET(SOC_HW_VERSION_DEV_NUM_BMSK, soc_info); 993 mhi_cntrl->major_version = FIELD_GET(SOC_HW_VERSION_MAJOR_VER_BMSK, soc_info); 994 mhi_cntrl->minor_version = FIELD_GET(SOC_HW_VERSION_MINOR_VER_BMSK, soc_info); 995 996 mhi_cntrl->index = ida_alloc(&mhi_controller_ida, GFP_KERNEL); 997 if (mhi_cntrl->index < 0) { 998 ret = mhi_cntrl->index; 999 goto err_destroy_wq; 1000 } 1001 1002 ret = mhi_init_irq_setup(mhi_cntrl); 1003 if (ret) 1004 goto err_ida_free; 1005 1006 /* Register controller with MHI bus */ 1007 mhi_dev = mhi_alloc_device(mhi_cntrl); 1008 if (IS_ERR(mhi_dev)) { 1009 dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate MHI device\n"); 1010 ret = PTR_ERR(mhi_dev); 1011 goto error_setup_irq; 1012 } 1013 1014 mhi_dev->dev_type = MHI_DEVICE_CONTROLLER; 1015 mhi_dev->mhi_cntrl = mhi_cntrl; 1016 dev_set_name(&mhi_dev->dev, "mhi%d", mhi_cntrl->index); 1017 mhi_dev->name = dev_name(&mhi_dev->dev); 1018 1019 /* Init wakeup source */ 1020 device_init_wakeup(&mhi_dev->dev, true); 1021 1022 ret = device_add(&mhi_dev->dev); 1023 if (ret) 1024 goto err_release_dev; 1025 1026 mhi_cntrl->mhi_dev = mhi_dev; 1027 1028 mhi_create_debugfs(mhi_cntrl); 1029 1030 return 0; 1031 1032 err_release_dev: 1033 put_device(&mhi_dev->dev); 1034 error_setup_irq: 1035 mhi_deinit_free_irq(mhi_cntrl); 1036 err_ida_free: 1037 ida_free(&mhi_controller_ida, mhi_cntrl->index); 1038 err_destroy_wq: 1039 destroy_workqueue(mhi_cntrl->hiprio_wq); 1040 err_free_cmd: 1041 kfree(mhi_cntrl->mhi_cmd); 1042 err_free_event: 1043 kfree(mhi_cntrl->mhi_event); 1044 vfree(mhi_cntrl->mhi_chan); 1045 1046 return ret; 1047 } 1048 EXPORT_SYMBOL_GPL(mhi_register_controller); 1049 1050 void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) 1051 { 1052 struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev; 1053 struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan; 1054 unsigned int i; 1055 1056 mhi_deinit_free_irq(mhi_cntrl); 1057 mhi_destroy_debugfs(mhi_cntrl); 1058 1059 destroy_workqueue(mhi_cntrl->hiprio_wq); 1060 kfree(mhi_cntrl->mhi_cmd); 1061 kfree(mhi_cntrl->mhi_event); 1062 1063 /* Drop the references to MHI devices created for channels */ 1064 for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { 1065 if (!mhi_chan->mhi_dev) 1066 continue; 1067 1068 put_device(&mhi_chan->mhi_dev->dev); 1069 } 1070 vfree(mhi_cntrl->mhi_chan); 1071 1072 device_del(&mhi_dev->dev); 1073 put_device(&mhi_dev->dev); 1074 1075 ida_free(&mhi_controller_ida, mhi_cntrl->index); 1076 } 1077 EXPORT_SYMBOL_GPL(mhi_unregister_controller); 1078 1079 struct mhi_controller *mhi_alloc_controller(void) 1080 { 1081 struct mhi_controller *mhi_cntrl; 1082 1083 mhi_cntrl = kzalloc(sizeof(*mhi_cntrl), GFP_KERNEL); 1084 1085 return mhi_cntrl; 1086 } 1087 EXPORT_SYMBOL_GPL(mhi_alloc_controller); 1088 1089 void mhi_free_controller(struct mhi_controller *mhi_cntrl) 1090 { 1091 kfree(mhi_cntrl); 1092 } 1093 EXPORT_SYMBOL_GPL(mhi_free_controller); 1094 1095 int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) 1096 { 1097 struct device *dev = &mhi_cntrl->mhi_dev->dev; 1098 u32 bhi_off, bhie_off; 1099 int ret; 1100 1101 mutex_lock(&mhi_cntrl->pm_mutex); 1102 1103 ret = mhi_init_dev_ctxt(mhi_cntrl); 1104 if (ret) 1105 goto error_dev_ctxt; 1106 1107 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIOFF, &bhi_off); 1108 if (ret) { 1109 dev_err(dev, "Error getting BHI offset\n"); 1110 goto error_reg_offset; 1111 } 1112 1113 if (bhi_off >= mhi_cntrl->reg_len) { 1114 dev_err(dev, "BHI offset: 0x%x is out of range: 0x%zx\n", 1115 bhi_off, mhi_cntrl->reg_len); 1116 ret = -ERANGE; 1117 goto error_reg_offset; 1118 } 1119 mhi_cntrl->bhi = mhi_cntrl->regs + bhi_off; 1120 1121 if (mhi_cntrl->fbc_download || mhi_cntrl->rddm_size) { 1122 ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, BHIEOFF, 1123 &bhie_off); 1124 if (ret) { 1125 dev_err(dev, "Error getting BHIE offset\n"); 1126 goto error_reg_offset; 1127 } 1128 1129 if (bhie_off >= mhi_cntrl->reg_len) { 1130 dev_err(dev, 1131 "BHIe offset: 0x%x is out of range: 0x%zx\n", 1132 bhie_off, mhi_cntrl->reg_len); 1133 ret = -ERANGE; 1134 goto error_reg_offset; 1135 } 1136 mhi_cntrl->bhie = mhi_cntrl->regs + bhie_off; 1137 } 1138 1139 if (mhi_cntrl->rddm_size) { 1140 /* 1141 * This controller supports RDDM, so we need to manually clear 1142 * BHIE RX registers since POR values are undefined. 1143 */ 1144 memset_io(mhi_cntrl->bhie + BHIE_RXVECADDR_LOW_OFFS, 1145 0, BHIE_RXVECSTATUS_OFFS - BHIE_RXVECADDR_LOW_OFFS + 1146 4); 1147 /* 1148 * Allocate RDDM table for debugging purpose if specified 1149 */ 1150 mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, 1151 mhi_cntrl->rddm_size); 1152 if (mhi_cntrl->rddm_image) { 1153 ret = mhi_rddm_prepare(mhi_cntrl, 1154 mhi_cntrl->rddm_image); 1155 if (ret) { 1156 mhi_free_bhie_table(mhi_cntrl, 1157 mhi_cntrl->rddm_image); 1158 goto error_reg_offset; 1159 } 1160 } 1161 } 1162 1163 mutex_unlock(&mhi_cntrl->pm_mutex); 1164 1165 return 0; 1166 1167 error_reg_offset: 1168 mhi_deinit_dev_ctxt(mhi_cntrl); 1169 1170 error_dev_ctxt: 1171 mutex_unlock(&mhi_cntrl->pm_mutex); 1172 1173 return ret; 1174 } 1175 EXPORT_SYMBOL_GPL(mhi_prepare_for_power_up); 1176 1177 void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl) 1178 { 1179 if (mhi_cntrl->fbc_image) { 1180 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); 1181 mhi_cntrl->fbc_image = NULL; 1182 } 1183 1184 if (mhi_cntrl->rddm_image) { 1185 mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); 1186 mhi_cntrl->rddm_image = NULL; 1187 } 1188 1189 mhi_cntrl->bhi = NULL; 1190 mhi_cntrl->bhie = NULL; 1191 1192 mhi_deinit_dev_ctxt(mhi_cntrl); 1193 } 1194 EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down); 1195 1196 static void mhi_release_device(struct device *dev) 1197 { 1198 struct mhi_device *mhi_dev = to_mhi_device(dev); 1199 1200 /* 1201 * We need to set the mhi_chan->mhi_dev to NULL here since the MHI 1202 * devices for the channels will only get created if the mhi_dev 1203 * associated with it is NULL. This scenario will happen during the 1204 * controller suspend and resume. 1205 */ 1206 if (mhi_dev->ul_chan) 1207 mhi_dev->ul_chan->mhi_dev = NULL; 1208 1209 if (mhi_dev->dl_chan) 1210 mhi_dev->dl_chan->mhi_dev = NULL; 1211 1212 kfree(mhi_dev); 1213 } 1214 1215 struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl) 1216 { 1217 struct mhi_device *mhi_dev; 1218 struct device *dev; 1219 1220 mhi_dev = kzalloc(sizeof(*mhi_dev), GFP_KERNEL); 1221 if (!mhi_dev) 1222 return ERR_PTR(-ENOMEM); 1223 1224 dev = &mhi_dev->dev; 1225 device_initialize(dev); 1226 dev->bus = &mhi_bus_type; 1227 dev->release = mhi_release_device; 1228 1229 if (mhi_cntrl->mhi_dev) { 1230 /* for MHI client devices, parent is the MHI controller device */ 1231 dev->parent = &mhi_cntrl->mhi_dev->dev; 1232 } else { 1233 /* for MHI controller device, parent is the bus device (e.g. pci device) */ 1234 dev->parent = mhi_cntrl->cntrl_dev; 1235 } 1236 1237 mhi_dev->mhi_cntrl = mhi_cntrl; 1238 mhi_dev->dev_wake = 0; 1239 1240 return mhi_dev; 1241 } 1242 1243 static int mhi_driver_probe(struct device *dev) 1244 { 1245 struct mhi_device *mhi_dev = to_mhi_device(dev); 1246 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1247 struct device_driver *drv = dev->driver; 1248 struct mhi_driver *mhi_drv = to_mhi_driver(drv); 1249 struct mhi_event *mhi_event; 1250 struct mhi_chan *ul_chan = mhi_dev->ul_chan; 1251 struct mhi_chan *dl_chan = mhi_dev->dl_chan; 1252 int ret; 1253 1254 /* Bring device out of LPM */ 1255 ret = mhi_device_get_sync(mhi_dev); 1256 if (ret) 1257 return ret; 1258 1259 ret = -EINVAL; 1260 1261 if (ul_chan) { 1262 /* 1263 * If channel supports LPM notifications then status_cb should 1264 * be provided 1265 */ 1266 if (ul_chan->lpm_notify && !mhi_drv->status_cb) 1267 goto exit_probe; 1268 1269 /* For non-offload channels then xfer_cb should be provided */ 1270 if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb) 1271 goto exit_probe; 1272 1273 ul_chan->xfer_cb = mhi_drv->ul_xfer_cb; 1274 } 1275 1276 ret = -EINVAL; 1277 if (dl_chan) { 1278 /* 1279 * If channel supports LPM notifications then status_cb should 1280 * be provided 1281 */ 1282 if (dl_chan->lpm_notify && !mhi_drv->status_cb) 1283 goto exit_probe; 1284 1285 /* For non-offload channels then xfer_cb should be provided */ 1286 if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb) 1287 goto exit_probe; 1288 1289 mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index]; 1290 1291 /* 1292 * If the channel event ring is managed by client, then 1293 * status_cb must be provided so that the framework can 1294 * notify pending data 1295 */ 1296 if (mhi_event->cl_manage && !mhi_drv->status_cb) 1297 goto exit_probe; 1298 1299 dl_chan->xfer_cb = mhi_drv->dl_xfer_cb; 1300 } 1301 1302 /* Call the user provided probe function */ 1303 ret = mhi_drv->probe(mhi_dev, mhi_dev->id); 1304 if (ret) 1305 goto exit_probe; 1306 1307 mhi_device_put(mhi_dev); 1308 1309 return ret; 1310 1311 exit_probe: 1312 mhi_unprepare_from_transfer(mhi_dev); 1313 1314 mhi_device_put(mhi_dev); 1315 1316 return ret; 1317 } 1318 1319 static int mhi_driver_remove(struct device *dev) 1320 { 1321 struct mhi_device *mhi_dev = to_mhi_device(dev); 1322 struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver); 1323 struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; 1324 struct mhi_chan *mhi_chan; 1325 enum mhi_ch_state ch_state[] = { 1326 MHI_CH_STATE_DISABLED, 1327 MHI_CH_STATE_DISABLED 1328 }; 1329 int dir; 1330 1331 /* Skip if it is a controller device */ 1332 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) 1333 return 0; 1334 1335 /* Reset both channels */ 1336 for (dir = 0; dir < 2; dir++) { 1337 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; 1338 1339 if (!mhi_chan) 1340 continue; 1341 1342 /* Wake all threads waiting for completion */ 1343 write_lock_irq(&mhi_chan->lock); 1344 mhi_chan->ccs = MHI_EV_CC_INVALID; 1345 complete_all(&mhi_chan->completion); 1346 write_unlock_irq(&mhi_chan->lock); 1347 1348 /* Set the channel state to disabled */ 1349 mutex_lock(&mhi_chan->mutex); 1350 write_lock_irq(&mhi_chan->lock); 1351 ch_state[dir] = mhi_chan->ch_state; 1352 mhi_chan->ch_state = MHI_CH_STATE_SUSPENDED; 1353 write_unlock_irq(&mhi_chan->lock); 1354 1355 /* Reset the non-offload channel */ 1356 if (!mhi_chan->offload_ch) 1357 mhi_reset_chan(mhi_cntrl, mhi_chan); 1358 1359 mutex_unlock(&mhi_chan->mutex); 1360 } 1361 1362 mhi_drv->remove(mhi_dev); 1363 1364 /* De-init channel if it was enabled */ 1365 for (dir = 0; dir < 2; dir++) { 1366 mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; 1367 1368 if (!mhi_chan) 1369 continue; 1370 1371 mutex_lock(&mhi_chan->mutex); 1372 1373 if ((ch_state[dir] == MHI_CH_STATE_ENABLED || 1374 ch_state[dir] == MHI_CH_STATE_STOP) && 1375 !mhi_chan->offload_ch) 1376 mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); 1377 1378 mhi_chan->ch_state = MHI_CH_STATE_DISABLED; 1379 1380 mutex_unlock(&mhi_chan->mutex); 1381 } 1382 1383 while (mhi_dev->dev_wake) 1384 mhi_device_put(mhi_dev); 1385 1386 return 0; 1387 } 1388 1389 int __mhi_driver_register(struct mhi_driver *mhi_drv, struct module *owner) 1390 { 1391 struct device_driver *driver = &mhi_drv->driver; 1392 1393 if (!mhi_drv->probe || !mhi_drv->remove) 1394 return -EINVAL; 1395 1396 driver->bus = &mhi_bus_type; 1397 driver->owner = owner; 1398 driver->probe = mhi_driver_probe; 1399 driver->remove = mhi_driver_remove; 1400 1401 return driver_register(driver); 1402 } 1403 EXPORT_SYMBOL_GPL(__mhi_driver_register); 1404 1405 void mhi_driver_unregister(struct mhi_driver *mhi_drv) 1406 { 1407 driver_unregister(&mhi_drv->driver); 1408 } 1409 EXPORT_SYMBOL_GPL(mhi_driver_unregister); 1410 1411 static int mhi_uevent(const struct device *dev, struct kobj_uevent_env *env) 1412 { 1413 const struct mhi_device *mhi_dev = to_mhi_device(dev); 1414 1415 return add_uevent_var(env, "MODALIAS=" MHI_DEVICE_MODALIAS_FMT, 1416 mhi_dev->name); 1417 } 1418 1419 static int mhi_match(struct device *dev, struct device_driver *drv) 1420 { 1421 struct mhi_device *mhi_dev = to_mhi_device(dev); 1422 struct mhi_driver *mhi_drv = to_mhi_driver(drv); 1423 const struct mhi_device_id *id; 1424 1425 /* 1426 * If the device is a controller type then there is no client driver 1427 * associated with it 1428 */ 1429 if (mhi_dev->dev_type == MHI_DEVICE_CONTROLLER) 1430 return 0; 1431 1432 for (id = mhi_drv->id_table; id->chan[0]; id++) 1433 if (!strcmp(mhi_dev->name, id->chan)) { 1434 mhi_dev->id = id; 1435 return 1; 1436 } 1437 1438 return 0; 1439 }; 1440 1441 struct bus_type mhi_bus_type = { 1442 .name = "mhi", 1443 .dev_name = "mhi", 1444 .match = mhi_match, 1445 .uevent = mhi_uevent, 1446 .dev_groups = mhi_dev_groups, 1447 }; 1448 1449 static int __init mhi_init(void) 1450 { 1451 mhi_debugfs_init(); 1452 return bus_register(&mhi_bus_type); 1453 } 1454 1455 static void __exit mhi_exit(void) 1456 { 1457 mhi_debugfs_exit(); 1458 bus_unregister(&mhi_bus_type); 1459 } 1460 1461 postcore_initcall(mhi_init); 1462 module_exit(mhi_exit); 1463 1464 MODULE_LICENSE("GPL v2"); 1465 MODULE_DESCRIPTION("Modem Host Interface"); 1466