1# 2# Bus Devices 3# 4 5menu "Bus devices" 6 7config ARM_CCI 8 bool 9 10config ARM_CCI_PMU 11 bool 12 select ARM_CCI 13 14config ARM_CCI400_COMMON 15 bool 16 select ARM_CCI 17 18config ARM_CCI400_PMU 19 bool "ARM CCI400 PMU support" 20 depends on (ARM && CPU_V7) || ARM64 21 depends on PERF_EVENTS 22 select ARM_CCI400_COMMON 23 select ARM_CCI_PMU 24 help 25 Support for PMU events monitoring on the ARM CCI-400 (cache coherent 26 interconnect). CCI-400 supports counting events related to the 27 connected slave/master interfaces. 28 29config ARM_CCI400_PORT_CTRL 30 bool 31 depends on ARM && OF && CPU_V7 32 select ARM_CCI400_COMMON 33 help 34 Low level power management driver for CCI400 cache coherent 35 interconnect for ARM platforms. 36 37config ARM_CCI500_PMU 38 bool "ARM CCI500 PMU support" 39 depends on (ARM && CPU_V7) || ARM64 40 depends on PERF_EVENTS 41 select ARM_CCI_PMU 42 help 43 Support for PMU events monitoring on the ARM CCI-500 cache coherent 44 interconnect. CCI-500 provides 8 independent event counters, which 45 can count events pertaining to the slave/master interfaces as well 46 as the internal events to the CCI. 47 48 If unsure, say Y 49 50config ARM_CCN 51 bool "ARM CCN driver support" 52 depends on ARM || ARM64 53 depends on PERF_EVENTS 54 help 55 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network) 56 interconnect. 57 58config BRCMSTB_GISB_ARB 59 bool "Broadcom STB GISB bus arbiter" 60 depends on ARM || MIPS 61 help 62 Driver for the Broadcom Set Top Box System-on-a-chip internal bus 63 arbiter. This driver provides timeout and target abort error handling 64 and internal bus master decoding. 65 66config IMX_WEIM 67 bool "Freescale EIM DRIVER" 68 depends on ARCH_MXC 69 help 70 Driver for i.MX WEIM controller. 71 The WEIM(Wireless External Interface Module) works like a bus. 72 You can attach many different devices on it, such as NOR, onenand. 73 74config MIPS_CDMM 75 bool "MIPS Common Device Memory Map (CDMM) Driver" 76 depends on CPU_MIPSR2 77 help 78 Driver needed for the MIPS Common Device Memory Map bus in MIPS 79 cores. This bus is for per-CPU tightly coupled devices such as the 80 Fast Debug Channel (FDC). 81 82 For this to work, either your bootloader needs to enable the CDMM 83 region at an unused physical address on the boot CPU, or else your 84 platform code needs to implement mips_cdmm_phys_base() (see 85 asm/cdmm.h). 86 87config MVEBU_MBUS 88 bool 89 depends on PLAT_ORION 90 help 91 Driver needed for the MBus configuration on Marvell EBU SoCs 92 (Kirkwood, Dove, Orion5x, MV78XX0 and Armada 370/XP). 93 94config OMAP_INTERCONNECT 95 tristate "OMAP INTERCONNECT DRIVER" 96 depends on ARCH_OMAP2PLUS 97 98 help 99 Driver to enable OMAP interconnect error handling driver. 100 101config OMAP_OCP2SCP 102 tristate "OMAP OCP2SCP DRIVER" 103 depends on ARCH_OMAP2PLUS 104 help 105 Driver to enable ocp2scp module which transforms ocp interface 106 protocol to scp protocol. In OMAP4, USB PHY is connected via 107 OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via 108 OCP2SCP. 109 110config SIMPLE_PM_BUS 111 bool "Simple Power-Managed Bus Driver" 112 depends on OF && PM 113 depends on ARCH_SHMOBILE || COMPILE_TEST 114 help 115 Driver for transparent busses that don't need a real driver, but 116 where the bus controller is part of a PM domain, or under the control 117 of a functional clock, and thus relies on runtime PM for managing 118 this PM domain and/or clock. 119 An example of such a bus controller is the Renesas Bus State 120 Controller (BSC, sometimes called "LBSC within Bus Bridge", or 121 "External Bus Interface") as found on several Renesas ARM SoCs. 122 123config VEXPRESS_CONFIG 124 bool "Versatile Express configuration bus" 125 default y if ARCH_VEXPRESS 126 depends on ARM || ARM64 127 depends on OF 128 select REGMAP 129 help 130 Platform configuration infrastructure for the ARM Ltd. 131 Versatile Express. 132endmenu 133