1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2021 MediaTek Inc. */ 3 4 #define FIRMWARE_MT7663 "mediatek/mt7663pr2h.bin" 5 #define FIRMWARE_MT7668 "mediatek/mt7668pr2h.bin" 6 #define FIRMWARE_MT7961 "mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin" 7 8 #define HCI_EV_WMT 0xe4 9 #define HCI_WMT_MAX_EVENT_SIZE 64 10 11 #define BTMTK_WMT_REG_WRITE 0x1 12 #define BTMTK_WMT_REG_READ 0x2 13 14 #define MT7921_BTSYS_RST 0x70002610 15 #define MT7921_BTSYS_RST_WITH_GPIO BIT(7) 16 17 #define MT7921_PINMUX_0 0x70005050 18 #define MT7921_PINMUX_1 0x70005054 19 20 #define MT7921_DLSTATUS 0x7c053c10 21 #define BT_DL_STATE BIT(1) 22 23 enum { 24 BTMTK_WMT_PATCH_DWNLD = 0x1, 25 BTMTK_WMT_TEST = 0x2, 26 BTMTK_WMT_WAKEUP = 0x3, 27 BTMTK_WMT_HIF = 0x4, 28 BTMTK_WMT_FUNC_CTRL = 0x6, 29 BTMTK_WMT_RST = 0x7, 30 BTMTK_WMT_REGISTER = 0x8, 31 BTMTK_WMT_SEMAPHORE = 0x17, 32 }; 33 34 enum { 35 BTMTK_WMT_INVALID, 36 BTMTK_WMT_PATCH_UNDONE, 37 BTMTK_WMT_PATCH_PROGRESS, 38 BTMTK_WMT_PATCH_DONE, 39 BTMTK_WMT_ON_UNDONE, 40 BTMTK_WMT_ON_DONE, 41 BTMTK_WMT_ON_PROGRESS, 42 }; 43 44 struct btmtk_wmt_hdr { 45 u8 dir; 46 u8 op; 47 __le16 dlen; 48 u8 flag; 49 } __packed; 50 51 struct btmtk_hci_wmt_cmd { 52 struct btmtk_wmt_hdr hdr; 53 u8 data[]; 54 } __packed; 55 56 struct btmtk_hci_wmt_evt { 57 struct hci_event_hdr hhdr; 58 struct btmtk_wmt_hdr whdr; 59 } __packed; 60 61 struct btmtk_hci_wmt_evt_funcc { 62 struct btmtk_hci_wmt_evt hwhdr; 63 __be16 status; 64 } __packed; 65 66 struct btmtk_hci_wmt_evt_reg { 67 struct btmtk_hci_wmt_evt hwhdr; 68 u8 rsv[2]; 69 u8 num; 70 __le32 addr; 71 __le32 val; 72 } __packed; 73 74 struct btmtk_tci_sleep { 75 u8 mode; 76 __le16 duration; 77 __le16 host_duration; 78 u8 host_wakeup_pin; 79 u8 time_compensation; 80 } __packed; 81 82 struct btmtk_wakeon { 83 u8 mode; 84 u8 gpo; 85 u8 active_high; 86 __le16 enable_delay; 87 __le16 wakeup_delay; 88 } __packed; 89 90 struct btmtk_sco { 91 u8 clock_config; 92 u8 transmit_format_config; 93 u8 channel_format_config; 94 u8 channel_select_config; 95 } __packed; 96 97 struct reg_read_cmd { 98 u8 type; 99 u8 rsv; 100 u8 num; 101 __le32 addr; 102 } __packed; 103 104 struct reg_write_cmd { 105 u8 type; 106 u8 rsv; 107 u8 num; 108 __le32 addr; 109 __le32 data; 110 __le32 mask; 111 } __packed; 112 113 struct btmtk_hci_wmt_params { 114 u8 op; 115 u8 flag; 116 u16 dlen; 117 const void *data; 118 u32 *status; 119 }; 120 121 typedef int (*wmt_cmd_sync_func_t)(struct hci_dev *, 122 struct btmtk_hci_wmt_params *); 123 124 #if IS_ENABLED(CONFIG_BT_MTK) 125 126 int btmtk_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); 127 128 int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname, 129 wmt_cmd_sync_func_t wmt_cmd_sync); 130 131 int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname, 132 wmt_cmd_sync_func_t wmt_cmd_sync); 133 #else 134 135 static inline int btmtk_set_bdaddr(struct hci_dev *hdev, 136 const bdaddr_t *bdaddr) 137 { 138 return -EOPNOTSUPP; 139 } 140 141 static int btmtk_setup_firmware_79xx(struct hci_dev *hdev, const char *fwname, 142 wmt_cmd_sync_func_t wmt_cmd_sync) 143 { 144 return -EOPNOTSUPP; 145 } 146 147 static int btmtk_setup_firmware(struct hci_dev *hdev, const char *fwname, 148 wmt_cmd_sync_func_t wmt_cmd_sync) 149 { 150 return -EOPNOTSUPP; 151 } 152 153 #endif 154