1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * 4 * Bluetooth support for Intel PCIe devices 5 * 6 * Copyright (C) 2024 Intel Corporation 7 */ 8 9 /* Control and Status Register(BTINTEL_PCIE_CSR) */ 10 #define BTINTEL_PCIE_CSR_BASE (0x000) 11 #define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024) 12 #define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028) 13 #define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C) 14 #define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108) 15 #define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG (BTINTEL_PCIE_CSR_BASE + 0x114) 16 #define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118) 17 #define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C) 18 #define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C) 19 #define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460) 20 21 /* BTINTEL_PCIE_CSR Function Control Register */ 22 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0)) 23 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6)) 24 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7)) 25 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20)) 26 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28)) 27 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29)) 28 #define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31)) 29 30 /* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */ 31 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0)) 32 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1)) 33 #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2)) 34 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10)) 35 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11)) 36 #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16)) 37 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23)) 38 #define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY (BIT(24)) 39 40 /* Registers for MSI-X */ 41 #define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000) 42 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800) 43 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804) 44 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808) 45 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C) 46 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810) 47 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814) 48 #define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880) 49 #define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause)) 50 51 /* Causes for the FH register interrupts */ 52 enum msix_fh_int_causes { 53 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */ 54 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */ 55 }; 56 57 /* Causes for the HW register interrupts */ 58 enum msix_hw_int_causes { 59 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */ 60 }; 61 62 /* PCIe device states 63 * Host-Device interface is active 64 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 65 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 66 */ 67 enum { 68 BTINTEL_PCIE_STATE_D0 = 0, 69 BTINTEL_PCIE_STATE_D3_HOT = 2, 70 BTINTEL_PCIE_STATE_D3_COLD = 3, 71 }; 72 #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 73 74 /* Minimum and Maximum number of MSI-X Vector 75 * Intel Bluetooth PCIe support only 1 vector 76 */ 77 #define BTINTEL_PCIE_MSIX_VEC_MAX 1 78 #define BTINTEL_PCIE_MSIX_VEC_MIN 1 79 80 /* Default poll time for MAC access during init */ 81 #define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000 82 83 /* Default interrupt timeout in msec */ 84 #define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000 85 86 /* The number of descriptors in TX/RX queues */ 87 #define BTINTEL_DESCS_COUNT 16 88 89 /* Number of Queue for TX and RX 90 * It indicates the index of the IA(Index Array) 91 */ 92 enum { 93 BTINTEL_PCIE_TXQ_NUM = 0, 94 BTINTEL_PCIE_RXQ_NUM = 1, 95 BTINTEL_PCIE_NUM_QUEUES = 2, 96 }; 97 98 /* The size of DMA buffer for TX and RX in bytes */ 99 #define BTINTEL_PCIE_BUFFER_SIZE 4096 100 101 /* DMA allocation alignment */ 102 #define BTINTEL_PCIE_DMA_POOL_ALIGNMENT 256 103 104 #define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500 105 106 /* Doorbell vector for TFD */ 107 #define BTINTEL_PCIE_TX_DB_VEC 0 108 109 /* Number of pending RX requests for downlink */ 110 #define BTINTEL_PCIE_RX_MAX_QUEUE 6 111 112 /* Doorbell vector for FRBD */ 113 #define BTINTEL_PCIE_RX_DB_VEC 513 114 115 /* RBD buffer size mapping */ 116 #define BTINTEL_PCIE_RBD_SIZE_4K 0x04 117 118 /* 119 * Struct for Context Information (v2) 120 * 121 * All members are write-only for host and read-only for device. 122 * 123 * @version: Version of context information 124 * @size: Size of context information 125 * @config: Config with which host wants peripheral to execute 126 * Subset of capability register published by device 127 * @addr_tr_hia: Address of TR Head Index Array 128 * @addr_tr_tia: Address of TR Tail Index Array 129 * @addr_cr_hia: Address of CR Head Index Array 130 * @addr_cr_tia: Address of CR Tail Index Array 131 * @num_tr_ia: Number of entries in TR Index Arrays 132 * @num_cr_ia: Number of entries in CR Index Arrays 133 * @rbd_siz: RBD Size { 0x4=4K } 134 * @addr_tfdq: Address of TFD Queue(tx) 135 * @addr_urbdq0: Address of URBD Queue(tx) 136 * @num_tfdq: Number of TFD in TFD Queue(tx) 137 * @num_urbdq0: Number of URBD in URBD Queue(tx) 138 * @tfdq_db_vec: Queue number of TFD 139 * @urbdq0_db_vec: Queue number of URBD 140 * @addr_frbdq: Address of FRBD Queue(rx) 141 * @addr_urbdq1: Address of URBD Queue(rx) 142 * @num_frbdq: Number of FRBD in FRBD Queue(rx) 143 * @frbdq_db_vec: Queue number of FRBD 144 * @num_urbdq1: Number of URBD in URBD Queue(rx) 145 * @urbdq_db_vec: Queue number of URBDQ1 146 * @tr_msi_vec: Transfer Ring MSI-X Vector 147 * @cr_msi_vec: Completion Ring MSI-X Vector 148 * @dbgc_addr: DBGC first fragment address 149 * @dbgc_size: DBGC buffer size 150 * @early_enable: Enarly debug enable 151 * @dbg_output_mode: Debug output mode 152 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) } 153 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI } 154 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1) 155 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK } 156 * @dbg_preset: Debug preset 157 * @ext_addr: Address of context information extension 158 * @ext_size: Size of context information part 159 * 160 * Total 38 DWords 161 */ 162 struct ctx_info { 163 u16 version; 164 u16 size; 165 u32 config; 166 u32 reserved_dw02; 167 u32 reserved_dw03; 168 u64 addr_tr_hia; 169 u64 addr_tr_tia; 170 u64 addr_cr_hia; 171 u64 addr_cr_tia; 172 u16 num_tr_ia; 173 u16 num_cr_ia; 174 u32 rbd_size:4, 175 reserved_dw13:28; 176 u64 addr_tfdq; 177 u64 addr_urbdq0; 178 u16 num_tfdq; 179 u16 num_urbdq0; 180 u16 tfdq_db_vec; 181 u16 urbdq0_db_vec; 182 u64 addr_frbdq; 183 u64 addr_urbdq1; 184 u16 num_frbdq; 185 u16 frbdq_db_vec; 186 u16 num_urbdq1; 187 u16 urbdq_db_vec; 188 u16 tr_msi_vec; 189 u16 cr_msi_vec; 190 u32 reserved_dw27; 191 u64 dbgc_addr; 192 u32 dbgc_size; 193 u32 early_enable:1, 194 reserved_dw31:3, 195 dbg_output_mode:4, 196 dbg_preset:8, 197 reserved2_dw31:16; 198 u64 ext_addr; 199 u32 ext_size; 200 u32 test_param; 201 u32 reserved_dw36; 202 u32 reserved_dw37; 203 } __packed; 204 205 /* Transfer Descriptor for TX 206 * @type: Not in use. Set to 0x0 207 * @size: Size of data in the buffer 208 * @addr: DMA Address of buffer 209 */ 210 struct tfd { 211 u8 type; 212 u16 size; 213 u8 reserved; 214 u64 addr; 215 u32 reserved1; 216 } __packed; 217 218 /* URB Descriptor for TX 219 * @tfd_index: Index of TFD in TFDQ + 1 220 * @num_txq: Queue index of TFD Queue 221 * @cmpl_count: Completion count. Always 0x01 222 * @immediate_cmpl: Immediate completion flag: Always 0x01 223 */ 224 struct urbd0 { 225 u32 tfd_index:16, 226 num_txq:8, 227 cmpl_count:4, 228 reserved:3, 229 immediate_cmpl:1; 230 } __packed; 231 232 /* FRB Descriptor for RX 233 * @tag: RX buffer tag (index of RX buffer queue) 234 * @addr: Address of buffer 235 */ 236 struct frbd { 237 u32 tag:16, 238 reserved:16; 239 u32 reserved2; 240 u64 addr; 241 } __packed; 242 243 /* URB Descriptor for RX 244 * @frbd_tag: Tag from FRBD 245 * @status: Status 246 */ 247 struct urbd1 { 248 u32 frbd_tag:16, 249 status:1, 250 reserved:14, 251 fixed:1; 252 } __packed; 253 254 /* RFH header in RX packet 255 * @packet_len: Length of the data in the buffer 256 * @rxq: RX Queue number 257 * @cmd_id: Command ID. Not in Use 258 */ 259 struct rfh_hdr { 260 u64 packet_len:16, 261 rxq:6, 262 reserved:10, 263 cmd_id:16, 264 reserved1:16; 265 } __packed; 266 267 /* Internal data buffer 268 * @data: pointer to the data buffer 269 * @p_addr: physical address of data buffer 270 */ 271 struct data_buf { 272 u8 *data; 273 dma_addr_t data_p_addr; 274 }; 275 276 /* Index Array */ 277 struct ia { 278 dma_addr_t tr_hia_p_addr; 279 u16 *tr_hia; 280 dma_addr_t tr_tia_p_addr; 281 u16 *tr_tia; 282 dma_addr_t cr_hia_p_addr; 283 u16 *cr_hia; 284 dma_addr_t cr_tia_p_addr; 285 u16 *cr_tia; 286 }; 287 288 /* Structure for TX Queue 289 * @count: Number of descriptors 290 * @tfds: Array of TFD 291 * @urbd0s: Array of URBD0 292 * @buf: Array of data_buf structure 293 */ 294 struct txq { 295 u16 count; 296 297 dma_addr_t tfds_p_addr; 298 struct tfd *tfds; 299 300 dma_addr_t urbd0s_p_addr; 301 struct urbd0 *urbd0s; 302 303 dma_addr_t buf_p_addr; 304 void *buf_v_addr; 305 struct data_buf *bufs; 306 }; 307 308 /* Structure for RX Queue 309 * @count: Number of descriptors 310 * @frbds: Array of FRBD 311 * @urbd1s: Array of URBD1 312 * @buf: Array of data_buf structure 313 */ 314 struct rxq { 315 u16 count; 316 317 dma_addr_t frbds_p_addr; 318 struct frbd *frbds; 319 320 dma_addr_t urbd1s_p_addr; 321 struct urbd1 *urbd1s; 322 323 dma_addr_t buf_p_addr; 324 void *buf_v_addr; 325 struct data_buf *bufs; 326 }; 327 328 /* struct btintel_pcie_data 329 * @pdev: pci device 330 * @hdev: hdev device 331 * @flags: driver state 332 * @irq_lock: spinlock for MSI-X 333 * @hci_rx_lock: spinlock for HCI RX flow 334 * @base_addr: pci base address (from BAR) 335 * @msix_entries: array of MSI-X entries 336 * @msix_enabled: true if MSI-X is enabled; 337 * @alloc_vecs: number of interrupt vectors allocated 338 * @def_irq: default irq for all causes 339 * @fh_init_mask: initial unmasked rxq causes 340 * @hw_init_mask: initial unmaksed hw causes 341 * @boot_stage_cache: cached value of boot stage register 342 * @img_resp_cache: cached value of image response register 343 * @cnvi: CNVi register value 344 * @cnvr: CNVr register value 345 * @gp0_received: condition for gp0 interrupt 346 * @gp0_wait_q: wait_q for gp0 interrupt 347 * @tx_wait_done: condition for tx interrupt 348 * @tx_wait_q: wait_q for tx interrupt 349 * @workqueue: workqueue for RX work 350 * @rx_skb_q: SKB queue for RX packet 351 * @rx_work: RX work struct to process the RX packet in @rx_skb_q 352 * @dma_pool: DMA pool for descriptors, index array and ci 353 * @dma_p_addr: DMA address for pool 354 * @dma_v_addr: address of pool 355 * @ci_p_addr: DMA address for CI struct 356 * @ci: CI struct 357 * @ia: Index Array struct 358 * @txq: TX Queue struct 359 * @rxq: RX Queue struct 360 * @alive_intr_ctxt: Alive interrupt context 361 */ 362 struct btintel_pcie_data { 363 struct pci_dev *pdev; 364 struct hci_dev *hdev; 365 366 unsigned long flags; 367 /* lock used in MSI-X interrupt */ 368 spinlock_t irq_lock; 369 /* lock to serialize rx events */ 370 spinlock_t hci_rx_lock; 371 372 void __iomem *base_addr; 373 374 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX]; 375 bool msix_enabled; 376 u32 alloc_vecs; 377 u32 def_irq; 378 379 u32 fh_init_mask; 380 u32 hw_init_mask; 381 382 u32 boot_stage_cache; 383 u32 img_resp_cache; 384 385 u32 cnvi; 386 u32 cnvr; 387 388 bool gp0_received; 389 wait_queue_head_t gp0_wait_q; 390 391 bool tx_wait_done; 392 wait_queue_head_t tx_wait_q; 393 394 struct workqueue_struct *workqueue; 395 struct sk_buff_head rx_skb_q; 396 struct work_struct rx_work; 397 398 struct dma_pool *dma_pool; 399 dma_addr_t dma_p_addr; 400 void *dma_v_addr; 401 402 dma_addr_t ci_p_addr; 403 struct ctx_info *ci; 404 struct ia ia; 405 struct txq txq; 406 struct rxq rxq; 407 u32 alive_intr_ctxt; 408 }; 409 410 static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data, 411 u32 offset) 412 { 413 return ioread32(data->base_addr + offset); 414 } 415 416 static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data, 417 u32 offset, u8 val) 418 { 419 iowrite8(val, data->base_addr + offset); 420 } 421 422 static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data, 423 u32 offset, u32 val) 424 { 425 iowrite32(val, data->base_addr + offset); 426 } 427 428 static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data, 429 u32 offset, u32 bits) 430 { 431 u32 r; 432 433 r = ioread32(data->base_addr + offset); 434 r |= bits; 435 iowrite32(r, data->base_addr + offset); 436 } 437 438 static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data, 439 u32 offset, u32 bits) 440 { 441 u32 r; 442 443 r = ioread32(data->base_addr + offset); 444 r &= ~bits; 445 iowrite32(r, data->base_addr + offset); 446 } 447