1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * 4 * Bluetooth support for Intel PCIe devices 5 * 6 * Copyright (C) 2024 Intel Corporation 7 */ 8 9 /* Control and Status Register(BTINTEL_PCIE_CSR) */ 10 #define BTINTEL_PCIE_CSR_BASE (0x000) 11 #define BTINTEL_PCIE_CSR_FUNC_CTRL_REG (BTINTEL_PCIE_CSR_BASE + 0x024) 12 #define BTINTEL_PCIE_CSR_HW_REV_REG (BTINTEL_PCIE_CSR_BASE + 0x028) 13 #define BTINTEL_PCIE_CSR_RF_ID_REG (BTINTEL_PCIE_CSR_BASE + 0x09C) 14 #define BTINTEL_PCIE_CSR_BOOT_STAGE_REG (BTINTEL_PCIE_CSR_BASE + 0x108) 15 #define BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG (BTINTEL_PCIE_CSR_BASE + 0x114) 16 #define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118) 17 #define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C) 18 #define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C) 19 #define BTINTEL_PCIE_PRPH_DEV_ADDR_REG (BTINTEL_PCIE_CSR_BASE + 0x440) 20 #define BTINTEL_PCIE_PRPH_DEV_RD_REG (BTINTEL_PCIE_CSR_BASE + 0x458) 21 #define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460) 22 23 /* BTINTEL_PCIE_CSR Function Control Register */ 24 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA (BIT(0)) 25 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6)) 26 #define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7)) 27 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20)) 28 29 #define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ (BIT(21)) 30 /* Stop MAC Access disconnection request */ 31 #define BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS (BIT(22)) 32 #define BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ (BIT(23)) 33 34 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28)) 35 #define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29)) 36 #define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31)) 37 38 /* Value for BTINTEL_PCIE_CSR_BOOT_STAGE register */ 39 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM (BIT(0)) 40 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML (BIT(1)) 41 #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW (BIT(2)) 42 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN (BIT(10)) 43 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN (BIT(11)) 44 #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON (BIT(16)) 45 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ALIVE (BIT(23)) 46 #define BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY (BIT(24)) 47 48 /* Registers for MSI-X */ 49 #define BTINTEL_PCIE_CSR_MSIX_BASE (0x2000) 50 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0800) 51 #define BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0804) 52 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0808) 53 #define BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK (BTINTEL_PCIE_CSR_MSIX_BASE + 0x080C) 54 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0810) 55 #define BTINTEL_PCIE_CSR_MSIX_AUTOMASK_EN (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0814) 56 #define BTINTEL_PCIE_CSR_MSIX_IVAR_BASE (BTINTEL_PCIE_CSR_MSIX_BASE + 0x0880) 57 #define BTINTEL_PCIE_CSR_MSIX_IVAR(cause) (BTINTEL_PCIE_CSR_MSIX_IVAR_BASE + (cause)) 58 59 /* IOSF Debug Register */ 60 #define BTINTEL_PCIE_DBGC_BASE_ADDR (0xf3800300) 61 #define BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x1C) 62 #define BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND (BTINTEL_PCIE_DBGC_BASE_ADDR + 0x2C) 63 64 #define BTINTEL_PCIE_DBG_IDX_BIT_MASK 0x0F 65 #define BTINTEL_PCIE_DBGC_DBG_BUF_IDX(data) (((data) >> 24) & BTINTEL_PCIE_DBG_IDX_BIT_MASK) 66 #define BTINTEL_PCIE_DBG_OFFSET_BIT_MASK 0xFFFFFF 67 68 /* The DRAM buffer count, each buffer size, and 69 * fragment buffer size 70 */ 71 #define BTINTEL_PCIE_DBGC_BUFFER_COUNT 16 72 #define BTINTEL_PCIE_DBGC_BUFFER_SIZE (256 * 1024) /* 256 KB */ 73 74 #define BTINTEL_PCIE_DBGC_FRAG_VERSION 1 75 #define BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT BTINTEL_PCIE_DBGC_BUFFER_COUNT 76 77 /* Magic number(4), version(4), size of payload length(4) */ 78 #define BTINTEL_PCIE_DBGC_FRAG_HEADER_SIZE 12 79 80 /* Num of alloc Dbg buff (4) + (LSB(4), MSB(4), Size(4)) for each buffer */ 81 #define BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE 196 82 83 /* Causes for the FH register interrupts */ 84 enum msix_fh_int_causes { 85 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0 = BIT(0), /* cause 0 */ 86 BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1 = BIT(1), /* cause 1 */ 87 }; 88 89 /* Causes for the HW register interrupts */ 90 enum msix_hw_int_causes { 91 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */ 92 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP = BIT(3), /* cause 35 */ 93 }; 94 95 /* PCIe device states 96 * Host-Device interface is active 97 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 98 * Host-Device interface is inactive(as reflected by IPC_SLEEP_CONTROL_CSR_AD) 99 */ 100 enum { 101 BTINTEL_PCIE_STATE_D0 = 0, 102 BTINTEL_PCIE_STATE_D3_HOT = 2, 103 BTINTEL_PCIE_STATE_D3_COLD = 3, 104 }; 105 106 enum { 107 BTINTEL_PCIE_CORE_HALTED, 108 BTINTEL_PCIE_HWEXP_INPROGRESS, 109 BTINTEL_PCIE_COREDUMP_INPROGRESS 110 }; 111 112 enum btintel_pcie_tlv_type { 113 BTINTEL_CNVI_BT, 114 BTINTEL_WRITE_PTR, 115 BTINTEL_WRAP_CTR, 116 BTINTEL_TRIGGER_REASON, 117 BTINTEL_FW_SHA, 118 BTINTEL_CNVR_TOP, 119 BTINTEL_CNVI_TOP, 120 BTINTEL_DUMP_TIME, 121 BTINTEL_FW_BUILD, 122 }; 123 124 #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7) 125 126 /* Minimum and Maximum number of MSI-X Vector 127 * Intel Bluetooth PCIe support only 1 vector 128 */ 129 #define BTINTEL_PCIE_MSIX_VEC_MAX 1 130 #define BTINTEL_PCIE_MSIX_VEC_MIN 1 131 132 /* Default poll time for MAC access during init */ 133 #define BTINTEL_DEFAULT_MAC_ACCESS_TIMEOUT_US 200000 134 135 /* Default interrupt timeout in msec */ 136 #define BTINTEL_DEFAULT_INTR_TIMEOUT_MS 3000 137 138 /* The number of descriptors in TX/RX queues */ 139 #define BTINTEL_DESCS_COUNT 16 140 141 /* Number of Queue for TX and RX 142 * It indicates the index of the IA(Index Array) 143 */ 144 enum { 145 BTINTEL_PCIE_TXQ_NUM = 0, 146 BTINTEL_PCIE_RXQ_NUM = 1, 147 BTINTEL_PCIE_NUM_QUEUES = 2, 148 }; 149 150 /* The size of DMA buffer for TX and RX in bytes */ 151 #define BTINTEL_PCIE_BUFFER_SIZE 4096 152 153 /* DMA allocation alignment */ 154 #define BTINTEL_PCIE_DMA_POOL_ALIGNMENT 256 155 156 #define BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS 500 157 158 /* Doorbell vector for TFD */ 159 #define BTINTEL_PCIE_TX_DB_VEC 0 160 161 /* Number of pending RX requests for downlink */ 162 #define BTINTEL_PCIE_RX_MAX_QUEUE 6 163 164 /* Doorbell vector for FRBD */ 165 #define BTINTEL_PCIE_RX_DB_VEC 513 166 167 /* RBD buffer size mapping */ 168 #define BTINTEL_PCIE_RBD_SIZE_4K 0x04 169 170 /* 171 * Struct for Context Information (v2) 172 * 173 * All members are write-only for host and read-only for device. 174 * 175 * @version: Version of context information 176 * @size: Size of context information 177 * @config: Config with which host wants peripheral to execute 178 * Subset of capability register published by device 179 * @addr_tr_hia: Address of TR Head Index Array 180 * @addr_tr_tia: Address of TR Tail Index Array 181 * @addr_cr_hia: Address of CR Head Index Array 182 * @addr_cr_tia: Address of CR Tail Index Array 183 * @num_tr_ia: Number of entries in TR Index Arrays 184 * @num_cr_ia: Number of entries in CR Index Arrays 185 * @rbd_siz: RBD Size { 0x4=4K } 186 * @addr_tfdq: Address of TFD Queue(tx) 187 * @addr_urbdq0: Address of URBD Queue(tx) 188 * @num_tfdq: Number of TFD in TFD Queue(tx) 189 * @num_urbdq0: Number of URBD in URBD Queue(tx) 190 * @tfdq_db_vec: Queue number of TFD 191 * @urbdq0_db_vec: Queue number of URBD 192 * @addr_frbdq: Address of FRBD Queue(rx) 193 * @addr_urbdq1: Address of URBD Queue(rx) 194 * @num_frbdq: Number of FRBD in FRBD Queue(rx) 195 * @frbdq_db_vec: Queue number of FRBD 196 * @num_urbdq1: Number of URBD in URBD Queue(rx) 197 * @urbdq_db_vec: Queue number of URBDQ1 198 * @tr_msi_vec: Transfer Ring MSI-X Vector 199 * @cr_msi_vec: Completion Ring MSI-X Vector 200 * @dbgc_addr: DBGC first fragment address 201 * @dbgc_size: DBGC buffer size 202 * @early_enable: Enarly debug enable 203 * @dbg_output_mode: Debug output mode 204 * Bit[4] DBGC O/P { 0=SRAM, 1=DRAM(not relevant for NPK) } 205 * Bit[5] DBGC I/P { 0=BDBG, 1=DBGI } 206 * Bits[6:7] DBGI O/P(relevant if bit[5] = 1) 207 * 0=BT DBGC, 1=WiFi DBGC, 2=NPK } 208 * @dbg_preset: Debug preset 209 * @ext_addr: Address of context information extension 210 * @ext_size: Size of context information part 211 * 212 * Total 38 DWords 213 */ 214 struct ctx_info { 215 u16 version; 216 u16 size; 217 u32 config; 218 u32 reserved_dw02; 219 u32 reserved_dw03; 220 u64 addr_tr_hia; 221 u64 addr_tr_tia; 222 u64 addr_cr_hia; 223 u64 addr_cr_tia; 224 u16 num_tr_ia; 225 u16 num_cr_ia; 226 u32 rbd_size:4, 227 reserved_dw13:28; 228 u64 addr_tfdq; 229 u64 addr_urbdq0; 230 u16 num_tfdq; 231 u16 num_urbdq0; 232 u16 tfdq_db_vec; 233 u16 urbdq0_db_vec; 234 u64 addr_frbdq; 235 u64 addr_urbdq1; 236 u16 num_frbdq; 237 u16 frbdq_db_vec; 238 u16 num_urbdq1; 239 u16 urbdq_db_vec; 240 u16 tr_msi_vec; 241 u16 cr_msi_vec; 242 u32 reserved_dw27; 243 u64 dbgc_addr; 244 u32 dbgc_size; 245 u32 early_enable:1, 246 reserved_dw31:3, 247 dbg_output_mode:4, 248 dbg_preset:8, 249 reserved2_dw31:16; 250 u64 ext_addr; 251 u32 ext_size; 252 u32 test_param; 253 u32 reserved_dw36; 254 u32 reserved_dw37; 255 } __packed; 256 257 /* Transfer Descriptor for TX 258 * @type: Not in use. Set to 0x0 259 * @size: Size of data in the buffer 260 * @addr: DMA Address of buffer 261 */ 262 struct tfd { 263 u8 type; 264 u16 size; 265 u8 reserved; 266 u64 addr; 267 u32 reserved1; 268 } __packed; 269 270 /* URB Descriptor for TX 271 * @tfd_index: Index of TFD in TFDQ + 1 272 * @num_txq: Queue index of TFD Queue 273 * @cmpl_count: Completion count. Always 0x01 274 * @immediate_cmpl: Immediate completion flag: Always 0x01 275 */ 276 struct urbd0 { 277 u32 tfd_index:16, 278 num_txq:8, 279 cmpl_count:4, 280 reserved:3, 281 immediate_cmpl:1; 282 } __packed; 283 284 /* FRB Descriptor for RX 285 * @tag: RX buffer tag (index of RX buffer queue) 286 * @addr: Address of buffer 287 */ 288 struct frbd { 289 u32 tag:16, 290 reserved:16; 291 u32 reserved2; 292 u64 addr; 293 } __packed; 294 295 /* URB Descriptor for RX 296 * @frbd_tag: Tag from FRBD 297 * @status: Status 298 */ 299 struct urbd1 { 300 u32 frbd_tag:16, 301 status:1, 302 reserved:14, 303 fixed:1; 304 } __packed; 305 306 /* RFH header in RX packet 307 * @packet_len: Length of the data in the buffer 308 * @rxq: RX Queue number 309 * @cmd_id: Command ID. Not in Use 310 */ 311 struct rfh_hdr { 312 u64 packet_len:16, 313 rxq:6, 314 reserved:10, 315 cmd_id:16, 316 reserved1:16; 317 } __packed; 318 319 /* Internal data buffer 320 * @data: pointer to the data buffer 321 * @p_addr: physical address of data buffer 322 */ 323 struct data_buf { 324 u8 *data; 325 dma_addr_t data_p_addr; 326 }; 327 328 /* Index Array */ 329 struct ia { 330 dma_addr_t tr_hia_p_addr; 331 u16 *tr_hia; 332 dma_addr_t tr_tia_p_addr; 333 u16 *tr_tia; 334 dma_addr_t cr_hia_p_addr; 335 u16 *cr_hia; 336 dma_addr_t cr_tia_p_addr; 337 u16 *cr_tia; 338 }; 339 340 /* Structure for TX Queue 341 * @count: Number of descriptors 342 * @tfds: Array of TFD 343 * @urbd0s: Array of URBD0 344 * @buf: Array of data_buf structure 345 */ 346 struct txq { 347 u16 count; 348 349 dma_addr_t tfds_p_addr; 350 struct tfd *tfds; 351 352 dma_addr_t urbd0s_p_addr; 353 struct urbd0 *urbd0s; 354 355 dma_addr_t buf_p_addr; 356 void *buf_v_addr; 357 struct data_buf *bufs; 358 }; 359 360 /* Structure for RX Queue 361 * @count: Number of descriptors 362 * @frbds: Array of FRBD 363 * @urbd1s: Array of URBD1 364 * @buf: Array of data_buf structure 365 */ 366 struct rxq { 367 u16 count; 368 369 dma_addr_t frbds_p_addr; 370 struct frbd *frbds; 371 372 dma_addr_t urbd1s_p_addr; 373 struct urbd1 *urbd1s; 374 375 dma_addr_t buf_p_addr; 376 void *buf_v_addr; 377 struct data_buf *bufs; 378 }; 379 380 /* Structure for DRAM Buffer 381 * @count: Number of descriptors 382 * @buf: Array of data_buf structure 383 */ 384 struct btintel_pcie_dbgc { 385 u16 count; 386 387 void *frag_v_addr; 388 dma_addr_t frag_p_addr; 389 u16 frag_size; 390 391 dma_addr_t buf_p_addr; 392 void *buf_v_addr; 393 struct data_buf *bufs; 394 }; 395 396 struct btintel_pcie_dump_header { 397 const char *driver_name; 398 u32 cnvi_top; 399 u32 cnvr_top; 400 u16 fw_timestamp; 401 u8 fw_build_type; 402 u32 fw_build_num; 403 u32 fw_git_sha1; 404 u32 cnvi_bt; 405 u32 write_ptr; 406 u32 wrap_ctr; 407 u16 trigger_reason; 408 int state; 409 }; 410 411 /* struct btintel_pcie_data 412 * @pdev: pci device 413 * @hdev: hdev device 414 * @flags: driver state 415 * @irq_lock: spinlock for MSI-X 416 * @hci_rx_lock: spinlock for HCI RX flow 417 * @base_addr: pci base address (from BAR) 418 * @msix_entries: array of MSI-X entries 419 * @msix_enabled: true if MSI-X is enabled; 420 * @alloc_vecs: number of interrupt vectors allocated 421 * @def_irq: default irq for all causes 422 * @fh_init_mask: initial unmasked rxq causes 423 * @hw_init_mask: initial unmaksed hw causes 424 * @boot_stage_cache: cached value of boot stage register 425 * @img_resp_cache: cached value of image response register 426 * @cnvi: CNVi register value 427 * @cnvr: CNVr register value 428 * @gp0_received: condition for gp0 interrupt 429 * @gp0_wait_q: wait_q for gp0 interrupt 430 * @tx_wait_done: condition for tx interrupt 431 * @tx_wait_q: wait_q for tx interrupt 432 * @workqueue: workqueue for RX work 433 * @rx_skb_q: SKB queue for RX packet 434 * @rx_work: RX work struct to process the RX packet in @rx_skb_q 435 * @dma_pool: DMA pool for descriptors, index array and ci 436 * @dma_p_addr: DMA address for pool 437 * @dma_v_addr: address of pool 438 * @ci_p_addr: DMA address for CI struct 439 * @ci: CI struct 440 * @ia: Index Array struct 441 * @txq: TX Queue struct 442 * @rxq: RX Queue struct 443 * @alive_intr_ctxt: Alive interrupt context 444 */ 445 struct btintel_pcie_data { 446 struct pci_dev *pdev; 447 struct hci_dev *hdev; 448 449 unsigned long flags; 450 /* lock used in MSI-X interrupt */ 451 spinlock_t irq_lock; 452 /* lock to serialize rx events */ 453 spinlock_t hci_rx_lock; 454 455 void __iomem *base_addr; 456 457 struct msix_entry msix_entries[BTINTEL_PCIE_MSIX_VEC_MAX]; 458 bool msix_enabled; 459 u32 alloc_vecs; 460 u32 def_irq; 461 462 u32 fh_init_mask; 463 u32 hw_init_mask; 464 465 u32 boot_stage_cache; 466 u32 img_resp_cache; 467 468 u32 cnvi; 469 u32 cnvr; 470 471 bool gp0_received; 472 wait_queue_head_t gp0_wait_q; 473 474 bool tx_wait_done; 475 wait_queue_head_t tx_wait_q; 476 477 struct workqueue_struct *workqueue; 478 struct sk_buff_head rx_skb_q; 479 struct work_struct rx_work; 480 481 struct dma_pool *dma_pool; 482 dma_addr_t dma_p_addr; 483 void *dma_v_addr; 484 485 dma_addr_t ci_p_addr; 486 struct ctx_info *ci; 487 struct ia ia; 488 struct txq txq; 489 struct rxq rxq; 490 u32 alive_intr_ctxt; 491 struct btintel_pcie_dbgc dbgc; 492 struct btintel_pcie_dump_header dmp_hdr; 493 }; 494 495 static inline u32 btintel_pcie_rd_reg32(struct btintel_pcie_data *data, 496 u32 offset) 497 { 498 return ioread32(data->base_addr + offset); 499 } 500 501 static inline void btintel_pcie_wr_reg8(struct btintel_pcie_data *data, 502 u32 offset, u8 val) 503 { 504 iowrite8(val, data->base_addr + offset); 505 } 506 507 static inline void btintel_pcie_wr_reg32(struct btintel_pcie_data *data, 508 u32 offset, u32 val) 509 { 510 iowrite32(val, data->base_addr + offset); 511 } 512 513 static inline void btintel_pcie_set_reg_bits(struct btintel_pcie_data *data, 514 u32 offset, u32 bits) 515 { 516 u32 r; 517 518 r = ioread32(data->base_addr + offset); 519 r |= bits; 520 iowrite32(r, data->base_addr + offset); 521 } 522 523 static inline void btintel_pcie_clr_reg_bits(struct btintel_pcie_data *data, 524 u32 offset, u32 bits) 525 { 526 u32 r; 527 528 r = ioread32(data->base_addr + offset); 529 r &= ~bits; 530 iowrite32(r, data->base_addr + offset); 531 } 532 533 static inline u32 btintel_pcie_rd_dev_mem(struct btintel_pcie_data *data, 534 u32 addr) 535 { 536 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_PRPH_DEV_ADDR_REG, addr); 537 return btintel_pcie_rd_reg32(data, BTINTEL_PCIE_PRPH_DEV_RD_REG); 538 } 539 540