1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * Bluetooth support for Intel PCIe devices 5 * 6 * Copyright (C) 2024 Intel Corporation 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/firmware.h> 12 #include <linux/overflow.h> 13 #include <linux/pci.h> 14 #include <linux/string.h> 15 #include <linux/wait.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 19 #include <linux/unaligned.h> 20 #include <linux/devcoredump.h> 21 22 #include <net/bluetooth/bluetooth.h> 23 #include <net/bluetooth/hci_core.h> 24 #include <net/bluetooth/hci_drv.h> 25 26 #include "btintel.h" 27 #include "btintel_pcie.h" 28 29 #define VERSION "0.1" 30 31 #define BTINTEL_PCI_DEVICE(dev, subdev) \ 32 .vendor = PCI_VENDOR_ID_INTEL, \ 33 .device = (dev), \ 34 .subvendor = PCI_ANY_ID, \ 35 .subdevice = (subdev), \ 36 .driver_data = 0 37 38 #define POLL_INTERVAL_US 10 39 40 #define BTINTEL_PCIE_DMA_ALIGN_128B 128 /* 128 byte aligned */ 41 42 /* Intel Bluetooth PCIe device id table */ 43 static const struct pci_device_id btintel_pcie_table[] = { 44 /* BlazarI, Wildcat Lake */ 45 { BTINTEL_PCI_DEVICE(0x4D76, PCI_ANY_ID) }, 46 /* BlazarI, Lunar Lake */ 47 { BTINTEL_PCI_DEVICE(0xA876, PCI_ANY_ID) }, 48 /* Scorpious, Panther Lake-H484 */ 49 { BTINTEL_PCI_DEVICE(0xE376, PCI_ANY_ID) }, 50 /* Scorpious, Panther Lake-H404 */ 51 { BTINTEL_PCI_DEVICE(0xE476, PCI_ANY_ID) }, 52 /* Scorpious2, Nova Lake-PCD-H */ 53 { BTINTEL_PCI_DEVICE(0xD346, PCI_ANY_ID) }, 54 /* Scorpious2, Nova Lake-PCD-S */ 55 { BTINTEL_PCI_DEVICE(0x6E74, PCI_ANY_ID) }, 56 { 0 } 57 }; 58 MODULE_DEVICE_TABLE(pci, btintel_pcie_table); 59 60 struct btintel_pcie_dev_recovery { 61 struct list_head list; 62 u8 count; 63 time64_t last_error; 64 char name[]; 65 }; 66 67 /* Intel PCIe uses 4 bytes of HCI type instead of 1 byte BT SIG HCI type */ 68 #define BTINTEL_PCIE_HCI_TYPE_LEN 4 69 #define BTINTEL_PCIE_HCI_CMD_PKT 0x00000001 70 #define BTINTEL_PCIE_HCI_ACL_PKT 0x00000002 71 #define BTINTEL_PCIE_HCI_SCO_PKT 0x00000003 72 #define BTINTEL_PCIE_HCI_EVT_PKT 0x00000004 73 #define BTINTEL_PCIE_HCI_ISO_PKT 0x00000005 74 75 #define BTINTEL_PCIE_MAGIC_NUM 0xA5A5A5A5 76 77 #define BTINTEL_PCIE_BLZR_HWEXP_SIZE 1024 78 #define BTINTEL_PCIE_BLZR_HWEXP_DMP_ADDR 0xB00A7C00 79 80 #define BTINTEL_PCIE_SCP_HWEXP_SIZE 4096 81 #define BTINTEL_PCIE_SCP_HWEXP_DMP_ADDR 0xB030F800 82 83 #define BTINTEL_PCIE_SCP2_HWEXP_SIZE 4096 84 #define BTINTEL_PCIE_SCP2_HWEXP_DMP_ADDR 0xB031D000 85 86 #define BTINTEL_PCIE_MAGIC_NUM 0xA5A5A5A5 87 88 #define BTINTEL_PCIE_TRIGGER_REASON_USER_TRIGGER 0x17A2 89 #define BTINTEL_PCIE_TRIGGER_REASON_FW_ASSERT 0x1E61 90 91 #define BTINTEL_PCIE_RESET_WINDOW_SECS 5 92 #define BTINTEL_PCIE_FLR_MAX_RETRY 1 93 94 /* Alive interrupt context */ 95 enum { 96 BTINTEL_PCIE_ROM, 97 BTINTEL_PCIE_FW_DL, 98 BTINTEL_PCIE_HCI_RESET, 99 BTINTEL_PCIE_INTEL_HCI_RESET1, 100 BTINTEL_PCIE_INTEL_HCI_RESET2, 101 BTINTEL_PCIE_D0, 102 BTINTEL_PCIE_D3 103 }; 104 105 /* Structure for dbgc fragment buffer 106 * @buf_addr_lsb: LSB of the buffer's physical address 107 * @buf_addr_msb: MSB of the buffer's physical address 108 * @buf_size: Total size of the buffer 109 */ 110 struct btintel_pcie_dbgc_ctxt_buf { 111 u32 buf_addr_lsb; 112 u32 buf_addr_msb; 113 u32 buf_size; 114 }; 115 116 /* Structure for dbgc fragment 117 * @magic_num: 0XA5A5A5A5 118 * @ver: For Driver-FW compatibility 119 * @total_size: Total size of the payload debug info 120 * @num_buf: Num of allocated debug bufs 121 * @bufs: All buffer's addresses and sizes 122 */ 123 struct btintel_pcie_dbgc_ctxt { 124 u32 magic_num; 125 u32 ver; 126 u32 total_size; 127 u32 num_buf; 128 struct btintel_pcie_dbgc_ctxt_buf bufs[BTINTEL_PCIE_DBGC_BUFFER_COUNT]; 129 }; 130 131 struct btintel_pcie_removal { 132 struct pci_dev *pdev; 133 struct work_struct work; 134 }; 135 136 static LIST_HEAD(btintel_pcie_recovery_list); 137 static DEFINE_SPINLOCK(btintel_pcie_recovery_lock); 138 139 static inline char *btintel_pcie_alivectxt_state2str(u32 alive_intr_ctxt) 140 { 141 switch (alive_intr_ctxt) { 142 case BTINTEL_PCIE_ROM: 143 return "rom"; 144 case BTINTEL_PCIE_FW_DL: 145 return "fw_dl"; 146 case BTINTEL_PCIE_D0: 147 return "d0"; 148 case BTINTEL_PCIE_D3: 149 return "d3"; 150 case BTINTEL_PCIE_HCI_RESET: 151 return "hci_reset"; 152 case BTINTEL_PCIE_INTEL_HCI_RESET1: 153 return "intel_reset1"; 154 case BTINTEL_PCIE_INTEL_HCI_RESET2: 155 return "intel_reset2"; 156 default: 157 return "unknown"; 158 } 159 } 160 161 /* This function initializes the memory for DBGC buffers and formats the 162 * DBGC fragment which consists header info and DBGC buffer's LSB, MSB and 163 * size as the payload 164 */ 165 static int btintel_pcie_setup_dbgc(struct btintel_pcie_data *data) 166 { 167 struct btintel_pcie_dbgc_ctxt db_frag; 168 struct data_buf *buf; 169 int i; 170 171 data->dbgc.count = BTINTEL_PCIE_DBGC_BUFFER_COUNT; 172 data->dbgc.bufs = devm_kcalloc(&data->pdev->dev, data->dbgc.count, 173 sizeof(*buf), GFP_KERNEL); 174 if (!data->dbgc.bufs) 175 return -ENOMEM; 176 177 data->dbgc.buf_v_addr = dmam_alloc_coherent(&data->pdev->dev, 178 data->dbgc.count * 179 BTINTEL_PCIE_DBGC_BUFFER_SIZE, 180 &data->dbgc.buf_p_addr, 181 GFP_KERNEL | __GFP_NOWARN); 182 if (!data->dbgc.buf_v_addr) 183 return -ENOMEM; 184 185 data->dbgc.frag_v_addr = dmam_alloc_coherent(&data->pdev->dev, 186 sizeof(struct btintel_pcie_dbgc_ctxt), 187 &data->dbgc.frag_p_addr, 188 GFP_KERNEL | __GFP_NOWARN); 189 if (!data->dbgc.frag_v_addr) 190 return -ENOMEM; 191 192 data->dbgc.frag_size = sizeof(struct btintel_pcie_dbgc_ctxt); 193 194 db_frag.magic_num = BTINTEL_PCIE_MAGIC_NUM; 195 db_frag.ver = BTINTEL_PCIE_DBGC_FRAG_VERSION; 196 db_frag.total_size = BTINTEL_PCIE_DBGC_FRAG_PAYLOAD_SIZE; 197 db_frag.num_buf = BTINTEL_PCIE_DBGC_FRAG_BUFFER_COUNT; 198 199 for (i = 0; i < data->dbgc.count; i++) { 200 buf = &data->dbgc.bufs[i]; 201 buf->data_p_addr = data->dbgc.buf_p_addr + i * BTINTEL_PCIE_DBGC_BUFFER_SIZE; 202 buf->data = data->dbgc.buf_v_addr + i * BTINTEL_PCIE_DBGC_BUFFER_SIZE; 203 db_frag.bufs[i].buf_addr_lsb = lower_32_bits(buf->data_p_addr); 204 db_frag.bufs[i].buf_addr_msb = upper_32_bits(buf->data_p_addr); 205 db_frag.bufs[i].buf_size = BTINTEL_PCIE_DBGC_BUFFER_SIZE; 206 } 207 208 memcpy(data->dbgc.frag_v_addr, &db_frag, sizeof(db_frag)); 209 return 0; 210 } 211 212 static inline void ipc_print_ia_ring(struct hci_dev *hdev, struct ia *ia, 213 u16 queue_num) 214 { 215 bt_dev_dbg(hdev, "IA: %s: tr-h:%02u tr-t:%02u cr-h:%02u cr-t:%02u", 216 queue_num == BTINTEL_PCIE_TXQ_NUM ? "TXQ" : "RXQ", 217 ia->tr_hia[queue_num], ia->tr_tia[queue_num], 218 ia->cr_hia[queue_num], ia->cr_tia[queue_num]); 219 } 220 221 static inline void ipc_print_urbd1(struct hci_dev *hdev, struct urbd1 *urbd1, 222 u16 index) 223 { 224 bt_dev_dbg(hdev, "RXQ:urbd1(%u) frbd_tag:%u status: 0x%x fixed:0x%x", 225 index, urbd1->frbd_tag, urbd1->status, urbd1->fixed); 226 } 227 228 static struct btintel_pcie_data *btintel_pcie_get_data(struct msix_entry *entry) 229 { 230 u8 queue = entry->entry; 231 struct msix_entry *entries = entry - queue; 232 233 return container_of(entries, struct btintel_pcie_data, msix_entries[0]); 234 } 235 236 /* Set the doorbell for TXQ to notify the device that @index (actually index-1) 237 * of the TFD is updated and ready to transmit. 238 */ 239 static void btintel_pcie_set_tx_db(struct btintel_pcie_data *data, u16 index) 240 { 241 u32 val; 242 243 val = index; 244 val |= (BTINTEL_PCIE_TX_DB_VEC << 16); 245 246 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR, val); 247 } 248 249 /* Copy the data to next(@tfd_index) data buffer and update the TFD(transfer 250 * descriptor) with the data length and the DMA address of the data buffer. 251 */ 252 static void btintel_pcie_prepare_tx(struct txq *txq, u16 tfd_index, 253 struct sk_buff *skb) 254 { 255 struct data_buf *buf; 256 struct tfd *tfd; 257 258 tfd = &txq->tfds[tfd_index]; 259 memset(tfd, 0, sizeof(*tfd)); 260 261 buf = &txq->bufs[tfd_index]; 262 263 tfd->size = skb->len; 264 tfd->addr = buf->data_p_addr; 265 266 /* Copy the outgoing data to DMA buffer */ 267 memcpy(buf->data, skb->data, tfd->size); 268 } 269 270 static inline void btintel_pcie_dump_debug_registers(struct hci_dev *hdev) 271 { 272 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 273 u16 cr_hia, cr_tia; 274 u32 reg, mbox_reg; 275 struct sk_buff *skb; 276 u8 buf[80]; 277 278 skb = alloc_skb(1024, GFP_ATOMIC); 279 if (!skb) 280 return; 281 282 strscpy(buf, "---- Dump of debug registers ---"); 283 bt_dev_dbg(hdev, "%s", buf); 284 skb_put_data(skb, buf, strlen(buf)); 285 286 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_BOOT_STAGE_REG); 287 snprintf(buf, sizeof(buf), "boot stage: 0x%8.8x", reg); 288 bt_dev_dbg(hdev, "%s", buf); 289 skb_put_data(skb, buf, strlen(buf)); 290 data->boot_stage_cache = reg; 291 292 if (reg & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING) 293 bt_dev_warn(hdev, "Controller device warning (boot_stage: 0x%8.8x)", reg); 294 295 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_IPC_STATUS_REG); 296 snprintf(buf, sizeof(buf), "ipc status: 0x%8.8x", reg); 297 skb_put_data(skb, buf, strlen(buf)); 298 bt_dev_dbg(hdev, "%s", buf); 299 300 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_IPC_CONTROL_REG); 301 snprintf(buf, sizeof(buf), "ipc control: 0x%8.8x", reg); 302 skb_put_data(skb, buf, strlen(buf)); 303 bt_dev_dbg(hdev, "%s", buf); 304 305 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG); 306 snprintf(buf, sizeof(buf), "ipc sleep control: 0x%8.8x", reg); 307 skb_put_data(skb, buf, strlen(buf)); 308 bt_dev_dbg(hdev, "%s", buf); 309 310 /*Read the Mail box status and registers*/ 311 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_MBOX_STATUS_REG); 312 snprintf(buf, sizeof(buf), "mbox status: 0x%8.8x", reg); 313 skb_put_data(skb, buf, strlen(buf)); 314 if (reg & BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX1) { 315 mbox_reg = btintel_pcie_rd_reg32(data, 316 BTINTEL_PCIE_CSR_MBOX_1_REG); 317 snprintf(buf, sizeof(buf), "mbox_1: 0x%8.8x", mbox_reg); 318 skb_put_data(skb, buf, strlen(buf)); 319 bt_dev_dbg(hdev, "%s", buf); 320 } 321 322 if (reg & BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX2) { 323 mbox_reg = btintel_pcie_rd_reg32(data, 324 BTINTEL_PCIE_CSR_MBOX_2_REG); 325 snprintf(buf, sizeof(buf), "mbox_2: 0x%8.8x", mbox_reg); 326 skb_put_data(skb, buf, strlen(buf)); 327 bt_dev_dbg(hdev, "%s", buf); 328 } 329 330 if (reg & BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX3) { 331 mbox_reg = btintel_pcie_rd_reg32(data, 332 BTINTEL_PCIE_CSR_MBOX_3_REG); 333 snprintf(buf, sizeof(buf), "mbox_3: 0x%8.8x", mbox_reg); 334 skb_put_data(skb, buf, strlen(buf)); 335 bt_dev_dbg(hdev, "%s", buf); 336 } 337 338 if (reg & BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX4) { 339 mbox_reg = btintel_pcie_rd_reg32(data, 340 BTINTEL_PCIE_CSR_MBOX_4_REG); 341 snprintf(buf, sizeof(buf), "mbox_4: 0x%8.8x", mbox_reg); 342 skb_put_data(skb, buf, strlen(buf)); 343 bt_dev_dbg(hdev, "%s", buf); 344 } 345 346 cr_hia = data->ia.cr_hia[BTINTEL_PCIE_RXQ_NUM]; 347 cr_tia = data->ia.cr_tia[BTINTEL_PCIE_RXQ_NUM]; 348 snprintf(buf, sizeof(buf), "rxq: cr_tia: %u cr_hia: %u", cr_tia, cr_hia); 349 skb_put_data(skb, buf, strlen(buf)); 350 bt_dev_dbg(hdev, "%s", buf); 351 352 cr_hia = data->ia.cr_hia[BTINTEL_PCIE_TXQ_NUM]; 353 cr_tia = data->ia.cr_tia[BTINTEL_PCIE_TXQ_NUM]; 354 snprintf(buf, sizeof(buf), "txq: cr_tia: %u cr_hia: %u", cr_tia, cr_hia); 355 skb_put_data(skb, buf, strlen(buf)); 356 bt_dev_dbg(hdev, "%s", buf); 357 strscpy(buf, "--------------------------------"); 358 bt_dev_dbg(hdev, "%s", buf); 359 360 hci_recv_diag(hdev, skb); 361 } 362 363 static int btintel_pcie_send_sync(struct btintel_pcie_data *data, 364 struct sk_buff *skb, u32 pkt_type, u16 opcode) 365 { 366 int ret; 367 u16 tfd_index; 368 u32 old_ctxt; 369 bool wait_on_alive = false; 370 struct hci_dev *hdev = data->hdev; 371 372 struct txq *txq = &data->txq; 373 374 tfd_index = data->ia.tr_hia[BTINTEL_PCIE_TXQ_NUM]; 375 376 if (tfd_index > txq->count) 377 return -ERANGE; 378 379 /* Firmware raises alive interrupt on HCI_OP_RESET or 380 * BTINTEL_HCI_OP_RESET 381 */ 382 wait_on_alive = (pkt_type == BTINTEL_PCIE_HCI_CMD_PKT && 383 (opcode == BTINTEL_HCI_OP_RESET || opcode == HCI_OP_RESET)); 384 385 if (wait_on_alive) { 386 data->gp0_received = false; 387 old_ctxt = data->alive_intr_ctxt; 388 data->alive_intr_ctxt = 389 (opcode == BTINTEL_HCI_OP_RESET ? BTINTEL_PCIE_INTEL_HCI_RESET1 : 390 BTINTEL_PCIE_HCI_RESET); 391 bt_dev_dbg(data->hdev, "sending cmd: 0x%4.4x alive context changed: %s -> %s", 392 opcode, btintel_pcie_alivectxt_state2str(old_ctxt), 393 btintel_pcie_alivectxt_state2str(data->alive_intr_ctxt)); 394 } 395 396 memcpy(skb_push(skb, BTINTEL_PCIE_HCI_TYPE_LEN), &pkt_type, 397 BTINTEL_PCIE_HCI_TYPE_LEN); 398 399 /* Prepare for TX. It updates the TFD with the length of data and 400 * address of the DMA buffer, and copy the data to the DMA buffer 401 */ 402 btintel_pcie_prepare_tx(txq, tfd_index, skb); 403 404 tfd_index = (tfd_index + 1) % txq->count; 405 data->ia.tr_hia[BTINTEL_PCIE_TXQ_NUM] = tfd_index; 406 407 /* Arm wait event condition */ 408 data->tx_wait_done = false; 409 410 /* Set the doorbell to notify the device */ 411 btintel_pcie_set_tx_db(data, tfd_index); 412 413 /* Wait for the complete interrupt - URBD0 */ 414 ret = wait_event_timeout(data->tx_wait_q, data->tx_wait_done, 415 msecs_to_jiffies(BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS)); 416 if (!ret) { 417 bt_dev_err(data->hdev, "Timeout (%u ms) on tx completion", 418 BTINTEL_PCIE_TX_WAIT_TIMEOUT_MS); 419 btintel_pcie_dump_debug_registers(data->hdev); 420 return -ETIME; 421 } 422 423 if (wait_on_alive) { 424 ret = wait_event_timeout(data->gp0_wait_q, 425 data->gp0_received, 426 msecs_to_jiffies(BTINTEL_DEFAULT_INTR_TIMEOUT_MS)); 427 if (!ret) { 428 hdev->stat.err_tx++; 429 bt_dev_err(hdev, "Timeout (%u ms) on alive interrupt, alive context: %s", 430 BTINTEL_DEFAULT_INTR_TIMEOUT_MS, 431 btintel_pcie_alivectxt_state2str(data->alive_intr_ctxt)); 432 return -ETIME; 433 } 434 } 435 return 0; 436 } 437 438 /* Set the doorbell for RXQ to notify the device that @index (actually index-1) 439 * is available to receive the data 440 */ 441 static void btintel_pcie_set_rx_db(struct btintel_pcie_data *data, u16 index) 442 { 443 u32 val; 444 445 val = index; 446 val |= (BTINTEL_PCIE_RX_DB_VEC << 16); 447 448 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR, val); 449 } 450 451 /* Update the FRBD (free buffer descriptor) with the @frbd_index and the 452 * DMA address of the free buffer. 453 */ 454 static void btintel_pcie_prepare_rx(struct rxq *rxq, u16 frbd_index) 455 { 456 struct data_buf *buf; 457 struct frbd *frbd; 458 459 /* Get the buffer of the FRBD for DMA */ 460 buf = &rxq->bufs[frbd_index]; 461 462 frbd = &rxq->frbds[frbd_index]; 463 memset(frbd, 0, sizeof(*frbd)); 464 465 /* Update FRBD */ 466 frbd->tag = frbd_index; 467 frbd->addr = buf->data_p_addr; 468 } 469 470 static int btintel_pcie_submit_rx(struct btintel_pcie_data *data) 471 { 472 u16 frbd_index; 473 struct rxq *rxq = &data->rxq; 474 475 frbd_index = data->ia.tr_hia[BTINTEL_PCIE_RXQ_NUM]; 476 477 if (frbd_index > rxq->count) 478 return -ERANGE; 479 480 /* Prepare for RX submit. It updates the FRBD with the address of DMA 481 * buffer 482 */ 483 btintel_pcie_prepare_rx(rxq, frbd_index); 484 485 frbd_index = (frbd_index + 1) % rxq->count; 486 data->ia.tr_hia[BTINTEL_PCIE_RXQ_NUM] = frbd_index; 487 ipc_print_ia_ring(data->hdev, &data->ia, BTINTEL_PCIE_RXQ_NUM); 488 489 /* Set the doorbell to notify the device */ 490 btintel_pcie_set_rx_db(data, frbd_index); 491 492 return 0; 493 } 494 495 static int btintel_pcie_start_rx(struct btintel_pcie_data *data) 496 { 497 int i, ret; 498 struct rxq *rxq = &data->rxq; 499 500 /* Post (BTINTEL_PCIE_RX_DESCS_COUNT - 3) buffers to overcome the 501 * hardware issues leading to race condition at the firmware. 502 */ 503 504 for (i = 0; i < rxq->count - 3; i++) { 505 ret = btintel_pcie_submit_rx(data); 506 if (ret) 507 return ret; 508 } 509 510 return 0; 511 } 512 513 static void btintel_pcie_reset_ia(struct btintel_pcie_data *data) 514 { 515 memset(data->ia.tr_hia, 0, sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES); 516 memset(data->ia.tr_tia, 0, sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES); 517 memset(data->ia.cr_hia, 0, sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES); 518 memset(data->ia.cr_tia, 0, sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES); 519 } 520 521 static int btintel_pcie_reset_bt(struct btintel_pcie_data *data) 522 { 523 u32 reg; 524 int retry = 3; 525 526 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 527 528 reg &= ~(BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA | 529 BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT | 530 BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT); 531 reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON; 532 533 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); 534 535 do { 536 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 537 if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS) 538 break; 539 usleep_range(10000, 12000); 540 541 } while (--retry > 0); 542 usleep_range(10000, 12000); 543 544 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 545 546 reg &= ~(BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA | 547 BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT | 548 BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT); 549 reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET; 550 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); 551 usleep_range(10000, 12000); 552 553 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 554 bt_dev_dbg(data->hdev, "csr register after reset: 0x%8.8x", reg); 555 556 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_BOOT_STAGE_REG); 557 558 /* If shared hardware reset is success then boot stage register shall be 559 * set to 0 560 */ 561 return reg == 0 ? 0 : -ENODEV; 562 } 563 564 static void btintel_pcie_mac_init(struct btintel_pcie_data *data) 565 { 566 u32 reg; 567 568 /* Set MAC_INIT bit to start primary bootloader */ 569 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 570 reg &= ~(BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT | 571 BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON | 572 BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET); 573 reg |= (BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA | 574 BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT); 575 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); 576 } 577 578 static int btintel_pcie_get_mac_access(struct btintel_pcie_data *data) 579 { 580 u32 reg; 581 int retry = 15; 582 583 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 584 585 reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS; 586 reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ; 587 if ((reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS) == 0) 588 reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ; 589 590 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); 591 592 do { 593 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 594 if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS) 595 return 0; 596 /* Need delay here for Target Access harwdware to settle down*/ 597 usleep_range(1000, 1200); 598 599 } while (--retry > 0); 600 601 return -ETIME; 602 } 603 604 static void btintel_pcie_release_mac_access(struct btintel_pcie_data *data) 605 { 606 u32 reg; 607 608 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 609 610 if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ) 611 reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ; 612 613 if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS) 614 reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS; 615 616 if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ) 617 reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ; 618 619 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); 620 } 621 622 static void *btintel_pcie_copy_tlv(void *dest, enum btintel_pcie_tlv_type type, 623 void *data, size_t size) 624 { 625 struct intel_tlv *tlv; 626 627 tlv = dest; 628 tlv->type = type; 629 tlv->len = size; 630 memcpy(tlv->val, data, tlv->len); 631 return dest + sizeof(*tlv) + size; 632 } 633 634 static int btintel_pcie_read_dram_buffers(struct btintel_pcie_data *data) 635 { 636 u32 offset, prev_size, wr_ptr_status, dump_size, data_len; 637 struct btintel_pcie_dbgc *dbgc = &data->dbgc; 638 struct hci_dev *hdev = data->hdev; 639 u8 *pdata, *p, buf_idx; 640 struct intel_tlv *tlv; 641 struct timespec64 now; 642 struct tm tm_now; 643 char fw_build[128]; 644 char ts[128]; 645 char vendor[64]; 646 char driver[64]; 647 648 if (!IS_ENABLED(CONFIG_DEV_COREDUMP)) 649 return -EOPNOTSUPP; 650 651 652 wr_ptr_status = btintel_pcie_rd_dev_mem(data, BTINTEL_PCIE_DBGC_CUR_DBGBUFF_STATUS); 653 offset = wr_ptr_status & BTINTEL_PCIE_DBG_OFFSET_BIT_MASK; 654 655 buf_idx = BTINTEL_PCIE_DBGC_DBG_BUF_IDX(wr_ptr_status); 656 if (buf_idx > dbgc->count) { 657 bt_dev_warn(hdev, "Buffer index is invalid"); 658 return -EINVAL; 659 } 660 661 prev_size = buf_idx * BTINTEL_PCIE_DBGC_BUFFER_SIZE; 662 if (prev_size + offset >= prev_size) 663 data->dmp_hdr.write_ptr = prev_size + offset; 664 else 665 return -EINVAL; 666 667 strscpy(vendor, "Vendor: Intel\n"); 668 snprintf(driver, sizeof(driver), "Driver: %s\n", 669 data->dmp_hdr.driver_name); 670 671 ktime_get_real_ts64(&now); 672 time64_to_tm(now.tv_sec, 0, &tm_now); 673 snprintf(ts, sizeof(ts), "Dump Time: %02d-%02d-%04ld %02d:%02d:%02d", 674 tm_now.tm_mday, tm_now.tm_mon + 1, tm_now.tm_year + 1900, 675 tm_now.tm_hour, tm_now.tm_min, tm_now.tm_sec); 676 677 snprintf(fw_build, sizeof(fw_build), 678 "Firmware Timestamp: Year %u WW %02u buildtype %u build %u", 679 2000 + (data->dmp_hdr.fw_timestamp >> 8), 680 data->dmp_hdr.fw_timestamp & 0xff, data->dmp_hdr.fw_build_type, 681 data->dmp_hdr.fw_build_num); 682 683 data_len = sizeof(*tlv) + sizeof(data->dmp_hdr.cnvi_bt) + 684 sizeof(*tlv) + sizeof(data->dmp_hdr.write_ptr) + 685 sizeof(*tlv) + sizeof(data->dmp_hdr.wrap_ctr) + 686 sizeof(*tlv) + sizeof(data->dmp_hdr.trigger_reason) + 687 sizeof(*tlv) + sizeof(data->dmp_hdr.fw_git_sha1) + 688 sizeof(*tlv) + sizeof(data->dmp_hdr.cnvr_top) + 689 sizeof(*tlv) + sizeof(data->dmp_hdr.cnvi_top) + 690 sizeof(*tlv) + strlen(ts) + 691 sizeof(*tlv) + strlen(fw_build) + 692 sizeof(*tlv) + strlen(vendor) + 693 sizeof(*tlv) + strlen(driver); 694 695 /* 696 * sizeof(u32) - signature 697 * sizeof(data_len) - to store tlv data size 698 * data_len - TLV data 699 */ 700 dump_size = sizeof(u32) + sizeof(data_len) + data_len; 701 702 703 /* Add debug buffers data length to dump size */ 704 dump_size += BTINTEL_PCIE_DBGC_BUFFER_SIZE * dbgc->count; 705 706 pdata = vmalloc(dump_size); 707 if (!pdata) 708 return -ENOMEM; 709 p = pdata; 710 711 *(u32 *)p = BTINTEL_PCIE_MAGIC_NUM; 712 p += sizeof(u32); 713 714 *(u32 *)p = data_len; 715 p += sizeof(u32); 716 717 718 p = btintel_pcie_copy_tlv(p, BTINTEL_VENDOR, vendor, strlen(vendor)); 719 p = btintel_pcie_copy_tlv(p, BTINTEL_DRIVER, driver, strlen(driver)); 720 p = btintel_pcie_copy_tlv(p, BTINTEL_DUMP_TIME, ts, strlen(ts)); 721 p = btintel_pcie_copy_tlv(p, BTINTEL_FW_BUILD, fw_build, 722 strlen(fw_build)); 723 p = btintel_pcie_copy_tlv(p, BTINTEL_CNVI_BT, &data->dmp_hdr.cnvi_bt, 724 sizeof(data->dmp_hdr.cnvi_bt)); 725 p = btintel_pcie_copy_tlv(p, BTINTEL_WRITE_PTR, &data->dmp_hdr.write_ptr, 726 sizeof(data->dmp_hdr.write_ptr)); 727 p = btintel_pcie_copy_tlv(p, BTINTEL_WRAP_CTR, &data->dmp_hdr.wrap_ctr, 728 sizeof(data->dmp_hdr.wrap_ctr)); 729 730 data->dmp_hdr.wrap_ctr = btintel_pcie_rd_dev_mem(data, 731 BTINTEL_PCIE_DBGC_DBGBUFF_WRAP_ARND); 732 733 p = btintel_pcie_copy_tlv(p, BTINTEL_TRIGGER_REASON, &data->dmp_hdr.trigger_reason, 734 sizeof(data->dmp_hdr.trigger_reason)); 735 p = btintel_pcie_copy_tlv(p, BTINTEL_FW_SHA, &data->dmp_hdr.fw_git_sha1, 736 sizeof(data->dmp_hdr.fw_git_sha1)); 737 p = btintel_pcie_copy_tlv(p, BTINTEL_CNVR_TOP, &data->dmp_hdr.cnvr_top, 738 sizeof(data->dmp_hdr.cnvr_top)); 739 p = btintel_pcie_copy_tlv(p, BTINTEL_CNVI_TOP, &data->dmp_hdr.cnvi_top, 740 sizeof(data->dmp_hdr.cnvi_top)); 741 742 memcpy(p, dbgc->bufs[0].data, dbgc->count * BTINTEL_PCIE_DBGC_BUFFER_SIZE); 743 dev_coredumpv(&hdev->dev, pdata, dump_size, GFP_KERNEL); 744 return 0; 745 } 746 747 static void btintel_pcie_dump_traces(struct hci_dev *hdev) 748 { 749 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 750 int ret = 0; 751 752 ret = btintel_pcie_get_mac_access(data); 753 if (ret) { 754 bt_dev_err(hdev, "Failed to get mac access: (%d)", ret); 755 return; 756 } 757 758 ret = btintel_pcie_read_dram_buffers(data); 759 760 btintel_pcie_release_mac_access(data); 761 762 if (ret) 763 bt_dev_err(hdev, "Failed to dump traces: (%d)", ret); 764 } 765 766 /* This function enables BT function by setting BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT bit in 767 * BTINTEL_PCIE_CSR_FUNC_CTRL_REG register and wait for MSI-X with 768 * BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0. 769 * Then the host reads firmware version from BTINTEL_CSR_F2D_MBX and the boot stage 770 * from BTINTEL_PCIE_CSR_BOOT_STAGE_REG. 771 */ 772 static int btintel_pcie_enable_bt(struct btintel_pcie_data *data) 773 { 774 int err; 775 u32 reg; 776 777 data->gp0_received = false; 778 779 /* Update the DMA address of CI struct to CSR */ 780 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG, 781 data->ci_p_addr & 0xffffffff); 782 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG, 783 (u64)data->ci_p_addr >> 32); 784 785 /* Reset the cached value of boot stage. it is updated by the MSI-X 786 * gp0 interrupt handler. 787 */ 788 data->boot_stage_cache = 0x0; 789 790 /* Set MAC_INIT bit to start primary bootloader */ 791 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 792 reg &= ~(BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT | 793 BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON | 794 BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET); 795 reg |= (BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA | 796 BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT); 797 798 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg); 799 800 /* MAC is ready. Enable BT FUNC */ 801 btintel_pcie_set_reg_bits(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, 802 BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT); 803 804 btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG); 805 806 /* wait for interrupt from the device after booting up to primary 807 * bootloader. 808 */ 809 data->alive_intr_ctxt = BTINTEL_PCIE_ROM; 810 err = wait_event_timeout(data->gp0_wait_q, data->gp0_received, 811 msecs_to_jiffies(BTINTEL_DEFAULT_INTR_TIMEOUT_MS)); 812 if (!err) 813 return -ETIME; 814 815 /* Check cached boot stage is BTINTEL_PCIE_CSR_BOOT_STAGE_ROM(BIT(0)) */ 816 if (~data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_ROM) 817 return -ENODEV; 818 819 return 0; 820 } 821 822 static inline bool btintel_pcie_in_op(struct btintel_pcie_data *data) 823 { 824 return data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW; 825 } 826 827 static inline bool btintel_pcie_in_iml(struct btintel_pcie_data *data) 828 { 829 return data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_IML && 830 !(data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW); 831 } 832 833 static inline bool btintel_pcie_in_d3(struct btintel_pcie_data *data) 834 { 835 return data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY; 836 } 837 838 static inline bool btintel_pcie_in_d0(struct btintel_pcie_data *data) 839 { 840 return !(data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_D3_STATE_READY); 841 } 842 843 static inline bool btintel_pcie_in_device_halt(struct btintel_pcie_data *data) 844 { 845 return data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED; 846 } 847 848 static void btintel_pcie_wr_sleep_cntrl(struct btintel_pcie_data *data, 849 u32 dxstate) 850 { 851 bt_dev_dbg(data->hdev, "writing sleep_ctl_reg: 0x%8.8x", dxstate); 852 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_IPC_SLEEP_CTL_REG, dxstate); 853 } 854 855 static int btintel_pcie_read_device_mem(struct btintel_pcie_data *data, 856 void *buf, u32 dev_addr, int len) 857 { 858 int err; 859 u32 *val = buf; 860 861 /* Get device mac access */ 862 err = btintel_pcie_get_mac_access(data); 863 if (err) { 864 bt_dev_err(data->hdev, "Failed to get mac access %d", err); 865 return err; 866 } 867 868 for (; len > 0; len -= 4, dev_addr += 4, val++) 869 *val = btintel_pcie_rd_dev_mem(data, dev_addr); 870 871 btintel_pcie_release_mac_access(data); 872 873 return 0; 874 } 875 876 static inline bool btintel_pcie_in_lockdown(struct btintel_pcie_data *data) 877 { 878 return (data->boot_stage_cache & 879 BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN) || 880 (data->boot_stage_cache & 881 BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN); 882 } 883 884 static inline bool btintel_pcie_in_error(struct btintel_pcie_data *data) 885 { 886 if (data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING) 887 bt_dev_warn(data->hdev, "Controller device warning (boot_stage: 0x%8.8x)", 888 data->boot_stage_cache); 889 890 return data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER; 891 } 892 893 static void btintel_pcie_msix_gp1_handler(struct btintel_pcie_data *data) 894 { 895 bt_dev_err(data->hdev, "Received gp1 mailbox interrupt"); 896 btintel_pcie_dump_debug_registers(data->hdev); 897 } 898 899 /* This function handles the MSI-X interrupt for gp0 cause (bit 0 in 900 * BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES) which is sent for boot stage and image response. 901 */ 902 static void btintel_pcie_msix_gp0_handler(struct btintel_pcie_data *data) 903 { 904 bool submit_rx, signal_waitq; 905 u32 reg, old_ctxt; 906 907 /* This interrupt is for three different causes and it is not easy to 908 * know what causes the interrupt. So, it compares each register value 909 * with cached value and update it before it wake up the queue. 910 */ 911 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_BOOT_STAGE_REG); 912 if (reg != data->boot_stage_cache) 913 data->boot_stage_cache = reg; 914 915 bt_dev_dbg(data->hdev, "Alive context: %s old_boot_stage: 0x%8.8x new_boot_stage: 0x%8.8x", 916 btintel_pcie_alivectxt_state2str(data->alive_intr_ctxt), 917 data->boot_stage_cache, reg); 918 reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_IMG_RESPONSE_REG); 919 if (reg != data->img_resp_cache) 920 data->img_resp_cache = reg; 921 922 if (btintel_pcie_in_error(data)) { 923 bt_dev_err(data->hdev, "Controller in error state (boot_stage: 0x%8.8x)", 924 data->boot_stage_cache); 925 btintel_pcie_dump_debug_registers(data->hdev); 926 return; 927 } 928 929 if (btintel_pcie_in_lockdown(data)) { 930 bt_dev_err(data->hdev, "Controller in lockdown state"); 931 btintel_pcie_dump_debug_registers(data->hdev); 932 return; 933 } 934 935 data->gp0_received = true; 936 937 old_ctxt = data->alive_intr_ctxt; 938 submit_rx = false; 939 signal_waitq = false; 940 941 switch (data->alive_intr_ctxt) { 942 case BTINTEL_PCIE_ROM: 943 data->alive_intr_ctxt = BTINTEL_PCIE_FW_DL; 944 signal_waitq = true; 945 break; 946 case BTINTEL_PCIE_FW_DL: 947 /* Error case is already handled. Ideally control shall not 948 * reach here 949 */ 950 break; 951 case BTINTEL_PCIE_INTEL_HCI_RESET1: 952 if (btintel_pcie_in_op(data)) { 953 submit_rx = true; 954 signal_waitq = true; 955 break; 956 } 957 958 if (btintel_pcie_in_iml(data)) { 959 submit_rx = true; 960 signal_waitq = true; 961 data->alive_intr_ctxt = BTINTEL_PCIE_FW_DL; 962 break; 963 } 964 break; 965 case BTINTEL_PCIE_INTEL_HCI_RESET2: 966 if (btintel_test_and_clear_flag(data->hdev, INTEL_WAIT_FOR_D0)) { 967 btintel_wake_up_flag(data->hdev, INTEL_WAIT_FOR_D0); 968 data->alive_intr_ctxt = BTINTEL_PCIE_D0; 969 } 970 break; 971 case BTINTEL_PCIE_D0: 972 if (btintel_pcie_in_d3(data)) { 973 data->alive_intr_ctxt = BTINTEL_PCIE_D3; 974 signal_waitq = true; 975 break; 976 } 977 break; 978 case BTINTEL_PCIE_D3: 979 if (btintel_pcie_in_d0(data)) { 980 data->alive_intr_ctxt = BTINTEL_PCIE_D0; 981 submit_rx = true; 982 signal_waitq = true; 983 break; 984 } 985 break; 986 case BTINTEL_PCIE_HCI_RESET: 987 data->alive_intr_ctxt = BTINTEL_PCIE_D0; 988 submit_rx = true; 989 signal_waitq = true; 990 break; 991 default: 992 bt_dev_err(data->hdev, "Unknown state: 0x%2.2x", 993 data->alive_intr_ctxt); 994 break; 995 } 996 997 if (submit_rx) { 998 btintel_pcie_reset_ia(data); 999 btintel_pcie_start_rx(data); 1000 } 1001 1002 if (signal_waitq) { 1003 bt_dev_dbg(data->hdev, "wake up gp0 wait_q"); 1004 wake_up(&data->gp0_wait_q); 1005 } 1006 1007 if (old_ctxt != data->alive_intr_ctxt) 1008 bt_dev_dbg(data->hdev, "alive context changed: %s -> %s", 1009 btintel_pcie_alivectxt_state2str(old_ctxt), 1010 btintel_pcie_alivectxt_state2str(data->alive_intr_ctxt)); 1011 } 1012 1013 /* This function handles the MSX-X interrupt for rx queue 0 which is for TX 1014 */ 1015 static void btintel_pcie_msix_tx_handle(struct btintel_pcie_data *data) 1016 { 1017 u16 cr_tia, cr_hia; 1018 struct txq *txq; 1019 struct urbd0 *urbd0; 1020 1021 cr_tia = data->ia.cr_tia[BTINTEL_PCIE_TXQ_NUM]; 1022 cr_hia = data->ia.cr_hia[BTINTEL_PCIE_TXQ_NUM]; 1023 1024 if (cr_tia == cr_hia) 1025 return; 1026 1027 txq = &data->txq; 1028 1029 while (cr_tia != cr_hia) { 1030 data->tx_wait_done = true; 1031 wake_up(&data->tx_wait_q); 1032 1033 urbd0 = &txq->urbd0s[cr_tia]; 1034 1035 if (urbd0->tfd_index > txq->count) 1036 return; 1037 1038 cr_tia = (cr_tia + 1) % txq->count; 1039 data->ia.cr_tia[BTINTEL_PCIE_TXQ_NUM] = cr_tia; 1040 ipc_print_ia_ring(data->hdev, &data->ia, BTINTEL_PCIE_TXQ_NUM); 1041 } 1042 } 1043 1044 static int btintel_pcie_recv_event(struct hci_dev *hdev, struct sk_buff *skb) 1045 { 1046 struct hci_event_hdr *hdr = (void *)skb->data; 1047 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 1048 1049 if (skb->len > HCI_EVENT_HDR_SIZE && hdr->evt == 0xff && 1050 hdr->plen > 0) { 1051 const void *ptr = skb->data + HCI_EVENT_HDR_SIZE + 1; 1052 unsigned int len = skb->len - HCI_EVENT_HDR_SIZE - 1; 1053 1054 if (btintel_test_flag(hdev, INTEL_BOOTLOADER)) { 1055 switch (skb->data[2]) { 1056 case 0x02: 1057 /* When switching to the operational firmware 1058 * the device sends a vendor specific event 1059 * indicating that the bootup completed. 1060 */ 1061 btintel_bootup(hdev, ptr, len); 1062 1063 /* If bootup event is from operational image, 1064 * driver needs to write sleep control register to 1065 * move into D0 state 1066 */ 1067 if (btintel_pcie_in_op(data)) { 1068 btintel_pcie_wr_sleep_cntrl(data, BTINTEL_PCIE_STATE_D0); 1069 data->alive_intr_ctxt = BTINTEL_PCIE_INTEL_HCI_RESET2; 1070 kfree_skb(skb); 1071 return 0; 1072 } 1073 1074 if (btintel_pcie_in_iml(data)) { 1075 /* In case of IML, there is no concept 1076 * of D0 transition. Just mimic as if 1077 * IML moved to D0 by clearing INTEL_WAIT_FOR_D0 1078 * bit and waking up the task waiting on 1079 * INTEL_WAIT_FOR_D0. This is required 1080 * as intel_boot() is common function for 1081 * both IML and OP image loading. 1082 */ 1083 if (btintel_test_and_clear_flag(data->hdev, 1084 INTEL_WAIT_FOR_D0)) 1085 btintel_wake_up_flag(data->hdev, 1086 INTEL_WAIT_FOR_D0); 1087 } 1088 kfree_skb(skb); 1089 return 0; 1090 case 0x06: 1091 /* When the firmware loading completes the 1092 * device sends out a vendor specific event 1093 * indicating the result of the firmware 1094 * loading. 1095 */ 1096 btintel_secure_send_result(hdev, ptr, len); 1097 kfree_skb(skb); 1098 return 0; 1099 } 1100 } 1101 1102 /* This is a debug event that comes from IML and OP image when it 1103 * starts execution. There is no need pass this event to stack. 1104 */ 1105 if (skb->data[2] == 0x97) { 1106 hci_recv_diag(hdev, skb); 1107 return 0; 1108 } 1109 } 1110 1111 return hci_recv_frame(hdev, skb); 1112 } 1113 /* Process the received rx data 1114 * It check the frame header to identify the data type and create skb 1115 * and calling HCI API 1116 */ 1117 static int btintel_pcie_recv_frame(struct btintel_pcie_data *data, 1118 struct sk_buff *skb) 1119 { 1120 int ret; 1121 u8 pkt_type; 1122 u16 plen; 1123 u32 pcie_pkt_type; 1124 void *pdata; 1125 struct hci_dev *hdev = data->hdev; 1126 1127 spin_lock(&data->hci_rx_lock); 1128 1129 /* The first 4 bytes indicates the Intel PCIe specific packet type */ 1130 pdata = skb_pull_data(skb, BTINTEL_PCIE_HCI_TYPE_LEN); 1131 if (!pdata) { 1132 bt_dev_err(hdev, "Corrupted packet received"); 1133 ret = -EILSEQ; 1134 goto exit_error; 1135 } 1136 1137 pcie_pkt_type = get_unaligned_le32(pdata); 1138 1139 switch (pcie_pkt_type) { 1140 case BTINTEL_PCIE_HCI_ACL_PKT: 1141 if (skb->len >= HCI_ACL_HDR_SIZE) { 1142 plen = HCI_ACL_HDR_SIZE + __le16_to_cpu(hci_acl_hdr(skb)->dlen); 1143 pkt_type = HCI_ACLDATA_PKT; 1144 } else { 1145 bt_dev_err(hdev, "ACL packet is too short"); 1146 ret = -EILSEQ; 1147 goto exit_error; 1148 } 1149 break; 1150 1151 case BTINTEL_PCIE_HCI_SCO_PKT: 1152 if (skb->len >= HCI_SCO_HDR_SIZE) { 1153 plen = HCI_SCO_HDR_SIZE + hci_sco_hdr(skb)->dlen; 1154 pkt_type = HCI_SCODATA_PKT; 1155 } else { 1156 bt_dev_err(hdev, "SCO packet is too short"); 1157 ret = -EILSEQ; 1158 goto exit_error; 1159 } 1160 break; 1161 1162 case BTINTEL_PCIE_HCI_EVT_PKT: 1163 if (skb->len >= HCI_EVENT_HDR_SIZE) { 1164 plen = HCI_EVENT_HDR_SIZE + hci_event_hdr(skb)->plen; 1165 pkt_type = HCI_EVENT_PKT; 1166 } else { 1167 bt_dev_err(hdev, "Event packet is too short"); 1168 ret = -EILSEQ; 1169 goto exit_error; 1170 } 1171 break; 1172 1173 case BTINTEL_PCIE_HCI_ISO_PKT: 1174 if (skb->len >= HCI_ISO_HDR_SIZE) { 1175 plen = HCI_ISO_HDR_SIZE + __le16_to_cpu(hci_iso_hdr(skb)->dlen); 1176 pkt_type = HCI_ISODATA_PKT; 1177 } else { 1178 bt_dev_err(hdev, "ISO packet is too short"); 1179 ret = -EILSEQ; 1180 goto exit_error; 1181 } 1182 break; 1183 1184 default: 1185 bt_dev_err(hdev, "Invalid packet type received: 0x%4.4x", 1186 pcie_pkt_type); 1187 ret = -EINVAL; 1188 goto exit_error; 1189 } 1190 1191 if (skb->len < plen) { 1192 bt_dev_err(hdev, "Received corrupted packet. type: 0x%2.2x", 1193 pkt_type); 1194 ret = -EILSEQ; 1195 goto exit_error; 1196 } 1197 1198 bt_dev_dbg(hdev, "pkt_type: 0x%2.2x len: %u", pkt_type, plen); 1199 1200 hci_skb_pkt_type(skb) = pkt_type; 1201 hdev->stat.byte_rx += plen; 1202 skb_trim(skb, plen); 1203 1204 if (pcie_pkt_type == BTINTEL_PCIE_HCI_EVT_PKT) 1205 ret = btintel_pcie_recv_event(hdev, skb); 1206 else 1207 ret = hci_recv_frame(hdev, skb); 1208 skb = NULL; /* skb is freed in the callee */ 1209 1210 exit_error: 1211 kfree_skb(skb); 1212 1213 if (ret) 1214 hdev->stat.err_rx++; 1215 1216 spin_unlock(&data->hci_rx_lock); 1217 1218 return ret; 1219 } 1220 1221 static void btintel_pcie_read_hwexp(struct btintel_pcie_data *data) 1222 { 1223 int len, err, offset, pending; 1224 struct sk_buff *skb; 1225 u8 *buf, prefix[64]; 1226 u32 addr, val; 1227 u16 pkt_len; 1228 1229 struct tlv { 1230 u8 type; 1231 __le16 len; 1232 u8 val[]; 1233 } __packed; 1234 1235 struct tlv *tlv; 1236 1237 switch (data->dmp_hdr.cnvi_top & 0xfff) { 1238 case BTINTEL_CNVI_BLAZARI: 1239 case BTINTEL_CNVI_BLAZARIW: 1240 /* only from step B0 onwards */ 1241 if (INTEL_CNVX_TOP_STEP(data->dmp_hdr.cnvi_top) != 0x01) 1242 return; 1243 len = BTINTEL_PCIE_BLZR_HWEXP_SIZE; /* exception data length */ 1244 addr = BTINTEL_PCIE_BLZR_HWEXP_DMP_ADDR; 1245 break; 1246 case BTINTEL_CNVI_SCP: 1247 len = BTINTEL_PCIE_SCP_HWEXP_SIZE; 1248 addr = BTINTEL_PCIE_SCP_HWEXP_DMP_ADDR; 1249 break; 1250 case BTINTEL_CNVI_SCP2: 1251 case BTINTEL_CNVI_SCP2F: 1252 len = BTINTEL_PCIE_SCP2_HWEXP_SIZE; 1253 addr = BTINTEL_PCIE_SCP2_HWEXP_DMP_ADDR; 1254 break; 1255 default: 1256 bt_dev_err(data->hdev, "Unsupported cnvi 0x%8.8x", data->dmp_hdr.cnvi_top); 1257 return; 1258 } 1259 1260 buf = kzalloc(len, GFP_KERNEL); 1261 if (!buf) 1262 goto exit_on_error; 1263 1264 btintel_pcie_mac_init(data); 1265 1266 err = btintel_pcie_read_device_mem(data, buf, addr, len); 1267 if (err) 1268 goto exit_on_error; 1269 1270 val = get_unaligned_le32(buf); 1271 if (val != BTINTEL_PCIE_MAGIC_NUM) { 1272 bt_dev_err(data->hdev, "Invalid exception dump signature: 0x%8.8x", 1273 val); 1274 goto exit_on_error; 1275 } 1276 1277 snprintf(prefix, sizeof(prefix), "Bluetooth: %s: ", bt_dev_name(data->hdev)); 1278 1279 offset = 4; 1280 do { 1281 pending = len - offset; 1282 if (pending < sizeof(*tlv)) 1283 break; 1284 tlv = (struct tlv *)(buf + offset); 1285 1286 /* If type == 0, then there are no more TLVs to be parsed */ 1287 if (!tlv->type) { 1288 bt_dev_dbg(data->hdev, "Invalid TLV type 0"); 1289 break; 1290 } 1291 pkt_len = le16_to_cpu(tlv->len); 1292 offset += sizeof(*tlv); 1293 pending = len - offset; 1294 if (pkt_len > pending) 1295 break; 1296 1297 offset += pkt_len; 1298 1299 /* Only TLVs of type == 1 are HCI events, no need to process other 1300 * TLVs 1301 */ 1302 if (tlv->type != 1) 1303 continue; 1304 1305 bt_dev_dbg(data->hdev, "TLV packet length: %u", pkt_len); 1306 if (pkt_len > HCI_MAX_EVENT_SIZE) 1307 break; 1308 skb = bt_skb_alloc(pkt_len, GFP_KERNEL); 1309 if (!skb) 1310 goto exit_on_error; 1311 hci_skb_pkt_type(skb) = HCI_EVENT_PKT; 1312 skb_put_data(skb, tlv->val, pkt_len); 1313 1314 /* copy Intel specific pcie packet type */ 1315 val = BTINTEL_PCIE_HCI_EVT_PKT; 1316 memcpy(skb_push(skb, BTINTEL_PCIE_HCI_TYPE_LEN), &val, 1317 BTINTEL_PCIE_HCI_TYPE_LEN); 1318 1319 print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_OFFSET, 16, 1, 1320 tlv->val, pkt_len, false); 1321 1322 btintel_pcie_recv_frame(data, skb); 1323 } while (offset < len); 1324 1325 exit_on_error: 1326 kfree(buf); 1327 } 1328 1329 static void btintel_pcie_msix_hw_exp_handler(struct btintel_pcie_data *data) 1330 { 1331 bt_dev_err(data->hdev, "Received hw exception interrupt"); 1332 1333 if (test_and_set_bit(BTINTEL_PCIE_CORE_HALTED, &data->flags)) 1334 return; 1335 1336 if (test_and_set_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags)) 1337 return; 1338 1339 /* Trigger device core dump when there is HW exception */ 1340 if (!test_and_set_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags)) 1341 data->dmp_hdr.trigger_reason = BTINTEL_PCIE_TRIGGER_REASON_FW_ASSERT; 1342 1343 queue_work(data->workqueue, &data->rx_work); 1344 } 1345 1346 static void btintel_pcie_rx_work(struct work_struct *work) 1347 { 1348 struct btintel_pcie_data *data = container_of(work, 1349 struct btintel_pcie_data, rx_work); 1350 struct sk_buff *skb; 1351 1352 if (test_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags)) { 1353 btintel_pcie_dump_traces(data->hdev); 1354 clear_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags); 1355 } 1356 1357 if (test_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags)) { 1358 /* Unlike usb products, controller will not send hardware 1359 * exception event on exception. Instead controller writes the 1360 * hardware event to device memory along with optional debug 1361 * events, raises MSIX and halts. Driver shall read the 1362 * exception event from device memory and passes it stack for 1363 * further processing. 1364 */ 1365 btintel_pcie_read_hwexp(data); 1366 clear_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags); 1367 } 1368 1369 /* Process the sk_buf in queue and send to the HCI layer */ 1370 while ((skb = skb_dequeue(&data->rx_skb_q))) { 1371 btintel_pcie_recv_frame(data, skb); 1372 } 1373 } 1374 1375 /* create sk_buff with data and save it to queue and start RX work */ 1376 static int btintel_pcie_submit_rx_work(struct btintel_pcie_data *data, u8 status, 1377 void *buf) 1378 { 1379 int ret, len; 1380 struct rfh_hdr *rfh_hdr; 1381 struct sk_buff *skb; 1382 1383 rfh_hdr = buf; 1384 1385 len = rfh_hdr->packet_len; 1386 if (len <= 0) { 1387 ret = -EINVAL; 1388 goto resubmit; 1389 } 1390 1391 /* Remove RFH header */ 1392 buf += sizeof(*rfh_hdr); 1393 1394 skb = alloc_skb(len, GFP_ATOMIC); 1395 if (!skb) 1396 goto resubmit; 1397 1398 skb_put_data(skb, buf, len); 1399 skb_queue_tail(&data->rx_skb_q, skb); 1400 queue_work(data->workqueue, &data->rx_work); 1401 1402 resubmit: 1403 ret = btintel_pcie_submit_rx(data); 1404 1405 return ret; 1406 } 1407 1408 /* Handles the MSI-X interrupt for rx queue 1 which is for RX */ 1409 static void btintel_pcie_msix_rx_handle(struct btintel_pcie_data *data) 1410 { 1411 u16 cr_hia, cr_tia; 1412 struct rxq *rxq; 1413 struct urbd1 *urbd1; 1414 struct data_buf *buf; 1415 int ret; 1416 struct hci_dev *hdev = data->hdev; 1417 1418 cr_hia = data->ia.cr_hia[BTINTEL_PCIE_RXQ_NUM]; 1419 cr_tia = data->ia.cr_tia[BTINTEL_PCIE_RXQ_NUM]; 1420 1421 bt_dev_dbg(hdev, "RXQ: cr_hia: %u cr_tia: %u", cr_hia, cr_tia); 1422 1423 /* Check CR_TIA and CR_HIA for change */ 1424 if (cr_tia == cr_hia) 1425 return; 1426 1427 rxq = &data->rxq; 1428 1429 /* The firmware sends multiple CD in a single MSI-X and it needs to 1430 * process all received CDs in this interrupt. 1431 */ 1432 while (cr_tia != cr_hia) { 1433 urbd1 = &rxq->urbd1s[cr_tia]; 1434 ipc_print_urbd1(data->hdev, urbd1, cr_tia); 1435 1436 buf = &rxq->bufs[urbd1->frbd_tag]; 1437 if (!buf) { 1438 bt_dev_err(hdev, "RXQ: failed to get the DMA buffer for %d", 1439 urbd1->frbd_tag); 1440 return; 1441 } 1442 1443 ret = btintel_pcie_submit_rx_work(data, urbd1->status, 1444 buf->data); 1445 if (ret) { 1446 bt_dev_err(hdev, "RXQ: failed to submit rx request"); 1447 return; 1448 } 1449 1450 cr_tia = (cr_tia + 1) % rxq->count; 1451 data->ia.cr_tia[BTINTEL_PCIE_RXQ_NUM] = cr_tia; 1452 ipc_print_ia_ring(data->hdev, &data->ia, BTINTEL_PCIE_RXQ_NUM); 1453 } 1454 } 1455 1456 static inline bool btintel_pcie_is_rxq_empty(struct btintel_pcie_data *data) 1457 { 1458 return data->ia.cr_hia[BTINTEL_PCIE_RXQ_NUM] == data->ia.cr_tia[BTINTEL_PCIE_RXQ_NUM]; 1459 } 1460 1461 static inline bool btintel_pcie_is_txackq_empty(struct btintel_pcie_data *data) 1462 { 1463 return data->ia.cr_tia[BTINTEL_PCIE_TXQ_NUM] == data->ia.cr_hia[BTINTEL_PCIE_TXQ_NUM]; 1464 } 1465 1466 static irqreturn_t btintel_pcie_irq_msix_handler(int irq, void *dev_id) 1467 { 1468 struct msix_entry *entry = dev_id; 1469 struct btintel_pcie_data *data = btintel_pcie_get_data(entry); 1470 u32 intr_fh, intr_hw; 1471 1472 spin_lock(&data->irq_lock); 1473 intr_fh = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES); 1474 intr_hw = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES); 1475 1476 /* Clear causes registers to avoid being handling the same cause */ 1477 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_FH_INT_CAUSES, intr_fh); 1478 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES, intr_hw); 1479 spin_unlock(&data->irq_lock); 1480 1481 if (unlikely(!(intr_fh | intr_hw))) { 1482 /* Ignore interrupt, inta == 0 */ 1483 return IRQ_NONE; 1484 } 1485 1486 /* This interrupt is raised when there is an hardware exception */ 1487 if (intr_hw & BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP) 1488 btintel_pcie_msix_hw_exp_handler(data); 1489 1490 if (intr_hw & BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP1) 1491 btintel_pcie_msix_gp1_handler(data); 1492 1493 1494 /* For TX */ 1495 if (intr_fh & BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0) { 1496 btintel_pcie_msix_tx_handle(data); 1497 if (!btintel_pcie_is_rxq_empty(data)) 1498 btintel_pcie_msix_rx_handle(data); 1499 } 1500 1501 /* For RX */ 1502 if (intr_fh & BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1) { 1503 btintel_pcie_msix_rx_handle(data); 1504 if (!btintel_pcie_is_txackq_empty(data)) 1505 btintel_pcie_msix_tx_handle(data); 1506 } 1507 1508 /* This interrupt is triggered by the firmware after updating 1509 * boot_stage register and image_response register 1510 */ 1511 if (intr_hw & BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0) 1512 btintel_pcie_msix_gp0_handler(data); 1513 1514 /* 1515 * Before sending the interrupt the HW disables it to prevent a nested 1516 * interrupt. This is done by writing 1 to the corresponding bit in 1517 * the mask register. After handling the interrupt, it should be 1518 * re-enabled by clearing this bit. This register is defined as write 1 1519 * clear (W1C) register, meaning that it's cleared by writing 1 1520 * to the bit. 1521 */ 1522 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_AUTOMASK_ST, 1523 BIT(entry->entry)); 1524 1525 return IRQ_HANDLED; 1526 } 1527 1528 /* This function requests the irq for MSI-X and registers the handlers per irq. 1529 * Currently, it requests only 1 irq for all interrupt causes. 1530 */ 1531 static int btintel_pcie_setup_irq(struct btintel_pcie_data *data) 1532 { 1533 int err; 1534 int num_irqs, i; 1535 1536 for (i = 0; i < BTINTEL_PCIE_MSIX_VEC_MAX; i++) 1537 data->msix_entries[i].entry = i; 1538 1539 num_irqs = pci_alloc_irq_vectors(data->pdev, BTINTEL_PCIE_MSIX_VEC_MIN, 1540 BTINTEL_PCIE_MSIX_VEC_MAX, PCI_IRQ_MSIX); 1541 if (num_irqs < 0) 1542 return num_irqs; 1543 1544 data->alloc_vecs = num_irqs; 1545 data->msix_enabled = 1; 1546 data->def_irq = 0; 1547 1548 /* setup irq handler */ 1549 for (i = 0; i < data->alloc_vecs; i++) { 1550 struct msix_entry *msix_entry; 1551 1552 msix_entry = &data->msix_entries[i]; 1553 msix_entry->vector = pci_irq_vector(data->pdev, i); 1554 1555 err = devm_request_threaded_irq(&data->pdev->dev, 1556 msix_entry->vector, 1557 NULL, 1558 btintel_pcie_irq_msix_handler, 1559 IRQF_ONESHOT | IRQF_SHARED, 1560 KBUILD_MODNAME, 1561 msix_entry); 1562 if (err) { 1563 pci_free_irq_vectors(data->pdev); 1564 data->alloc_vecs = 0; 1565 return err; 1566 } 1567 } 1568 return 0; 1569 } 1570 1571 struct btintel_pcie_causes_list { 1572 u32 cause; 1573 u32 mask_reg; 1574 u8 cause_num; 1575 }; 1576 1577 static struct btintel_pcie_causes_list causes_list[] = { 1578 { BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK, 0x00 }, 1579 { BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK, 0x01 }, 1580 { BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, 0x20 }, 1581 { BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, 0x23 }, 1582 }; 1583 1584 /* This function configures the interrupt masks for both HW_INT_CAUSES and 1585 * FH_INT_CAUSES which are meaningful to us. 1586 * 1587 * After resetting BT function via PCIE FLR or FUNC_CTRL reset, the driver 1588 * need to call this function again to configure since the masks 1589 * are reset to 0xFFFFFFFF after reset. 1590 */ 1591 static void btintel_pcie_config_msix(struct btintel_pcie_data *data) 1592 { 1593 int i; 1594 int val = data->def_irq | BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE; 1595 1596 /* Set Non Auto Clear Cause */ 1597 for (i = 0; i < ARRAY_SIZE(causes_list); i++) { 1598 btintel_pcie_wr_reg8(data, 1599 BTINTEL_PCIE_CSR_MSIX_IVAR(causes_list[i].cause_num), 1600 val); 1601 btintel_pcie_clr_reg_bits(data, 1602 causes_list[i].mask_reg, 1603 causes_list[i].cause); 1604 } 1605 1606 /* Save the initial interrupt mask */ 1607 data->fh_init_mask = ~btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK); 1608 data->hw_init_mask = ~btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK); 1609 } 1610 1611 static int btintel_pcie_config_pcie(struct pci_dev *pdev, 1612 struct btintel_pcie_data *data) 1613 { 1614 int err; 1615 1616 err = pcim_enable_device(pdev); 1617 if (err) 1618 return err; 1619 1620 pci_set_master(pdev); 1621 1622 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1623 if (err) { 1624 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1625 if (err) 1626 return err; 1627 } 1628 1629 data->base_addr = pcim_iomap_region(pdev, 0, KBUILD_MODNAME); 1630 if (IS_ERR(data->base_addr)) 1631 return PTR_ERR(data->base_addr); 1632 1633 err = btintel_pcie_setup_irq(data); 1634 if (err) 1635 return err; 1636 1637 /* Configure MSI-X with causes list */ 1638 btintel_pcie_config_msix(data); 1639 1640 return 0; 1641 } 1642 1643 static void btintel_pcie_init_ci(struct btintel_pcie_data *data, 1644 struct ctx_info *ci) 1645 { 1646 ci->version = 0x1; 1647 ci->size = sizeof(*ci); 1648 ci->config = 0x0000; 1649 ci->addr_cr_hia = data->ia.cr_hia_p_addr; 1650 ci->addr_tr_tia = data->ia.tr_tia_p_addr; 1651 ci->addr_cr_tia = data->ia.cr_tia_p_addr; 1652 ci->addr_tr_hia = data->ia.tr_hia_p_addr; 1653 ci->num_cr_ia = BTINTEL_PCIE_NUM_QUEUES; 1654 ci->num_tr_ia = BTINTEL_PCIE_NUM_QUEUES; 1655 ci->addr_urbdq0 = data->txq.urbd0s_p_addr; 1656 ci->addr_tfdq = data->txq.tfds_p_addr; 1657 ci->num_tfdq = data->txq.count; 1658 ci->num_urbdq0 = data->txq.count; 1659 ci->tfdq_db_vec = BTINTEL_PCIE_TXQ_NUM; 1660 ci->urbdq0_db_vec = BTINTEL_PCIE_TXQ_NUM; 1661 ci->rbd_size = BTINTEL_PCIE_RBD_SIZE_4K; 1662 ci->addr_frbdq = data->rxq.frbds_p_addr; 1663 ci->num_frbdq = data->rxq.count; 1664 ci->frbdq_db_vec = BTINTEL_PCIE_RXQ_NUM; 1665 ci->addr_urbdq1 = data->rxq.urbd1s_p_addr; 1666 ci->num_urbdq1 = data->rxq.count; 1667 ci->urbdq_db_vec = BTINTEL_PCIE_RXQ_NUM; 1668 1669 ci->dbg_output_mode = 0x01; 1670 ci->dbgc_addr = data->dbgc.frag_p_addr; 1671 ci->dbgc_size = data->dbgc.frag_size; 1672 ci->dbg_preset = 0x00; 1673 } 1674 1675 static void btintel_pcie_free_txq_bufs(struct btintel_pcie_data *data, 1676 struct txq *txq) 1677 { 1678 /* Free data buffers first */ 1679 dma_free_coherent(&data->pdev->dev, txq->count * BTINTEL_PCIE_BUFFER_SIZE, 1680 txq->buf_v_addr, txq->buf_p_addr); 1681 kfree(txq->bufs); 1682 } 1683 1684 static int btintel_pcie_setup_txq_bufs(struct btintel_pcie_data *data, 1685 struct txq *txq) 1686 { 1687 int i; 1688 struct data_buf *buf; 1689 1690 /* Allocate the same number of buffers as the descriptor */ 1691 txq->bufs = kmalloc_objs(*buf, txq->count); 1692 if (!txq->bufs) 1693 return -ENOMEM; 1694 1695 /* Allocate full chunk of data buffer for DMA first and do indexing and 1696 * initialization next, so it can be freed easily 1697 */ 1698 txq->buf_v_addr = dma_alloc_coherent(&data->pdev->dev, 1699 txq->count * BTINTEL_PCIE_BUFFER_SIZE, 1700 &txq->buf_p_addr, 1701 GFP_KERNEL | __GFP_NOWARN); 1702 if (!txq->buf_v_addr) { 1703 kfree(txq->bufs); 1704 return -ENOMEM; 1705 } 1706 1707 /* Setup the allocated DMA buffer to bufs. Each data_buf should 1708 * have virtual address and physical address 1709 */ 1710 for (i = 0; i < txq->count; i++) { 1711 buf = &txq->bufs[i]; 1712 buf->data_p_addr = txq->buf_p_addr + (i * BTINTEL_PCIE_BUFFER_SIZE); 1713 buf->data = txq->buf_v_addr + (i * BTINTEL_PCIE_BUFFER_SIZE); 1714 } 1715 1716 return 0; 1717 } 1718 1719 static void btintel_pcie_free_rxq_bufs(struct btintel_pcie_data *data, 1720 struct rxq *rxq) 1721 { 1722 /* Free data buffers first */ 1723 dma_free_coherent(&data->pdev->dev, rxq->count * BTINTEL_PCIE_BUFFER_SIZE, 1724 rxq->buf_v_addr, rxq->buf_p_addr); 1725 kfree(rxq->bufs); 1726 } 1727 1728 static int btintel_pcie_setup_rxq_bufs(struct btintel_pcie_data *data, 1729 struct rxq *rxq) 1730 { 1731 int i; 1732 struct data_buf *buf; 1733 1734 /* Allocate the same number of buffers as the descriptor */ 1735 rxq->bufs = kmalloc_objs(*buf, rxq->count); 1736 if (!rxq->bufs) 1737 return -ENOMEM; 1738 1739 /* Allocate full chunk of data buffer for DMA first and do indexing and 1740 * initialization next, so it can be freed easily 1741 */ 1742 rxq->buf_v_addr = dma_alloc_coherent(&data->pdev->dev, 1743 rxq->count * BTINTEL_PCIE_BUFFER_SIZE, 1744 &rxq->buf_p_addr, 1745 GFP_KERNEL | __GFP_NOWARN); 1746 if (!rxq->buf_v_addr) { 1747 kfree(rxq->bufs); 1748 return -ENOMEM; 1749 } 1750 1751 /* Setup the allocated DMA buffer to bufs. Each data_buf should 1752 * have virtual address and physical address 1753 */ 1754 for (i = 0; i < rxq->count; i++) { 1755 buf = &rxq->bufs[i]; 1756 buf->data_p_addr = rxq->buf_p_addr + (i * BTINTEL_PCIE_BUFFER_SIZE); 1757 buf->data = rxq->buf_v_addr + (i * BTINTEL_PCIE_BUFFER_SIZE); 1758 } 1759 1760 return 0; 1761 } 1762 1763 static void btintel_pcie_free(struct btintel_pcie_data *data) 1764 { 1765 btintel_pcie_free_rxq_bufs(data, &data->rxq); 1766 btintel_pcie_free_txq_bufs(data, &data->txq); 1767 1768 dma_pool_free(data->dma_pool, data->dma_v_addr, data->dma_p_addr); 1769 dma_pool_destroy(data->dma_pool); 1770 } 1771 1772 /* Allocate tx and rx queues, any related data structures and buffers. 1773 */ 1774 static int btintel_pcie_alloc(struct btintel_pcie_data *data) 1775 { 1776 int err = 0; 1777 size_t total; 1778 dma_addr_t p_addr; 1779 void *v_addr; 1780 size_t tfd_size, frbd_size, ctx_size, ci_size, urbd0_size, urbd1_size; 1781 1782 /* Allocate the chunk of DMA memory for descriptors, index array, and 1783 * context information, instead of allocating individually. 1784 * The DMA memory for data buffer is allocated while setting up the 1785 * each queue. 1786 * 1787 * Total size is sum of the following and each of the individual sizes 1788 * are aligned to 128 bytes before adding up. 1789 * 1790 * + size of TFD * Number of descriptors in queue 1791 * + size of URBD0 * Number of descriptors in queue 1792 * + size of FRBD * Number of descriptors in queue 1793 * + size of URBD1 * Number of descriptors in queue 1794 * + size of index * Number of queues(2) * type of index array(4) 1795 * + size of context information 1796 */ 1797 tfd_size = ALIGN(sizeof(struct tfd) * BTINTEL_PCIE_TX_DESCS_COUNT, 1798 BTINTEL_PCIE_DMA_ALIGN_128B); 1799 urbd0_size = ALIGN(sizeof(struct urbd0) * BTINTEL_PCIE_TX_DESCS_COUNT, 1800 BTINTEL_PCIE_DMA_ALIGN_128B); 1801 1802 frbd_size = ALIGN(sizeof(struct frbd) * BTINTEL_PCIE_RX_DESCS_COUNT, 1803 BTINTEL_PCIE_DMA_ALIGN_128B); 1804 urbd1_size = ALIGN(sizeof(struct urbd1) * BTINTEL_PCIE_RX_DESCS_COUNT, 1805 BTINTEL_PCIE_DMA_ALIGN_128B); 1806 1807 ci_size = ALIGN(sizeof(u16) * BTINTEL_PCIE_NUM_QUEUES, 1808 BTINTEL_PCIE_DMA_ALIGN_128B); 1809 1810 ctx_size = ALIGN(sizeof(struct ctx_info), BTINTEL_PCIE_DMA_ALIGN_128B); 1811 1812 total = tfd_size + urbd0_size + frbd_size + urbd1_size + ctx_size + ci_size * 4; 1813 1814 data->dma_pool = dma_pool_create(KBUILD_MODNAME, &data->pdev->dev, 1815 total, BTINTEL_PCIE_DMA_ALIGN_128B, 0); 1816 if (!data->dma_pool) { 1817 err = -ENOMEM; 1818 goto exit_error; 1819 } 1820 1821 v_addr = dma_pool_zalloc(data->dma_pool, GFP_KERNEL | __GFP_NOWARN, 1822 &p_addr); 1823 if (!v_addr) { 1824 dma_pool_destroy(data->dma_pool); 1825 err = -ENOMEM; 1826 goto exit_error; 1827 } 1828 1829 data->dma_p_addr = p_addr; 1830 data->dma_v_addr = v_addr; 1831 1832 /* Setup descriptor count */ 1833 data->txq.count = BTINTEL_PCIE_TX_DESCS_COUNT; 1834 data->rxq.count = BTINTEL_PCIE_RX_DESCS_COUNT; 1835 1836 /* Setup tfds */ 1837 data->txq.tfds_p_addr = p_addr; 1838 data->txq.tfds = v_addr; 1839 1840 p_addr += tfd_size; 1841 v_addr += tfd_size; 1842 1843 /* Setup urbd0 */ 1844 data->txq.urbd0s_p_addr = p_addr; 1845 data->txq.urbd0s = v_addr; 1846 1847 p_addr += urbd0_size; 1848 v_addr += urbd0_size; 1849 1850 /* Setup FRBD*/ 1851 data->rxq.frbds_p_addr = p_addr; 1852 data->rxq.frbds = v_addr; 1853 1854 p_addr += frbd_size; 1855 v_addr += frbd_size; 1856 1857 /* Setup urbd1 */ 1858 data->rxq.urbd1s_p_addr = p_addr; 1859 data->rxq.urbd1s = v_addr; 1860 1861 p_addr += urbd1_size; 1862 v_addr += urbd1_size; 1863 1864 /* Setup data buffers for txq */ 1865 err = btintel_pcie_setup_txq_bufs(data, &data->txq); 1866 if (err) 1867 goto exit_error_pool; 1868 1869 /* Setup data buffers for rxq */ 1870 err = btintel_pcie_setup_rxq_bufs(data, &data->rxq); 1871 if (err) 1872 goto exit_error_txq; 1873 1874 /* TR Head Index Array */ 1875 data->ia.tr_hia_p_addr = p_addr; 1876 data->ia.tr_hia = v_addr; 1877 p_addr += ci_size; 1878 v_addr += ci_size; 1879 1880 /* TR Tail Index Array */ 1881 data->ia.tr_tia_p_addr = p_addr; 1882 data->ia.tr_tia = v_addr; 1883 p_addr += ci_size; 1884 v_addr += ci_size; 1885 1886 /* CR Head index Array */ 1887 data->ia.cr_hia_p_addr = p_addr; 1888 data->ia.cr_hia = v_addr; 1889 p_addr += ci_size; 1890 v_addr += ci_size; 1891 1892 /* CR Tail Index Array */ 1893 data->ia.cr_tia_p_addr = p_addr; 1894 data->ia.cr_tia = v_addr; 1895 p_addr += ci_size; 1896 v_addr += ci_size; 1897 1898 /* Setup data buffers for dbgc */ 1899 err = btintel_pcie_setup_dbgc(data); 1900 if (err) 1901 goto exit_error_txq; 1902 1903 /* Setup Context Information */ 1904 data->ci = v_addr; 1905 data->ci_p_addr = p_addr; 1906 1907 /* Initialize the CI */ 1908 btintel_pcie_init_ci(data, data->ci); 1909 1910 return 0; 1911 1912 exit_error_txq: 1913 btintel_pcie_free_txq_bufs(data, &data->txq); 1914 exit_error_pool: 1915 dma_pool_free(data->dma_pool, data->dma_v_addr, data->dma_p_addr); 1916 dma_pool_destroy(data->dma_pool); 1917 exit_error: 1918 return err; 1919 } 1920 1921 static int btintel_pcie_open(struct hci_dev *hdev) 1922 { 1923 bt_dev_dbg(hdev, ""); 1924 1925 return 0; 1926 } 1927 1928 static int btintel_pcie_close(struct hci_dev *hdev) 1929 { 1930 bt_dev_dbg(hdev, ""); 1931 1932 return 0; 1933 } 1934 1935 static int btintel_pcie_inject_cmd_complete(struct hci_dev *hdev, __u16 opcode) 1936 { 1937 struct sk_buff *skb; 1938 struct hci_event_hdr *hdr; 1939 struct hci_ev_cmd_complete *evt; 1940 1941 skb = bt_skb_alloc(sizeof(*hdr) + sizeof(*evt) + 1, GFP_KERNEL); 1942 if (!skb) 1943 return -ENOMEM; 1944 1945 hdr = (struct hci_event_hdr *)skb_put(skb, sizeof(*hdr)); 1946 hdr->evt = HCI_EV_CMD_COMPLETE; 1947 hdr->plen = sizeof(*evt) + 1; 1948 1949 evt = (struct hci_ev_cmd_complete *)skb_put(skb, sizeof(*evt)); 1950 evt->ncmd = 0x01; 1951 evt->opcode = cpu_to_le16(opcode); 1952 1953 *(u8 *)skb_put(skb, 1) = 0x00; 1954 1955 hci_skb_pkt_type(skb) = HCI_EVENT_PKT; 1956 1957 return hci_recv_frame(hdev, skb); 1958 } 1959 1960 static int btintel_pcie_send_frame(struct hci_dev *hdev, 1961 struct sk_buff *skb) 1962 { 1963 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 1964 struct hci_command_hdr *cmd; 1965 __u16 opcode = ~0; 1966 int ret; 1967 u32 type; 1968 1969 if (test_bit(BTINTEL_PCIE_CORE_HALTED, &data->flags)) 1970 return -ENODEV; 1971 1972 /* Due to the fw limitation, the type header of the packet should be 1973 * 4 bytes unlike 1 byte for UART. In UART, the firmware can read 1974 * the first byte to get the packet type and redirect the rest of data 1975 * packet to the right handler. 1976 * 1977 * But for PCIe, THF(Transfer Flow Handler) fetches the 4 bytes of data 1978 * from DMA memory and by the time it reads the first 4 bytes, it has 1979 * already consumed some part of packet. Thus the packet type indicator 1980 * for iBT PCIe is 4 bytes. 1981 * 1982 * Luckily, when HCI core creates the skb, it allocates 8 bytes of 1983 * head room for profile and driver use, and before sending the data 1984 * to the device, append the iBT PCIe packet type in the front. 1985 */ 1986 switch (hci_skb_pkt_type(skb)) { 1987 case HCI_COMMAND_PKT: 1988 type = BTINTEL_PCIE_HCI_CMD_PKT; 1989 cmd = (void *)skb->data; 1990 opcode = le16_to_cpu(cmd->opcode); 1991 if (btintel_test_flag(hdev, INTEL_BOOTLOADER)) { 1992 struct hci_command_hdr *cmd = (void *)skb->data; 1993 __u16 opcode = le16_to_cpu(cmd->opcode); 1994 1995 /* When the BTINTEL_HCI_OP_RESET command is issued to 1996 * boot into the operational firmware, it will actually 1997 * not send a command complete event. To keep the flow 1998 * control working inject that event here. 1999 */ 2000 if (opcode == BTINTEL_HCI_OP_RESET) 2001 btintel_pcie_inject_cmd_complete(hdev, opcode); 2002 } 2003 2004 hdev->stat.cmd_tx++; 2005 break; 2006 case HCI_ACLDATA_PKT: 2007 type = BTINTEL_PCIE_HCI_ACL_PKT; 2008 hdev->stat.acl_tx++; 2009 break; 2010 case HCI_SCODATA_PKT: 2011 type = BTINTEL_PCIE_HCI_SCO_PKT; 2012 hdev->stat.sco_tx++; 2013 break; 2014 case HCI_ISODATA_PKT: 2015 type = BTINTEL_PCIE_HCI_ISO_PKT; 2016 break; 2017 default: 2018 bt_dev_err(hdev, "Unknown HCI packet type"); 2019 return -EILSEQ; 2020 } 2021 2022 ret = btintel_pcie_send_sync(data, skb, type, opcode); 2023 if (ret) { 2024 hdev->stat.err_tx++; 2025 bt_dev_err(hdev, "Failed to send frame (%d)", ret); 2026 goto exit_error; 2027 } 2028 2029 hdev->stat.byte_tx += skb->len; 2030 kfree_skb(skb); 2031 2032 exit_error: 2033 return ret; 2034 } 2035 2036 static void btintel_pcie_release_hdev(struct btintel_pcie_data *data) 2037 { 2038 struct hci_dev *hdev; 2039 2040 hdev = data->hdev; 2041 hci_unregister_dev(hdev); 2042 hci_free_dev(hdev); 2043 data->hdev = NULL; 2044 } 2045 2046 static void btintel_pcie_disable_interrupts(struct btintel_pcie_data *data) 2047 { 2048 spin_lock(&data->irq_lock); 2049 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK, data->fh_init_mask); 2050 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, data->hw_init_mask); 2051 spin_unlock(&data->irq_lock); 2052 } 2053 2054 static void btintel_pcie_enable_interrupts(struct btintel_pcie_data *data) 2055 { 2056 spin_lock(&data->irq_lock); 2057 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK, ~data->fh_init_mask); 2058 btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, ~data->hw_init_mask); 2059 spin_unlock(&data->irq_lock); 2060 } 2061 2062 static void btintel_pcie_synchronize_irqs(struct btintel_pcie_data *data) 2063 { 2064 for (int i = 0; i < data->alloc_vecs; i++) 2065 synchronize_irq(data->msix_entries[i].vector); 2066 } 2067 2068 static int btintel_pcie_setup_internal(struct hci_dev *hdev) 2069 { 2070 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 2071 const u8 param[1] = { 0xFF }; 2072 struct intel_version_tlv ver_tlv; 2073 struct sk_buff *skb; 2074 int err; 2075 2076 BT_DBG("%s", hdev->name); 2077 2078 skb = __hci_cmd_sync(hdev, 0xfc05, 1, param, HCI_CMD_TIMEOUT); 2079 if (IS_ERR(skb)) { 2080 bt_dev_err(hdev, "Reading Intel version command failed (%ld)", 2081 PTR_ERR(skb)); 2082 return PTR_ERR(skb); 2083 } 2084 2085 /* Check the status */ 2086 if (skb->data[0]) { 2087 bt_dev_err(hdev, "Intel Read Version command failed (%02x)", 2088 skb->data[0]); 2089 err = -EIO; 2090 goto exit_error; 2091 } 2092 2093 /* Apply the common HCI quirks for Intel device */ 2094 hci_set_quirk(hdev, HCI_QUIRK_STRICT_DUPLICATE_FILTER); 2095 hci_set_quirk(hdev, HCI_QUIRK_SIMULTANEOUS_DISCOVERY); 2096 hci_set_quirk(hdev, HCI_QUIRK_NON_PERSISTENT_DIAG); 2097 2098 /* Set up the quality report callback for Intel devices */ 2099 hdev->set_quality_report = btintel_set_quality_report; 2100 2101 memset(&ver_tlv, 0, sizeof(ver_tlv)); 2102 /* For TLV type device, parse the tlv data */ 2103 err = btintel_parse_version_tlv(hdev, &ver_tlv, skb); 2104 if (err) { 2105 bt_dev_err(hdev, "Failed to parse TLV version information"); 2106 goto exit_error; 2107 } 2108 2109 switch (INTEL_HW_PLATFORM(ver_tlv.cnvi_bt)) { 2110 case 0x37: 2111 break; 2112 default: 2113 bt_dev_err(hdev, "Unsupported Intel hardware platform (0x%2x)", 2114 INTEL_HW_PLATFORM(ver_tlv.cnvi_bt)); 2115 err = -EINVAL; 2116 goto exit_error; 2117 } 2118 2119 /* Check for supported iBT hardware variants of this firmware 2120 * loading method. 2121 * 2122 * This check has been put in place to ensure correct forward 2123 * compatibility options when newer hardware variants come 2124 * along. 2125 */ 2126 switch (INTEL_HW_VARIANT(ver_tlv.cnvi_bt)) { 2127 case 0x1e: /* BzrI */ 2128 case 0x1f: /* ScP */ 2129 case 0x20: /* ScP2 */ 2130 case 0x21: /* ScP2 F */ 2131 case 0x22: /* BzrIW */ 2132 /* Display version information of TLV type */ 2133 btintel_version_info_tlv(hdev, &ver_tlv); 2134 2135 /* Apply the device specific HCI quirks for TLV based devices 2136 * 2137 * All TLV based devices support WBS 2138 */ 2139 hci_set_quirk(hdev, HCI_QUIRK_WIDEBAND_SPEECH_SUPPORTED); 2140 2141 /* Setup MSFT Extension support */ 2142 btintel_set_msft_opcode(hdev, 2143 INTEL_HW_VARIANT(ver_tlv.cnvi_bt)); 2144 2145 err = btintel_bootloader_setup_tlv(hdev, &ver_tlv); 2146 if (err) 2147 goto exit_error; 2148 break; 2149 default: 2150 bt_dev_err(hdev, "Unsupported Intel hw variant (%u)", 2151 INTEL_HW_VARIANT(ver_tlv.cnvi_bt)); 2152 err = -EINVAL; 2153 goto exit_error; 2154 break; 2155 } 2156 2157 data->dmp_hdr.cnvi_top = ver_tlv.cnvi_top; 2158 data->dmp_hdr.cnvr_top = ver_tlv.cnvr_top; 2159 data->dmp_hdr.fw_timestamp = ver_tlv.timestamp; 2160 data->dmp_hdr.fw_build_type = ver_tlv.build_type; 2161 data->dmp_hdr.fw_build_num = ver_tlv.build_num; 2162 data->dmp_hdr.cnvi_bt = ver_tlv.cnvi_bt; 2163 2164 if (ver_tlv.img_type == 0x02 || ver_tlv.img_type == 0x03) 2165 data->dmp_hdr.fw_git_sha1 = ver_tlv.git_sha1; 2166 2167 btintel_print_fseq_info(hdev); 2168 exit_error: 2169 kfree_skb(skb); 2170 2171 return err; 2172 } 2173 2174 static int btintel_pcie_setup(struct hci_dev *hdev) 2175 { 2176 int err, fw_dl_retry = 0; 2177 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 2178 2179 while ((err = btintel_pcie_setup_internal(hdev)) && fw_dl_retry++ < 1) { 2180 bt_dev_err(hdev, "Firmware download retry count: %d", 2181 fw_dl_retry); 2182 btintel_pcie_dump_debug_registers(hdev); 2183 btintel_pcie_disable_interrupts(data); 2184 btintel_pcie_synchronize_irqs(data); 2185 err = btintel_pcie_reset_bt(data); 2186 if (err) { 2187 bt_dev_err(hdev, "Failed to do shr reset: %d", err); 2188 break; 2189 } 2190 usleep_range(10000, 12000); 2191 btintel_pcie_reset_ia(data); 2192 btintel_pcie_enable_interrupts(data); 2193 btintel_pcie_config_msix(data); 2194 err = btintel_pcie_enable_bt(data); 2195 if (err) { 2196 bt_dev_err(hdev, "Failed to enable hardware: %d", err); 2197 break; 2198 } 2199 btintel_pcie_start_rx(data); 2200 } 2201 2202 if (!err) 2203 set_bit(BTINTEL_PCIE_SETUP_DONE, &data->flags); 2204 return err; 2205 } 2206 2207 static struct btintel_pcie_dev_recovery * 2208 btintel_pcie_get_recovery(struct pci_dev *pdev, struct device *dev) 2209 { 2210 struct btintel_pcie_dev_recovery *tmp, *data = NULL; 2211 const char *name = pci_name(pdev); 2212 const size_t name_len = strlen(name) + 1; 2213 struct hci_dev *hdev = to_hci_dev(dev); 2214 2215 spin_lock(&btintel_pcie_recovery_lock); 2216 list_for_each_entry(tmp, &btintel_pcie_recovery_list, list) { 2217 if (strcmp(tmp->name, name)) 2218 continue; 2219 data = tmp; 2220 break; 2221 } 2222 spin_unlock(&btintel_pcie_recovery_lock); 2223 2224 if (data) { 2225 bt_dev_dbg(hdev, "Found restart data for BDF: %s", data->name); 2226 return data; 2227 } 2228 2229 data = kzalloc_flex(*data, name, name_len, GFP_ATOMIC); 2230 if (!data) 2231 return NULL; 2232 2233 strscpy(data->name, name, name_len); 2234 spin_lock(&btintel_pcie_recovery_lock); 2235 list_add_tail(&data->list, &btintel_pcie_recovery_list); 2236 spin_unlock(&btintel_pcie_recovery_lock); 2237 2238 return data; 2239 } 2240 2241 static void btintel_pcie_free_restart_list(void) 2242 { 2243 struct btintel_pcie_dev_recovery *tmp; 2244 2245 while ((tmp = list_first_entry_or_null(&btintel_pcie_recovery_list, 2246 typeof(*tmp), list))) { 2247 list_del(&tmp->list); 2248 kfree(tmp); 2249 } 2250 } 2251 2252 static void btintel_pcie_inc_recovery_count(struct pci_dev *pdev, 2253 struct device *dev) 2254 { 2255 struct btintel_pcie_dev_recovery *data; 2256 time64_t retry_window; 2257 2258 data = btintel_pcie_get_recovery(pdev, dev); 2259 if (!data) 2260 return; 2261 2262 retry_window = ktime_get_boottime_seconds() - data->last_error; 2263 if (data->count == 0) { 2264 data->last_error = ktime_get_boottime_seconds(); 2265 data->count++; 2266 } else if (retry_window < BTINTEL_PCIE_RESET_WINDOW_SECS && 2267 data->count <= BTINTEL_PCIE_FLR_MAX_RETRY) { 2268 data->count++; 2269 } else if (retry_window > BTINTEL_PCIE_RESET_WINDOW_SECS) { 2270 data->last_error = 0; 2271 data->count = 0; 2272 } 2273 } 2274 2275 static int btintel_pcie_setup_hdev(struct btintel_pcie_data *data); 2276 2277 static void btintel_pcie_removal_work(struct work_struct *wk) 2278 { 2279 struct btintel_pcie_removal *removal = 2280 container_of(wk, struct btintel_pcie_removal, work); 2281 struct pci_dev *pdev = removal->pdev; 2282 struct btintel_pcie_data *data; 2283 int err; 2284 2285 pci_lock_rescan_remove(); 2286 2287 if (!pdev->bus) 2288 goto error; 2289 2290 data = pci_get_drvdata(pdev); 2291 2292 btintel_pcie_disable_interrupts(data); 2293 btintel_pcie_synchronize_irqs(data); 2294 2295 flush_work(&data->rx_work); 2296 2297 bt_dev_dbg(data->hdev, "Release bluetooth interface"); 2298 btintel_pcie_release_hdev(data); 2299 2300 err = pci_reset_function(pdev); 2301 if (err) { 2302 BT_ERR("Failed resetting the pcie device (%d)", err); 2303 goto error; 2304 } 2305 2306 btintel_pcie_enable_interrupts(data); 2307 btintel_pcie_config_msix(data); 2308 2309 err = btintel_pcie_enable_bt(data); 2310 if (err) { 2311 BT_ERR("Failed to enable bluetooth hardware after reset (%d)", 2312 err); 2313 goto error; 2314 } 2315 2316 btintel_pcie_reset_ia(data); 2317 btintel_pcie_start_rx(data); 2318 data->flags = 0; 2319 2320 err = btintel_pcie_setup_hdev(data); 2321 if (err) { 2322 BT_ERR("Failed registering hdev (%d)", err); 2323 goto error; 2324 } 2325 error: 2326 pci_dev_put(pdev); 2327 pci_unlock_rescan_remove(); 2328 kfree(removal); 2329 } 2330 2331 static void btintel_pcie_reset(struct hci_dev *hdev) 2332 { 2333 struct btintel_pcie_removal *removal; 2334 struct btintel_pcie_data *data; 2335 2336 data = hci_get_drvdata(hdev); 2337 2338 if (!test_bit(BTINTEL_PCIE_SETUP_DONE, &data->flags)) 2339 return; 2340 2341 if (test_and_set_bit(BTINTEL_PCIE_RECOVERY_IN_PROGRESS, &data->flags)) 2342 return; 2343 2344 removal = kzalloc_obj(*removal, GFP_ATOMIC); 2345 if (!removal) 2346 return; 2347 2348 removal->pdev = data->pdev; 2349 INIT_WORK(&removal->work, btintel_pcie_removal_work); 2350 pci_dev_get(removal->pdev); 2351 schedule_work(&removal->work); 2352 } 2353 2354 static void btintel_pcie_hw_error(struct hci_dev *hdev, u8 code) 2355 { 2356 struct btintel_pcie_dev_recovery *data; 2357 struct btintel_pcie_data *dev_data = hci_get_drvdata(hdev); 2358 struct pci_dev *pdev = dev_data->pdev; 2359 time64_t retry_window; 2360 2361 if (code == 0x13) { 2362 bt_dev_err(hdev, "Encountered top exception"); 2363 return; 2364 } 2365 2366 data = btintel_pcie_get_recovery(pdev, &hdev->dev); 2367 if (!data) 2368 return; 2369 2370 retry_window = ktime_get_boottime_seconds() - data->last_error; 2371 2372 if (retry_window < BTINTEL_PCIE_RESET_WINDOW_SECS && 2373 data->count >= BTINTEL_PCIE_FLR_MAX_RETRY) { 2374 bt_dev_err(hdev, "Exhausted maximum: %d recovery attempts: %d", 2375 BTINTEL_PCIE_FLR_MAX_RETRY, data->count); 2376 bt_dev_dbg(hdev, "Boot time: %lld seconds", 2377 ktime_get_boottime_seconds()); 2378 bt_dev_dbg(hdev, "last error at: %lld seconds", 2379 data->last_error); 2380 return; 2381 } 2382 btintel_pcie_inc_recovery_count(pdev, &hdev->dev); 2383 btintel_pcie_reset(hdev); 2384 } 2385 2386 static bool btintel_pcie_wakeup(struct hci_dev *hdev) 2387 { 2388 struct btintel_pcie_data *data = hci_get_drvdata(hdev); 2389 2390 return device_may_wakeup(&data->pdev->dev); 2391 } 2392 2393 static const struct { 2394 u16 opcode; 2395 const char *desc; 2396 } btintel_pcie_hci_drv_supported_commands[] = { 2397 /* Common commands */ 2398 { HCI_DRV_OP_READ_INFO, "Read Info" }, 2399 }; 2400 2401 static int btintel_pcie_hci_drv_read_info(struct hci_dev *hdev, void *data, 2402 u16 data_len) 2403 { 2404 struct hci_drv_rp_read_info *rp; 2405 size_t rp_size; 2406 int err, i; 2407 u16 opcode, num_supported_commands = 2408 ARRAY_SIZE(btintel_pcie_hci_drv_supported_commands); 2409 2410 rp_size = struct_size(rp, supported_commands, num_supported_commands); 2411 2412 rp = kmalloc(rp_size, GFP_KERNEL); 2413 if (!rp) 2414 return -ENOMEM; 2415 2416 strscpy_pad(rp->driver_name, KBUILD_MODNAME); 2417 2418 rp->num_supported_commands = cpu_to_le16(num_supported_commands); 2419 for (i = 0; i < num_supported_commands; i++) { 2420 opcode = btintel_pcie_hci_drv_supported_commands[i].opcode; 2421 bt_dev_dbg(hdev, 2422 "Supported HCI Drv command (0x%02x|0x%04x): %s", 2423 hci_opcode_ogf(opcode), 2424 hci_opcode_ocf(opcode), 2425 btintel_pcie_hci_drv_supported_commands[i].desc); 2426 rp->supported_commands[i] = cpu_to_le16(opcode); 2427 } 2428 2429 err = hci_drv_cmd_complete(hdev, HCI_DRV_OP_READ_INFO, 2430 HCI_DRV_STATUS_SUCCESS, 2431 rp, rp_size); 2432 2433 kfree(rp); 2434 return err; 2435 } 2436 2437 static const struct hci_drv_handler btintel_pcie_hci_drv_common_handlers[] = { 2438 { btintel_pcie_hci_drv_read_info, HCI_DRV_READ_INFO_SIZE }, 2439 }; 2440 2441 static const struct hci_drv_handler btintel_pcie_hci_drv_specific_handlers[] = {}; 2442 2443 static struct hci_drv btintel_pcie_hci_drv = { 2444 .common_handler_count = ARRAY_SIZE(btintel_pcie_hci_drv_common_handlers), 2445 .common_handlers = btintel_pcie_hci_drv_common_handlers, 2446 .specific_handler_count = ARRAY_SIZE(btintel_pcie_hci_drv_specific_handlers), 2447 .specific_handlers = btintel_pcie_hci_drv_specific_handlers, 2448 }; 2449 2450 static int btintel_pcie_setup_hdev(struct btintel_pcie_data *data) 2451 { 2452 int err; 2453 struct hci_dev *hdev; 2454 2455 hdev = hci_alloc_dev_priv(sizeof(struct btintel_data)); 2456 if (!hdev) 2457 return -ENOMEM; 2458 2459 hdev->bus = HCI_PCI; 2460 hci_set_drvdata(hdev, data); 2461 2462 data->hdev = hdev; 2463 SET_HCIDEV_DEV(hdev, &data->pdev->dev); 2464 2465 hdev->manufacturer = 2; 2466 hdev->open = btintel_pcie_open; 2467 hdev->close = btintel_pcie_close; 2468 hdev->send = btintel_pcie_send_frame; 2469 hdev->setup = btintel_pcie_setup; 2470 hdev->shutdown = btintel_shutdown_combined; 2471 hdev->hw_error = btintel_pcie_hw_error; 2472 hdev->set_diag = btintel_set_diag; 2473 hdev->set_bdaddr = btintel_set_bdaddr; 2474 hdev->reset = btintel_pcie_reset; 2475 hdev->wakeup = btintel_pcie_wakeup; 2476 hdev->hci_drv = &btintel_pcie_hci_drv; 2477 2478 err = hci_register_dev(hdev); 2479 if (err < 0) { 2480 BT_ERR("Failed to register to hdev (%d)", err); 2481 goto exit_error; 2482 } 2483 2484 data->dmp_hdr.driver_name = KBUILD_MODNAME; 2485 return 0; 2486 2487 exit_error: 2488 hci_free_dev(hdev); 2489 return err; 2490 } 2491 2492 static int btintel_pcie_probe(struct pci_dev *pdev, 2493 const struct pci_device_id *ent) 2494 { 2495 int err; 2496 struct btintel_pcie_data *data; 2497 2498 if (!pdev) 2499 return -ENODEV; 2500 2501 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 2502 if (!data) 2503 return -ENOMEM; 2504 2505 data->pdev = pdev; 2506 2507 spin_lock_init(&data->irq_lock); 2508 spin_lock_init(&data->hci_rx_lock); 2509 2510 init_waitqueue_head(&data->gp0_wait_q); 2511 data->gp0_received = false; 2512 2513 init_waitqueue_head(&data->tx_wait_q); 2514 data->tx_wait_done = false; 2515 2516 data->workqueue = alloc_ordered_workqueue(KBUILD_MODNAME, WQ_HIGHPRI); 2517 if (!data->workqueue) 2518 return -ENOMEM; 2519 2520 skb_queue_head_init(&data->rx_skb_q); 2521 INIT_WORK(&data->rx_work, btintel_pcie_rx_work); 2522 2523 data->boot_stage_cache = 0x00; 2524 data->img_resp_cache = 0x00; 2525 2526 err = btintel_pcie_config_pcie(pdev, data); 2527 if (err) 2528 goto exit_error; 2529 2530 pci_set_drvdata(pdev, data); 2531 2532 err = btintel_pcie_alloc(data); 2533 if (err) 2534 goto exit_error; 2535 2536 err = btintel_pcie_enable_bt(data); 2537 if (err) 2538 goto exit_error; 2539 2540 /* CNV information (CNVi and CNVr) is in CSR */ 2541 data->cnvi = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_HW_REV_REG); 2542 2543 data->cnvr = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_RF_ID_REG); 2544 2545 err = btintel_pcie_start_rx(data); 2546 if (err) 2547 goto exit_error; 2548 2549 err = btintel_pcie_setup_hdev(data); 2550 if (err) 2551 goto exit_error; 2552 2553 bt_dev_dbg(data->hdev, "cnvi: 0x%8.8x cnvr: 0x%8.8x", data->cnvi, 2554 data->cnvr); 2555 return 0; 2556 2557 exit_error: 2558 /* reset device before exit */ 2559 btintel_pcie_reset_bt(data); 2560 2561 pci_clear_master(pdev); 2562 2563 pci_set_drvdata(pdev, NULL); 2564 2565 return err; 2566 } 2567 2568 static void btintel_pcie_remove(struct pci_dev *pdev) 2569 { 2570 struct btintel_pcie_data *data; 2571 2572 data = pci_get_drvdata(pdev); 2573 2574 btintel_pcie_disable_interrupts(data); 2575 2576 btintel_pcie_synchronize_irqs(data); 2577 2578 flush_work(&data->rx_work); 2579 2580 btintel_pcie_reset_bt(data); 2581 for (int i = 0; i < data->alloc_vecs; i++) { 2582 struct msix_entry *msix_entry; 2583 2584 msix_entry = &data->msix_entries[i]; 2585 free_irq(msix_entry->vector, msix_entry); 2586 } 2587 2588 pci_free_irq_vectors(pdev); 2589 2590 btintel_pcie_release_hdev(data); 2591 2592 destroy_workqueue(data->workqueue); 2593 2594 btintel_pcie_free(data); 2595 2596 pci_clear_master(pdev); 2597 2598 pci_set_drvdata(pdev, NULL); 2599 } 2600 2601 #ifdef CONFIG_DEV_COREDUMP 2602 static void btintel_pcie_coredump(struct device *dev) 2603 { 2604 struct pci_dev *pdev = to_pci_dev(dev); 2605 struct btintel_pcie_data *data = pci_get_drvdata(pdev); 2606 2607 if (test_and_set_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, &data->flags)) 2608 return; 2609 2610 data->dmp_hdr.trigger_reason = BTINTEL_PCIE_TRIGGER_REASON_USER_TRIGGER; 2611 queue_work(data->workqueue, &data->rx_work); 2612 } 2613 #endif 2614 2615 static int btintel_pcie_set_dxstate(struct btintel_pcie_data *data, u32 dxstate) 2616 { 2617 int retry = 0, status; 2618 u32 dx_intr_timeout_ms = 200; 2619 2620 do { 2621 data->gp0_received = false; 2622 2623 btintel_pcie_wr_sleep_cntrl(data, dxstate); 2624 2625 status = wait_event_timeout(data->gp0_wait_q, data->gp0_received, 2626 msecs_to_jiffies(dx_intr_timeout_ms)); 2627 2628 if (status) 2629 return 0; 2630 2631 bt_dev_warn(data->hdev, 2632 "Timeout (%u ms) on alive interrupt for D%d entry, retry count %d", 2633 dx_intr_timeout_ms, dxstate, retry); 2634 2635 /* clear gp0 cause */ 2636 btintel_pcie_clr_reg_bits(data, 2637 BTINTEL_PCIE_CSR_MSIX_HW_INT_CAUSES, 2638 BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0); 2639 2640 /* A hardware bug may cause the alive interrupt to be missed. 2641 * Check if the controller reached the expected state and retry 2642 * the operation only if it hasn't. 2643 */ 2644 if (dxstate == BTINTEL_PCIE_STATE_D0) { 2645 if (btintel_pcie_in_d0(data)) 2646 return 0; 2647 } else { 2648 if (btintel_pcie_in_d3(data)) 2649 return 0; 2650 } 2651 2652 } while (++retry < BTINTEL_PCIE_DX_TRANSITION_MAX_RETRIES); 2653 2654 return -EBUSY; 2655 } 2656 2657 static int btintel_pcie_suspend_late(struct device *dev, pm_message_t mesg) 2658 { 2659 struct pci_dev *pdev = to_pci_dev(dev); 2660 struct btintel_pcie_data *data; 2661 ktime_t start; 2662 u32 dxstate; 2663 int err; 2664 2665 data = pci_get_drvdata(pdev); 2666 2667 dxstate = (mesg.event == PM_EVENT_SUSPEND ? 2668 BTINTEL_PCIE_STATE_D3_HOT : BTINTEL_PCIE_STATE_D3_COLD); 2669 2670 data->pm_sx_event = mesg.event; 2671 2672 start = ktime_get(); 2673 2674 /* Refer: 6.4.11.7 -> Platform power management */ 2675 err = btintel_pcie_set_dxstate(data, dxstate); 2676 2677 if (err) 2678 return err; 2679 2680 bt_dev_dbg(data->hdev, 2681 "device entered into d3 state from d0 in %lld us", 2682 ktime_to_us(ktime_get() - start)); 2683 return err; 2684 } 2685 2686 static int btintel_pcie_suspend(struct device *dev) 2687 { 2688 return btintel_pcie_suspend_late(dev, PMSG_SUSPEND); 2689 } 2690 2691 static int btintel_pcie_hibernate(struct device *dev) 2692 { 2693 return btintel_pcie_suspend_late(dev, PMSG_HIBERNATE); 2694 } 2695 2696 static int btintel_pcie_freeze(struct device *dev) 2697 { 2698 return btintel_pcie_suspend_late(dev, PMSG_FREEZE); 2699 } 2700 2701 static int btintel_pcie_resume(struct device *dev) 2702 { 2703 struct pci_dev *pdev = to_pci_dev(dev); 2704 struct btintel_pcie_data *data; 2705 ktime_t start; 2706 int err; 2707 2708 data = pci_get_drvdata(pdev); 2709 data->gp0_received = false; 2710 2711 start = ktime_get(); 2712 2713 /* When the system enters S4 (hibernate) mode, bluetooth device loses 2714 * power, which results in the erasure of its loaded firmware. 2715 * Consequently, function level reset (flr) is required on system 2716 * resume to bring the controller back into an operational state by 2717 * initiating a new firmware download. 2718 */ 2719 2720 if (data->pm_sx_event == PM_EVENT_FREEZE || 2721 data->pm_sx_event == PM_EVENT_HIBERNATE) { 2722 set_bit(BTINTEL_PCIE_CORE_HALTED, &data->flags); 2723 btintel_pcie_reset(data->hdev); 2724 return 0; 2725 } 2726 2727 /* Refer: 6.4.11.7 -> Platform power management */ 2728 err = btintel_pcie_set_dxstate(data, BTINTEL_PCIE_STATE_D0); 2729 2730 if (err == 0) { 2731 bt_dev_dbg(data->hdev, 2732 "device entered into d0 state from d3 in %lld us", 2733 ktime_to_us(ktime_get() - start)); 2734 return err; 2735 } 2736 2737 /* Trigger function level reset if the controller is in error 2738 * state during resume() to bring back the controller to 2739 * operational mode 2740 */ 2741 2742 data->boot_stage_cache = btintel_pcie_rd_reg32(data, 2743 BTINTEL_PCIE_CSR_BOOT_STAGE_REG); 2744 if (btintel_pcie_in_error(data) || 2745 btintel_pcie_in_device_halt(data)) { 2746 bt_dev_err(data->hdev, "Controller in error state for D0 entry"); 2747 if (!test_and_set_bit(BTINTEL_PCIE_COREDUMP_INPROGRESS, 2748 &data->flags)) { 2749 data->dmp_hdr.trigger_reason = 2750 BTINTEL_PCIE_TRIGGER_REASON_FW_ASSERT; 2751 queue_work(data->workqueue, &data->rx_work); 2752 } 2753 set_bit(BTINTEL_PCIE_CORE_HALTED, &data->flags); 2754 btintel_pcie_reset(data->hdev); 2755 } 2756 return err; 2757 } 2758 2759 static const struct dev_pm_ops btintel_pcie_pm_ops = { 2760 .suspend = btintel_pcie_suspend, 2761 .resume = btintel_pcie_resume, 2762 .freeze = btintel_pcie_freeze, 2763 .thaw = btintel_pcie_resume, 2764 .poweroff = btintel_pcie_hibernate, 2765 .restore = btintel_pcie_resume, 2766 }; 2767 2768 static struct pci_driver btintel_pcie_driver = { 2769 .name = KBUILD_MODNAME, 2770 .id_table = btintel_pcie_table, 2771 .probe = btintel_pcie_probe, 2772 .remove = btintel_pcie_remove, 2773 .driver.pm = pm_sleep_ptr(&btintel_pcie_pm_ops), 2774 #ifdef CONFIG_DEV_COREDUMP 2775 .driver.coredump = btintel_pcie_coredump 2776 #endif 2777 }; 2778 2779 static int __init btintel_pcie_init(void) 2780 { 2781 return pci_register_driver(&btintel_pcie_driver); 2782 } 2783 2784 static void __exit btintel_pcie_exit(void) 2785 { 2786 pci_unregister_driver(&btintel_pcie_driver); 2787 btintel_pcie_free_restart_list(); 2788 } 2789 2790 module_init(btintel_pcie_init); 2791 module_exit(btintel_pcie_exit); 2792 2793 MODULE_AUTHOR("Tedd Ho-Jeong An <tedd.an@intel.com>"); 2794 MODULE_DESCRIPTION("Intel Bluetooth PCIe transport driver ver " VERSION); 2795 MODULE_VERSION(VERSION); 2796 MODULE_LICENSE("GPL"); 2797