1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * 4 * Bluetooth support for Intel devices 5 * 6 * Copyright (C) 2015 Intel Corporation 7 */ 8 9 /* List of tlv type */ 10 enum { 11 INTEL_TLV_CNVI_TOP = 0x10, 12 INTEL_TLV_CNVR_TOP, 13 INTEL_TLV_CNVI_BT, 14 INTEL_TLV_CNVR_BT, 15 INTEL_TLV_CNVI_OTP, 16 INTEL_TLV_CNVR_OTP, 17 INTEL_TLV_DEV_REV_ID, 18 INTEL_TLV_USB_VENDOR_ID, 19 INTEL_TLV_USB_PRODUCT_ID, 20 INTEL_TLV_PCIE_VENDOR_ID, 21 INTEL_TLV_PCIE_DEVICE_ID, 22 INTEL_TLV_PCIE_SUBSYSTEM_ID, 23 INTEL_TLV_IMAGE_TYPE, 24 INTEL_TLV_TIME_STAMP, 25 INTEL_TLV_BUILD_TYPE, 26 INTEL_TLV_BUILD_NUM, 27 INTEL_TLV_FW_BUILD_PRODUCT, 28 INTEL_TLV_FW_BUILD_HW, 29 INTEL_TLV_FW_STEP, 30 INTEL_TLV_BT_SPEC, 31 INTEL_TLV_MFG_NAME, 32 INTEL_TLV_HCI_REV, 33 INTEL_TLV_LMP_SUBVER, 34 INTEL_TLV_OTP_PATCH_VER, 35 INTEL_TLV_SECURE_BOOT, 36 INTEL_TLV_KEY_FROM_HDR, 37 INTEL_TLV_OTP_LOCK, 38 INTEL_TLV_API_LOCK, 39 INTEL_TLV_DEBUG_LOCK, 40 INTEL_TLV_MIN_FW, 41 INTEL_TLV_LIMITED_CCE, 42 INTEL_TLV_SBE_TYPE, 43 INTEL_TLV_OTP_BDADDR, 44 INTEL_TLV_UNLOCKED_STATE, 45 INTEL_TLV_GIT_SHA1, 46 INTEL_TLV_FW_ID = 0x50 47 }; 48 49 struct intel_tlv { 50 u8 type; 51 u8 len; 52 u8 val[]; 53 } __packed; 54 55 #define BTINTEL_HCI_OP_RESET 0xfc01 56 #define BTINTEL_HCI_OP_DEBUG 0xfcd9 57 58 #define BTINTEL_CNVI_BLAZARI 0x900 /* BlazarI - Lunar Lake */ 59 #define BTINTEL_CNVI_BLAZARIW 0x901 /* BlazarIW - Wildcat Lake */ 60 #define BTINTEL_CNVI_GAP 0x910 /* Gale Peak2 - Meteor Lake */ 61 #define BTINTEL_CNVI_BLAZARU 0x930 /* BlazarU - Meteor Lake */ 62 #define BTINTEL_CNVI_SCP 0xA00 /* Scorpius Peak - Panther Lake */ 63 #define BTINTEL_CNVI_SCP2 0xA10 /* Scorpius Peak2 - Nova Lake */ 64 #define BTINTEL_CNVI_SCP2F 0xA20 /* Scorpius Peak2F - Nova Lake */ 65 66 /* CNVR */ 67 #define BTINTEL_CNVR_FMP2 0x910 68 69 #define BTINTEL_IMG_BOOTLOADER 0x01 /* Bootloader image */ 70 #define BTINTEL_IMG_IML 0x02 /* Intermediate image */ 71 #define BTINTEL_IMG_OP 0x03 /* Operational image */ 72 73 #define BTINTEL_FWID_MAXLEN 64 74 75 /* CNVi Hardware variant */ 76 #define BTINTEL_HWID_GAP 0x1c /* Gale Peak2 - Meteor Lake */ 77 #define BTINTEL_HWID_BZRI 0x1e /* BlazarI - Lunar Lake */ 78 #define BTINTEL_HWID_BZRU 0x1d /* BlazarU - Meteor Lake */ 79 #define BTINTEL_HWID_SCP 0x1f /* Scorpius Peak - Panther Lake */ 80 #define BTINTEL_HWID_SCP2 0x20 /* Scorpius Peak2 - Nova Lake */ 81 #define BTINTEL_HWID_SCP2F 0x21 /* Scorpius Peak2-F - Nova Lake */ 82 #define BTINTEL_HWID_BZRIW 0x22 /* BlazarIW - Wildcat Lake */ 83 84 extern const guid_t btintel_guid_dsm; 85 86 struct intel_version_tlv { 87 u32 cnvi_top; 88 u32 cnvr_top; 89 u32 cnvi_bt; 90 u32 cnvr_bt; 91 u16 dev_rev_id; 92 u8 img_type; 93 u16 timestamp; 94 u8 build_type; 95 u32 build_num; 96 u8 secure_boot; 97 u8 otp_lock; 98 u8 api_lock; 99 u8 debug_lock; 100 u8 min_fw_build_nn; 101 u8 min_fw_build_cw; 102 u8 min_fw_build_yy; 103 u8 limited_cce; 104 u8 sbe_type; 105 u32 git_sha1; 106 u8 fw_id[BTINTEL_FWID_MAXLEN]; 107 bdaddr_t otp_bd_addr; 108 }; 109 110 struct intel_version { 111 u8 status; 112 u8 hw_platform; 113 u8 hw_variant; 114 u8 hw_revision; 115 u8 fw_variant; 116 u8 fw_revision; 117 u8 fw_build_num; 118 u8 fw_build_ww; 119 u8 fw_build_yy; 120 u8 fw_patch_num; 121 } __packed; 122 123 struct intel_boot_params { 124 __u8 status; 125 __u8 otp_format; 126 __u8 otp_content; 127 __u8 otp_patch; 128 __le16 dev_revid; 129 __u8 secure_boot; 130 __u8 key_from_hdr; 131 __u8 key_type; 132 __u8 otp_lock; 133 __u8 api_lock; 134 __u8 debug_lock; 135 bdaddr_t otp_bdaddr; 136 __u8 min_fw_build_nn; 137 __u8 min_fw_build_cw; 138 __u8 min_fw_build_yy; 139 __u8 limited_cce; 140 __u8 unlocked_state; 141 } __packed; 142 143 struct intel_bootup { 144 __u8 zero; 145 __u8 num_cmds; 146 __u8 source; 147 __u8 reset_type; 148 __u8 reset_reason; 149 __u8 ddc_status; 150 } __packed; 151 152 struct intel_secure_send_result { 153 __u8 result; 154 __le16 opcode; 155 __u8 status; 156 } __packed; 157 158 struct intel_reset { 159 __u8 reset_type; 160 __u8 patch_enable; 161 __u8 ddc_reload; 162 __u8 boot_option; 163 __le32 boot_param; 164 } __packed; 165 166 struct intel_debug_features { 167 __u8 page1[16]; 168 } __packed; 169 170 struct intel_offload_use_cases { 171 __u8 status; 172 __u8 preset[8]; 173 } __packed; 174 175 #define INTEL_OP_PPAG_CMD 0xFE0B 176 struct hci_ppag_enable_cmd { 177 __le32 ppag_enable_flags; 178 } __packed; 179 180 #define INTEL_TLV_TYPE_ID 0x01 181 182 #define INTEL_TLV_SYSTEM_EXCEPTION 0x00 183 #define INTEL_TLV_FATAL_EXCEPTION 0x01 184 #define INTEL_TLV_DEBUG_EXCEPTION 0x02 185 #define INTEL_TLV_TEST_EXCEPTION 0xDE 186 187 struct btintel_cp_ddc_write { 188 u8 len; 189 __le16 id; 190 u8 data[]; 191 } __packed; 192 193 /* Bluetooth SAR feature (BRDS), Revision 1 */ 194 struct btintel_sar_inc_pwr { 195 u8 revision; 196 u32 bt_sar_bios; /* Mode of SAR control to be used, 1:enabled in bios */ 197 u32 inc_power_mode; /* Increased power mode */ 198 u8 sar_2400_chain_a; /* Sar power restriction LB */ 199 u8 br; 200 u8 edr2; 201 u8 edr3; 202 u8 le; 203 u8 le_2mhz; 204 u8 le_lr; 205 }; 206 207 #define INTEL_HW_PLATFORM(cnvx_bt) ((u8)(((cnvx_bt) & 0x0000ff00) >> 8)) 208 #define INTEL_HW_VARIANT(cnvx_bt) ((u8)(((cnvx_bt) & 0x003f0000) >> 16)) 209 #define INTEL_CNVX_TOP_TYPE(cnvx_top) ((cnvx_top) & 0x00000fff) 210 #define INTEL_CNVX_TOP_STEP(cnvx_top) (((cnvx_top) & 0x0f000000) >> 24) 211 #define INTEL_CNVX_TOP_PACK_SWAB(t, s) __swab16(((__u16)(((t) << 4) | (s)))) 212 213 enum { 214 INTEL_BOOTLOADER, 215 INTEL_DOWNLOADING, 216 INTEL_FIRMWARE_LOADED, 217 INTEL_FIRMWARE_FAILED, 218 INTEL_BOOTING, 219 INTEL_BROKEN_INITIAL_NCMD, 220 INTEL_BROKEN_SHUTDOWN_LED, 221 INTEL_ROM_LEGACY, 222 INTEL_ROM_LEGACY_NO_WBS_SUPPORT, 223 INTEL_ACPI_RESET_ACTIVE, 224 INTEL_WAIT_FOR_D0, 225 226 __INTEL_NUM_FLAGS, 227 }; 228 229 struct btintel_data { 230 DECLARE_BITMAP(flags, __INTEL_NUM_FLAGS); 231 int (*acpi_reset_method)(struct hci_dev *hdev); 232 }; 233 234 #define btintel_set_flag(hdev, nr) \ 235 do { \ 236 struct btintel_data *intel = hci_get_priv((hdev)); \ 237 set_bit((nr), intel->flags); \ 238 } while (0) 239 240 #define btintel_clear_flag(hdev, nr) \ 241 do { \ 242 struct btintel_data *intel = hci_get_priv((hdev)); \ 243 clear_bit((nr), intel->flags); \ 244 } while (0) 245 246 #define btintel_wake_up_flag(hdev, nr) \ 247 do { \ 248 struct btintel_data *intel = hci_get_priv((hdev)); \ 249 wake_up_bit(intel->flags, (nr)); \ 250 } while (0) 251 252 #define btintel_get_flag(hdev) \ 253 (((struct btintel_data *)hci_get_priv(hdev))->flags) 254 255 #define btintel_test_flag(hdev, nr) test_bit((nr), btintel_get_flag(hdev)) 256 #define btintel_test_and_clear_flag(hdev, nr) test_and_clear_bit((nr), btintel_get_flag(hdev)) 257 #define btintel_wait_on_flag_timeout(hdev, nr, m, to) \ 258 wait_on_bit_timeout(btintel_get_flag(hdev), (nr), m, to) 259 260 #if IS_ENABLED(CONFIG_BT_INTEL) || IS_ENABLED(CONFIG_BT_INTEL_PCIE) 261 262 int btintel_check_bdaddr(struct hci_dev *hdev); 263 int btintel_enter_mfg(struct hci_dev *hdev); 264 int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched); 265 int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr); 266 int btintel_set_diag(struct hci_dev *hdev, bool enable); 267 268 int btintel_version_info(struct hci_dev *hdev, struct intel_version *ver); 269 int btintel_load_ddc_config(struct hci_dev *hdev, const char *ddc_name); 270 int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug); 271 int btintel_read_version(struct hci_dev *hdev, struct intel_version *ver); 272 struct regmap *btintel_regmap_init(struct hci_dev *hdev, u16 opcode_read, 273 u16 opcode_write); 274 int btintel_send_intel_reset(struct hci_dev *hdev, u32 boot_param); 275 int btintel_read_boot_params(struct hci_dev *hdev, 276 struct intel_boot_params *params); 277 int btintel_download_firmware(struct hci_dev *dev, struct intel_version *ver, 278 const struct firmware *fw, u32 *boot_param); 279 int btintel_configure_setup(struct hci_dev *hdev, const char *driver_name); 280 int btintel_recv_event(struct hci_dev *hdev, struct sk_buff *skb); 281 void btintel_bootup(struct hci_dev *hdev, const void *ptr, unsigned int len); 282 void btintel_secure_send_result(struct hci_dev *hdev, 283 const void *ptr, unsigned int len); 284 int btintel_set_quality_report(struct hci_dev *hdev, bool enable); 285 int btintel_version_info_tlv(struct hci_dev *hdev, 286 struct intel_version_tlv *version); 287 int btintel_parse_version_tlv(struct hci_dev *hdev, 288 struct intel_version_tlv *version, 289 struct sk_buff *skb); 290 void btintel_set_msft_opcode(struct hci_dev *hdev, u8 hw_variant); 291 int btintel_bootloader_setup_tlv(struct hci_dev *hdev, 292 struct intel_version_tlv *ver); 293 int btintel_shutdown_combined(struct hci_dev *hdev); 294 void btintel_hw_error(struct hci_dev *hdev, u8 code); 295 void btintel_print_fseq_info(struct hci_dev *hdev); 296 int btintel_acpi_reset_method(struct hci_dev *hdev); 297 #else 298 299 static inline int btintel_check_bdaddr(struct hci_dev *hdev) 300 { 301 return -EOPNOTSUPP; 302 } 303 304 static inline int btintel_enter_mfg(struct hci_dev *hdev) 305 { 306 return -EOPNOTSUPP; 307 } 308 309 static inline int btintel_exit_mfg(struct hci_dev *hdev, bool reset, bool patched) 310 { 311 return -EOPNOTSUPP; 312 } 313 314 static inline int btintel_set_bdaddr(struct hci_dev *hdev, const bdaddr_t *bdaddr) 315 { 316 return -EOPNOTSUPP; 317 } 318 319 static inline int btintel_set_diag(struct hci_dev *hdev, bool enable) 320 { 321 return -EOPNOTSUPP; 322 } 323 324 static inline int btintel_version_info(struct hci_dev *hdev, 325 struct intel_version *ver) 326 { 327 return -EOPNOTSUPP; 328 } 329 330 static inline int btintel_load_ddc_config(struct hci_dev *hdev, 331 const char *ddc_name) 332 { 333 return -EOPNOTSUPP; 334 } 335 336 static inline int btintel_set_event_mask_mfg(struct hci_dev *hdev, bool debug) 337 { 338 return -EOPNOTSUPP; 339 } 340 341 static inline int btintel_read_version(struct hci_dev *hdev, 342 struct intel_version *ver) 343 { 344 return -EOPNOTSUPP; 345 } 346 347 static inline struct regmap *btintel_regmap_init(struct hci_dev *hdev, 348 u16 opcode_read, 349 u16 opcode_write) 350 { 351 return ERR_PTR(-EINVAL); 352 } 353 354 static inline int btintel_send_intel_reset(struct hci_dev *hdev, 355 u32 reset_param) 356 { 357 return -EOPNOTSUPP; 358 } 359 360 static inline int btintel_read_boot_params(struct hci_dev *hdev, 361 struct intel_boot_params *params) 362 { 363 return -EOPNOTSUPP; 364 } 365 366 static inline int btintel_download_firmware(struct hci_dev *dev, 367 const struct firmware *fw, 368 u32 *boot_param) 369 { 370 return -EOPNOTSUPP; 371 } 372 373 static inline int btintel_configure_setup(struct hci_dev *hdev, 374 const char *driver_name) 375 { 376 return -ENODEV; 377 } 378 379 static inline void btintel_bootup(struct hci_dev *hdev, 380 const void *ptr, unsigned int len) 381 { 382 } 383 384 static inline void btintel_secure_send_result(struct hci_dev *hdev, 385 const void *ptr, unsigned int len) 386 { 387 } 388 389 static inline int btintel_set_quality_report(struct hci_dev *hdev, bool enable) 390 { 391 return -ENODEV; 392 } 393 394 static inline int btintel_version_info_tlv(struct hci_dev *hdev, 395 struct intel_version_tlv *version) 396 { 397 return -EOPNOTSUPP; 398 } 399 400 static inline int btintel_parse_version_tlv(struct hci_dev *hdev, 401 struct intel_version_tlv *version, 402 struct sk_buff *skb) 403 { 404 return -EOPNOTSUPP; 405 } 406 407 static inline void btintel_set_msft_opcode(struct hci_dev *hdev, u8 hw_variant) 408 409 { 410 } 411 412 static inline int btintel_bootloader_setup_tlv(struct hci_dev *hdev, 413 struct intel_version_tlv *ver) 414 { 415 return -ENODEV; 416 } 417 418 static inline int btintel_shutdown_combined(struct hci_dev *hdev) 419 { 420 return -ENODEV; 421 } 422 423 static inline void btintel_hw_error(struct hci_dev *hdev, u8 code) 424 { 425 } 426 427 static inline void btintel_print_fseq_info(struct hci_dev *hdev) 428 { 429 } 430 static inline int btintel_acpi_reset_method(struct hci_dev *hdev) 431 { 432 return -ENODEV; 433 } 434 #endif 435