1 /* 2 * Broadcom specific AMBA 3 * Bus scanning 4 * 5 * Licensed under the GNU/GPL. See COPYING for details. 6 */ 7 8 #include "scan.h" 9 #include "bcma_private.h" 10 11 #include <linux/bcma/bcma.h> 12 #include <linux/bcma/bcma_regs.h> 13 #include <linux/pci.h> 14 #include <linux/io.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/slab.h> 17 18 struct bcma_device_id_name { 19 u16 id; 20 const char *name; 21 }; 22 23 static const struct bcma_device_id_name bcma_arm_device_names[] = { 24 { BCMA_CORE_4706_MAC_GBIT_COMMON, "BCM4706 GBit MAC Common" }, 25 { BCMA_CORE_ARM_1176, "ARM 1176" }, 26 { BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" }, 27 { BCMA_CORE_ARM_CM3, "ARM CM3" }, 28 }; 29 30 static const struct bcma_device_id_name bcma_bcm_device_names[] = { 31 { BCMA_CORE_OOB_ROUTER, "OOB Router" }, 32 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" }, 33 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" }, 34 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" }, 35 { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" }, 36 { BCMA_CORE_NS_DMA, "DMA" }, 37 { BCMA_CORE_NS_SDIO3, "SDIO3" }, 38 { BCMA_CORE_NS_USB20, "USB 2.0" }, 39 { BCMA_CORE_NS_USB30, "USB 3.0" }, 40 { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" }, 41 { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" }, 42 { BCMA_CORE_NS_ROM, "ROM" }, 43 { BCMA_CORE_NS_NAND, "NAND flash controller" }, 44 { BCMA_CORE_NS_QSPI, "SPI flash controller" }, 45 { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" }, 46 { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" }, 47 { BCMA_CORE_AMEMC, "AMEMC (DDR)" }, 48 { BCMA_CORE_ALTA, "ALTA (I2S)" }, 49 { BCMA_CORE_INVALID, "Invalid" }, 50 { BCMA_CORE_CHIPCOMMON, "ChipCommon" }, 51 { BCMA_CORE_ILINE20, "ILine 20" }, 52 { BCMA_CORE_SRAM, "SRAM" }, 53 { BCMA_CORE_SDRAM, "SDRAM" }, 54 { BCMA_CORE_PCI, "PCI" }, 55 { BCMA_CORE_ETHERNET, "Fast Ethernet" }, 56 { BCMA_CORE_V90, "V90" }, 57 { BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" }, 58 { BCMA_CORE_ADSL, "ADSL" }, 59 { BCMA_CORE_ILINE100, "ILine 100" }, 60 { BCMA_CORE_IPSEC, "IPSEC" }, 61 { BCMA_CORE_UTOPIA, "UTOPIA" }, 62 { BCMA_CORE_PCMCIA, "PCMCIA" }, 63 { BCMA_CORE_INTERNAL_MEM, "Internal Memory" }, 64 { BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" }, 65 { BCMA_CORE_OFDM, "OFDM" }, 66 { BCMA_CORE_EXTIF, "EXTIF" }, 67 { BCMA_CORE_80211, "IEEE 802.11" }, 68 { BCMA_CORE_PHY_A, "PHY A" }, 69 { BCMA_CORE_PHY_B, "PHY B" }, 70 { BCMA_CORE_PHY_G, "PHY G" }, 71 { BCMA_CORE_USB11_HOST, "USB 1.1 Host" }, 72 { BCMA_CORE_USB11_DEV, "USB 1.1 Device" }, 73 { BCMA_CORE_USB20_HOST, "USB 2.0 Host" }, 74 { BCMA_CORE_USB20_DEV, "USB 2.0 Device" }, 75 { BCMA_CORE_SDIO_HOST, "SDIO Host" }, 76 { BCMA_CORE_ROBOSWITCH, "Roboswitch" }, 77 { BCMA_CORE_PARA_ATA, "PATA" }, 78 { BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" }, 79 { BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" }, 80 { BCMA_CORE_PCIE, "PCIe" }, 81 { BCMA_CORE_PHY_N, "PHY N" }, 82 { BCMA_CORE_SRAM_CTL, "SRAM Controller" }, 83 { BCMA_CORE_MINI_MACPHY, "Mini MACPHY" }, 84 { BCMA_CORE_PHY_LP, "PHY LP" }, 85 { BCMA_CORE_PMU, "PMU" }, 86 { BCMA_CORE_PHY_SSN, "PHY SSN" }, 87 { BCMA_CORE_SDIO_DEV, "SDIO Device" }, 88 { BCMA_CORE_PHY_HT, "PHY HT" }, 89 { BCMA_CORE_MAC_GBIT, "GBit MAC" }, 90 { BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" }, 91 { BCMA_CORE_PCIE_RC, "PCIe Root Complex" }, 92 { BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" }, 93 { BCMA_CORE_SHARED_COMMON, "Common Shared" }, 94 { BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" }, 95 { BCMA_CORE_SPI_HOST, "SPI Host" }, 96 { BCMA_CORE_I2S, "I2S" }, 97 { BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" }, 98 { BCMA_CORE_SHIM, "SHIM" }, 99 { BCMA_CORE_PCIE2, "PCIe Gen2" }, 100 { BCMA_CORE_ARM_CR4, "ARM CR4" }, 101 { BCMA_CORE_GCI, "GCI" }, 102 { BCMA_CORE_CMEM, "CNDS DDR2/3 memory controller" }, 103 { BCMA_CORE_ARM_CA7, "ARM CA7" }, 104 { BCMA_CORE_DEFAULT, "Default" }, 105 }; 106 107 static const struct bcma_device_id_name bcma_mips_device_names[] = { 108 { BCMA_CORE_MIPS, "MIPS" }, 109 { BCMA_CORE_MIPS_3302, "MIPS 3302" }, 110 { BCMA_CORE_MIPS_74K, "MIPS 74K" }, 111 }; 112 113 static const char *bcma_device_name(const struct bcma_device_id *id) 114 { 115 const struct bcma_device_id_name *names; 116 int size, i; 117 118 /* search manufacturer specific names */ 119 switch (id->manuf) { 120 case BCMA_MANUF_ARM: 121 names = bcma_arm_device_names; 122 size = ARRAY_SIZE(bcma_arm_device_names); 123 break; 124 case BCMA_MANUF_BCM: 125 names = bcma_bcm_device_names; 126 size = ARRAY_SIZE(bcma_bcm_device_names); 127 break; 128 case BCMA_MANUF_MIPS: 129 names = bcma_mips_device_names; 130 size = ARRAY_SIZE(bcma_mips_device_names); 131 break; 132 default: 133 return "UNKNOWN"; 134 } 135 136 for (i = 0; i < size; i++) { 137 if (names[i].id == id->id) 138 return names[i].name; 139 } 140 141 return "UNKNOWN"; 142 } 143 144 static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx, 145 u16 offset) 146 { 147 return readl(bus->mmio + offset); 148 } 149 150 static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr) 151 { 152 if (bus->hosttype == BCMA_HOSTTYPE_PCI) 153 pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN, 154 addr); 155 } 156 157 static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr) 158 { 159 u32 ent = readl(*eromptr); 160 (*eromptr)++; 161 return ent; 162 } 163 164 static void bcma_erom_push_ent(u32 __iomem **eromptr) 165 { 166 (*eromptr)--; 167 } 168 169 static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr) 170 { 171 u32 ent = bcma_erom_get_ent(bus, eromptr); 172 if (!(ent & SCAN_ER_VALID)) 173 return -ENOENT; 174 if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI) 175 return -ENOENT; 176 return ent; 177 } 178 179 static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr) 180 { 181 u32 ent = bcma_erom_get_ent(bus, eromptr); 182 bcma_erom_push_ent(eromptr); 183 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID)); 184 } 185 186 static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr) 187 { 188 u32 ent = bcma_erom_get_ent(bus, eromptr); 189 bcma_erom_push_ent(eromptr); 190 return (((ent & SCAN_ER_VALID)) && 191 ((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) && 192 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE)); 193 } 194 195 static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr) 196 { 197 u32 ent; 198 while (1) { 199 ent = bcma_erom_get_ent(bus, eromptr); 200 if ((ent & SCAN_ER_VALID) && 201 ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI)) 202 break; 203 if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID)) 204 break; 205 } 206 bcma_erom_push_ent(eromptr); 207 } 208 209 static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr) 210 { 211 u32 ent = bcma_erom_get_ent(bus, eromptr); 212 if (!(ent & SCAN_ER_VALID)) 213 return -ENOENT; 214 if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP) 215 return -ENOENT; 216 return ent; 217 } 218 219 static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr, 220 u32 type, u8 port) 221 { 222 u32 addrl, addrh, sizel, sizeh = 0; 223 u32 size; 224 225 u32 ent = bcma_erom_get_ent(bus, eromptr); 226 if ((!(ent & SCAN_ER_VALID)) || 227 ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) || 228 ((ent & SCAN_ADDR_TYPE) != type) || 229 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) { 230 bcma_erom_push_ent(eromptr); 231 return (u32)-EINVAL; 232 } 233 234 addrl = ent & SCAN_ADDR_ADDR; 235 if (ent & SCAN_ADDR_AG32) 236 addrh = bcma_erom_get_ent(bus, eromptr); 237 else 238 addrh = 0; 239 240 if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) { 241 size = bcma_erom_get_ent(bus, eromptr); 242 sizel = size & SCAN_SIZE_SZ; 243 if (size & SCAN_SIZE_SG32) 244 sizeh = bcma_erom_get_ent(bus, eromptr); 245 } else 246 sizel = SCAN_ADDR_SZ_BASE << 247 ((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT); 248 249 return addrl; 250 } 251 252 static struct bcma_device *bcma_find_core_by_index(struct bcma_bus *bus, 253 u16 index) 254 { 255 struct bcma_device *core; 256 257 list_for_each_entry(core, &bus->cores, list) { 258 if (core->core_index == index) 259 return core; 260 } 261 return NULL; 262 } 263 264 static struct bcma_device *bcma_find_core_reverse(struct bcma_bus *bus, u16 coreid) 265 { 266 struct bcma_device *core; 267 268 list_for_each_entry_reverse(core, &bus->cores, list) { 269 if (core->id.id == coreid) 270 return core; 271 } 272 return NULL; 273 } 274 275 #define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO) 276 277 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr, 278 struct bcma_device_id *match, int core_num, 279 struct bcma_device *core) 280 { 281 u32 tmp; 282 u8 i, j, k; 283 s32 cia, cib; 284 u8 ports[2], wrappers[2]; 285 286 /* get CIs */ 287 cia = bcma_erom_get_ci(bus, eromptr); 288 if (cia < 0) { 289 bcma_erom_push_ent(eromptr); 290 if (bcma_erom_is_end(bus, eromptr)) 291 return -ESPIPE; 292 return -EILSEQ; 293 } 294 cib = bcma_erom_get_ci(bus, eromptr); 295 if (cib < 0) 296 return -EILSEQ; 297 298 /* parse CIs */ 299 core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT; 300 core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT; 301 core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT; 302 ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT; 303 ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT; 304 wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT; 305 wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT; 306 core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT; 307 308 if (((core->id.manuf == BCMA_MANUF_ARM) && 309 (core->id.id == 0xFFF)) || 310 (ports[1] == 0)) { 311 bcma_erom_skip_component(bus, eromptr); 312 return -ENXIO; 313 } 314 315 /* check if component is a core at all */ 316 if (wrappers[0] + wrappers[1] == 0) { 317 /* Some specific cores don't need wrappers */ 318 switch (core->id.id) { 319 case BCMA_CORE_4706_MAC_GBIT_COMMON: 320 case BCMA_CORE_NS_CHIPCOMMON_B: 321 case BCMA_CORE_PMU: 322 case BCMA_CORE_GCI: 323 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */ 324 break; 325 default: 326 bcma_erom_skip_component(bus, eromptr); 327 return -ENXIO; 328 } 329 } 330 331 if (bcma_erom_is_bridge(bus, eromptr)) { 332 bcma_erom_skip_component(bus, eromptr); 333 return -ENXIO; 334 } 335 336 if (bcma_find_core_by_index(bus, core_num)) { 337 bcma_erom_skip_component(bus, eromptr); 338 return -ENODEV; 339 } 340 341 if (match && ((match->manuf != BCMA_ANY_MANUF && 342 match->manuf != core->id.manuf) || 343 (match->id != BCMA_ANY_ID && match->id != core->id.id) || 344 (match->rev != BCMA_ANY_REV && match->rev != core->id.rev) || 345 (match->class != BCMA_ANY_CLASS && match->class != core->id.class) 346 )) { 347 bcma_erom_skip_component(bus, eromptr); 348 return -ENODEV; 349 } 350 351 /* get & parse master ports */ 352 for (i = 0; i < ports[0]; i++) { 353 s32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr); 354 if (mst_port_d < 0) 355 return -EILSEQ; 356 } 357 358 /* First Slave Address Descriptor should be port 0: 359 * the main register space for the core 360 */ 361 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0); 362 if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) { 363 /* Try again to see if it is a bridge */ 364 tmp = bcma_erom_get_addr_desc(bus, eromptr, 365 SCAN_ADDR_TYPE_BRIDGE, 0); 366 if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) { 367 return -EILSEQ; 368 } else { 369 bcma_info(bus, "Bridge found\n"); 370 return -ENXIO; 371 } 372 } 373 core->addr = tmp; 374 375 /* get & parse slave ports */ 376 k = 0; 377 for (i = 0; i < ports[1]; i++) { 378 for (j = 0; ; j++) { 379 tmp = bcma_erom_get_addr_desc(bus, eromptr, 380 SCAN_ADDR_TYPE_SLAVE, i); 381 if (IS_ERR_VALUE_U32(tmp)) { 382 /* no more entries for port _i_ */ 383 /* pr_debug("erom: slave port %d " 384 * "has %d descriptors\n", i, j); */ 385 break; 386 } else if (k < ARRAY_SIZE(core->addr_s)) { 387 core->addr_s[k] = tmp; 388 k++; 389 } 390 } 391 } 392 393 /* get & parse master wrappers */ 394 for (i = 0; i < wrappers[0]; i++) { 395 for (j = 0; ; j++) { 396 tmp = bcma_erom_get_addr_desc(bus, eromptr, 397 SCAN_ADDR_TYPE_MWRAP, i); 398 if (IS_ERR_VALUE_U32(tmp)) { 399 /* no more entries for port _i_ */ 400 /* pr_debug("erom: master wrapper %d " 401 * "has %d descriptors\n", i, j); */ 402 break; 403 } else { 404 if (i == 0 && j == 0) 405 core->wrap = tmp; 406 } 407 } 408 } 409 410 /* get & parse slave wrappers */ 411 for (i = 0; i < wrappers[1]; i++) { 412 u8 hack = (ports[1] == 1) ? 0 : 1; 413 for (j = 0; ; j++) { 414 tmp = bcma_erom_get_addr_desc(bus, eromptr, 415 SCAN_ADDR_TYPE_SWRAP, i + hack); 416 if (IS_ERR_VALUE_U32(tmp)) { 417 /* no more entries for port _i_ */ 418 /* pr_debug("erom: master wrapper %d " 419 * has %d descriptors\n", i, j); */ 420 break; 421 } else { 422 if (wrappers[0] == 0 && !i && !j) 423 core->wrap = tmp; 424 } 425 } 426 } 427 if (bus->hosttype == BCMA_HOSTTYPE_SOC) { 428 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE); 429 if (!core->io_addr) 430 return -ENOMEM; 431 if (core->wrap) { 432 core->io_wrap = ioremap_nocache(core->wrap, 433 BCMA_CORE_SIZE); 434 if (!core->io_wrap) { 435 iounmap(core->io_addr); 436 return -ENOMEM; 437 } 438 } 439 } 440 return 0; 441 } 442 443 void bcma_detect_chip(struct bcma_bus *bus) 444 { 445 s32 tmp; 446 struct bcma_chipinfo *chipinfo = &(bus->chipinfo); 447 char chip_id[8]; 448 449 bcma_scan_switch_core(bus, BCMA_ADDR_BASE); 450 451 tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID); 452 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT; 453 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT; 454 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT; 455 456 snprintf(chip_id, ARRAY_SIZE(chip_id), 457 (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id); 458 bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n", 459 chip_id, chipinfo->rev, chipinfo->pkg); 460 } 461 462 int bcma_bus_scan(struct bcma_bus *bus) 463 { 464 u32 erombase; 465 u32 __iomem *eromptr, *eromend; 466 467 int err, core_num = 0; 468 469 /* Skip if bus was already scanned (e.g. during early register) */ 470 if (bus->nr_cores) 471 return 0; 472 473 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM); 474 if (bus->hosttype == BCMA_HOSTTYPE_SOC) { 475 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE); 476 if (!eromptr) 477 return -ENOMEM; 478 } else { 479 eromptr = bus->mmio; 480 } 481 482 eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32); 483 484 bcma_scan_switch_core(bus, erombase); 485 486 while (eromptr < eromend) { 487 struct bcma_device *other_core; 488 struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL); 489 if (!core) { 490 err = -ENOMEM; 491 goto out; 492 } 493 INIT_LIST_HEAD(&core->list); 494 core->bus = bus; 495 496 err = bcma_get_next_core(bus, &eromptr, NULL, core_num, core); 497 if (err < 0) { 498 kfree(core); 499 if (err == -ENODEV) { 500 core_num++; 501 continue; 502 } else if (err == -ENXIO) { 503 continue; 504 } else if (err == -ESPIPE) { 505 break; 506 } 507 goto out; 508 } 509 510 core->core_index = core_num++; 511 bus->nr_cores++; 512 other_core = bcma_find_core_reverse(bus, core->id.id); 513 core->core_unit = (other_core == NULL) ? 0 : other_core->core_unit + 1; 514 bcma_prepare_core(bus, core); 515 516 bcma_info(bus, "Core %d found: %s (manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n", 517 core->core_index, bcma_device_name(&core->id), 518 core->id.manuf, core->id.id, core->id.rev, 519 core->id.class); 520 521 list_add_tail(&core->list, &bus->cores); 522 } 523 524 err = 0; 525 out: 526 if (bus->hosttype == BCMA_HOSTTYPE_SOC) 527 iounmap(eromptr); 528 529 return err; 530 } 531