1 /* 2 * Broadcom specific AMBA 3 * PCI Core 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include "bcma_private.h" 12 #include <linux/bcma/bcma.h> 13 14 /************************************************** 15 * R/W ops. 16 **************************************************/ 17 18 static u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) 19 { 20 pcicore_write32(pc, 0x130, address); 21 pcicore_read32(pc, 0x130); 22 return pcicore_read32(pc, 0x134); 23 } 24 25 #if 0 26 static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) 27 { 28 pcicore_write32(pc, 0x130, address); 29 pcicore_read32(pc, 0x130); 30 pcicore_write32(pc, 0x134, data); 31 } 32 #endif 33 34 static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) 35 { 36 const u16 mdio_control = 0x128; 37 const u16 mdio_data = 0x12C; 38 u32 v; 39 int i; 40 41 v = (1 << 30); /* Start of Transaction */ 42 v |= (1 << 28); /* Write Transaction */ 43 v |= (1 << 17); /* Turnaround */ 44 v |= (0x1F << 18); 45 v |= (phy << 4); 46 pcicore_write32(pc, mdio_data, v); 47 48 udelay(10); 49 for (i = 0; i < 200; i++) { 50 v = pcicore_read32(pc, mdio_control); 51 if (v & 0x100 /* Trans complete */) 52 break; 53 msleep(1); 54 } 55 } 56 57 static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) 58 { 59 const u16 mdio_control = 0x128; 60 const u16 mdio_data = 0x12C; 61 int max_retries = 10; 62 u16 ret = 0; 63 u32 v; 64 int i; 65 66 v = 0x80; /* Enable Preamble Sequence */ 67 v |= 0x2; /* MDIO Clock Divisor */ 68 pcicore_write32(pc, mdio_control, v); 69 70 if (pc->core->id.rev >= 10) { 71 max_retries = 200; 72 bcma_pcie_mdio_set_phy(pc, device); 73 } 74 75 v = (1 << 30); /* Start of Transaction */ 76 v |= (1 << 29); /* Read Transaction */ 77 v |= (1 << 17); /* Turnaround */ 78 if (pc->core->id.rev < 10) 79 v |= (u32)device << 22; 80 v |= (u32)address << 18; 81 pcicore_write32(pc, mdio_data, v); 82 /* Wait for the device to complete the transaction */ 83 udelay(10); 84 for (i = 0; i < max_retries; i++) { 85 v = pcicore_read32(pc, mdio_control); 86 if (v & 0x100 /* Trans complete */) { 87 udelay(10); 88 ret = pcicore_read32(pc, mdio_data); 89 break; 90 } 91 msleep(1); 92 } 93 pcicore_write32(pc, mdio_control, 0); 94 return ret; 95 } 96 97 static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, 98 u8 address, u16 data) 99 { 100 const u16 mdio_control = 0x128; 101 const u16 mdio_data = 0x12C; 102 int max_retries = 10; 103 u32 v; 104 int i; 105 106 v = 0x80; /* Enable Preamble Sequence */ 107 v |= 0x2; /* MDIO Clock Divisor */ 108 pcicore_write32(pc, mdio_control, v); 109 110 if (pc->core->id.rev >= 10) { 111 max_retries = 200; 112 bcma_pcie_mdio_set_phy(pc, device); 113 } 114 115 v = (1 << 30); /* Start of Transaction */ 116 v |= (1 << 28); /* Write Transaction */ 117 v |= (1 << 17); /* Turnaround */ 118 if (pc->core->id.rev < 10) 119 v |= (u32)device << 22; 120 v |= (u32)address << 18; 121 v |= data; 122 pcicore_write32(pc, mdio_data, v); 123 /* Wait for the device to complete the transaction */ 124 udelay(10); 125 for (i = 0; i < max_retries; i++) { 126 v = pcicore_read32(pc, mdio_control); 127 if (v & 0x100 /* Trans complete */) 128 break; 129 msleep(1); 130 } 131 pcicore_write32(pc, mdio_control, 0); 132 } 133 134 /************************************************** 135 * Workarounds. 136 **************************************************/ 137 138 static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) 139 { 140 return (bcma_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; 141 } 142 143 static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) 144 { 145 const u8 serdes_pll_device = 0x1D; 146 const u8 serdes_rx_device = 0x1F; 147 u16 tmp; 148 149 bcma_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, 150 bcma_pcicore_polarity_workaround(pc)); 151 tmp = bcma_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); 152 if (tmp & 0x4000) 153 bcma_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); 154 } 155 156 /************************************************** 157 * Init. 158 **************************************************/ 159 160 static void bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) 161 { 162 bcma_pcicore_serdes_workaround(pc); 163 } 164 165 static bool bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) 166 { 167 struct bcma_bus *bus = pc->core->bus; 168 u16 chipid_top; 169 170 chipid_top = (bus->chipinfo.id & 0xFF00); 171 if (chipid_top != 0x4700 && 172 chipid_top != 0x5300) 173 return false; 174 175 #ifdef CONFIG_SSB_DRIVER_PCICORE 176 if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI) 177 return false; 178 #endif /* CONFIG_SSB_DRIVER_PCICORE */ 179 180 #if 0 181 /* TODO: on BCMA we use address from EROM instead of magic formula */ 182 u32 tmp; 183 return !mips_busprobe32(tmp, (bus->mmio + 184 (pc->core->core_index * BCMA_CORE_SIZE))); 185 #endif 186 187 return true; 188 } 189 190 void bcma_core_pci_init(struct bcma_drv_pci *pc) 191 { 192 if (pc->setup_done) 193 return; 194 195 if (bcma_core_pci_is_in_hostmode(pc)) { 196 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE 197 bcma_core_pci_hostmode_init(pc); 198 #else 199 pr_err("Driver compiled without support for hostmode PCI\n"); 200 #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ 201 } else { 202 bcma_core_pci_clientmode_init(pc); 203 } 204 205 pc->setup_done = true; 206 } 207 208 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, 209 bool enable) 210 { 211 struct pci_dev *pdev = pc->core->bus->host_pci; 212 u32 coremask, tmp; 213 int err = 0; 214 215 if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) { 216 /* This bcma device is not on a PCI host-bus. So the IRQs are 217 * not routed through the PCI core. 218 * So we must not enable routing through the PCI core. */ 219 goto out; 220 } 221 222 err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); 223 if (err) 224 goto out; 225 226 coremask = BIT(core->core_index) << 8; 227 if (enable) 228 tmp |= coremask; 229 else 230 tmp &= ~coremask; 231 232 err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); 233 234 out: 235 return err; 236 } 237 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); 238