1 /* 2 * Broadcom specific AMBA 3 * Broadcom MIPS32 74K core driver 4 * 5 * Copyright 2009, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> 7 * Copyright 2010, Bernhard Loos <bernhardloos@googlemail.com> 8 * Copyright 2011, Hauke Mehrtens <hauke@hauke-m.de> 9 * 10 * Licensed under the GNU/GPL. See COPYING for details. 11 */ 12 13 #include "bcma_private.h" 14 15 #include <linux/bcma/bcma.h> 16 17 #include <linux/mtd/physmap.h> 18 #include <linux/platform_device.h> 19 #include <linux/serial.h> 20 #include <linux/serial_core.h> 21 #include <linux/serial_reg.h> 22 #include <linux/time.h> 23 #ifdef CONFIG_BCM47XX 24 #include <bcm47xx_nvram.h> 25 #endif 26 27 enum bcma_boot_dev { 28 BCMA_BOOT_DEV_UNK = 0, 29 BCMA_BOOT_DEV_ROM, 30 BCMA_BOOT_DEV_PARALLEL, 31 BCMA_BOOT_DEV_SERIAL, 32 BCMA_BOOT_DEV_NAND, 33 }; 34 35 static const char * const part_probes[] = { "bcm47xxpart", NULL }; 36 37 static struct physmap_flash_data bcma_pflash_data = { 38 .part_probe_types = part_probes, 39 }; 40 41 static struct resource bcma_pflash_resource = { 42 .name = "bcma_pflash", 43 .flags = IORESOURCE_MEM, 44 }; 45 46 struct platform_device bcma_pflash_dev = { 47 .name = "physmap-flash", 48 .dev = { 49 .platform_data = &bcma_pflash_data, 50 }, 51 .resource = &bcma_pflash_resource, 52 .num_resources = 1, 53 }; 54 55 /* The 47162a0 hangs when reading MIPS DMP registers registers */ 56 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev) 57 { 58 return dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM47162 && 59 dev->bus->chipinfo.rev == 0 && dev->id.id == BCMA_CORE_MIPS_74K; 60 } 61 62 /* The 5357b0 hangs when reading USB20H DMP registers */ 63 static inline bool bcma_core_mips_bcm5357b0_quirk(struct bcma_device *dev) 64 { 65 return (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || 66 dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) && 67 dev->bus->chipinfo.pkg == 11 && 68 dev->id.id == BCMA_CORE_USB20_HOST; 69 } 70 71 static inline u32 mips_read32(struct bcma_drv_mips *mcore, 72 u16 offset) 73 { 74 return bcma_read32(mcore->core, offset); 75 } 76 77 static inline void mips_write32(struct bcma_drv_mips *mcore, 78 u16 offset, 79 u32 value) 80 { 81 bcma_write32(mcore->core, offset, value); 82 } 83 84 static const u32 ipsflag_irq_mask[] = { 85 0, 86 BCMA_MIPS_IPSFLAG_IRQ1, 87 BCMA_MIPS_IPSFLAG_IRQ2, 88 BCMA_MIPS_IPSFLAG_IRQ3, 89 BCMA_MIPS_IPSFLAG_IRQ4, 90 }; 91 92 static const u32 ipsflag_irq_shift[] = { 93 0, 94 BCMA_MIPS_IPSFLAG_IRQ1_SHIFT, 95 BCMA_MIPS_IPSFLAG_IRQ2_SHIFT, 96 BCMA_MIPS_IPSFLAG_IRQ3_SHIFT, 97 BCMA_MIPS_IPSFLAG_IRQ4_SHIFT, 98 }; 99 100 static u32 bcma_core_mips_irqflag(struct bcma_device *dev) 101 { 102 u32 flag; 103 104 if (bcma_core_mips_bcm47162a0_quirk(dev)) 105 return dev->core_index; 106 if (bcma_core_mips_bcm5357b0_quirk(dev)) 107 return dev->core_index; 108 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30); 109 110 if (flag) 111 return flag & 0x1F; 112 else 113 return 0x3f; 114 } 115 116 /* Get the MIPS IRQ assignment for a specified device. 117 * If unassigned, 0 is returned. 118 * If disabled, 5 is returned. 119 * If not supported, 6 is returned. 120 */ 121 static unsigned int bcma_core_mips_irq(struct bcma_device *dev) 122 { 123 struct bcma_device *mdev = dev->bus->drv_mips.core; 124 u32 irqflag; 125 unsigned int irq; 126 127 irqflag = bcma_core_mips_irqflag(dev); 128 if (irqflag == 0x3f) 129 return 6; 130 131 for (irq = 0; irq <= 4; irq++) 132 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) & 133 (1 << irqflag)) 134 return irq; 135 136 return 5; 137 } 138 139 unsigned int bcma_core_irq(struct bcma_device *dev) 140 { 141 unsigned int mips_irq = bcma_core_mips_irq(dev); 142 return mips_irq <= 4 ? mips_irq + 2 : 0; 143 } 144 EXPORT_SYMBOL(bcma_core_irq); 145 146 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq) 147 { 148 unsigned int oldirq = bcma_core_mips_irq(dev); 149 struct bcma_bus *bus = dev->bus; 150 struct bcma_device *mdev = bus->drv_mips.core; 151 u32 irqflag; 152 153 irqflag = bcma_core_mips_irqflag(dev); 154 BUG_ON(oldirq == 6); 155 156 dev->irq = irq + 2; 157 158 /* clear the old irq */ 159 if (oldirq == 0) 160 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), 161 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) & 162 ~(1 << irqflag)); 163 else if (oldirq != 5) 164 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0); 165 166 /* assign the new one */ 167 if (irq == 0) { 168 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0), 169 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) | 170 (1 << irqflag)); 171 } else { 172 u32 irqinitmask = bcma_read32(mdev, 173 BCMA_MIPS_MIPS74K_INTMASK(irq)); 174 if (irqinitmask) { 175 struct bcma_device *core; 176 177 /* backplane irq line is in use, find out who uses 178 * it and set user to irq 0 179 */ 180 list_for_each_entry(core, &bus->cores, list) { 181 if ((1 << bcma_core_mips_irqflag(core)) == 182 irqinitmask) { 183 bcma_core_mips_set_irq(core, 0); 184 break; 185 } 186 } 187 } 188 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq), 189 1 << irqflag); 190 } 191 192 bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n", 193 dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2); 194 } 195 196 static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq, 197 u16 coreid, u8 unit) 198 { 199 struct bcma_device *core; 200 201 core = bcma_find_core_unit(bus, coreid, unit); 202 if (!core) { 203 bcma_warn(bus, 204 "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n", 205 coreid, unit); 206 return; 207 } 208 209 bcma_core_mips_set_irq(core, irq); 210 } 211 212 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq) 213 { 214 int i; 215 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; 216 printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id); 217 for (i = 0; i <= 6; i++) 218 printk(" %s%s", irq_name[i], i == irq ? "*" : " "); 219 printk("\n"); 220 } 221 222 static void bcma_core_mips_dump_irq(struct bcma_bus *bus) 223 { 224 struct bcma_device *core; 225 226 list_for_each_entry(core, &bus->cores, list) { 227 bcma_core_mips_print_irq(core, bcma_core_mips_irq(core)); 228 } 229 } 230 231 u32 bcma_cpu_clock(struct bcma_drv_mips *mcore) 232 { 233 struct bcma_bus *bus = mcore->core->bus; 234 235 if (bus->drv_cc.capabilities & BCMA_CC_CAP_PMU) 236 return bcma_pmu_get_cpu_clock(&bus->drv_cc); 237 238 bcma_err(bus, "No PMU available, need this to get the cpu clock\n"); 239 return 0; 240 } 241 EXPORT_SYMBOL(bcma_cpu_clock); 242 243 static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus) 244 { 245 struct bcma_drv_cc *cc = &bus->drv_cc; 246 u8 cc_rev = cc->core->id.rev; 247 248 if (cc_rev == 42) { 249 struct bcma_device *core; 250 251 core = bcma_find_core(bus, BCMA_CORE_NS_ROM); 252 if (core) { 253 switch (bcma_aread32(core, BCMA_IOST) & 254 BCMA_NS_ROM_IOST_BOOT_DEV_MASK) { 255 case BCMA_NS_ROM_IOST_BOOT_DEV_NOR: 256 return BCMA_BOOT_DEV_SERIAL; 257 case BCMA_NS_ROM_IOST_BOOT_DEV_NAND: 258 return BCMA_BOOT_DEV_NAND; 259 case BCMA_NS_ROM_IOST_BOOT_DEV_ROM: 260 default: 261 return BCMA_BOOT_DEV_ROM; 262 } 263 } 264 } else { 265 if (cc_rev == 38) { 266 if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT) 267 return BCMA_BOOT_DEV_NAND; 268 else if (cc->status & BIT(5)) 269 return BCMA_BOOT_DEV_ROM; 270 } 271 272 if ((cc->capabilities & BCMA_CC_CAP_FLASHT) == 273 BCMA_CC_FLASHT_PARA) 274 return BCMA_BOOT_DEV_PARALLEL; 275 else 276 return BCMA_BOOT_DEV_SERIAL; 277 } 278 279 return BCMA_BOOT_DEV_SERIAL; 280 } 281 282 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore) 283 { 284 struct bcma_bus *bus = mcore->core->bus; 285 struct bcma_drv_cc *cc = &bus->drv_cc; 286 struct bcma_pflash *pflash = &cc->pflash; 287 enum bcma_boot_dev boot_dev; 288 289 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) { 290 case BCMA_CC_FLASHT_STSER: 291 case BCMA_CC_FLASHT_ATSER: 292 bcma_debug(bus, "Found serial flash\n"); 293 bcma_sflash_init(cc); 294 break; 295 case BCMA_CC_FLASHT_PARA: 296 bcma_debug(bus, "Found parallel flash\n"); 297 pflash->present = true; 298 pflash->window = BCMA_SOC_FLASH2; 299 pflash->window_size = BCMA_SOC_FLASH2_SZ; 300 301 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) & 302 BCMA_CC_FLASH_CFG_DS) == 0) 303 pflash->buswidth = 1; 304 else 305 pflash->buswidth = 2; 306 307 bcma_pflash_data.width = pflash->buswidth; 308 bcma_pflash_resource.start = pflash->window; 309 bcma_pflash_resource.end = pflash->window + pflash->window_size; 310 311 break; 312 default: 313 bcma_err(bus, "Flash type not supported\n"); 314 } 315 316 if (cc->core->id.rev == 38 || 317 bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { 318 if (cc->capabilities & BCMA_CC_CAP_NFLASH) { 319 bcma_debug(bus, "Found NAND flash\n"); 320 bcma_nflash_init(cc); 321 } 322 } 323 324 /* Determine flash type this SoC boots from */ 325 boot_dev = bcma_boot_dev(bus); 326 switch (boot_dev) { 327 case BCMA_BOOT_DEV_PARALLEL: 328 case BCMA_BOOT_DEV_SERIAL: 329 #ifdef CONFIG_BCM47XX 330 bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH2, 331 BCMA_SOC_FLASH2_SZ); 332 #endif 333 break; 334 case BCMA_BOOT_DEV_NAND: 335 #ifdef CONFIG_BCM47XX 336 bcm47xx_nvram_init_from_mem(BCMA_SOC_FLASH1, 337 BCMA_SOC_FLASH1_SZ); 338 #endif 339 break; 340 default: 341 break; 342 } 343 } 344 345 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) 346 { 347 struct bcma_bus *bus = mcore->core->bus; 348 349 if (mcore->early_setup_done) 350 return; 351 352 bcma_chipco_serial_init(&bus->drv_cc); 353 bcma_core_mips_flash_detect(mcore); 354 355 mcore->early_setup_done = true; 356 } 357 358 static void bcma_fix_i2s_irqflag(struct bcma_bus *bus) 359 { 360 struct bcma_device *cpu, *pcie, *i2s; 361 362 /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK) 363 * (IRQ flags > 7 are ignored when setting the interrupt masks) 364 */ 365 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 && 366 bus->chipinfo.id != BCMA_CHIP_ID_BCM4748) 367 return; 368 369 cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K); 370 pcie = bcma_find_core(bus, BCMA_CORE_PCIE); 371 i2s = bcma_find_core(bus, BCMA_CORE_I2S); 372 if (cpu && pcie && i2s && 373 bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 && 374 bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 && 375 bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) { 376 bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504); 377 bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504); 378 bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87); 379 bcma_debug(bus, 380 "Moved i2s interrupt to oob line 7 instead of 8\n"); 381 } 382 } 383 384 void bcma_core_mips_init(struct bcma_drv_mips *mcore) 385 { 386 struct bcma_bus *bus; 387 struct bcma_device *core; 388 bus = mcore->core->bus; 389 390 if (mcore->setup_done) 391 return; 392 393 bcma_debug(bus, "Initializing MIPS core...\n"); 394 395 bcma_core_mips_early_init(mcore); 396 397 bcma_fix_i2s_irqflag(bus); 398 399 switch (bus->chipinfo.id) { 400 case BCMA_CHIP_ID_BCM4716: 401 case BCMA_CHIP_ID_BCM4748: 402 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); 403 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); 404 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); 405 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0); 406 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); 407 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); 408 break; 409 case BCMA_CHIP_ID_BCM5356: 410 case BCMA_CHIP_ID_BCM47162: 411 case BCMA_CHIP_ID_BCM53572: 412 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); 413 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); 414 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); 415 break; 416 case BCMA_CHIP_ID_BCM5357: 417 case BCMA_CHIP_ID_BCM4749: 418 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0); 419 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0); 420 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0); 421 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0); 422 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0); 423 break; 424 case BCMA_CHIP_ID_BCM4706: 425 bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0); 426 bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT, 427 0); 428 bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1); 429 bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0); 430 bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON, 431 0); 432 break; 433 default: 434 list_for_each_entry(core, &bus->cores, list) { 435 core->irq = bcma_core_irq(core); 436 } 437 bcma_err(bus, 438 "Unknown device (0x%x) found, can not configure IRQs\n", 439 bus->chipinfo.id); 440 } 441 bcma_debug(bus, "IRQ reconfiguration done\n"); 442 bcma_core_mips_dump_irq(bus); 443 444 mcore->setup_done = true; 445 } 446