1 /* 2 * Broadcom specific AMBA 3 * ChipCommon Power Management Unit driver 4 * 5 * Copyright 2009, Michael Buesch <m@bues.ch> 6 * Copyright 2007, 2011, Broadcom Corporation 7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/export.h> 14 #include <linux/bcma/bcma.h> 15 16 static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset) 17 { 18 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 19 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 20 return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 21 } 22 23 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value) 24 { 25 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 26 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 27 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); 28 } 29 EXPORT_SYMBOL_GPL(bcma_chipco_pll_write); 30 31 void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, 32 u32 set) 33 { 34 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 35 bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR); 36 bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set); 37 } 38 EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset); 39 40 void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc, 41 u32 offset, u32 mask, u32 set) 42 { 43 bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset); 44 bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR); 45 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set); 46 } 47 EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset); 48 49 void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask, 50 u32 set) 51 { 52 bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset); 53 bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR); 54 bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set); 55 } 56 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset); 57 58 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc) 59 { 60 struct bcma_bus *bus = cc->core->bus; 61 u32 min_msk = 0, max_msk = 0; 62 63 switch (bus->chipinfo.id) { 64 case BCMA_CHIP_ID_BCM4313: 65 min_msk = 0x200D; 66 max_msk = 0xFFFF; 67 break; 68 default: 69 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n", 70 bus->chipinfo.id); 71 } 72 73 /* Set the resource masks. */ 74 if (min_msk) 75 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk); 76 if (max_msk) 77 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk); 78 79 /* 80 * Add some delay; allow resources to come up and settle. 81 * Delay is required for SoC (early init). 82 */ 83 mdelay(2); 84 } 85 86 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */ 87 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable) 88 { 89 struct bcma_bus *bus = cc->core->bus; 90 u32 val; 91 92 val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL); 93 if (enable) { 94 val |= BCMA_CHIPCTL_4331_EXTPA_EN; 95 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11) 96 val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; 97 else if (bus->chipinfo.rev > 0) 98 val |= BCMA_CHIPCTL_4331_EXTPA_EN2; 99 } else { 100 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN; 101 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2; 102 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5; 103 } 104 bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val); 105 } 106 107 static void bcma_pmu_workarounds(struct bcma_drv_cc *cc) 108 { 109 struct bcma_bus *bus = cc->core->bus; 110 111 switch (bus->chipinfo.id) { 112 case BCMA_CHIP_ID_BCM4313: 113 /* enable 12 mA drive strenth for 4313 and set chipControl 114 register bit 1 */ 115 bcma_chipco_chipctl_maskset(cc, 0, 116 ~BCMA_CCTRL_4313_12MA_LED_DRIVE, 117 BCMA_CCTRL_4313_12MA_LED_DRIVE); 118 break; 119 case BCMA_CHIP_ID_BCM4331: 120 case BCMA_CHIP_ID_BCM43431: 121 /* Ext PA lines must be enabled for tx on BCM4331 */ 122 bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true); 123 break; 124 case BCMA_CHIP_ID_BCM43224: 125 case BCMA_CHIP_ID_BCM43421: 126 /* enable 12 mA drive strenth for 43224 and set chipControl 127 register bit 15 */ 128 if (bus->chipinfo.rev == 0) { 129 bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL, 130 ~BCMA_CCTRL_43224_GPIO_TOGGLE, 131 BCMA_CCTRL_43224_GPIO_TOGGLE); 132 bcma_chipco_chipctl_maskset(cc, 0, 133 ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE, 134 BCMA_CCTRL_43224A0_12MA_LED_DRIVE); 135 } else { 136 bcma_chipco_chipctl_maskset(cc, 0, 137 ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE, 138 BCMA_CCTRL_43224B0_12MA_LED_DRIVE); 139 } 140 break; 141 default: 142 bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n", 143 bus->chipinfo.id); 144 } 145 } 146 147 void bcma_pmu_early_init(struct bcma_drv_cc *cc) 148 { 149 u32 pmucap; 150 151 pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP); 152 cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION); 153 154 bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n", 155 cc->pmu.rev, pmucap); 156 } 157 158 void bcma_pmu_init(struct bcma_drv_cc *cc) 159 { 160 if (cc->pmu.rev == 1) 161 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL, 162 ~BCMA_CC_PMU_CTL_NOILPONW); 163 else 164 bcma_cc_set32(cc, BCMA_CC_PMU_CTL, 165 BCMA_CC_PMU_CTL_NOILPONW); 166 167 bcma_pmu_resources_init(cc); 168 bcma_pmu_workarounds(cc); 169 } 170 171 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc) 172 { 173 struct bcma_bus *bus = cc->core->bus; 174 175 switch (bus->chipinfo.id) { 176 case BCMA_CHIP_ID_BCM4716: 177 case BCMA_CHIP_ID_BCM4748: 178 case BCMA_CHIP_ID_BCM47162: 179 case BCMA_CHIP_ID_BCM4313: 180 case BCMA_CHIP_ID_BCM5357: 181 case BCMA_CHIP_ID_BCM4749: 182 case BCMA_CHIP_ID_BCM53572: 183 /* always 20Mhz */ 184 return 20000 * 1000; 185 case BCMA_CHIP_ID_BCM5356: 186 case BCMA_CHIP_ID_BCM4706: 187 /* always 25Mhz */ 188 return 25000 * 1000; 189 default: 190 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n", 191 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK); 192 } 193 return BCMA_CC_PMU_ALP_CLOCK; 194 } 195 196 /* Find the output of the "m" pll divider given pll controls that start with 197 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc. 198 */ 199 static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m) 200 { 201 u32 tmp, div, ndiv, p1, p2, fc; 202 struct bcma_bus *bus = cc->core->bus; 203 204 BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0)); 205 206 BUG_ON(!m || m > 4); 207 208 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || 209 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) { 210 /* Detect failure in clock setting */ 211 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 212 if (tmp & 0x40000) 213 return 133 * 1000000; 214 } 215 216 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF); 217 p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT; 218 p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT; 219 220 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF); 221 div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) & 222 BCMA_CC_PPL_MDIV_MASK; 223 224 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF); 225 ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT; 226 227 /* Do calculation in Mhz */ 228 fc = bcma_pmu_get_alp_clock(cc) / 1000000; 229 fc = (p1 * ndiv * fc) / p2; 230 231 /* Return clock in Hertz */ 232 return (fc / div) * 1000000; 233 } 234 235 static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m) 236 { 237 u32 tmp, ndiv, p1div, p2div; 238 u32 clock; 239 240 BUG_ON(!m || m > 4); 241 242 /* Get N, P1 and P2 dividers to determine CPU clock */ 243 tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF); 244 ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK) 245 >> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT; 246 p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK) 247 >> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT; 248 p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK) 249 >> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT; 250 251 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 252 if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION) 253 /* Low cost bonding: Fixed reference clock 25MHz and m = 4 */ 254 clock = (25000000 / 4) * ndiv * p2div / p1div; 255 else 256 /* Fixed reference clock 25MHz and m = 2 */ 257 clock = (25000000 / 2) * ndiv * p2div / p1div; 258 259 if (m == BCMA_CC_PMU5_MAINPLL_SSB) 260 clock = clock / 4; 261 262 return clock; 263 } 264 265 /* query bus clock frequency for PMU-enabled chipcommon */ 266 static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc) 267 { 268 struct bcma_bus *bus = cc->core->bus; 269 270 switch (bus->chipinfo.id) { 271 case BCMA_CHIP_ID_BCM4716: 272 case BCMA_CHIP_ID_BCM4748: 273 case BCMA_CHIP_ID_BCM47162: 274 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0, 275 BCMA_CC_PMU5_MAINPLL_SSB); 276 case BCMA_CHIP_ID_BCM5356: 277 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0, 278 BCMA_CC_PMU5_MAINPLL_SSB); 279 case BCMA_CHIP_ID_BCM5357: 280 case BCMA_CHIP_ID_BCM4749: 281 return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0, 282 BCMA_CC_PMU5_MAINPLL_SSB); 283 case BCMA_CHIP_ID_BCM4706: 284 return bcma_pmu_pll_clock_bcm4706(cc, 285 BCMA_CC_PMU4706_MAINPLL_PLL0, 286 BCMA_CC_PMU5_MAINPLL_SSB); 287 case BCMA_CHIP_ID_BCM53572: 288 return 75000000; 289 default: 290 bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n", 291 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK); 292 } 293 return BCMA_CC_PMU_HT_CLOCK; 294 } 295 296 /* query cpu clock frequency for PMU-enabled chipcommon */ 297 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc) 298 { 299 struct bcma_bus *bus = cc->core->bus; 300 301 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) 302 return 300000000; 303 304 /* New PMUs can have different clock for bus and CPU */ 305 if (cc->pmu.rev >= 5) { 306 u32 pll; 307 switch (bus->chipinfo.id) { 308 case BCMA_CHIP_ID_BCM4706: 309 return bcma_pmu_pll_clock_bcm4706(cc, 310 BCMA_CC_PMU4706_MAINPLL_PLL0, 311 BCMA_CC_PMU5_MAINPLL_CPU); 312 case BCMA_CHIP_ID_BCM5356: 313 pll = BCMA_CC_PMU5356_MAINPLL_PLL0; 314 break; 315 case BCMA_CHIP_ID_BCM5357: 316 case BCMA_CHIP_ID_BCM4749: 317 pll = BCMA_CC_PMU5357_MAINPLL_PLL0; 318 break; 319 default: 320 pll = BCMA_CC_PMU4716_MAINPLL_PLL0; 321 break; 322 } 323 324 return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU); 325 } 326 327 /* On old PMUs CPU has the same clock as the bus */ 328 return bcma_pmu_get_bus_clock(cc); 329 } 330 331 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset, 332 u32 value) 333 { 334 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset); 335 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value); 336 } 337 338 void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid) 339 { 340 u32 tmp = 0; 341 u8 phypll_offset = 0; 342 u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5}; 343 u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc}; 344 struct bcma_bus *bus = cc->core->bus; 345 346 switch (bus->chipinfo.id) { 347 case BCMA_CHIP_ID_BCM5357: 348 case BCMA_CHIP_ID_BCM4749: 349 case BCMA_CHIP_ID_BCM53572: 350 /* 5357[ab]0, 43236[ab]0, and 6362b0 */ 351 352 /* BCM5357 needs to touch PLL1_PLLCTL[02], 353 so offset PLL0_PLLCTL[02] by 6 */ 354 phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 || 355 bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 || 356 bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0; 357 358 /* RMW only the P1 divider */ 359 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, 360 BCMA_CC_PMU_PLL_CTL0 + phypll_offset); 361 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 362 tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK)); 363 tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT); 364 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); 365 366 /* RMW only the int feedback divider */ 367 bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, 368 BCMA_CC_PMU_PLL_CTL2 + phypll_offset); 369 tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA); 370 tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK); 371 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT; 372 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp); 373 374 tmp = 1 << 10; 375 break; 376 377 case BCMA_CHIP_ID_BCM4331: 378 case BCMA_CHIP_ID_BCM43431: 379 if (spuravoid == 2) { 380 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 381 0x11500014); 382 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 383 0x0FC00a08); 384 } else if (spuravoid == 1) { 385 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 386 0x11500014); 387 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 388 0x0F600a08); 389 } else { 390 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 391 0x11100014); 392 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 393 0x03000a08); 394 } 395 tmp = 1 << 10; 396 break; 397 398 case BCMA_CHIP_ID_BCM43224: 399 case BCMA_CHIP_ID_BCM43225: 400 case BCMA_CHIP_ID_BCM43421: 401 if (spuravoid == 1) { 402 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 403 0x11500010); 404 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 405 0x000C0C06); 406 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 407 0x0F600a08); 408 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 409 0x00000000); 410 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 411 0x2001E920); 412 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 413 0x88888815); 414 } else { 415 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 416 0x11100010); 417 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 418 0x000c0c06); 419 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 420 0x03000a08); 421 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 422 0x00000000); 423 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 424 0x200005c0); 425 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 426 0x88888815); 427 } 428 tmp = 1 << 10; 429 break; 430 431 case BCMA_CHIP_ID_BCM4716: 432 case BCMA_CHIP_ID_BCM4748: 433 case BCMA_CHIP_ID_BCM47162: 434 if (spuravoid == 1) { 435 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 436 0x11500060); 437 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 438 0x080C0C06); 439 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 440 0x0F600000); 441 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 442 0x00000000); 443 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 444 0x2001E924); 445 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 446 0x88888815); 447 } else { 448 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 449 0x11100060); 450 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 451 0x080c0c06); 452 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 453 0x03000000); 454 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 455 0x00000000); 456 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 457 0x200005c0); 458 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 459 0x88888815); 460 } 461 462 tmp = 3 << 9; 463 break; 464 465 case BCMA_CHIP_ID_BCM43227: 466 case BCMA_CHIP_ID_BCM43228: 467 case BCMA_CHIP_ID_BCM43428: 468 /* LCNXN */ 469 /* PLL Settings for spur avoidance on/off mode, 470 no on2 support for 43228A0 */ 471 if (spuravoid == 1) { 472 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 473 0x01100014); 474 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 475 0x040C0C06); 476 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 477 0x03140A08); 478 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 479 0x00333333); 480 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 481 0x202C2820); 482 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 483 0x88888815); 484 } else { 485 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0, 486 0x11100014); 487 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1, 488 0x040c0c06); 489 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2, 490 0x03000a08); 491 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3, 492 0x00000000); 493 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4, 494 0x200005c0); 495 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5, 496 0x88888815); 497 } 498 tmp = 1 << 10; 499 break; 500 default: 501 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n", 502 bus->chipinfo.id); 503 break; 504 } 505 506 tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL); 507 bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp); 508 } 509 EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate); 510