1 /* 2 * Broadcom specific AMBA 3 * ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/bcm47xx_wdt.h> 14 #include <linux/export.h> 15 #include <linux/platform_device.h> 16 #include <linux/bcma/bcma.h> 17 18 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, 19 u32 mask, u32 value) 20 { 21 value &= mask; 22 value |= bcma_cc_read32(cc, offset) & ~mask; 23 bcma_cc_write32(cc, offset, value); 24 25 return value; 26 } 27 28 u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) 29 { 30 if (cc->capabilities & BCMA_CC_CAP_PMU) 31 return bcma_pmu_get_alp_clock(cc); 32 33 return 20000000; 34 } 35 EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); 36 37 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) 38 { 39 struct bcma_bus *bus = cc->core->bus; 40 u32 nb; 41 42 if (cc->capabilities & BCMA_CC_CAP_PMU) { 43 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 44 nb = 32; 45 else if (cc->core->id.rev < 26) 46 nb = 16; 47 else 48 nb = (cc->core->id.rev >= 37) ? 32 : 24; 49 } else { 50 nb = 28; 51 } 52 if (nb == 32) 53 return 0xffffffff; 54 else 55 return (1 << nb) - 1; 56 } 57 58 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, 59 u32 ticks) 60 { 61 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 62 63 return bcma_chipco_watchdog_timer_set(cc, ticks); 64 } 65 66 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, 67 u32 ms) 68 { 69 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 70 u32 ticks; 71 72 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); 73 return ticks / cc->ticks_per_ms; 74 } 75 76 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) 77 { 78 struct bcma_bus *bus = cc->core->bus; 79 80 if (cc->capabilities & BCMA_CC_CAP_PMU) { 81 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 82 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP 83 * clock 84 */ 85 return bcma_chipco_get_alp_clock(cc) / 4000; 86 else 87 /* based on 32KHz ILP clock */ 88 return 32; 89 } else { 90 return bcma_chipco_get_alp_clock(cc) / 1000; 91 } 92 } 93 94 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 95 { 96 struct bcm47xx_wdt wdt = {}; 97 struct platform_device *pdev; 98 99 wdt.driver_data = cc; 100 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; 101 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; 102 wdt.max_timer_ms = 103 bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; 104 105 pdev = platform_device_register_data(NULL, "bcm47xx-wdt", 106 cc->core->bus->num, &wdt, 107 sizeof(wdt)); 108 if (IS_ERR(pdev)) 109 return PTR_ERR(pdev); 110 111 cc->watchdog = pdev; 112 113 return 0; 114 } 115 116 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 117 { 118 if (cc->early_setup_done) 119 return; 120 121 spin_lock_init(&cc->gpio_lock); 122 123 if (cc->core->id.rev >= 11) 124 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 125 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); 126 if (cc->core->id.rev >= 35) 127 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); 128 129 if (cc->capabilities & BCMA_CC_CAP_PMU) 130 bcma_pmu_early_init(cc); 131 132 cc->early_setup_done = true; 133 } 134 135 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) 136 { 137 u32 leddc_on = 10; 138 u32 leddc_off = 90; 139 140 if (cc->setup_done) 141 return; 142 143 bcma_core_chipcommon_early_init(cc); 144 145 if (cc->core->id.rev >= 20) { 146 u32 pullup = 0, pulldown = 0; 147 148 if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) { 149 pullup = 0x402e0; 150 pulldown = 0x20500; 151 } 152 153 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup); 154 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown); 155 } 156 157 if (cc->capabilities & BCMA_CC_CAP_PMU) 158 bcma_pmu_init(cc); 159 if (cc->capabilities & BCMA_CC_CAP_PCTL) 160 bcma_err(cc->core->bus, "Power control not implemented!\n"); 161 162 if (cc->core->id.rev >= 16) { 163 if (cc->core->bus->sprom.leddc_on_time && 164 cc->core->bus->sprom.leddc_off_time) { 165 leddc_on = cc->core->bus->sprom.leddc_on_time; 166 leddc_off = cc->core->bus->sprom.leddc_off_time; 167 } 168 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, 169 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | 170 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); 171 } 172 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); 173 174 cc->setup_done = true; 175 } 176 177 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 178 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 179 { 180 u32 maxt; 181 182 maxt = bcma_chipco_watchdog_get_max_timer(cc); 183 if (cc->capabilities & BCMA_CC_CAP_PMU) { 184 if (ticks == 1) 185 ticks = 2; 186 else if (ticks > maxt) 187 ticks = maxt; 188 bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); 189 } else { 190 struct bcma_bus *bus = cc->core->bus; 191 192 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 && 193 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018) 194 bcma_core_set_clockmode(cc->core, 195 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC); 196 197 if (ticks > maxt) 198 ticks = maxt; 199 /* instant NMI */ 200 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); 201 } 202 return ticks; 203 } 204 205 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) 206 { 207 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); 208 } 209 210 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) 211 { 212 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; 213 } 214 215 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) 216 { 217 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; 218 } 219 220 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) 221 { 222 unsigned long flags; 223 u32 res; 224 225 spin_lock_irqsave(&cc->gpio_lock, flags); 226 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); 227 spin_unlock_irqrestore(&cc->gpio_lock, flags); 228 229 return res; 230 } 231 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); 232 233 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) 234 { 235 unsigned long flags; 236 u32 res; 237 238 spin_lock_irqsave(&cc->gpio_lock, flags); 239 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); 240 spin_unlock_irqrestore(&cc->gpio_lock, flags); 241 242 return res; 243 } 244 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); 245 246 /* 247 * If the bit is set to 0, chipcommon controlls this GPIO, 248 * if the bit is set to 1, it is used by some part of the chip and not our code. 249 */ 250 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) 251 { 252 unsigned long flags; 253 u32 res; 254 255 spin_lock_irqsave(&cc->gpio_lock, flags); 256 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); 257 spin_unlock_irqrestore(&cc->gpio_lock, flags); 258 259 return res; 260 } 261 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); 262 263 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) 264 { 265 unsigned long flags; 266 u32 res; 267 268 spin_lock_irqsave(&cc->gpio_lock, flags); 269 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); 270 spin_unlock_irqrestore(&cc->gpio_lock, flags); 271 272 return res; 273 } 274 275 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) 276 { 277 unsigned long flags; 278 u32 res; 279 280 spin_lock_irqsave(&cc->gpio_lock, flags); 281 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); 282 spin_unlock_irqrestore(&cc->gpio_lock, flags); 283 284 return res; 285 } 286 287 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) 288 { 289 unsigned long flags; 290 u32 res; 291 292 if (cc->core->id.rev < 20) 293 return 0; 294 295 spin_lock_irqsave(&cc->gpio_lock, flags); 296 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); 297 spin_unlock_irqrestore(&cc->gpio_lock, flags); 298 299 return res; 300 } 301 302 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) 303 { 304 unsigned long flags; 305 u32 res; 306 307 if (cc->core->id.rev < 20) 308 return 0; 309 310 spin_lock_irqsave(&cc->gpio_lock, flags); 311 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); 312 spin_unlock_irqrestore(&cc->gpio_lock, flags); 313 314 return res; 315 } 316 317 #ifdef CONFIG_BCMA_DRIVER_MIPS 318 void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 319 { 320 unsigned int irq; 321 u32 baud_base; 322 u32 i; 323 unsigned int ccrev = cc->core->id.rev; 324 struct bcma_serial_port *ports = cc->serial_ports; 325 326 if (ccrev >= 11 && ccrev != 15) { 327 baud_base = bcma_chipco_get_alp_clock(cc); 328 if (ccrev >= 21) { 329 /* Turn off UART clock before switching clocksource. */ 330 bcma_cc_write32(cc, BCMA_CC_CORECTL, 331 bcma_cc_read32(cc, BCMA_CC_CORECTL) 332 & ~BCMA_CC_CORECTL_UARTCLKEN); 333 } 334 /* Set the override bit so we don't divide it */ 335 bcma_cc_write32(cc, BCMA_CC_CORECTL, 336 bcma_cc_read32(cc, BCMA_CC_CORECTL) 337 | BCMA_CC_CORECTL_UARTCLK0); 338 if (ccrev >= 21) { 339 /* Re-enable the UART clock. */ 340 bcma_cc_write32(cc, BCMA_CC_CORECTL, 341 bcma_cc_read32(cc, BCMA_CC_CORECTL) 342 | BCMA_CC_CORECTL_UARTCLKEN); 343 } 344 } else { 345 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", 346 ccrev); 347 return; 348 } 349 350 irq = bcma_core_irq(cc->core, 0); 351 352 /* Determine the registers of the UARTs */ 353 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); 354 for (i = 0; i < cc->nr_serial_ports; i++) { 355 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + 356 (i * 256); 357 ports[i].irq = irq; 358 ports[i].baud_base = baud_base; 359 ports[i].reg_shift = 0; 360 } 361 } 362 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 363