1 /* 2 * Broadcom specific AMBA 3 * ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/bcm47xx_wdt.h> 14 #include <linux/export.h> 15 #include <linux/platform_device.h> 16 #include <linux/bcma/bcma.h> 17 18 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, 19 u32 mask, u32 value) 20 { 21 value &= mask; 22 value |= bcma_cc_read32(cc, offset) & ~mask; 23 bcma_cc_write32(cc, offset, value); 24 25 return value; 26 } 27 28 static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) 29 { 30 if (cc->capabilities & BCMA_CC_CAP_PMU) 31 return bcma_pmu_get_alp_clock(cc); 32 33 return 20000000; 34 } 35 36 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) 37 { 38 struct bcma_bus *bus = cc->core->bus; 39 u32 nb; 40 41 if (cc->capabilities & BCMA_CC_CAP_PMU) { 42 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 43 nb = 32; 44 else if (cc->core->id.rev < 26) 45 nb = 16; 46 else 47 nb = (cc->core->id.rev >= 37) ? 32 : 24; 48 } else { 49 nb = 28; 50 } 51 if (nb == 32) 52 return 0xffffffff; 53 else 54 return (1 << nb) - 1; 55 } 56 57 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, 58 u32 ticks) 59 { 60 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 61 62 return bcma_chipco_watchdog_timer_set(cc, ticks); 63 } 64 65 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, 66 u32 ms) 67 { 68 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 69 u32 ticks; 70 71 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); 72 return ticks / cc->ticks_per_ms; 73 } 74 75 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) 76 { 77 struct bcma_bus *bus = cc->core->bus; 78 79 if (cc->capabilities & BCMA_CC_CAP_PMU) { 80 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 81 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP clock */ 82 return bcma_chipco_get_alp_clock(cc) / 4000; 83 else 84 /* based on 32KHz ILP clock */ 85 return 32; 86 } else { 87 return bcma_chipco_get_alp_clock(cc) / 1000; 88 } 89 } 90 91 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 92 { 93 struct bcm47xx_wdt wdt = {}; 94 struct platform_device *pdev; 95 96 wdt.driver_data = cc; 97 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; 98 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; 99 wdt.max_timer_ms = bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; 100 101 pdev = platform_device_register_data(NULL, "bcm47xx-wdt", 102 cc->core->bus->num, &wdt, 103 sizeof(wdt)); 104 if (IS_ERR(pdev)) 105 return PTR_ERR(pdev); 106 107 cc->watchdog = pdev; 108 109 return 0; 110 } 111 112 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 113 { 114 if (cc->early_setup_done) 115 return; 116 117 if (cc->core->id.rev >= 11) 118 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 119 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); 120 if (cc->core->id.rev >= 35) 121 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); 122 123 if (cc->capabilities & BCMA_CC_CAP_PMU) 124 bcma_pmu_early_init(cc); 125 126 cc->early_setup_done = true; 127 } 128 129 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) 130 { 131 u32 leddc_on = 10; 132 u32 leddc_off = 90; 133 134 if (cc->setup_done) 135 return; 136 137 bcma_core_chipcommon_early_init(cc); 138 139 if (cc->core->id.rev >= 20) { 140 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0); 141 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0); 142 } 143 144 if (cc->capabilities & BCMA_CC_CAP_PMU) 145 bcma_pmu_init(cc); 146 if (cc->capabilities & BCMA_CC_CAP_PCTL) 147 bcma_err(cc->core->bus, "Power control not implemented!\n"); 148 149 if (cc->core->id.rev >= 16) { 150 if (cc->core->bus->sprom.leddc_on_time && 151 cc->core->bus->sprom.leddc_off_time) { 152 leddc_on = cc->core->bus->sprom.leddc_on_time; 153 leddc_off = cc->core->bus->sprom.leddc_off_time; 154 } 155 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, 156 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | 157 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); 158 } 159 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); 160 161 cc->setup_done = true; 162 } 163 164 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 165 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 166 { 167 u32 maxt; 168 enum bcma_clkmode clkmode; 169 170 maxt = bcma_chipco_watchdog_get_max_timer(cc); 171 if (cc->capabilities & BCMA_CC_CAP_PMU) { 172 if (ticks == 1) 173 ticks = 2; 174 else if (ticks > maxt) 175 ticks = maxt; 176 bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); 177 } else { 178 clkmode = ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC; 179 bcma_core_set_clockmode(cc->core, clkmode); 180 if (ticks > maxt) 181 ticks = maxt; 182 /* instant NMI */ 183 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); 184 } 185 return ticks; 186 } 187 188 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) 189 { 190 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); 191 } 192 193 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) 194 { 195 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; 196 } 197 198 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) 199 { 200 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; 201 } 202 203 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) 204 { 205 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); 206 } 207 208 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) 209 { 210 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); 211 } 212 213 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) 214 { 215 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); 216 } 217 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); 218 219 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) 220 { 221 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); 222 } 223 224 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) 225 { 226 return bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); 227 } 228 229 #ifdef CONFIG_BCMA_DRIVER_MIPS 230 void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 231 { 232 unsigned int irq; 233 u32 baud_base; 234 u32 i; 235 unsigned int ccrev = cc->core->id.rev; 236 struct bcma_serial_port *ports = cc->serial_ports; 237 238 if (ccrev >= 11 && ccrev != 15) { 239 baud_base = bcma_chipco_get_alp_clock(cc); 240 if (ccrev >= 21) { 241 /* Turn off UART clock before switching clocksource. */ 242 bcma_cc_write32(cc, BCMA_CC_CORECTL, 243 bcma_cc_read32(cc, BCMA_CC_CORECTL) 244 & ~BCMA_CC_CORECTL_UARTCLKEN); 245 } 246 /* Set the override bit so we don't divide it */ 247 bcma_cc_write32(cc, BCMA_CC_CORECTL, 248 bcma_cc_read32(cc, BCMA_CC_CORECTL) 249 | BCMA_CC_CORECTL_UARTCLK0); 250 if (ccrev >= 21) { 251 /* Re-enable the UART clock. */ 252 bcma_cc_write32(cc, BCMA_CC_CORECTL, 253 bcma_cc_read32(cc, BCMA_CC_CORECTL) 254 | BCMA_CC_CORECTL_UARTCLKEN); 255 } 256 } else { 257 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", ccrev); 258 return; 259 } 260 261 irq = bcma_core_mips_irq(cc->core); 262 263 /* Determine the registers of the UARTs */ 264 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); 265 for (i = 0; i < cc->nr_serial_ports; i++) { 266 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + 267 (i * 256); 268 ports[i].irq = irq; 269 ports[i].baud_base = baud_base; 270 ports[i].reg_shift = 0; 271 } 272 } 273 #endif /* CONFIG_BCMA_DRIVER_MIPS */ 274