1 /* 2 * Broadcom specific AMBA 3 * ChipCommon core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * Licensed under the GNU/GPL. See COPYING for details. 10 */ 11 12 #include "bcma_private.h" 13 #include <linux/bcm47xx_wdt.h> 14 #include <linux/export.h> 15 #include <linux/platform_device.h> 16 #include <linux/bcma/bcma.h> 17 18 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc); 19 20 static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset, 21 u32 mask, u32 value) 22 { 23 value &= mask; 24 value |= bcma_cc_read32(cc, offset) & ~mask; 25 bcma_cc_write32(cc, offset, value); 26 27 return value; 28 } 29 30 u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc) 31 { 32 if (cc->capabilities & BCMA_CC_CAP_PMU) 33 return bcma_pmu_get_alp_clock(cc); 34 35 return 20000000; 36 } 37 EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock); 38 39 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc) 40 { 41 struct bcma_bus *bus = cc->core->bus; 42 u32 nb; 43 44 if (cc->capabilities & BCMA_CC_CAP_PMU) { 45 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 46 nb = 32; 47 else if (cc->core->id.rev < 26) 48 nb = 16; 49 else 50 nb = (cc->core->id.rev >= 37) ? 32 : 24; 51 } else { 52 nb = 28; 53 } 54 if (nb == 32) 55 return 0xffffffff; 56 else 57 return (1 << nb) - 1; 58 } 59 60 static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, 61 u32 ticks) 62 { 63 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 64 65 return bcma_chipco_watchdog_timer_set(cc, ticks); 66 } 67 68 static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt, 69 u32 ms) 70 { 71 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt); 72 u32 ticks; 73 74 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms); 75 return ticks / cc->ticks_per_ms; 76 } 77 78 static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc) 79 { 80 struct bcma_bus *bus = cc->core->bus; 81 82 if (cc->capabilities & BCMA_CC_CAP_PMU) { 83 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) 84 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP 85 * clock 86 */ 87 return bcma_chipco_get_alp_clock(cc) / 4000; 88 else 89 /* based on 32KHz ILP clock */ 90 return 32; 91 } else { 92 return bcma_chipco_get_alp_clock(cc) / 1000; 93 } 94 } 95 96 int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc) 97 { 98 struct bcm47xx_wdt wdt = {}; 99 struct platform_device *pdev; 100 101 wdt.driver_data = cc; 102 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt; 103 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt; 104 wdt.max_timer_ms = 105 bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms; 106 107 pdev = platform_device_register_data(NULL, "bcm47xx-wdt", 108 cc->core->bus->num, &wdt, 109 sizeof(wdt)); 110 if (IS_ERR(pdev)) 111 return PTR_ERR(pdev); 112 113 cc->watchdog = pdev; 114 115 return 0; 116 } 117 118 void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc) 119 { 120 struct bcma_bus *bus = cc->core->bus; 121 122 if (cc->early_setup_done) 123 return; 124 125 spin_lock_init(&cc->gpio_lock); 126 127 if (cc->core->id.rev >= 11) 128 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT); 129 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP); 130 if (cc->core->id.rev >= 35) 131 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT); 132 133 if (cc->capabilities & BCMA_CC_CAP_PMU) 134 bcma_pmu_early_init(cc); 135 136 if (IS_BUILTIN(CONFIG_BCM47XX) && bus->hosttype == BCMA_HOSTTYPE_SOC) 137 bcma_chipco_serial_init(cc); 138 139 cc->early_setup_done = true; 140 } 141 142 void bcma_core_chipcommon_init(struct bcma_drv_cc *cc) 143 { 144 u32 leddc_on = 10; 145 u32 leddc_off = 90; 146 147 if (cc->setup_done) 148 return; 149 150 bcma_core_chipcommon_early_init(cc); 151 152 if (cc->core->id.rev >= 20) { 153 u32 pullup = 0, pulldown = 0; 154 155 if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) { 156 pullup = 0x402e0; 157 pulldown = 0x20500; 158 } 159 160 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup); 161 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown); 162 } 163 164 if (cc->capabilities & BCMA_CC_CAP_PMU) 165 bcma_pmu_init(cc); 166 if (cc->capabilities & BCMA_CC_CAP_PCTL) 167 bcma_err(cc->core->bus, "Power control not implemented!\n"); 168 169 if (cc->core->id.rev >= 16) { 170 if (cc->core->bus->sprom.leddc_on_time && 171 cc->core->bus->sprom.leddc_off_time) { 172 leddc_on = cc->core->bus->sprom.leddc_on_time; 173 leddc_off = cc->core->bus->sprom.leddc_off_time; 174 } 175 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER, 176 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) | 177 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT))); 178 } 179 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc); 180 181 cc->setup_done = true; 182 } 183 184 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */ 185 u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks) 186 { 187 u32 maxt; 188 189 maxt = bcma_chipco_watchdog_get_max_timer(cc); 190 if (cc->capabilities & BCMA_CC_CAP_PMU) { 191 if (ticks == 1) 192 ticks = 2; 193 else if (ticks > maxt) 194 ticks = maxt; 195 bcma_pmu_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks); 196 } else { 197 struct bcma_bus *bus = cc->core->bus; 198 199 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 && 200 bus->chipinfo.id != BCMA_CHIP_ID_BCM47094 && 201 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018) 202 bcma_core_set_clockmode(cc->core, 203 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC); 204 205 if (ticks > maxt) 206 ticks = maxt; 207 /* instant NMI */ 208 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks); 209 } 210 return ticks; 211 } 212 213 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value) 214 { 215 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value); 216 } 217 218 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask) 219 { 220 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask; 221 } 222 223 u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask) 224 { 225 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask; 226 } 227 228 u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value) 229 { 230 unsigned long flags; 231 u32 res; 232 233 spin_lock_irqsave(&cc->gpio_lock, flags); 234 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value); 235 spin_unlock_irqrestore(&cc->gpio_lock, flags); 236 237 return res; 238 } 239 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out); 240 241 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value) 242 { 243 unsigned long flags; 244 u32 res; 245 246 spin_lock_irqsave(&cc->gpio_lock, flags); 247 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value); 248 spin_unlock_irqrestore(&cc->gpio_lock, flags); 249 250 return res; 251 } 252 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen); 253 254 /* 255 * If the bit is set to 0, chipcommon controlls this GPIO, 256 * if the bit is set to 1, it is used by some part of the chip and not our code. 257 */ 258 u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value) 259 { 260 unsigned long flags; 261 u32 res; 262 263 spin_lock_irqsave(&cc->gpio_lock, flags); 264 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value); 265 spin_unlock_irqrestore(&cc->gpio_lock, flags); 266 267 return res; 268 } 269 EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control); 270 271 u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value) 272 { 273 unsigned long flags; 274 u32 res; 275 276 spin_lock_irqsave(&cc->gpio_lock, flags); 277 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value); 278 spin_unlock_irqrestore(&cc->gpio_lock, flags); 279 280 return res; 281 } 282 283 u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value) 284 { 285 unsigned long flags; 286 u32 res; 287 288 spin_lock_irqsave(&cc->gpio_lock, flags); 289 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value); 290 spin_unlock_irqrestore(&cc->gpio_lock, flags); 291 292 return res; 293 } 294 295 u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value) 296 { 297 unsigned long flags; 298 u32 res; 299 300 if (cc->core->id.rev < 20) 301 return 0; 302 303 spin_lock_irqsave(&cc->gpio_lock, flags); 304 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value); 305 spin_unlock_irqrestore(&cc->gpio_lock, flags); 306 307 return res; 308 } 309 310 u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value) 311 { 312 unsigned long flags; 313 u32 res; 314 315 if (cc->core->id.rev < 20) 316 return 0; 317 318 spin_lock_irqsave(&cc->gpio_lock, flags); 319 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value); 320 spin_unlock_irqrestore(&cc->gpio_lock, flags); 321 322 return res; 323 } 324 325 static void bcma_chipco_serial_init(struct bcma_drv_cc *cc) 326 { 327 #if IS_BUILTIN(CONFIG_BCM47XX) 328 unsigned int irq; 329 u32 baud_base; 330 u32 i; 331 unsigned int ccrev = cc->core->id.rev; 332 struct bcma_serial_port *ports = cc->serial_ports; 333 334 if (ccrev >= 11 && ccrev != 15) { 335 baud_base = bcma_chipco_get_alp_clock(cc); 336 if (ccrev >= 21) { 337 /* Turn off UART clock before switching clocksource. */ 338 bcma_cc_write32(cc, BCMA_CC_CORECTL, 339 bcma_cc_read32(cc, BCMA_CC_CORECTL) 340 & ~BCMA_CC_CORECTL_UARTCLKEN); 341 } 342 /* Set the override bit so we don't divide it */ 343 bcma_cc_write32(cc, BCMA_CC_CORECTL, 344 bcma_cc_read32(cc, BCMA_CC_CORECTL) 345 | BCMA_CC_CORECTL_UARTCLK0); 346 if (ccrev >= 21) { 347 /* Re-enable the UART clock. */ 348 bcma_cc_write32(cc, BCMA_CC_CORECTL, 349 bcma_cc_read32(cc, BCMA_CC_CORECTL) 350 | BCMA_CC_CORECTL_UARTCLKEN); 351 } 352 } else { 353 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n", 354 ccrev); 355 return; 356 } 357 358 irq = bcma_core_irq(cc->core, 0); 359 360 /* Determine the registers of the UARTs */ 361 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART); 362 for (i = 0; i < cc->nr_serial_ports; i++) { 363 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA + 364 (i * 256); 365 ports[i].irq = irq; 366 ports[i].baud_base = baud_base; 367 ports[i].reg_shift = 0; 368 } 369 #endif /* CONFIG_BCM47XX */ 370 } 371