1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // regmap based irq_chip 4 // 5 // Copyright 2011 Wolfson Microelectronics plc 6 // 7 // Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 8 9 #include <linux/device.h> 10 #include <linux/export.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/slab.h> 17 18 #include "internal.h" 19 20 struct regmap_irq_chip_data { 21 struct mutex lock; 22 struct irq_chip irq_chip; 23 24 struct regmap *map; 25 const struct regmap_irq_chip *chip; 26 27 int irq_base; 28 struct irq_domain *domain; 29 30 int irq; 31 int wake_count; 32 33 unsigned int mask_base; 34 unsigned int unmask_base; 35 36 void *status_reg_buf; 37 unsigned int *main_status_buf; 38 unsigned int *status_buf; 39 unsigned int *mask_buf; 40 unsigned int *mask_buf_def; 41 unsigned int *wake_buf; 42 unsigned int *type_buf; 43 unsigned int *type_buf_def; 44 unsigned int **virt_buf; 45 unsigned int **config_buf; 46 47 unsigned int irq_reg_stride; 48 49 unsigned int (*get_irq_reg)(struct regmap_irq_chip_data *data, 50 unsigned int base, int index); 51 52 unsigned int clear_status:1; 53 }; 54 55 static inline const 56 struct regmap_irq *irq_to_regmap_irq(struct regmap_irq_chip_data *data, 57 int irq) 58 { 59 return &data->chip->irqs[irq]; 60 } 61 62 static bool regmap_irq_can_bulk_read_status(struct regmap_irq_chip_data *data) 63 { 64 struct regmap *map = data->map; 65 66 /* 67 * While possible that a user-defined ->get_irq_reg() callback might 68 * be linear enough to support bulk reads, most of the time it won't. 69 * Therefore only allow them if the default callback is being used. 70 */ 71 return data->irq_reg_stride == 1 && map->reg_stride == 1 && 72 data->get_irq_reg == regmap_irq_get_irq_reg_linear && 73 !map->use_single_read; 74 } 75 76 static void regmap_irq_lock(struct irq_data *data) 77 { 78 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 79 80 mutex_lock(&d->lock); 81 } 82 83 static void regmap_irq_sync_unlock(struct irq_data *data) 84 { 85 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 86 struct regmap *map = d->map; 87 int i, j, ret; 88 u32 reg; 89 u32 val; 90 91 if (d->chip->runtime_pm) { 92 ret = pm_runtime_get_sync(map->dev); 93 if (ret < 0) 94 dev_err(map->dev, "IRQ sync failed to resume: %d\n", 95 ret); 96 } 97 98 if (d->clear_status) { 99 for (i = 0; i < d->chip->num_regs; i++) { 100 reg = d->get_irq_reg(d, d->chip->status_base, i); 101 102 ret = regmap_read(map, reg, &val); 103 if (ret) 104 dev_err(d->map->dev, 105 "Failed to clear the interrupt status bits\n"); 106 } 107 108 d->clear_status = false; 109 } 110 111 /* 112 * If there's been a change in the mask write it back to the 113 * hardware. We rely on the use of the regmap core cache to 114 * suppress pointless writes. 115 */ 116 for (i = 0; i < d->chip->num_regs; i++) { 117 if (d->mask_base) { 118 if (d->chip->handle_mask_sync) 119 d->chip->handle_mask_sync(d->map, i, 120 d->mask_buf_def[i], 121 d->mask_buf[i], 122 d->chip->irq_drv_data); 123 else { 124 reg = d->get_irq_reg(d, d->mask_base, i); 125 ret = regmap_update_bits(d->map, reg, 126 d->mask_buf_def[i], 127 d->mask_buf[i]); 128 if (ret) 129 dev_err(d->map->dev, "Failed to sync masks in %x\n", 130 reg); 131 } 132 } 133 134 if (d->unmask_base) { 135 reg = d->get_irq_reg(d, d->unmask_base, i); 136 ret = regmap_update_bits(d->map, reg, 137 d->mask_buf_def[i], ~d->mask_buf[i]); 138 if (ret) 139 dev_err(d->map->dev, "Failed to sync masks in %x\n", 140 reg); 141 } 142 143 reg = d->get_irq_reg(d, d->chip->wake_base, i); 144 if (d->wake_buf) { 145 if (d->chip->wake_invert) 146 ret = regmap_update_bits(d->map, reg, 147 d->mask_buf_def[i], 148 ~d->wake_buf[i]); 149 else 150 ret = regmap_update_bits(d->map, reg, 151 d->mask_buf_def[i], 152 d->wake_buf[i]); 153 if (ret != 0) 154 dev_err(d->map->dev, 155 "Failed to sync wakes in %x: %d\n", 156 reg, ret); 157 } 158 159 if (!d->chip->init_ack_masked) 160 continue; 161 /* 162 * Ack all the masked interrupts unconditionally, 163 * OR if there is masked interrupt which hasn't been Acked, 164 * it'll be ignored in irq handler, then may introduce irq storm 165 */ 166 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { 167 reg = d->get_irq_reg(d, d->chip->ack_base, i); 168 169 /* some chips ack by write 0 */ 170 if (d->chip->ack_invert) 171 ret = regmap_write(map, reg, ~d->mask_buf[i]); 172 else 173 ret = regmap_write(map, reg, d->mask_buf[i]); 174 if (d->chip->clear_ack) { 175 if (d->chip->ack_invert && !ret) 176 ret = regmap_write(map, reg, UINT_MAX); 177 else if (!ret) 178 ret = regmap_write(map, reg, 0); 179 } 180 if (ret != 0) 181 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", 182 reg, ret); 183 } 184 } 185 186 /* Don't update the type bits if we're using mask bits for irq type. */ 187 if (!d->chip->type_in_mask) { 188 for (i = 0; i < d->chip->num_type_reg; i++) { 189 if (!d->type_buf_def[i]) 190 continue; 191 reg = d->get_irq_reg(d, d->chip->type_base, i); 192 if (d->chip->type_invert) 193 ret = regmap_update_bits(d->map, reg, 194 d->type_buf_def[i], ~d->type_buf[i]); 195 else 196 ret = regmap_update_bits(d->map, reg, 197 d->type_buf_def[i], d->type_buf[i]); 198 if (ret != 0) 199 dev_err(d->map->dev, "Failed to sync type in %x\n", 200 reg); 201 } 202 } 203 204 if (d->chip->num_virt_regs) { 205 for (i = 0; i < d->chip->num_virt_regs; i++) { 206 for (j = 0; j < d->chip->num_regs; j++) { 207 reg = d->get_irq_reg(d, d->chip->virt_reg_base[i], 208 j); 209 ret = regmap_write(map, reg, d->virt_buf[i][j]); 210 if (ret != 0) 211 dev_err(d->map->dev, 212 "Failed to write virt 0x%x: %d\n", 213 reg, ret); 214 } 215 } 216 } 217 218 for (i = 0; i < d->chip->num_config_bases; i++) { 219 for (j = 0; j < d->chip->num_config_regs; j++) { 220 reg = d->get_irq_reg(d, d->chip->config_base[i], j); 221 ret = regmap_write(map, reg, d->config_buf[i][j]); 222 if (ret) 223 dev_err(d->map->dev, 224 "Failed to write config %x: %d\n", 225 reg, ret); 226 } 227 } 228 229 if (d->chip->runtime_pm) 230 pm_runtime_put(map->dev); 231 232 /* If we've changed our wakeup count propagate it to the parent */ 233 if (d->wake_count < 0) 234 for (i = d->wake_count; i < 0; i++) 235 irq_set_irq_wake(d->irq, 0); 236 else if (d->wake_count > 0) 237 for (i = 0; i < d->wake_count; i++) 238 irq_set_irq_wake(d->irq, 1); 239 240 d->wake_count = 0; 241 242 mutex_unlock(&d->lock); 243 } 244 245 static void regmap_irq_enable(struct irq_data *data) 246 { 247 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 248 struct regmap *map = d->map; 249 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 250 unsigned int reg = irq_data->reg_offset / map->reg_stride; 251 unsigned int mask; 252 253 /* 254 * The type_in_mask flag means that the underlying hardware uses 255 * separate mask bits for each interrupt trigger type, but we want 256 * to have a single logical interrupt with a configurable type. 257 * 258 * If the interrupt we're enabling defines any supported types 259 * then instead of using the regular mask bits for this interrupt, 260 * use the value previously written to the type buffer at the 261 * corresponding offset in regmap_irq_set_type(). 262 */ 263 if (d->chip->type_in_mask && irq_data->type.types_supported) 264 mask = d->type_buf[reg] & irq_data->mask; 265 else 266 mask = irq_data->mask; 267 268 if (d->chip->clear_on_unmask) 269 d->clear_status = true; 270 271 d->mask_buf[reg] &= ~mask; 272 } 273 274 static void regmap_irq_disable(struct irq_data *data) 275 { 276 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 277 struct regmap *map = d->map; 278 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 279 280 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; 281 } 282 283 static int regmap_irq_set_type(struct irq_data *data, unsigned int type) 284 { 285 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 286 struct regmap *map = d->map; 287 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 288 int reg, ret; 289 const struct regmap_irq_type *t = &irq_data->type; 290 291 if ((t->types_supported & type) != type) 292 return 0; 293 294 reg = t->type_reg_offset / map->reg_stride; 295 296 if (t->type_reg_mask) 297 d->type_buf[reg] &= ~t->type_reg_mask; 298 else 299 d->type_buf[reg] &= ~(t->type_falling_val | 300 t->type_rising_val | 301 t->type_level_low_val | 302 t->type_level_high_val); 303 switch (type) { 304 case IRQ_TYPE_EDGE_FALLING: 305 d->type_buf[reg] |= t->type_falling_val; 306 break; 307 308 case IRQ_TYPE_EDGE_RISING: 309 d->type_buf[reg] |= t->type_rising_val; 310 break; 311 312 case IRQ_TYPE_EDGE_BOTH: 313 d->type_buf[reg] |= (t->type_falling_val | 314 t->type_rising_val); 315 break; 316 317 case IRQ_TYPE_LEVEL_HIGH: 318 d->type_buf[reg] |= t->type_level_high_val; 319 break; 320 321 case IRQ_TYPE_LEVEL_LOW: 322 d->type_buf[reg] |= t->type_level_low_val; 323 break; 324 default: 325 return -EINVAL; 326 } 327 328 if (d->chip->set_type_virt) { 329 ret = d->chip->set_type_virt(d->virt_buf, type, data->hwirq, 330 reg); 331 if (ret) 332 return ret; 333 } 334 335 if (d->chip->set_type_config) { 336 ret = d->chip->set_type_config(d->config_buf, type, 337 irq_data, reg); 338 if (ret) 339 return ret; 340 } 341 342 return 0; 343 } 344 345 static int regmap_irq_set_wake(struct irq_data *data, unsigned int on) 346 { 347 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); 348 struct regmap *map = d->map; 349 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); 350 351 if (on) { 352 if (d->wake_buf) 353 d->wake_buf[irq_data->reg_offset / map->reg_stride] 354 &= ~irq_data->mask; 355 d->wake_count++; 356 } else { 357 if (d->wake_buf) 358 d->wake_buf[irq_data->reg_offset / map->reg_stride] 359 |= irq_data->mask; 360 d->wake_count--; 361 } 362 363 return 0; 364 } 365 366 static const struct irq_chip regmap_irq_chip = { 367 .irq_bus_lock = regmap_irq_lock, 368 .irq_bus_sync_unlock = regmap_irq_sync_unlock, 369 .irq_disable = regmap_irq_disable, 370 .irq_enable = regmap_irq_enable, 371 .irq_set_type = regmap_irq_set_type, 372 .irq_set_wake = regmap_irq_set_wake, 373 }; 374 375 static inline int read_sub_irq_data(struct regmap_irq_chip_data *data, 376 unsigned int b) 377 { 378 const struct regmap_irq_chip *chip = data->chip; 379 struct regmap *map = data->map; 380 struct regmap_irq_sub_irq_map *subreg; 381 unsigned int reg; 382 int i, ret = 0; 383 384 if (!chip->sub_reg_offsets) { 385 reg = data->get_irq_reg(data, chip->status_base, b); 386 ret = regmap_read(map, reg, &data->status_buf[b]); 387 } else { 388 /* 389 * Note we can't use ->get_irq_reg() here because the offsets 390 * in 'subreg' are *not* interchangeable with indices. 391 */ 392 subreg = &chip->sub_reg_offsets[b]; 393 for (i = 0; i < subreg->num_regs; i++) { 394 unsigned int offset = subreg->offset[i]; 395 unsigned int index = offset / map->reg_stride; 396 397 if (chip->not_fixed_stride) 398 ret = regmap_read(map, 399 chip->status_base + offset, 400 &data->status_buf[b]); 401 else 402 ret = regmap_read(map, 403 chip->status_base + offset, 404 &data->status_buf[index]); 405 406 if (ret) 407 break; 408 } 409 } 410 return ret; 411 } 412 413 static irqreturn_t regmap_irq_thread(int irq, void *d) 414 { 415 struct regmap_irq_chip_data *data = d; 416 const struct regmap_irq_chip *chip = data->chip; 417 struct regmap *map = data->map; 418 int ret, i; 419 bool handled = false; 420 u32 reg; 421 422 if (chip->handle_pre_irq) 423 chip->handle_pre_irq(chip->irq_drv_data); 424 425 if (chip->runtime_pm) { 426 ret = pm_runtime_get_sync(map->dev); 427 if (ret < 0) { 428 dev_err(map->dev, "IRQ thread failed to resume: %d\n", 429 ret); 430 goto exit; 431 } 432 } 433 434 /* 435 * Read only registers with active IRQs if the chip has 'main status 436 * register'. Else read in the statuses, using a single bulk read if 437 * possible in order to reduce the I/O overheads. 438 */ 439 440 if (chip->num_main_regs) { 441 unsigned int max_main_bits; 442 unsigned long size; 443 444 size = chip->num_regs * sizeof(unsigned int); 445 446 max_main_bits = (chip->num_main_status_bits) ? 447 chip->num_main_status_bits : chip->num_regs; 448 /* Clear the status buf as we don't read all status regs */ 449 memset(data->status_buf, 0, size); 450 451 /* We could support bulk read for main status registers 452 * but I don't expect to see devices with really many main 453 * status registers so let's only support single reads for the 454 * sake of simplicity. and add bulk reads only if needed 455 */ 456 for (i = 0; i < chip->num_main_regs; i++) { 457 /* 458 * For not_fixed_stride, don't use ->get_irq_reg(). 459 * It would produce an incorrect result. 460 */ 461 if (data->chip->not_fixed_stride) 462 reg = chip->main_status + 463 i * map->reg_stride * data->irq_reg_stride; 464 else 465 reg = data->get_irq_reg(data, 466 chip->main_status, i); 467 468 ret = regmap_read(map, reg, &data->main_status_buf[i]); 469 if (ret) { 470 dev_err(map->dev, 471 "Failed to read IRQ status %d\n", 472 ret); 473 goto exit; 474 } 475 } 476 477 /* Read sub registers with active IRQs */ 478 for (i = 0; i < chip->num_main_regs; i++) { 479 unsigned int b; 480 const unsigned long mreg = data->main_status_buf[i]; 481 482 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { 483 if (i * map->format.val_bytes * 8 + b > 484 max_main_bits) 485 break; 486 ret = read_sub_irq_data(data, b); 487 488 if (ret != 0) { 489 dev_err(map->dev, 490 "Failed to read IRQ status %d\n", 491 ret); 492 goto exit; 493 } 494 } 495 496 } 497 } else if (regmap_irq_can_bulk_read_status(data)) { 498 499 u8 *buf8 = data->status_reg_buf; 500 u16 *buf16 = data->status_reg_buf; 501 u32 *buf32 = data->status_reg_buf; 502 503 BUG_ON(!data->status_reg_buf); 504 505 ret = regmap_bulk_read(map, chip->status_base, 506 data->status_reg_buf, 507 chip->num_regs); 508 if (ret != 0) { 509 dev_err(map->dev, "Failed to read IRQ status: %d\n", 510 ret); 511 goto exit; 512 } 513 514 for (i = 0; i < data->chip->num_regs; i++) { 515 switch (map->format.val_bytes) { 516 case 1: 517 data->status_buf[i] = buf8[i]; 518 break; 519 case 2: 520 data->status_buf[i] = buf16[i]; 521 break; 522 case 4: 523 data->status_buf[i] = buf32[i]; 524 break; 525 default: 526 BUG(); 527 goto exit; 528 } 529 } 530 531 } else { 532 for (i = 0; i < data->chip->num_regs; i++) { 533 unsigned int reg = data->get_irq_reg(data, 534 data->chip->status_base, i); 535 ret = regmap_read(map, reg, &data->status_buf[i]); 536 537 if (ret != 0) { 538 dev_err(map->dev, 539 "Failed to read IRQ status: %d\n", 540 ret); 541 goto exit; 542 } 543 } 544 } 545 546 if (chip->status_invert) 547 for (i = 0; i < data->chip->num_regs; i++) 548 data->status_buf[i] = ~data->status_buf[i]; 549 550 /* 551 * Ignore masked IRQs and ack if we need to; we ack early so 552 * there is no race between handling and acknowledging the 553 * interrupt. We assume that typically few of the interrupts 554 * will fire simultaneously so don't worry about overhead from 555 * doing a write per register. 556 */ 557 for (i = 0; i < data->chip->num_regs; i++) { 558 data->status_buf[i] &= ~data->mask_buf[i]; 559 560 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { 561 reg = data->get_irq_reg(data, data->chip->ack_base, i); 562 563 if (chip->ack_invert) 564 ret = regmap_write(map, reg, 565 ~data->status_buf[i]); 566 else 567 ret = regmap_write(map, reg, 568 data->status_buf[i]); 569 if (chip->clear_ack) { 570 if (chip->ack_invert && !ret) 571 ret = regmap_write(map, reg, UINT_MAX); 572 else if (!ret) 573 ret = regmap_write(map, reg, 0); 574 } 575 if (ret != 0) 576 dev_err(map->dev, "Failed to ack 0x%x: %d\n", 577 reg, ret); 578 } 579 } 580 581 for (i = 0; i < chip->num_irqs; i++) { 582 if (data->status_buf[chip->irqs[i].reg_offset / 583 map->reg_stride] & chip->irqs[i].mask) { 584 handle_nested_irq(irq_find_mapping(data->domain, i)); 585 handled = true; 586 } 587 } 588 589 exit: 590 if (chip->runtime_pm) 591 pm_runtime_put(map->dev); 592 593 if (chip->handle_post_irq) 594 chip->handle_post_irq(chip->irq_drv_data); 595 596 if (handled) 597 return IRQ_HANDLED; 598 else 599 return IRQ_NONE; 600 } 601 602 static int regmap_irq_map(struct irq_domain *h, unsigned int virq, 603 irq_hw_number_t hw) 604 { 605 struct regmap_irq_chip_data *data = h->host_data; 606 607 irq_set_chip_data(virq, data); 608 irq_set_chip(virq, &data->irq_chip); 609 irq_set_nested_thread(virq, 1); 610 irq_set_parent(virq, data->irq); 611 irq_set_noprobe(virq); 612 613 return 0; 614 } 615 616 static const struct irq_domain_ops regmap_domain_ops = { 617 .map = regmap_irq_map, 618 .xlate = irq_domain_xlate_onetwocell, 619 }; 620 621 /** 622 * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback. 623 * @data: Data for the &struct regmap_irq_chip 624 * @base: Base register 625 * @index: Register index 626 * 627 * Returns the register address corresponding to the given @base and @index 628 * by the formula ``base + index * regmap_stride * irq_reg_stride``. 629 */ 630 unsigned int regmap_irq_get_irq_reg_linear(struct regmap_irq_chip_data *data, 631 unsigned int base, int index) 632 { 633 const struct regmap_irq_chip *chip = data->chip; 634 struct regmap *map = data->map; 635 636 /* 637 * FIXME: This is for backward compatibility and should be removed 638 * when not_fixed_stride is dropped (it's only used by qcom-pm8008). 639 */ 640 if (chip->not_fixed_stride && chip->sub_reg_offsets) { 641 struct regmap_irq_sub_irq_map *subreg; 642 643 subreg = &chip->sub_reg_offsets[0]; 644 return base + subreg->offset[0]; 645 } 646 647 return base + index * map->reg_stride * data->irq_reg_stride; 648 } 649 EXPORT_SYMBOL_GPL(regmap_irq_get_irq_reg_linear); 650 651 /** 652 * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback. 653 * @buf: Buffer containing configuration register values, this is a 2D array of 654 * `num_config_bases` rows, each of `num_config_regs` elements. 655 * @type: The requested IRQ type. 656 * @irq_data: The IRQ being configured. 657 * @idx: Index of the irq's config registers within each array `buf[i]` 658 * 659 * This is a &struct regmap_irq_chip->set_type_config callback suitable for 660 * chips with one config register. Register values are updated according to 661 * the &struct regmap_irq_type data associated with an IRQ. 662 */ 663 int regmap_irq_set_type_config_simple(unsigned int **buf, unsigned int type, 664 const struct regmap_irq *irq_data, int idx) 665 { 666 const struct regmap_irq_type *t = &irq_data->type; 667 668 if (t->type_reg_mask) 669 buf[0][idx] &= ~t->type_reg_mask; 670 else 671 buf[0][idx] &= ~(t->type_falling_val | 672 t->type_rising_val | 673 t->type_level_low_val | 674 t->type_level_high_val); 675 676 switch (type) { 677 case IRQ_TYPE_EDGE_FALLING: 678 buf[0][idx] |= t->type_falling_val; 679 break; 680 681 case IRQ_TYPE_EDGE_RISING: 682 buf[0][idx] |= t->type_rising_val; 683 break; 684 685 case IRQ_TYPE_EDGE_BOTH: 686 buf[0][idx] |= (t->type_falling_val | 687 t->type_rising_val); 688 break; 689 690 case IRQ_TYPE_LEVEL_HIGH: 691 buf[0][idx] |= t->type_level_high_val; 692 break; 693 694 case IRQ_TYPE_LEVEL_LOW: 695 buf[0][idx] |= t->type_level_low_val; 696 break; 697 698 default: 699 return -EINVAL; 700 } 701 702 return 0; 703 } 704 EXPORT_SYMBOL_GPL(regmap_irq_set_type_config_simple); 705 706 /** 707 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling 708 * 709 * @fwnode: The firmware node where the IRQ domain should be added to. 710 * @map: The regmap for the device. 711 * @irq: The IRQ the device uses to signal interrupts. 712 * @irq_flags: The IRQF_ flags to use for the primary interrupt. 713 * @irq_base: Allocate at specific IRQ number if irq_base > 0. 714 * @chip: Configuration for the interrupt controller. 715 * @data: Runtime data structure for the controller, allocated on success. 716 * 717 * Returns 0 on success or an errno on failure. 718 * 719 * In order for this to be efficient the chip really should use a 720 * register cache. The chip driver is responsible for restoring the 721 * register values used by the IRQ controller over suspend and resume. 722 */ 723 int regmap_add_irq_chip_fwnode(struct fwnode_handle *fwnode, 724 struct regmap *map, int irq, 725 int irq_flags, int irq_base, 726 const struct regmap_irq_chip *chip, 727 struct regmap_irq_chip_data **data) 728 { 729 struct regmap_irq_chip_data *d; 730 int i; 731 int ret = -ENOMEM; 732 int num_type_reg; 733 int num_regs; 734 u32 reg; 735 736 if (chip->num_regs <= 0) 737 return -EINVAL; 738 739 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) 740 return -EINVAL; 741 742 for (i = 0; i < chip->num_irqs; i++) { 743 if (chip->irqs[i].reg_offset % map->reg_stride) 744 return -EINVAL; 745 if (chip->irqs[i].reg_offset / map->reg_stride >= 746 chip->num_regs) 747 return -EINVAL; 748 } 749 750 if (chip->not_fixed_stride) { 751 dev_warn(map->dev, "not_fixed_stride is deprecated; use ->get_irq_reg() instead"); 752 753 for (i = 0; i < chip->num_regs; i++) 754 if (chip->sub_reg_offsets[i].num_regs != 1) 755 return -EINVAL; 756 } 757 758 if (chip->num_type_reg) 759 dev_warn(map->dev, "type registers are deprecated; use config registers instead"); 760 761 if (chip->num_virt_regs || chip->virt_reg_base || chip->set_type_virt) 762 dev_warn(map->dev, "virtual registers are deprecated; use config registers instead"); 763 764 if (irq_base) { 765 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); 766 if (irq_base < 0) { 767 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", 768 irq_base); 769 return irq_base; 770 } 771 } 772 773 d = kzalloc(sizeof(*d), GFP_KERNEL); 774 if (!d) 775 return -ENOMEM; 776 777 if (chip->num_main_regs) { 778 d->main_status_buf = kcalloc(chip->num_main_regs, 779 sizeof(*d->main_status_buf), 780 GFP_KERNEL); 781 782 if (!d->main_status_buf) 783 goto err_alloc; 784 } 785 786 d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), 787 GFP_KERNEL); 788 if (!d->status_buf) 789 goto err_alloc; 790 791 d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), 792 GFP_KERNEL); 793 if (!d->mask_buf) 794 goto err_alloc; 795 796 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), 797 GFP_KERNEL); 798 if (!d->mask_buf_def) 799 goto err_alloc; 800 801 if (chip->wake_base) { 802 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), 803 GFP_KERNEL); 804 if (!d->wake_buf) 805 goto err_alloc; 806 } 807 808 /* 809 * Use num_config_regs if defined, otherwise fall back to num_type_reg 810 * to maintain backward compatibility. 811 */ 812 num_type_reg = chip->num_config_regs ? chip->num_config_regs 813 : chip->num_type_reg; 814 num_regs = chip->type_in_mask ? chip->num_regs : num_type_reg; 815 if (num_regs) { 816 d->type_buf_def = kcalloc(num_regs, 817 sizeof(*d->type_buf_def), GFP_KERNEL); 818 if (!d->type_buf_def) 819 goto err_alloc; 820 821 d->type_buf = kcalloc(num_regs, sizeof(*d->type_buf), 822 GFP_KERNEL); 823 if (!d->type_buf) 824 goto err_alloc; 825 } 826 827 if (chip->num_virt_regs) { 828 /* 829 * Create virt_buf[chip->num_extra_config_regs][chip->num_regs] 830 */ 831 d->virt_buf = kcalloc(chip->num_virt_regs, sizeof(*d->virt_buf), 832 GFP_KERNEL); 833 if (!d->virt_buf) 834 goto err_alloc; 835 836 for (i = 0; i < chip->num_virt_regs; i++) { 837 d->virt_buf[i] = kcalloc(chip->num_regs, 838 sizeof(**d->virt_buf), 839 GFP_KERNEL); 840 if (!d->virt_buf[i]) 841 goto err_alloc; 842 } 843 } 844 845 if (chip->num_config_bases && chip->num_config_regs) { 846 /* 847 * Create config_buf[num_config_bases][num_config_regs] 848 */ 849 d->config_buf = kcalloc(chip->num_config_bases, 850 sizeof(*d->config_buf), GFP_KERNEL); 851 if (!d->config_buf) 852 goto err_alloc; 853 854 for (i = 0; i < chip->num_config_regs; i++) { 855 d->config_buf[i] = kcalloc(chip->num_config_regs, 856 sizeof(**d->config_buf), 857 GFP_KERNEL); 858 if (!d->config_buf[i]) 859 goto err_alloc; 860 } 861 } 862 863 d->irq_chip = regmap_irq_chip; 864 d->irq_chip.name = chip->name; 865 d->irq = irq; 866 d->map = map; 867 d->chip = chip; 868 d->irq_base = irq_base; 869 870 if (chip->mask_base && chip->unmask_base && 871 !chip->mask_unmask_non_inverted) { 872 /* 873 * Chips that specify both mask_base and unmask_base used to 874 * get inverted mask behavior by default, with no way to ask 875 * for the normal, non-inverted behavior. This "inverted by 876 * default" behavior is deprecated, but we have to support it 877 * until existing drivers have been fixed. 878 * 879 * Existing drivers should be updated by swapping mask_base 880 * and unmask_base and setting mask_unmask_non_inverted=true. 881 * New drivers should always set the flag. 882 */ 883 dev_warn(map->dev, "mask_base and unmask_base are inverted, please fix it"); 884 885 /* Might as well warn about mask_invert while we're at it... */ 886 if (chip->mask_invert) 887 dev_warn(map->dev, "mask_invert=true ignored"); 888 889 d->mask_base = chip->unmask_base; 890 d->unmask_base = chip->mask_base; 891 } else if (chip->mask_invert) { 892 /* 893 * Swap the roles of mask_base and unmask_base if the bits are 894 * inverted. This is deprecated, drivers should use unmask_base 895 * directly. 896 */ 897 dev_warn(map->dev, "mask_invert=true is deprecated; please switch to unmask_base"); 898 899 d->mask_base = chip->unmask_base; 900 d->unmask_base = chip->mask_base; 901 } else { 902 d->mask_base = chip->mask_base; 903 d->unmask_base = chip->unmask_base; 904 } 905 906 if (chip->irq_reg_stride) 907 d->irq_reg_stride = chip->irq_reg_stride; 908 else 909 d->irq_reg_stride = 1; 910 911 if (chip->get_irq_reg) 912 d->get_irq_reg = chip->get_irq_reg; 913 else 914 d->get_irq_reg = regmap_irq_get_irq_reg_linear; 915 916 if (regmap_irq_can_bulk_read_status(d)) { 917 d->status_reg_buf = kmalloc_array(chip->num_regs, 918 map->format.val_bytes, 919 GFP_KERNEL); 920 if (!d->status_reg_buf) 921 goto err_alloc; 922 } 923 924 mutex_init(&d->lock); 925 926 for (i = 0; i < chip->num_irqs; i++) 927 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] 928 |= chip->irqs[i].mask; 929 930 /* Mask all the interrupts by default */ 931 for (i = 0; i < chip->num_regs; i++) { 932 d->mask_buf[i] = d->mask_buf_def[i]; 933 934 if (d->mask_base) { 935 if (chip->handle_mask_sync) { 936 ret = chip->handle_mask_sync(d->map, i, 937 d->mask_buf_def[i], 938 d->mask_buf[i], 939 chip->irq_drv_data); 940 if (ret) 941 goto err_alloc; 942 } else { 943 reg = d->get_irq_reg(d, d->mask_base, i); 944 ret = regmap_update_bits(d->map, reg, 945 d->mask_buf_def[i], 946 d->mask_buf[i]); 947 if (ret) { 948 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", 949 reg, ret); 950 goto err_alloc; 951 } 952 } 953 } 954 955 if (d->unmask_base) { 956 reg = d->get_irq_reg(d, d->unmask_base, i); 957 ret = regmap_update_bits(d->map, reg, 958 d->mask_buf_def[i], ~d->mask_buf[i]); 959 if (ret) { 960 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", 961 reg, ret); 962 goto err_alloc; 963 } 964 } 965 966 if (!chip->init_ack_masked) 967 continue; 968 969 /* Ack masked but set interrupts */ 970 reg = d->get_irq_reg(d, d->chip->status_base, i); 971 ret = regmap_read(map, reg, &d->status_buf[i]); 972 if (ret != 0) { 973 dev_err(map->dev, "Failed to read IRQ status: %d\n", 974 ret); 975 goto err_alloc; 976 } 977 978 if (chip->status_invert) 979 d->status_buf[i] = ~d->status_buf[i]; 980 981 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { 982 reg = d->get_irq_reg(d, d->chip->ack_base, i); 983 if (chip->ack_invert) 984 ret = regmap_write(map, reg, 985 ~(d->status_buf[i] & d->mask_buf[i])); 986 else 987 ret = regmap_write(map, reg, 988 d->status_buf[i] & d->mask_buf[i]); 989 if (chip->clear_ack) { 990 if (chip->ack_invert && !ret) 991 ret = regmap_write(map, reg, UINT_MAX); 992 else if (!ret) 993 ret = regmap_write(map, reg, 0); 994 } 995 if (ret != 0) { 996 dev_err(map->dev, "Failed to ack 0x%x: %d\n", 997 reg, ret); 998 goto err_alloc; 999 } 1000 } 1001 } 1002 1003 /* Wake is disabled by default */ 1004 if (d->wake_buf) { 1005 for (i = 0; i < chip->num_regs; i++) { 1006 d->wake_buf[i] = d->mask_buf_def[i]; 1007 reg = d->get_irq_reg(d, d->chip->wake_base, i); 1008 1009 if (chip->wake_invert) 1010 ret = regmap_update_bits(d->map, reg, 1011 d->mask_buf_def[i], 1012 0); 1013 else 1014 ret = regmap_update_bits(d->map, reg, 1015 d->mask_buf_def[i], 1016 d->wake_buf[i]); 1017 if (ret != 0) { 1018 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", 1019 reg, ret); 1020 goto err_alloc; 1021 } 1022 } 1023 } 1024 1025 if (chip->num_type_reg && !chip->type_in_mask) { 1026 for (i = 0; i < chip->num_type_reg; ++i) { 1027 reg = d->get_irq_reg(d, d->chip->type_base, i); 1028 1029 ret = regmap_read(map, reg, &d->type_buf_def[i]); 1030 1031 if (d->chip->type_invert) 1032 d->type_buf_def[i] = ~d->type_buf_def[i]; 1033 1034 if (ret) { 1035 dev_err(map->dev, "Failed to get type defaults at 0x%x: %d\n", 1036 reg, ret); 1037 goto err_alloc; 1038 } 1039 } 1040 } 1041 1042 if (irq_base) 1043 d->domain = irq_domain_create_legacy(fwnode, chip->num_irqs, 1044 irq_base, 0, 1045 ®map_domain_ops, d); 1046 else 1047 d->domain = irq_domain_create_linear(fwnode, chip->num_irqs, 1048 ®map_domain_ops, d); 1049 if (!d->domain) { 1050 dev_err(map->dev, "Failed to create IRQ domain\n"); 1051 ret = -ENOMEM; 1052 goto err_alloc; 1053 } 1054 1055 ret = request_threaded_irq(irq, NULL, regmap_irq_thread, 1056 irq_flags | IRQF_ONESHOT, 1057 chip->name, d); 1058 if (ret != 0) { 1059 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", 1060 irq, chip->name, ret); 1061 goto err_domain; 1062 } 1063 1064 *data = d; 1065 1066 return 0; 1067 1068 err_domain: 1069 /* Should really dispose of the domain but... */ 1070 err_alloc: 1071 kfree(d->type_buf); 1072 kfree(d->type_buf_def); 1073 kfree(d->wake_buf); 1074 kfree(d->mask_buf_def); 1075 kfree(d->mask_buf); 1076 kfree(d->status_buf); 1077 kfree(d->status_reg_buf); 1078 if (d->virt_buf) { 1079 for (i = 0; i < chip->num_virt_regs; i++) 1080 kfree(d->virt_buf[i]); 1081 kfree(d->virt_buf); 1082 } 1083 if (d->config_buf) { 1084 for (i = 0; i < chip->num_config_bases; i++) 1085 kfree(d->config_buf[i]); 1086 kfree(d->config_buf); 1087 } 1088 kfree(d); 1089 return ret; 1090 } 1091 EXPORT_SYMBOL_GPL(regmap_add_irq_chip_fwnode); 1092 1093 /** 1094 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling 1095 * 1096 * @map: The regmap for the device. 1097 * @irq: The IRQ the device uses to signal interrupts. 1098 * @irq_flags: The IRQF_ flags to use for the primary interrupt. 1099 * @irq_base: Allocate at specific IRQ number if irq_base > 0. 1100 * @chip: Configuration for the interrupt controller. 1101 * @data: Runtime data structure for the controller, allocated on success. 1102 * 1103 * Returns 0 on success or an errno on failure. 1104 * 1105 * This is the same as regmap_add_irq_chip_fwnode, except that the firmware 1106 * node of the regmap is used. 1107 */ 1108 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, 1109 int irq_base, const struct regmap_irq_chip *chip, 1110 struct regmap_irq_chip_data **data) 1111 { 1112 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, 1113 irq_flags, irq_base, chip, data); 1114 } 1115 EXPORT_SYMBOL_GPL(regmap_add_irq_chip); 1116 1117 /** 1118 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip 1119 * 1120 * @irq: Primary IRQ for the device 1121 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip() 1122 * 1123 * This function also disposes of all mapped IRQs on the chip. 1124 */ 1125 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) 1126 { 1127 unsigned int virq; 1128 int i, hwirq; 1129 1130 if (!d) 1131 return; 1132 1133 free_irq(irq, d); 1134 1135 /* Dispose all virtual irq from irq domain before removing it */ 1136 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { 1137 /* Ignore hwirq if holes in the IRQ list */ 1138 if (!d->chip->irqs[hwirq].mask) 1139 continue; 1140 1141 /* 1142 * Find the virtual irq of hwirq on chip and if it is 1143 * there then dispose it 1144 */ 1145 virq = irq_find_mapping(d->domain, hwirq); 1146 if (virq) 1147 irq_dispose_mapping(virq); 1148 } 1149 1150 irq_domain_remove(d->domain); 1151 kfree(d->type_buf); 1152 kfree(d->type_buf_def); 1153 kfree(d->wake_buf); 1154 kfree(d->mask_buf_def); 1155 kfree(d->mask_buf); 1156 kfree(d->status_reg_buf); 1157 kfree(d->status_buf); 1158 if (d->config_buf) { 1159 for (i = 0; i < d->chip->num_config_bases; i++) 1160 kfree(d->config_buf[i]); 1161 kfree(d->config_buf); 1162 } 1163 kfree(d); 1164 } 1165 EXPORT_SYMBOL_GPL(regmap_del_irq_chip); 1166 1167 static void devm_regmap_irq_chip_release(struct device *dev, void *res) 1168 { 1169 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res; 1170 1171 regmap_del_irq_chip(d->irq, d); 1172 } 1173 1174 static int devm_regmap_irq_chip_match(struct device *dev, void *res, void *data) 1175 1176 { 1177 struct regmap_irq_chip_data **r = res; 1178 1179 if (!r || !*r) { 1180 WARN_ON(!r || !*r); 1181 return 0; 1182 } 1183 return *r == data; 1184 } 1185 1186 /** 1187 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode() 1188 * 1189 * @dev: The device pointer on which irq_chip belongs to. 1190 * @fwnode: The firmware node where the IRQ domain should be added to. 1191 * @map: The regmap for the device. 1192 * @irq: The IRQ the device uses to signal interrupts 1193 * @irq_flags: The IRQF_ flags to use for the primary interrupt. 1194 * @irq_base: Allocate at specific IRQ number if irq_base > 0. 1195 * @chip: Configuration for the interrupt controller. 1196 * @data: Runtime data structure for the controller, allocated on success 1197 * 1198 * Returns 0 on success or an errno on failure. 1199 * 1200 * The ®map_irq_chip_data will be automatically released when the device is 1201 * unbound. 1202 */ 1203 int devm_regmap_add_irq_chip_fwnode(struct device *dev, 1204 struct fwnode_handle *fwnode, 1205 struct regmap *map, int irq, 1206 int irq_flags, int irq_base, 1207 const struct regmap_irq_chip *chip, 1208 struct regmap_irq_chip_data **data) 1209 { 1210 struct regmap_irq_chip_data **ptr, *d; 1211 int ret; 1212 1213 ptr = devres_alloc(devm_regmap_irq_chip_release, sizeof(*ptr), 1214 GFP_KERNEL); 1215 if (!ptr) 1216 return -ENOMEM; 1217 1218 ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base, 1219 chip, &d); 1220 if (ret < 0) { 1221 devres_free(ptr); 1222 return ret; 1223 } 1224 1225 *ptr = d; 1226 devres_add(dev, ptr); 1227 *data = d; 1228 return 0; 1229 } 1230 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip_fwnode); 1231 1232 /** 1233 * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip() 1234 * 1235 * @dev: The device pointer on which irq_chip belongs to. 1236 * @map: The regmap for the device. 1237 * @irq: The IRQ the device uses to signal interrupts 1238 * @irq_flags: The IRQF_ flags to use for the primary interrupt. 1239 * @irq_base: Allocate at specific IRQ number if irq_base > 0. 1240 * @chip: Configuration for the interrupt controller. 1241 * @data: Runtime data structure for the controller, allocated on success 1242 * 1243 * Returns 0 on success or an errno on failure. 1244 * 1245 * The ®map_irq_chip_data will be automatically released when the device is 1246 * unbound. 1247 */ 1248 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq, 1249 int irq_flags, int irq_base, 1250 const struct regmap_irq_chip *chip, 1251 struct regmap_irq_chip_data **data) 1252 { 1253 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, 1254 irq, irq_flags, irq_base, chip, 1255 data); 1256 } 1257 EXPORT_SYMBOL_GPL(devm_regmap_add_irq_chip); 1258 1259 /** 1260 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip() 1261 * 1262 * @dev: Device for which the resource was allocated. 1263 * @irq: Primary IRQ for the device. 1264 * @data: ®map_irq_chip_data allocated by regmap_add_irq_chip(). 1265 * 1266 * A resource managed version of regmap_del_irq_chip(). 1267 */ 1268 void devm_regmap_del_irq_chip(struct device *dev, int irq, 1269 struct regmap_irq_chip_data *data) 1270 { 1271 int rc; 1272 1273 WARN_ON(irq != data->irq); 1274 rc = devres_release(dev, devm_regmap_irq_chip_release, 1275 devm_regmap_irq_chip_match, data); 1276 1277 if (rc != 0) 1278 WARN_ON(rc); 1279 } 1280 EXPORT_SYMBOL_GPL(devm_regmap_del_irq_chip); 1281 1282 /** 1283 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip 1284 * 1285 * @data: regmap irq controller to operate on. 1286 * 1287 * Useful for drivers to request their own IRQs. 1288 */ 1289 int regmap_irq_chip_get_base(struct regmap_irq_chip_data *data) 1290 { 1291 WARN_ON(!data->irq_base); 1292 return data->irq_base; 1293 } 1294 EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base); 1295 1296 /** 1297 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ 1298 * 1299 * @data: regmap irq controller to operate on. 1300 * @irq: index of the interrupt requested in the chip IRQs. 1301 * 1302 * Useful for drivers to request their own IRQs. 1303 */ 1304 int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq) 1305 { 1306 /* Handle holes in the IRQ list */ 1307 if (!data->chip->irqs[irq].mask) 1308 return -EINVAL; 1309 1310 return irq_create_mapping(data->domain, irq); 1311 } 1312 EXPORT_SYMBOL_GPL(regmap_irq_get_virq); 1313 1314 /** 1315 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip 1316 * 1317 * @data: regmap_irq controller to operate on. 1318 * 1319 * Useful for drivers to request their own IRQs and for integration 1320 * with subsystems. For ease of integration NULL is accepted as a 1321 * domain, allowing devices to just call this even if no domain is 1322 * allocated. 1323 */ 1324 struct irq_domain *regmap_irq_get_domain(struct regmap_irq_chip_data *data) 1325 { 1326 if (data) 1327 return data->domain; 1328 else 1329 return NULL; 1330 } 1331 EXPORT_SYMBOL_GPL(regmap_irq_get_domain); 1332