1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * nicstar.c 4 * 5 * Device driver supporting CBR for IDT 77201/77211 "NICStAR" based cards. 6 * 7 * IMPORTANT: The included file nicstarmac.c was NOT WRITTEN BY ME. 8 * It was taken from the frle-0.22 device driver. 9 * As the file doesn't have a copyright notice, in the file 10 * nicstarmac.copyright I put the copyright notice from the 11 * frle-0.22 device driver. 12 * Some code is based on the nicstar driver by M. Welsh. 13 * 14 * Author: Rui Prior (rprior@inescn.pt) 15 * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 16 * 17 * 18 * (C) INESC 1999 19 */ 20 21 /* 22 * IMPORTANT INFORMATION 23 * 24 * There are currently three types of spinlocks: 25 * 26 * 1 - Per card interrupt spinlock (to protect structures and such) 27 * 2 - Per SCQ scq spinlock 28 * 3 - Per card resource spinlock (to access registers, etc.) 29 * 30 * These must NEVER be grabbed in reverse order. 31 * 32 */ 33 34 /* Header files */ 35 36 #include <linux/module.h> 37 #include <linux/kernel.h> 38 #include <linux/skbuff.h> 39 #include <linux/atmdev.h> 40 #include <linux/atm.h> 41 #include <linux/pci.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/types.h> 44 #include <linux/string.h> 45 #include <linux/delay.h> 46 #include <linux/hex.h> 47 #include <linux/init.h> 48 #include <linux/sched.h> 49 #include <linux/timer.h> 50 #include <linux/interrupt.h> 51 #include <linux/bitops.h> 52 #include <linux/slab.h> 53 #include <linux/idr.h> 54 #include <asm/io.h> 55 #include <linux/uaccess.h> 56 #include <linux/atomic.h> 57 #include <linux/etherdevice.h> 58 #include "nicstar.h" 59 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI 60 #include "suni.h" 61 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 62 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 63 #include "idt77105.h" 64 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 65 66 /* Additional code */ 67 68 #include "nicstarmac.c" 69 70 /* Configurable parameters */ 71 72 #undef PHY_LOOPBACK 73 #undef TX_DEBUG 74 #undef RX_DEBUG 75 #undef GENERAL_DEBUG 76 #undef EXTRA_DEBUG 77 78 /* Do not touch these */ 79 80 #ifdef TX_DEBUG 81 #define TXPRINTK(args...) printk(args) 82 #else 83 #define TXPRINTK(args...) 84 #endif /* TX_DEBUG */ 85 86 #ifdef RX_DEBUG 87 #define RXPRINTK(args...) printk(args) 88 #else 89 #define RXPRINTK(args...) 90 #endif /* RX_DEBUG */ 91 92 #ifdef GENERAL_DEBUG 93 #define PRINTK(args...) printk(args) 94 #else 95 #define PRINTK(args...) do {} while (0) 96 #endif /* GENERAL_DEBUG */ 97 98 #ifdef EXTRA_DEBUG 99 #define XPRINTK(args...) printk(args) 100 #else 101 #define XPRINTK(args...) 102 #endif /* EXTRA_DEBUG */ 103 104 /* Macros */ 105 106 #define CMD_BUSY(card) (readl((card)->membase + STAT) & NS_STAT_CMDBZ) 107 108 #define NS_DELAY mdelay(1) 109 110 #define PTR_DIFF(a, b) ((u32)((unsigned long)(a) - (unsigned long)(b))) 111 112 #ifndef ATM_SKB 113 #define ATM_SKB(s) (&(s)->atm) 114 #endif 115 116 #define scq_virt_to_bus(scq, p) \ 117 (scq->dma + ((unsigned long)(p) - (unsigned long)(scq)->org)) 118 119 /* Function declarations */ 120 121 static u32 ns_read_sram(ns_dev * card, u32 sram_address); 122 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value, 123 int count); 124 static int ns_init_card(int i, struct pci_dev *pcidev); 125 static void ns_init_card_error(ns_dev * card, int error); 126 static scq_info *get_scq(ns_dev *card, int size, u32 scd); 127 static void free_scq(ns_dev *card, scq_info * scq, struct atm_vcc *vcc); 128 static void push_rxbufs(ns_dev *, struct sk_buff *); 129 static irqreturn_t ns_irq_handler(int irq, void *dev_id); 130 static int ns_open(struct atm_vcc *vcc); 131 static void ns_close(struct atm_vcc *vcc); 132 static void fill_tst(ns_dev * card, int n, vc_map * vc); 133 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb); 134 static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb); 135 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd, 136 struct sk_buff *skb, bool may_sleep); 137 static void process_tsq(ns_dev * card); 138 static void drain_scq(ns_dev * card, scq_info * scq, int pos); 139 static void process_rsq(ns_dev * card); 140 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe); 141 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb); 142 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count); 143 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb); 144 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb); 145 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb); 146 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page); 147 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg); 148 #ifdef EXTRA_DEBUG 149 static void which_list(ns_dev * card, struct sk_buff *skb); 150 #endif 151 static void ns_poll(struct timer_list *unused); 152 static void ns_phy_put(struct atm_dev *dev, unsigned char value, 153 unsigned long addr); 154 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr); 155 156 /* Global variables */ 157 158 static struct ns_dev *cards[NS_MAX_CARDS]; 159 static unsigned num_cards; 160 static const struct atmdev_ops atm_ops = { 161 .open = ns_open, 162 .close = ns_close, 163 .ioctl = ns_ioctl, 164 .send = ns_send, 165 .send_bh = ns_send_bh, 166 .phy_put = ns_phy_put, 167 .phy_get = ns_phy_get, 168 .proc_read = ns_proc_read, 169 .owner = THIS_MODULE, 170 }; 171 172 static struct timer_list ns_timer; 173 static char *mac[NS_MAX_CARDS]; 174 module_param_array(mac, charp, NULL, 0); 175 MODULE_DESCRIPTION("ATM NIC driver for IDT 77201/77211 \"NICStAR\" and Fore ForeRunnerLE."); 176 MODULE_LICENSE("GPL"); 177 178 /* Functions */ 179 180 static int nicstar_init_one(struct pci_dev *pcidev, 181 const struct pci_device_id *ent) 182 { 183 static int index = -1; 184 unsigned int error; 185 186 index++; 187 cards[index] = NULL; 188 189 error = ns_init_card(index, pcidev); 190 if (error) { 191 cards[index--] = NULL; /* don't increment index */ 192 goto err_out; 193 } 194 195 return 0; 196 err_out: 197 return -ENODEV; 198 } 199 200 static void nicstar_remove_one(struct pci_dev *pcidev) 201 { 202 int i, j; 203 ns_dev *card = pci_get_drvdata(pcidev); 204 struct sk_buff *hb; 205 struct sk_buff *iovb; 206 struct sk_buff *lb; 207 struct sk_buff *sb; 208 209 i = card->index; 210 211 if (cards[i] == NULL) 212 return; 213 214 if (card->atmdev->phy && card->atmdev->phy->stop) 215 card->atmdev->phy->stop(card->atmdev); 216 217 /* Stop everything */ 218 writel(0x00000000, card->membase + CFG); 219 220 /* De-register device */ 221 atm_dev_deregister(card->atmdev); 222 223 /* Disable PCI device */ 224 pci_disable_device(pcidev); 225 226 /* Free up resources */ 227 j = 0; 228 PRINTK("nicstar%d: freeing %d huge buffers.\n", i, card->hbpool.count); 229 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) { 230 dev_kfree_skb_any(hb); 231 j++; 232 } 233 PRINTK("nicstar%d: %d huge buffers freed.\n", i, j); 234 j = 0; 235 PRINTK("nicstar%d: freeing %d iovec buffers.\n", i, 236 card->iovpool.count); 237 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) { 238 dev_kfree_skb_any(iovb); 239 j++; 240 } 241 PRINTK("nicstar%d: %d iovec buffers freed.\n", i, j); 242 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 243 dev_kfree_skb_any(lb); 244 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 245 dev_kfree_skb_any(sb); 246 free_scq(card, card->scq0, NULL); 247 for (j = 0; j < NS_FRSCD_NUM; j++) { 248 if (card->scd2vc[j] != NULL) 249 free_scq(card, card->scd2vc[j]->scq, card->scd2vc[j]->tx_vcc); 250 } 251 idr_destroy(&card->idr); 252 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT, 253 card->rsq.org, card->rsq.dma); 254 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT, 255 card->tsq.org, card->tsq.dma); 256 free_irq(card->pcidev->irq, card); 257 iounmap(card->membase); 258 kfree(card); 259 } 260 261 static const struct pci_device_id nicstar_pci_tbl[] = { 262 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77201), 0 }, 263 {0,} /* terminate list */ 264 }; 265 266 MODULE_DEVICE_TABLE(pci, nicstar_pci_tbl); 267 268 static struct pci_driver nicstar_driver = { 269 .name = "nicstar", 270 .id_table = nicstar_pci_tbl, 271 .probe = nicstar_init_one, 272 .remove = nicstar_remove_one, 273 }; 274 275 static int __init nicstar_init(void) 276 { 277 unsigned error = 0; /* Initialized to remove compile warning */ 278 279 XPRINTK("nicstar: nicstar_init() called.\n"); 280 281 error = pci_register_driver(&nicstar_driver); 282 283 TXPRINTK("nicstar: TX debug enabled.\n"); 284 RXPRINTK("nicstar: RX debug enabled.\n"); 285 PRINTK("nicstar: General debug enabled.\n"); 286 #ifdef PHY_LOOPBACK 287 printk("nicstar: using PHY loopback.\n"); 288 #endif /* PHY_LOOPBACK */ 289 XPRINTK("nicstar: nicstar_init() returned.\n"); 290 291 if (!error) { 292 timer_setup(&ns_timer, ns_poll, 0); 293 ns_timer.expires = jiffies + NS_POLL_PERIOD; 294 add_timer(&ns_timer); 295 } 296 297 return error; 298 } 299 300 static void __exit nicstar_cleanup(void) 301 { 302 XPRINTK("nicstar: nicstar_cleanup() called.\n"); 303 304 timer_delete_sync(&ns_timer); 305 306 pci_unregister_driver(&nicstar_driver); 307 308 XPRINTK("nicstar: nicstar_cleanup() returned.\n"); 309 } 310 311 static u32 ns_read_sram(ns_dev * card, u32 sram_address) 312 { 313 unsigned long flags; 314 u32 data; 315 sram_address <<= 2; 316 sram_address &= 0x0007FFFC; /* address must be dword aligned */ 317 sram_address |= 0x50000000; /* SRAM read command */ 318 spin_lock_irqsave(&card->res_lock, flags); 319 while (CMD_BUSY(card)) ; 320 writel(sram_address, card->membase + CMD); 321 while (CMD_BUSY(card)) ; 322 data = readl(card->membase + DR0); 323 spin_unlock_irqrestore(&card->res_lock, flags); 324 return data; 325 } 326 327 static void ns_write_sram(ns_dev * card, u32 sram_address, u32 * value, 328 int count) 329 { 330 unsigned long flags; 331 int i, c; 332 count--; /* count range now is 0..3 instead of 1..4 */ 333 c = count; 334 c <<= 2; /* to use increments of 4 */ 335 spin_lock_irqsave(&card->res_lock, flags); 336 while (CMD_BUSY(card)) ; 337 for (i = 0; i <= c; i += 4) 338 writel(*(value++), card->membase + i); 339 /* Note: DR# registers are the first 4 dwords in nicstar's memspace, 340 so card->membase + DR0 == card->membase */ 341 sram_address <<= 2; 342 sram_address &= 0x0007FFFC; 343 sram_address |= (0x40000000 | count); 344 writel(sram_address, card->membase + CMD); 345 spin_unlock_irqrestore(&card->res_lock, flags); 346 } 347 348 static int ns_init_card(int i, struct pci_dev *pcidev) 349 { 350 int j; 351 struct ns_dev *card = NULL; 352 unsigned char pci_latency; 353 unsigned error; 354 u32 data; 355 u32 u32d[4]; 356 u32 ns_cfg_rctsize; 357 int bcount; 358 unsigned long membase; 359 360 error = 0; 361 362 if (pci_enable_device(pcidev)) { 363 printk("nicstar%d: can't enable PCI device\n", i); 364 error = 2; 365 ns_init_card_error(card, error); 366 return error; 367 } 368 if (dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)) != 0) { 369 printk(KERN_WARNING 370 "nicstar%d: No suitable DMA available.\n", i); 371 error = 2; 372 ns_init_card_error(card, error); 373 return error; 374 } 375 376 card = kmalloc(sizeof(*card), GFP_KERNEL); 377 if (!card) { 378 printk 379 ("nicstar%d: can't allocate memory for device structure.\n", 380 i); 381 error = 2; 382 ns_init_card_error(card, error); 383 return error; 384 } 385 cards[i] = card; 386 spin_lock_init(&card->int_lock); 387 spin_lock_init(&card->res_lock); 388 389 pci_set_drvdata(pcidev, card); 390 391 card->index = i; 392 card->atmdev = NULL; 393 card->pcidev = pcidev; 394 membase = pci_resource_start(pcidev, 1); 395 card->membase = ioremap(membase, NS_IOREMAP_SIZE); 396 if (!card->membase) { 397 printk("nicstar%d: can't ioremap() membase.\n", i); 398 error = 3; 399 ns_init_card_error(card, error); 400 return error; 401 } 402 PRINTK("nicstar%d: membase at 0x%p.\n", i, card->membase); 403 404 pci_set_master(pcidev); 405 406 if (pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency) != 0) { 407 printk("nicstar%d: can't read PCI latency timer.\n", i); 408 error = 6; 409 ns_init_card_error(card, error); 410 return error; 411 } 412 #ifdef NS_PCI_LATENCY 413 if (pci_latency < NS_PCI_LATENCY) { 414 PRINTK("nicstar%d: setting PCI latency timer to %d.\n", i, 415 NS_PCI_LATENCY); 416 for (j = 1; j < 4; j++) { 417 if (pci_write_config_byte 418 (pcidev, PCI_LATENCY_TIMER, NS_PCI_LATENCY) != 0) 419 break; 420 } 421 if (j == 4) { 422 printk 423 ("nicstar%d: can't set PCI latency timer to %d.\n", 424 i, NS_PCI_LATENCY); 425 error = 7; 426 ns_init_card_error(card, error); 427 return error; 428 } 429 } 430 #endif /* NS_PCI_LATENCY */ 431 432 /* Clear timer overflow */ 433 data = readl(card->membase + STAT); 434 if (data & NS_STAT_TMROF) 435 writel(NS_STAT_TMROF, card->membase + STAT); 436 437 /* Software reset */ 438 writel(NS_CFG_SWRST, card->membase + CFG); 439 NS_DELAY; 440 writel(0x00000000, card->membase + CFG); 441 442 /* PHY reset */ 443 writel(0x00000008, card->membase + GP); 444 NS_DELAY; 445 writel(0x00000001, card->membase + GP); 446 NS_DELAY; 447 while (CMD_BUSY(card)) ; 448 writel(NS_CMD_WRITE_UTILITY | 0x00000100, card->membase + CMD); /* Sync UTOPIA with SAR clock */ 449 NS_DELAY; 450 451 /* Detect PHY type */ 452 while (CMD_BUSY(card)) ; 453 writel(NS_CMD_READ_UTILITY | 0x00000200, card->membase + CMD); 454 while (CMD_BUSY(card)) ; 455 data = readl(card->membase + DR0); 456 switch (data) { 457 case 0x00000009: 458 printk("nicstar%d: PHY seems to be 25 Mbps.\n", i); 459 card->max_pcr = ATM_25_PCR; 460 while (CMD_BUSY(card)) ; 461 writel(0x00000008, card->membase + DR0); 462 writel(NS_CMD_WRITE_UTILITY | 0x00000200, card->membase + CMD); 463 /* Clear an eventual pending interrupt */ 464 writel(NS_STAT_SFBQF, card->membase + STAT); 465 #ifdef PHY_LOOPBACK 466 while (CMD_BUSY(card)) ; 467 writel(0x00000022, card->membase + DR0); 468 writel(NS_CMD_WRITE_UTILITY | 0x00000202, card->membase + CMD); 469 #endif /* PHY_LOOPBACK */ 470 break; 471 case 0x00000030: 472 case 0x00000031: 473 printk("nicstar%d: PHY seems to be 155 Mbps.\n", i); 474 card->max_pcr = ATM_OC3_PCR; 475 #ifdef PHY_LOOPBACK 476 while (CMD_BUSY(card)) ; 477 writel(0x00000002, card->membase + DR0); 478 writel(NS_CMD_WRITE_UTILITY | 0x00000205, card->membase + CMD); 479 #endif /* PHY_LOOPBACK */ 480 break; 481 default: 482 printk("nicstar%d: unknown PHY type (0x%08X).\n", i, data); 483 error = 8; 484 ns_init_card_error(card, error); 485 return error; 486 } 487 writel(0x00000000, card->membase + GP); 488 489 /* Determine SRAM size */ 490 data = 0x76543210; 491 ns_write_sram(card, 0x1C003, &data, 1); 492 data = 0x89ABCDEF; 493 ns_write_sram(card, 0x14003, &data, 1); 494 if (ns_read_sram(card, 0x14003) == 0x89ABCDEF && 495 ns_read_sram(card, 0x1C003) == 0x76543210) 496 card->sram_size = 128; 497 else 498 card->sram_size = 32; 499 PRINTK("nicstar%d: %dK x 32bit SRAM size.\n", i, card->sram_size); 500 501 card->rct_size = NS_MAX_RCTSIZE; 502 503 #if (NS_MAX_RCTSIZE == 4096) 504 if (card->sram_size == 128) 505 printk 506 ("nicstar%d: limiting maximum VCI. See NS_MAX_RCTSIZE in nicstar.h\n", 507 i); 508 #elif (NS_MAX_RCTSIZE == 16384) 509 if (card->sram_size == 32) { 510 printk 511 ("nicstar%d: wasting memory. See NS_MAX_RCTSIZE in nicstar.h\n", 512 i); 513 card->rct_size = 4096; 514 } 515 #else 516 #error NS_MAX_RCTSIZE must be either 4096 or 16384 in nicstar.c 517 #endif 518 519 card->vpibits = NS_VPIBITS; 520 if (card->rct_size == 4096) 521 card->vcibits = 12 - NS_VPIBITS; 522 else /* card->rct_size == 16384 */ 523 card->vcibits = 14 - NS_VPIBITS; 524 525 /* Initialize the nicstar eeprom/eprom stuff, for the MAC addr */ 526 if (mac[i] == NULL) 527 nicstar_init_eprom(card->membase); 528 529 /* Set the VPI/VCI MSb mask to zero so we can receive OAM cells */ 530 writel(0x00000000, card->membase + VPM); 531 532 card->intcnt = 0; 533 if (request_irq 534 (pcidev->irq, &ns_irq_handler, IRQF_SHARED, "nicstar", card) != 0) { 535 pr_err("nicstar%d: can't allocate IRQ %d.\n", i, pcidev->irq); 536 error = 9; 537 ns_init_card_error(card, error); 538 return error; 539 } 540 541 /* Initialize TSQ */ 542 card->tsq.org = dma_alloc_coherent(&card->pcidev->dev, 543 NS_TSQSIZE + NS_TSQ_ALIGNMENT, 544 &card->tsq.dma, GFP_KERNEL); 545 if (card->tsq.org == NULL) { 546 printk("nicstar%d: can't allocate TSQ.\n", i); 547 error = 10; 548 ns_init_card_error(card, error); 549 return error; 550 } 551 card->tsq.base = PTR_ALIGN(card->tsq.org, NS_TSQ_ALIGNMENT); 552 card->tsq.next = card->tsq.base; 553 card->tsq.last = card->tsq.base + (NS_TSQ_NUM_ENTRIES - 1); 554 for (j = 0; j < NS_TSQ_NUM_ENTRIES; j++) 555 ns_tsi_init(card->tsq.base + j); 556 writel(0x00000000, card->membase + TSQH); 557 writel(ALIGN(card->tsq.dma, NS_TSQ_ALIGNMENT), card->membase + TSQB); 558 PRINTK("nicstar%d: TSQ base at 0x%p.\n", i, card->tsq.base); 559 560 /* Initialize RSQ */ 561 card->rsq.org = dma_alloc_coherent(&card->pcidev->dev, 562 NS_RSQSIZE + NS_RSQ_ALIGNMENT, 563 &card->rsq.dma, GFP_KERNEL); 564 if (card->rsq.org == NULL) { 565 printk("nicstar%d: can't allocate RSQ.\n", i); 566 error = 11; 567 ns_init_card_error(card, error); 568 return error; 569 } 570 card->rsq.base = PTR_ALIGN(card->rsq.org, NS_RSQ_ALIGNMENT); 571 card->rsq.next = card->rsq.base; 572 card->rsq.last = card->rsq.base + (NS_RSQ_NUM_ENTRIES - 1); 573 for (j = 0; j < NS_RSQ_NUM_ENTRIES; j++) 574 ns_rsqe_init(card->rsq.base + j); 575 writel(0x00000000, card->membase + RSQH); 576 writel(ALIGN(card->rsq.dma, NS_RSQ_ALIGNMENT), card->membase + RSQB); 577 PRINTK("nicstar%d: RSQ base at 0x%p.\n", i, card->rsq.base); 578 579 /* Initialize SCQ0, the only VBR SCQ used */ 580 card->scq1 = NULL; 581 card->scq2 = NULL; 582 card->scq0 = get_scq(card, VBR_SCQSIZE, NS_VRSCD0); 583 if (card->scq0 == NULL) { 584 printk("nicstar%d: can't get SCQ0.\n", i); 585 error = 12; 586 ns_init_card_error(card, error); 587 return error; 588 } 589 u32d[0] = scq_virt_to_bus(card->scq0, card->scq0->base); 590 u32d[1] = (u32) 0x00000000; 591 u32d[2] = (u32) 0xffffffff; 592 u32d[3] = (u32) 0x00000000; 593 ns_write_sram(card, NS_VRSCD0, u32d, 4); 594 ns_write_sram(card, NS_VRSCD1, u32d, 4); /* These last two won't be used */ 595 ns_write_sram(card, NS_VRSCD2, u32d, 4); /* but are initialized, just in case... */ 596 card->scq0->scd = NS_VRSCD0; 597 PRINTK("nicstar%d: VBR-SCQ0 base at 0x%p.\n", i, card->scq0->base); 598 599 /* Initialize TSTs */ 600 card->tst_addr = NS_TST0; 601 card->tst_free_entries = NS_TST_NUM_ENTRIES; 602 data = NS_TST_OPCODE_VARIABLE; 603 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 604 ns_write_sram(card, NS_TST0 + j, &data, 1); 605 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST0); 606 ns_write_sram(card, NS_TST0 + NS_TST_NUM_ENTRIES, &data, 1); 607 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 608 ns_write_sram(card, NS_TST1 + j, &data, 1); 609 data = ns_tste_make(NS_TST_OPCODE_END, NS_TST1); 610 ns_write_sram(card, NS_TST1 + NS_TST_NUM_ENTRIES, &data, 1); 611 for (j = 0; j < NS_TST_NUM_ENTRIES; j++) 612 card->tste2vc[j] = NULL; 613 writel(NS_TST0 << 2, card->membase + TSTB); 614 615 /* Initialize RCT. AAL type is set on opening the VC. */ 616 #ifdef RCQ_SUPPORT 617 u32d[0] = NS_RCTE_RAWCELLINTEN; 618 #else 619 u32d[0] = 0x00000000; 620 #endif /* RCQ_SUPPORT */ 621 u32d[1] = 0x00000000; 622 u32d[2] = 0x00000000; 623 u32d[3] = 0xFFFFFFFF; 624 for (j = 0; j < card->rct_size; j++) 625 ns_write_sram(card, j * 4, u32d, 4); 626 627 memset(card->vcmap, 0, sizeof(card->vcmap)); 628 629 for (j = 0; j < NS_FRSCD_NUM; j++) 630 card->scd2vc[j] = NULL; 631 632 /* Initialize buffer levels */ 633 card->sbnr.min = MIN_SB; 634 card->sbnr.init = NUM_SB; 635 card->sbnr.max = MAX_SB; 636 card->lbnr.min = MIN_LB; 637 card->lbnr.init = NUM_LB; 638 card->lbnr.max = MAX_LB; 639 card->iovnr.min = MIN_IOVB; 640 card->iovnr.init = NUM_IOVB; 641 card->iovnr.max = MAX_IOVB; 642 card->hbnr.min = MIN_HB; 643 card->hbnr.init = NUM_HB; 644 card->hbnr.max = MAX_HB; 645 646 card->sm_handle = NULL; 647 card->sm_addr = 0x00000000; 648 card->lg_handle = NULL; 649 card->lg_addr = 0x00000000; 650 651 card->efbie = 1; /* To prevent push_rxbufs from enabling the interrupt */ 652 653 idr_init(&card->idr); 654 655 /* Pre-allocate some huge buffers */ 656 skb_queue_head_init(&card->hbpool.queue); 657 card->hbpool.count = 0; 658 for (j = 0; j < NUM_HB; j++) { 659 struct sk_buff *hb; 660 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 661 if (hb == NULL) { 662 printk 663 ("nicstar%d: can't allocate %dth of %d huge buffers.\n", 664 i, j, NUM_HB); 665 error = 13; 666 ns_init_card_error(card, error); 667 return error; 668 } 669 NS_PRV_BUFTYPE(hb) = BUF_NONE; 670 skb_queue_tail(&card->hbpool.queue, hb); 671 card->hbpool.count++; 672 } 673 674 /* Allocate large buffers */ 675 skb_queue_head_init(&card->lbpool.queue); 676 card->lbpool.count = 0; /* Not used */ 677 for (j = 0; j < NUM_LB; j++) { 678 struct sk_buff *lb; 679 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 680 if (lb == NULL) { 681 printk 682 ("nicstar%d: can't allocate %dth of %d large buffers.\n", 683 i, j, NUM_LB); 684 error = 14; 685 ns_init_card_error(card, error); 686 return error; 687 } 688 NS_PRV_BUFTYPE(lb) = BUF_LG; 689 skb_queue_tail(&card->lbpool.queue, lb); 690 skb_reserve(lb, NS_SMBUFSIZE); 691 push_rxbufs(card, lb); 692 /* Due to the implementation of push_rxbufs() this is 1, not 0 */ 693 if (j == 1) { 694 card->rcbuf = lb; 695 card->rawcell = (struct ns_rcqe *) lb->data; 696 card->rawch = NS_PRV_DMA(lb); 697 } 698 } 699 /* Test for strange behaviour which leads to crashes */ 700 if ((bcount = 701 ns_stat_lfbqc_get(readl(card->membase + STAT))) < card->lbnr.min) { 702 printk 703 ("nicstar%d: Strange... Just allocated %d large buffers and lfbqc = %d.\n", 704 i, j, bcount); 705 error = 14; 706 ns_init_card_error(card, error); 707 return error; 708 } 709 710 /* Allocate small buffers */ 711 skb_queue_head_init(&card->sbpool.queue); 712 card->sbpool.count = 0; /* Not used */ 713 for (j = 0; j < NUM_SB; j++) { 714 struct sk_buff *sb; 715 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 716 if (sb == NULL) { 717 printk 718 ("nicstar%d: can't allocate %dth of %d small buffers.\n", 719 i, j, NUM_SB); 720 error = 15; 721 ns_init_card_error(card, error); 722 return error; 723 } 724 NS_PRV_BUFTYPE(sb) = BUF_SM; 725 skb_queue_tail(&card->sbpool.queue, sb); 726 skb_reserve(sb, NS_AAL0_HEADER); 727 push_rxbufs(card, sb); 728 } 729 /* Test for strange behaviour which leads to crashes */ 730 if ((bcount = 731 ns_stat_sfbqc_get(readl(card->membase + STAT))) < card->sbnr.min) { 732 printk 733 ("nicstar%d: Strange... Just allocated %d small buffers and sfbqc = %d.\n", 734 i, j, bcount); 735 error = 15; 736 ns_init_card_error(card, error); 737 return error; 738 } 739 740 /* Allocate iovec buffers */ 741 skb_queue_head_init(&card->iovpool.queue); 742 card->iovpool.count = 0; 743 for (j = 0; j < NUM_IOVB; j++) { 744 struct sk_buff *iovb; 745 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 746 if (iovb == NULL) { 747 printk 748 ("nicstar%d: can't allocate %dth of %d iovec buffers.\n", 749 i, j, NUM_IOVB); 750 error = 16; 751 ns_init_card_error(card, error); 752 return error; 753 } 754 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 755 skb_queue_tail(&card->iovpool.queue, iovb); 756 card->iovpool.count++; 757 } 758 759 /* Configure NICStAR */ 760 if (card->rct_size == 4096) 761 ns_cfg_rctsize = NS_CFG_RCTSIZE_4096_ENTRIES; 762 else /* (card->rct_size == 16384) */ 763 ns_cfg_rctsize = NS_CFG_RCTSIZE_16384_ENTRIES; 764 765 card->efbie = 1; 766 767 /* Register device */ 768 card->atmdev = atm_dev_register("nicstar", &card->pcidev->dev, &atm_ops, 769 -1, NULL); 770 if (card->atmdev == NULL) { 771 printk("nicstar%d: can't register device.\n", i); 772 error = 17; 773 ns_init_card_error(card, error); 774 return error; 775 } 776 777 if (mac[i] == NULL || !mac_pton(mac[i], card->atmdev->esi)) { 778 nicstar_read_eprom(card->membase, NICSTAR_EPROM_MAC_ADDR_OFFSET, 779 card->atmdev->esi, 6); 780 if (ether_addr_equal(card->atmdev->esi, "\x00\x00\x00\x00\x00\x00")) { 781 nicstar_read_eprom(card->membase, 782 NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT, 783 card->atmdev->esi, 6); 784 } 785 } 786 787 printk("nicstar%d: MAC address %pM\n", i, card->atmdev->esi); 788 789 card->atmdev->dev_data = card; 790 card->atmdev->ci_range.vpi_bits = card->vpibits; 791 card->atmdev->ci_range.vci_bits = card->vcibits; 792 card->atmdev->link_rate = card->max_pcr; 793 card->atmdev->phy = NULL; 794 795 #ifdef CONFIG_ATM_NICSTAR_USE_SUNI 796 if (card->max_pcr == ATM_OC3_PCR) 797 suni_init(card->atmdev); 798 #endif /* CONFIG_ATM_NICSTAR_USE_SUNI */ 799 800 #ifdef CONFIG_ATM_NICSTAR_USE_IDT77105 801 if (card->max_pcr == ATM_25_PCR) 802 idt77105_init(card->atmdev); 803 #endif /* CONFIG_ATM_NICSTAR_USE_IDT77105 */ 804 805 if (card->atmdev->phy && card->atmdev->phy->start) 806 card->atmdev->phy->start(card->atmdev); 807 808 writel(NS_CFG_RXPATH | NS_CFG_SMBUFSIZE | NS_CFG_LGBUFSIZE | NS_CFG_EFBIE | NS_CFG_RSQSIZE | NS_CFG_VPIBITS | ns_cfg_rctsize | NS_CFG_RXINT_NODELAY | NS_CFG_RAWIE | /* Only enabled if RCQ_SUPPORT */ 809 NS_CFG_RSQAFIE | NS_CFG_TXEN | NS_CFG_TXIE | NS_CFG_TSQFIE_OPT | /* Only enabled if ENABLE_TSQFIE */ 810 NS_CFG_PHYIE, card->membase + CFG); 811 812 num_cards++; 813 814 return error; 815 } 816 817 static void ns_init_card_error(ns_dev *card, int error) 818 { 819 if (error >= 17) { 820 writel(0x00000000, card->membase + CFG); 821 } 822 if (error >= 16) { 823 struct sk_buff *iovb; 824 while ((iovb = skb_dequeue(&card->iovpool.queue)) != NULL) 825 dev_kfree_skb_any(iovb); 826 } 827 if (error >= 15) { 828 struct sk_buff *sb; 829 while ((sb = skb_dequeue(&card->sbpool.queue)) != NULL) 830 dev_kfree_skb_any(sb); 831 free_scq(card, card->scq0, NULL); 832 } 833 if (error >= 14) { 834 struct sk_buff *lb; 835 while ((lb = skb_dequeue(&card->lbpool.queue)) != NULL) 836 dev_kfree_skb_any(lb); 837 } 838 if (error >= 13) { 839 struct sk_buff *hb; 840 while ((hb = skb_dequeue(&card->hbpool.queue)) != NULL) 841 dev_kfree_skb_any(hb); 842 } 843 if (error >= 12) { 844 dma_free_coherent(&card->pcidev->dev, NS_RSQSIZE + NS_RSQ_ALIGNMENT, 845 card->rsq.org, card->rsq.dma); 846 } 847 if (error >= 11) { 848 dma_free_coherent(&card->pcidev->dev, NS_TSQSIZE + NS_TSQ_ALIGNMENT, 849 card->tsq.org, card->tsq.dma); 850 } 851 if (error >= 10) { 852 free_irq(card->pcidev->irq, card); 853 } 854 if (error >= 4) { 855 iounmap(card->membase); 856 } 857 if (error >= 3) { 858 pci_disable_device(card->pcidev); 859 kfree(card); 860 } 861 } 862 863 static scq_info *get_scq(ns_dev *card, int size, u32 scd) 864 { 865 scq_info *scq; 866 867 if (size != VBR_SCQSIZE && size != CBR_SCQSIZE) 868 return NULL; 869 870 scq = kmalloc(sizeof(*scq), GFP_KERNEL); 871 if (!scq) 872 return NULL; 873 scq->org = dma_alloc_coherent(&card->pcidev->dev, 874 2 * size, &scq->dma, GFP_KERNEL); 875 if (!scq->org) { 876 kfree(scq); 877 return NULL; 878 } 879 scq->skb = kcalloc(size / NS_SCQE_SIZE, sizeof(*scq->skb), 880 GFP_KERNEL); 881 if (!scq->skb) { 882 dma_free_coherent(&card->pcidev->dev, 883 2 * size, scq->org, scq->dma); 884 kfree(scq); 885 return NULL; 886 } 887 scq->num_entries = size / NS_SCQE_SIZE; 888 scq->base = PTR_ALIGN(scq->org, size); 889 scq->next = scq->base; 890 scq->last = scq->base + (scq->num_entries - 1); 891 scq->tail = scq->last; 892 scq->scd = scd; 893 scq->tbd_count = 0; 894 init_waitqueue_head(&scq->scqfull_waitq); 895 scq->full = 0; 896 spin_lock_init(&scq->lock); 897 898 return scq; 899 } 900 901 /* For variable rate SCQ vcc must be NULL */ 902 static void free_scq(ns_dev *card, scq_info *scq, struct atm_vcc *vcc) 903 { 904 int i; 905 906 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) 907 for (i = 0; i < scq->num_entries; i++) { 908 if (scq->skb[i] != NULL) { 909 vcc = ATM_SKB(scq->skb[i])->vcc; 910 if (vcc->pop != NULL) 911 vcc->pop(vcc, scq->skb[i]); 912 else 913 dev_kfree_skb_any(scq->skb[i]); 914 } 915 } else { /* vcc must be != NULL */ 916 917 if (vcc == NULL) { 918 printk 919 ("nicstar: free_scq() called with vcc == NULL for fixed rate scq."); 920 for (i = 0; i < scq->num_entries; i++) 921 dev_kfree_skb_any(scq->skb[i]); 922 } else 923 for (i = 0; i < scq->num_entries; i++) { 924 if (scq->skb[i] != NULL) { 925 if (vcc->pop != NULL) 926 vcc->pop(vcc, scq->skb[i]); 927 else 928 dev_kfree_skb_any(scq->skb[i]); 929 } 930 } 931 } 932 kfree(scq->skb); 933 dma_free_coherent(&card->pcidev->dev, 934 2 * (scq->num_entries == VBR_SCQ_NUM_ENTRIES ? 935 VBR_SCQSIZE : CBR_SCQSIZE), 936 scq->org, scq->dma); 937 kfree(scq); 938 } 939 940 /* The handles passed must be pointers to the sk_buff containing the small 941 or large buffer(s) cast to u32. */ 942 static void push_rxbufs(ns_dev * card, struct sk_buff *skb) 943 { 944 struct sk_buff *handle1, *handle2; 945 int id1, id2; 946 u32 addr1, addr2; 947 u32 stat; 948 unsigned long flags; 949 950 /* *BARF* */ 951 handle2 = NULL; 952 addr2 = 0; 953 handle1 = skb; 954 addr1 = dma_map_single(&card->pcidev->dev, 955 skb->data, 956 (NS_PRV_BUFTYPE(skb) == BUF_SM 957 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 958 DMA_TO_DEVICE); 959 NS_PRV_DMA(skb) = addr1; /* save so we can unmap later */ 960 961 #ifdef GENERAL_DEBUG 962 if (!addr1) 963 printk("nicstar%d: push_rxbufs called with addr1 = 0.\n", 964 card->index); 965 #endif /* GENERAL_DEBUG */ 966 967 stat = readl(card->membase + STAT); 968 card->sbfqc = ns_stat_sfbqc_get(stat); 969 card->lbfqc = ns_stat_lfbqc_get(stat); 970 if (NS_PRV_BUFTYPE(skb) == BUF_SM) { 971 if (!addr2) { 972 if (card->sm_addr) { 973 addr2 = card->sm_addr; 974 handle2 = card->sm_handle; 975 card->sm_addr = 0x00000000; 976 card->sm_handle = NULL; 977 } else { /* (!sm_addr) */ 978 979 card->sm_addr = addr1; 980 card->sm_handle = handle1; 981 } 982 } 983 } else { /* buf_type == BUF_LG */ 984 985 if (!addr2) { 986 if (card->lg_addr) { 987 addr2 = card->lg_addr; 988 handle2 = card->lg_handle; 989 card->lg_addr = 0x00000000; 990 card->lg_handle = NULL; 991 } else { /* (!lg_addr) */ 992 993 card->lg_addr = addr1; 994 card->lg_handle = handle1; 995 } 996 } 997 } 998 999 if (addr2) { 1000 if (NS_PRV_BUFTYPE(skb) == BUF_SM) { 1001 if (card->sbfqc >= card->sbnr.max) { 1002 skb_unlink(handle1, &card->sbpool.queue); 1003 dev_kfree_skb_any(handle1); 1004 skb_unlink(handle2, &card->sbpool.queue); 1005 dev_kfree_skb_any(handle2); 1006 return; 1007 } else 1008 card->sbfqc += 2; 1009 } else { /* (buf_type == BUF_LG) */ 1010 1011 if (card->lbfqc >= card->lbnr.max) { 1012 skb_unlink(handle1, &card->lbpool.queue); 1013 dev_kfree_skb_any(handle1); 1014 skb_unlink(handle2, &card->lbpool.queue); 1015 dev_kfree_skb_any(handle2); 1016 return; 1017 } else 1018 card->lbfqc += 2; 1019 } 1020 1021 id1 = idr_alloc(&card->idr, handle1, 0, 0, GFP_ATOMIC); 1022 if (id1 < 0) 1023 goto out; 1024 1025 id2 = idr_alloc(&card->idr, handle2, 0, 0, GFP_ATOMIC); 1026 if (id2 < 0) 1027 goto out; 1028 1029 spin_lock_irqsave(&card->res_lock, flags); 1030 while (CMD_BUSY(card)) ; 1031 writel(addr2, card->membase + DR3); 1032 writel(id2, card->membase + DR2); 1033 writel(addr1, card->membase + DR1); 1034 writel(id1, card->membase + DR0); 1035 writel(NS_CMD_WRITE_FREEBUFQ | NS_PRV_BUFTYPE(skb), 1036 card->membase + CMD); 1037 spin_unlock_irqrestore(&card->res_lock, flags); 1038 1039 XPRINTK("nicstar%d: Pushing %s buffers at 0x%x and 0x%x.\n", 1040 card->index, 1041 (NS_PRV_BUFTYPE(skb) == BUF_SM ? "small" : "large"), 1042 addr1, addr2); 1043 } 1044 1045 if (!card->efbie && card->sbfqc >= card->sbnr.min && 1046 card->lbfqc >= card->lbnr.min) { 1047 card->efbie = 1; 1048 writel((readl(card->membase + CFG) | NS_CFG_EFBIE), 1049 card->membase + CFG); 1050 } 1051 1052 out: 1053 return; 1054 } 1055 1056 static irqreturn_t ns_irq_handler(int irq, void *dev_id) 1057 { 1058 u32 stat_r; 1059 ns_dev *card; 1060 struct atm_dev *dev; 1061 unsigned long flags; 1062 1063 card = (ns_dev *) dev_id; 1064 dev = card->atmdev; 1065 card->intcnt++; 1066 1067 PRINTK("nicstar%d: NICStAR generated an interrupt\n", card->index); 1068 1069 spin_lock_irqsave(&card->int_lock, flags); 1070 1071 stat_r = readl(card->membase + STAT); 1072 1073 /* Transmit Status Indicator has been written to T. S. Queue */ 1074 if (stat_r & NS_STAT_TSIF) { 1075 TXPRINTK("nicstar%d: TSI interrupt\n", card->index); 1076 process_tsq(card); 1077 writel(NS_STAT_TSIF, card->membase + STAT); 1078 } 1079 1080 /* Incomplete CS-PDU has been transmitted */ 1081 if (stat_r & NS_STAT_TXICP) { 1082 writel(NS_STAT_TXICP, card->membase + STAT); 1083 TXPRINTK("nicstar%d: Incomplete CS-PDU transmitted.\n", 1084 card->index); 1085 } 1086 1087 /* Transmit Status Queue 7/8 full */ 1088 if (stat_r & NS_STAT_TSQF) { 1089 writel(NS_STAT_TSQF, card->membase + STAT); 1090 PRINTK("nicstar%d: TSQ full.\n", card->index); 1091 process_tsq(card); 1092 } 1093 1094 /* Timer overflow */ 1095 if (stat_r & NS_STAT_TMROF) { 1096 writel(NS_STAT_TMROF, card->membase + STAT); 1097 PRINTK("nicstar%d: Timer overflow.\n", card->index); 1098 } 1099 1100 /* PHY device interrupt signal active */ 1101 if (stat_r & NS_STAT_PHYI) { 1102 writel(NS_STAT_PHYI, card->membase + STAT); 1103 PRINTK("nicstar%d: PHY interrupt.\n", card->index); 1104 if (dev->phy && dev->phy->interrupt) { 1105 dev->phy->interrupt(dev); 1106 } 1107 } 1108 1109 /* Small Buffer Queue is full */ 1110 if (stat_r & NS_STAT_SFBQF) { 1111 writel(NS_STAT_SFBQF, card->membase + STAT); 1112 printk("nicstar%d: Small free buffer queue is full.\n", 1113 card->index); 1114 } 1115 1116 /* Large Buffer Queue is full */ 1117 if (stat_r & NS_STAT_LFBQF) { 1118 writel(NS_STAT_LFBQF, card->membase + STAT); 1119 printk("nicstar%d: Large free buffer queue is full.\n", 1120 card->index); 1121 } 1122 1123 /* Receive Status Queue is full */ 1124 if (stat_r & NS_STAT_RSQF) { 1125 writel(NS_STAT_RSQF, card->membase + STAT); 1126 printk("nicstar%d: RSQ full.\n", card->index); 1127 process_rsq(card); 1128 } 1129 1130 /* Complete CS-PDU received */ 1131 if (stat_r & NS_STAT_EOPDU) { 1132 RXPRINTK("nicstar%d: End of CS-PDU received.\n", card->index); 1133 process_rsq(card); 1134 writel(NS_STAT_EOPDU, card->membase + STAT); 1135 } 1136 1137 /* Raw cell received */ 1138 if (stat_r & NS_STAT_RAWCF) { 1139 writel(NS_STAT_RAWCF, card->membase + STAT); 1140 #ifndef RCQ_SUPPORT 1141 printk("nicstar%d: Raw cell received and no support yet...\n", 1142 card->index); 1143 #endif /* RCQ_SUPPORT */ 1144 /* NOTE: the following procedure may keep a raw cell pending until the 1145 next interrupt. As this preliminary support is only meant to 1146 avoid buffer leakage, this is not an issue. */ 1147 while (readl(card->membase + RAWCT) != card->rawch) { 1148 1149 if (ns_rcqe_islast(card->rawcell)) { 1150 struct sk_buff *oldbuf; 1151 1152 oldbuf = card->rcbuf; 1153 card->rcbuf = idr_find(&card->idr, 1154 ns_rcqe_nextbufhandle(card->rawcell)); 1155 card->rawch = NS_PRV_DMA(card->rcbuf); 1156 card->rawcell = (struct ns_rcqe *) 1157 card->rcbuf->data; 1158 recycle_rx_buf(card, oldbuf); 1159 } else { 1160 card->rawch += NS_RCQE_SIZE; 1161 card->rawcell++; 1162 } 1163 } 1164 } 1165 1166 /* Small buffer queue is empty */ 1167 if (stat_r & NS_STAT_SFBQE) { 1168 int i; 1169 struct sk_buff *sb; 1170 1171 writel(NS_STAT_SFBQE, card->membase + STAT); 1172 printk("nicstar%d: Small free buffer queue empty.\n", 1173 card->index); 1174 for (i = 0; i < card->sbnr.min; i++) { 1175 sb = dev_alloc_skb(NS_SMSKBSIZE); 1176 if (sb == NULL) { 1177 writel(readl(card->membase + CFG) & 1178 ~NS_CFG_EFBIE, card->membase + CFG); 1179 card->efbie = 0; 1180 break; 1181 } 1182 NS_PRV_BUFTYPE(sb) = BUF_SM; 1183 skb_queue_tail(&card->sbpool.queue, sb); 1184 skb_reserve(sb, NS_AAL0_HEADER); 1185 push_rxbufs(card, sb); 1186 } 1187 card->sbfqc = i; 1188 process_rsq(card); 1189 } 1190 1191 /* Large buffer queue empty */ 1192 if (stat_r & NS_STAT_LFBQE) { 1193 int i; 1194 struct sk_buff *lb; 1195 1196 writel(NS_STAT_LFBQE, card->membase + STAT); 1197 printk("nicstar%d: Large free buffer queue empty.\n", 1198 card->index); 1199 for (i = 0; i < card->lbnr.min; i++) { 1200 lb = dev_alloc_skb(NS_LGSKBSIZE); 1201 if (lb == NULL) { 1202 writel(readl(card->membase + CFG) & 1203 ~NS_CFG_EFBIE, card->membase + CFG); 1204 card->efbie = 0; 1205 break; 1206 } 1207 NS_PRV_BUFTYPE(lb) = BUF_LG; 1208 skb_queue_tail(&card->lbpool.queue, lb); 1209 skb_reserve(lb, NS_SMBUFSIZE); 1210 push_rxbufs(card, lb); 1211 } 1212 card->lbfqc = i; 1213 process_rsq(card); 1214 } 1215 1216 /* Receive Status Queue is 7/8 full */ 1217 if (stat_r & NS_STAT_RSQAF) { 1218 writel(NS_STAT_RSQAF, card->membase + STAT); 1219 RXPRINTK("nicstar%d: RSQ almost full.\n", card->index); 1220 process_rsq(card); 1221 } 1222 1223 spin_unlock_irqrestore(&card->int_lock, flags); 1224 PRINTK("nicstar%d: end of interrupt service\n", card->index); 1225 return IRQ_HANDLED; 1226 } 1227 1228 static int ns_open(struct atm_vcc *vcc) 1229 { 1230 ns_dev *card; 1231 vc_map *vc; 1232 unsigned long tmpl, modl; 1233 int tcr, tcra; /* target cell rate, and absolute value */ 1234 int n = 0; /* Number of entries in the TST. Initialized to remove 1235 the compiler warning. */ 1236 u32 u32d[4]; 1237 int frscdi = 0; /* Index of the SCD. Initialized to remove the compiler 1238 warning. How I wish compilers were clever enough to 1239 tell which variables can truly be used 1240 uninitialized... */ 1241 int inuse; /* tx or rx vc already in use by another vcc */ 1242 short vpi = vcc->vpi; 1243 int vci = vcc->vci; 1244 1245 card = (ns_dev *) vcc->dev->dev_data; 1246 PRINTK("nicstar%d: opening vpi.vci %d.%d \n", card->index, (int)vpi, 1247 vci); 1248 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) { 1249 PRINTK("nicstar%d: unsupported AAL.\n", card->index); 1250 return -EINVAL; 1251 } 1252 1253 vc = &(card->vcmap[vpi << card->vcibits | vci]); 1254 vcc->dev_data = vc; 1255 1256 inuse = 0; 1257 if (vcc->qos.txtp.traffic_class != ATM_NONE && vc->tx) 1258 inuse = 1; 1259 if (vcc->qos.rxtp.traffic_class != ATM_NONE && vc->rx) 1260 inuse += 2; 1261 if (inuse) { 1262 printk("nicstar%d: %s vci already in use.\n", card->index, 1263 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 1264 return -EINVAL; 1265 } 1266 1267 set_bit(ATM_VF_ADDR, &vcc->flags); 1268 1269 /* NOTE: You are not allowed to modify an open connection's QOS. To change 1270 that, remove the ATM_VF_PARTIAL flag checking. There may be other changes 1271 needed to do that. */ 1272 if (!test_bit(ATM_VF_PARTIAL, &vcc->flags)) { 1273 scq_info *scq; 1274 1275 set_bit(ATM_VF_PARTIAL, &vcc->flags); 1276 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1277 /* Check requested cell rate and availability of SCD */ 1278 if (vcc->qos.txtp.max_pcr == 0 && vcc->qos.txtp.pcr == 0 1279 && vcc->qos.txtp.min_pcr == 0) { 1280 PRINTK 1281 ("nicstar%d: trying to open a CBR vc with cell rate = 0 \n", 1282 card->index); 1283 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1284 clear_bit(ATM_VF_ADDR, &vcc->flags); 1285 return -EINVAL; 1286 } 1287 1288 tcr = atm_pcr_goal(&(vcc->qos.txtp)); 1289 tcra = tcr >= 0 ? tcr : -tcr; 1290 1291 PRINTK("nicstar%d: target cell rate = %d.\n", 1292 card->index, vcc->qos.txtp.max_pcr); 1293 1294 tmpl = 1295 (unsigned long)tcra *(unsigned long) 1296 NS_TST_NUM_ENTRIES; 1297 modl = tmpl % card->max_pcr; 1298 1299 n = (int)(tmpl / card->max_pcr); 1300 if (tcr > 0) { 1301 if (modl > 0) 1302 n++; 1303 } else if (tcr == 0) { 1304 if ((n = 1305 (card->tst_free_entries - 1306 NS_TST_RESERVED)) <= 0) { 1307 PRINTK 1308 ("nicstar%d: no CBR bandwidth free.\n", 1309 card->index); 1310 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1311 clear_bit(ATM_VF_ADDR, &vcc->flags); 1312 return -EINVAL; 1313 } 1314 } 1315 1316 if (n == 0) { 1317 printk 1318 ("nicstar%d: selected bandwidth < granularity.\n", 1319 card->index); 1320 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1321 clear_bit(ATM_VF_ADDR, &vcc->flags); 1322 return -EINVAL; 1323 } 1324 1325 if (n > (card->tst_free_entries - NS_TST_RESERVED)) { 1326 PRINTK 1327 ("nicstar%d: not enough free CBR bandwidth.\n", 1328 card->index); 1329 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1330 clear_bit(ATM_VF_ADDR, &vcc->flags); 1331 return -EINVAL; 1332 } else 1333 card->tst_free_entries -= n; 1334 1335 XPRINTK("nicstar%d: writing %d tst entries.\n", 1336 card->index, n); 1337 for (frscdi = 0; frscdi < NS_FRSCD_NUM; frscdi++) { 1338 if (card->scd2vc[frscdi] == NULL) { 1339 card->scd2vc[frscdi] = vc; 1340 break; 1341 } 1342 } 1343 if (frscdi == NS_FRSCD_NUM) { 1344 PRINTK 1345 ("nicstar%d: no SCD available for CBR channel.\n", 1346 card->index); 1347 card->tst_free_entries += n; 1348 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1349 clear_bit(ATM_VF_ADDR, &vcc->flags); 1350 return -EBUSY; 1351 } 1352 1353 vc->cbr_scd = NS_FRSCD + frscdi * NS_FRSCD_SIZE; 1354 1355 scq = get_scq(card, CBR_SCQSIZE, vc->cbr_scd); 1356 if (scq == NULL) { 1357 PRINTK("nicstar%d: can't get fixed rate SCQ.\n", 1358 card->index); 1359 card->scd2vc[frscdi] = NULL; 1360 card->tst_free_entries += n; 1361 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1362 clear_bit(ATM_VF_ADDR, &vcc->flags); 1363 return -ENOMEM; 1364 } 1365 vc->scq = scq; 1366 u32d[0] = scq_virt_to_bus(scq, scq->base); 1367 u32d[1] = (u32) 0x00000000; 1368 u32d[2] = (u32) 0xffffffff; 1369 u32d[3] = (u32) 0x00000000; 1370 ns_write_sram(card, vc->cbr_scd, u32d, 4); 1371 1372 fill_tst(card, n, vc); 1373 } else if (vcc->qos.txtp.traffic_class == ATM_UBR) { 1374 vc->cbr_scd = 0x00000000; 1375 vc->scq = card->scq0; 1376 } 1377 1378 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1379 vc->tx = 1; 1380 vc->tx_vcc = vcc; 1381 vc->tbd_count = 0; 1382 } 1383 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 1384 u32 status; 1385 1386 vc->rx = 1; 1387 vc->rx_vcc = vcc; 1388 vc->rx_iov = NULL; 1389 1390 /* Open the connection in hardware */ 1391 if (vcc->qos.aal == ATM_AAL5) 1392 status = NS_RCTE_AAL5 | NS_RCTE_CONNECTOPEN; 1393 else /* vcc->qos.aal == ATM_AAL0 */ 1394 status = NS_RCTE_AAL0 | NS_RCTE_CONNECTOPEN; 1395 #ifdef RCQ_SUPPORT 1396 status |= NS_RCTE_RAWCELLINTEN; 1397 #endif /* RCQ_SUPPORT */ 1398 ns_write_sram(card, 1399 NS_RCT + 1400 (vpi << card->vcibits | vci) * 1401 NS_RCT_ENTRY_SIZE, &status, 1); 1402 } 1403 1404 } 1405 1406 set_bit(ATM_VF_READY, &vcc->flags); 1407 return 0; 1408 } 1409 1410 static void ns_close(struct atm_vcc *vcc) 1411 { 1412 vc_map *vc; 1413 ns_dev *card; 1414 u32 data; 1415 int i; 1416 1417 vc = vcc->dev_data; 1418 card = vcc->dev->dev_data; 1419 PRINTK("nicstar%d: closing vpi.vci %d.%d \n", card->index, 1420 (int)vcc->vpi, vcc->vci); 1421 1422 clear_bit(ATM_VF_READY, &vcc->flags); 1423 1424 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 1425 u32 addr; 1426 unsigned long flags; 1427 1428 addr = 1429 NS_RCT + 1430 (vcc->vpi << card->vcibits | vcc->vci) * NS_RCT_ENTRY_SIZE; 1431 spin_lock_irqsave(&card->res_lock, flags); 1432 while (CMD_BUSY(card)) ; 1433 writel(NS_CMD_CLOSE_CONNECTION | addr << 2, 1434 card->membase + CMD); 1435 spin_unlock_irqrestore(&card->res_lock, flags); 1436 1437 vc->rx = 0; 1438 if (vc->rx_iov != NULL) { 1439 struct sk_buff *iovb; 1440 u32 stat; 1441 1442 stat = readl(card->membase + STAT); 1443 card->sbfqc = ns_stat_sfbqc_get(stat); 1444 card->lbfqc = ns_stat_lfbqc_get(stat); 1445 1446 PRINTK 1447 ("nicstar%d: closing a VC with pending rx buffers.\n", 1448 card->index); 1449 iovb = vc->rx_iov; 1450 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 1451 NS_PRV_IOVCNT(iovb)); 1452 NS_PRV_IOVCNT(iovb) = 0; 1453 spin_lock_irqsave(&card->int_lock, flags); 1454 recycle_iov_buf(card, iovb); 1455 spin_unlock_irqrestore(&card->int_lock, flags); 1456 vc->rx_iov = NULL; 1457 } 1458 } 1459 1460 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1461 vc->tx = 0; 1462 } 1463 1464 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1465 unsigned long flags; 1466 ns_scqe *scqep; 1467 scq_info *scq; 1468 1469 scq = vc->scq; 1470 1471 for (;;) { 1472 spin_lock_irqsave(&scq->lock, flags); 1473 scqep = scq->next; 1474 if (scqep == scq->base) 1475 scqep = scq->last; 1476 else 1477 scqep--; 1478 if (scqep == scq->tail) { 1479 spin_unlock_irqrestore(&scq->lock, flags); 1480 break; 1481 } 1482 /* If the last entry is not a TSR, place one in the SCQ in order to 1483 be able to completely drain it and then close. */ 1484 if (!ns_scqe_is_tsr(scqep) && scq->tail != scq->next) { 1485 ns_scqe tsr; 1486 u32 scdi, scqi; 1487 u32 data; 1488 int index; 1489 1490 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1491 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1492 scqi = scq->next - scq->base; 1493 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1494 tsr.word_3 = 0x00000000; 1495 tsr.word_4 = 0x00000000; 1496 *scq->next = tsr; 1497 index = (int)scqi; 1498 scq->skb[index] = NULL; 1499 if (scq->next == scq->last) 1500 scq->next = scq->base; 1501 else 1502 scq->next++; 1503 data = scq_virt_to_bus(scq, scq->next); 1504 ns_write_sram(card, scq->scd, &data, 1); 1505 } 1506 spin_unlock_irqrestore(&scq->lock, flags); 1507 schedule(); 1508 } 1509 1510 /* Free all TST entries */ 1511 data = NS_TST_OPCODE_VARIABLE; 1512 for (i = 0; i < NS_TST_NUM_ENTRIES; i++) { 1513 if (card->tste2vc[i] == vc) { 1514 ns_write_sram(card, card->tst_addr + i, &data, 1515 1); 1516 card->tste2vc[i] = NULL; 1517 card->tst_free_entries++; 1518 } 1519 } 1520 1521 card->scd2vc[(vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE] = NULL; 1522 free_scq(card, vc->scq, vcc); 1523 } 1524 1525 /* remove all references to vcc before deleting it */ 1526 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 1527 unsigned long flags; 1528 scq_info *scq = card->scq0; 1529 1530 spin_lock_irqsave(&scq->lock, flags); 1531 1532 for (i = 0; i < scq->num_entries; i++) { 1533 if (scq->skb[i] && ATM_SKB(scq->skb[i])->vcc == vcc) { 1534 ATM_SKB(scq->skb[i])->vcc = NULL; 1535 atm_return(vcc, scq->skb[i]->truesize); 1536 PRINTK 1537 ("nicstar: deleted pending vcc mapping\n"); 1538 } 1539 } 1540 1541 spin_unlock_irqrestore(&scq->lock, flags); 1542 } 1543 1544 vcc->dev_data = NULL; 1545 clear_bit(ATM_VF_PARTIAL, &vcc->flags); 1546 clear_bit(ATM_VF_ADDR, &vcc->flags); 1547 1548 #ifdef RX_DEBUG 1549 { 1550 u32 stat, cfg; 1551 stat = readl(card->membase + STAT); 1552 cfg = readl(card->membase + CFG); 1553 printk("STAT = 0x%08X CFG = 0x%08X \n", stat, cfg); 1554 printk 1555 ("TSQ: base = 0x%p next = 0x%p last = 0x%p TSQT = 0x%08X \n", 1556 card->tsq.base, card->tsq.next, 1557 card->tsq.last, readl(card->membase + TSQT)); 1558 printk 1559 ("RSQ: base = 0x%p next = 0x%p last = 0x%p RSQT = 0x%08X \n", 1560 card->rsq.base, card->rsq.next, 1561 card->rsq.last, readl(card->membase + RSQT)); 1562 printk("Empty free buffer queue interrupt %s \n", 1563 card->efbie ? "enabled" : "disabled"); 1564 printk("SBCNT = %d count = %d LBCNT = %d count = %d \n", 1565 ns_stat_sfbqc_get(stat), card->sbpool.count, 1566 ns_stat_lfbqc_get(stat), card->lbpool.count); 1567 printk("hbpool.count = %d iovpool.count = %d \n", 1568 card->hbpool.count, card->iovpool.count); 1569 } 1570 #endif /* RX_DEBUG */ 1571 } 1572 1573 static void fill_tst(ns_dev * card, int n, vc_map * vc) 1574 { 1575 u32 new_tst; 1576 unsigned long cl; 1577 int e, r; 1578 u32 data; 1579 1580 /* It would be very complicated to keep the two TSTs synchronized while 1581 assuring that writes are only made to the inactive TST. So, for now I 1582 will use only one TST. If problems occur, I will change this again */ 1583 1584 new_tst = card->tst_addr; 1585 1586 /* Fill procedure */ 1587 1588 for (e = 0; e < NS_TST_NUM_ENTRIES; e++) { 1589 if (card->tste2vc[e] == NULL) 1590 break; 1591 } 1592 if (e == NS_TST_NUM_ENTRIES) { 1593 printk("nicstar%d: No free TST entries found. \n", card->index); 1594 return; 1595 } 1596 1597 r = n; 1598 cl = NS_TST_NUM_ENTRIES; 1599 data = ns_tste_make(NS_TST_OPCODE_FIXED, vc->cbr_scd); 1600 1601 while (r > 0) { 1602 if (cl >= NS_TST_NUM_ENTRIES && card->tste2vc[e] == NULL) { 1603 card->tste2vc[e] = vc; 1604 ns_write_sram(card, new_tst + e, &data, 1); 1605 cl -= NS_TST_NUM_ENTRIES; 1606 r--; 1607 } 1608 1609 if (++e == NS_TST_NUM_ENTRIES) { 1610 e = 0; 1611 } 1612 cl += n; 1613 } 1614 1615 /* End of fill procedure */ 1616 1617 data = ns_tste_make(NS_TST_OPCODE_END, new_tst); 1618 ns_write_sram(card, new_tst + NS_TST_NUM_ENTRIES, &data, 1); 1619 ns_write_sram(card, card->tst_addr + NS_TST_NUM_ENTRIES, &data, 1); 1620 card->tst_addr = new_tst; 1621 } 1622 1623 static int _ns_send(struct atm_vcc *vcc, struct sk_buff *skb, bool may_sleep) 1624 { 1625 ns_dev *card; 1626 vc_map *vc; 1627 scq_info *scq; 1628 unsigned long buflen; 1629 ns_scqe scqe; 1630 u32 flags; /* TBD flags, not CPU flags */ 1631 1632 card = vcc->dev->dev_data; 1633 TXPRINTK("nicstar%d: ns_send() called.\n", card->index); 1634 if ((vc = (vc_map *) vcc->dev_data) == NULL) { 1635 printk("nicstar%d: vcc->dev_data == NULL on ns_send().\n", 1636 card->index); 1637 atomic_inc(&vcc->stats->tx_err); 1638 dev_kfree_skb_any(skb); 1639 return -EINVAL; 1640 } 1641 1642 if (!vc->tx) { 1643 printk("nicstar%d: Trying to transmit on a non-tx VC.\n", 1644 card->index); 1645 atomic_inc(&vcc->stats->tx_err); 1646 dev_kfree_skb_any(skb); 1647 return -EINVAL; 1648 } 1649 1650 if (vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0) { 1651 printk("nicstar%d: Only AAL0 and AAL5 are supported.\n", 1652 card->index); 1653 atomic_inc(&vcc->stats->tx_err); 1654 dev_kfree_skb_any(skb); 1655 return -EINVAL; 1656 } 1657 1658 if (skb_shinfo(skb)->nr_frags != 0) { 1659 printk("nicstar%d: No scatter-gather yet.\n", card->index); 1660 atomic_inc(&vcc->stats->tx_err); 1661 dev_kfree_skb_any(skb); 1662 return -EINVAL; 1663 } 1664 1665 ATM_SKB(skb)->vcc = vcc; 1666 1667 NS_PRV_DMA(skb) = dma_map_single(&card->pcidev->dev, skb->data, 1668 skb->len, DMA_TO_DEVICE); 1669 1670 if (vcc->qos.aal == ATM_AAL5) { 1671 buflen = (skb->len + 47 + 8) / 48 * 48; /* Multiple of 48 */ 1672 flags = NS_TBD_AAL5; 1673 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb)); 1674 scqe.word_3 = cpu_to_le32(skb->len); 1675 scqe.word_4 = 1676 ns_tbd_mkword_4(0, (u32) vcc->vpi, (u32) vcc->vci, 0, 1677 ATM_SKB(skb)-> 1678 atm_options & ATM_ATMOPT_CLP ? 1 : 0); 1679 flags |= NS_TBD_EOPDU; 1680 } else { /* (vcc->qos.aal == ATM_AAL0) */ 1681 1682 buflen = ATM_CELL_PAYLOAD; /* i.e., 48 bytes */ 1683 flags = NS_TBD_AAL0; 1684 scqe.word_2 = cpu_to_le32(NS_PRV_DMA(skb) + NS_AAL0_HEADER); 1685 scqe.word_3 = cpu_to_le32(0x00000000); 1686 if (*skb->data & 0x02) /* Payload type 1 - end of pdu */ 1687 flags |= NS_TBD_EOPDU; 1688 scqe.word_4 = 1689 cpu_to_le32(*((u32 *) skb->data) & ~NS_TBD_VC_MASK); 1690 /* Force the VPI/VCI to be the same as in VCC struct */ 1691 scqe.word_4 |= 1692 cpu_to_le32((((u32) vcc-> 1693 vpi) << NS_TBD_VPI_SHIFT | ((u32) vcc-> 1694 vci) << 1695 NS_TBD_VCI_SHIFT) & NS_TBD_VC_MASK); 1696 } 1697 1698 if (vcc->qos.txtp.traffic_class == ATM_CBR) { 1699 scqe.word_1 = ns_tbd_mkword_1_novbr(flags, (u32) buflen); 1700 scq = ((vc_map *) vcc->dev_data)->scq; 1701 } else { 1702 scqe.word_1 = 1703 ns_tbd_mkword_1(flags, (u32) 1, (u32) 1, (u32) buflen); 1704 scq = card->scq0; 1705 } 1706 1707 if (push_scqe(card, vc, scq, &scqe, skb, may_sleep) != 0) { 1708 atomic_inc(&vcc->stats->tx_err); 1709 dma_unmap_single(&card->pcidev->dev, NS_PRV_DMA(skb), skb->len, 1710 DMA_TO_DEVICE); 1711 dev_kfree_skb_any(skb); 1712 return -EIO; 1713 } 1714 atomic_inc(&vcc->stats->tx); 1715 1716 return 0; 1717 } 1718 1719 static int ns_send(struct atm_vcc *vcc, struct sk_buff *skb) 1720 { 1721 return _ns_send(vcc, skb, true); 1722 } 1723 1724 static int ns_send_bh(struct atm_vcc *vcc, struct sk_buff *skb) 1725 { 1726 return _ns_send(vcc, skb, false); 1727 } 1728 1729 static int push_scqe(ns_dev * card, vc_map * vc, scq_info * scq, ns_scqe * tbd, 1730 struct sk_buff *skb, bool may_sleep) 1731 { 1732 unsigned long flags; 1733 ns_scqe tsr; 1734 u32 scdi, scqi; 1735 int scq_is_vbr; 1736 u32 data; 1737 int index; 1738 1739 spin_lock_irqsave(&scq->lock, flags); 1740 while (scq->tail == scq->next) { 1741 if (!may_sleep) { 1742 spin_unlock_irqrestore(&scq->lock, flags); 1743 printk("nicstar%d: Error pushing TBD.\n", card->index); 1744 return 1; 1745 } 1746 1747 scq->full = 1; 1748 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq, 1749 scq->tail != scq->next, 1750 scq->lock, 1751 SCQFULL_TIMEOUT); 1752 1753 if (scq->full) { 1754 spin_unlock_irqrestore(&scq->lock, flags); 1755 printk("nicstar%d: Timeout pushing TBD.\n", 1756 card->index); 1757 return 1; 1758 } 1759 } 1760 *scq->next = *tbd; 1761 index = (int)(scq->next - scq->base); 1762 scq->skb[index] = skb; 1763 XPRINTK("nicstar%d: sending skb at 0x%p (pos %d).\n", 1764 card->index, skb, index); 1765 XPRINTK("nicstar%d: TBD written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n", 1766 card->index, le32_to_cpu(tbd->word_1), le32_to_cpu(tbd->word_2), 1767 le32_to_cpu(tbd->word_3), le32_to_cpu(tbd->word_4), 1768 scq->next); 1769 if (scq->next == scq->last) 1770 scq->next = scq->base; 1771 else 1772 scq->next++; 1773 1774 vc->tbd_count++; 1775 if (scq->num_entries == VBR_SCQ_NUM_ENTRIES) { 1776 scq->tbd_count++; 1777 scq_is_vbr = 1; 1778 } else 1779 scq_is_vbr = 0; 1780 1781 if (vc->tbd_count >= MAX_TBD_PER_VC 1782 || scq->tbd_count >= MAX_TBD_PER_SCQ) { 1783 int has_run = 0; 1784 1785 while (scq->tail == scq->next) { 1786 if (!may_sleep) { 1787 data = scq_virt_to_bus(scq, scq->next); 1788 ns_write_sram(card, scq->scd, &data, 1); 1789 spin_unlock_irqrestore(&scq->lock, flags); 1790 printk("nicstar%d: Error pushing TSR.\n", 1791 card->index); 1792 return 0; 1793 } 1794 1795 scq->full = 1; 1796 if (has_run++) 1797 break; 1798 wait_event_interruptible_lock_irq_timeout(scq->scqfull_waitq, 1799 scq->tail != scq->next, 1800 scq->lock, 1801 SCQFULL_TIMEOUT); 1802 } 1803 1804 if (!scq->full) { 1805 tsr.word_1 = ns_tsr_mkword_1(NS_TSR_INTENABLE); 1806 if (scq_is_vbr) 1807 scdi = NS_TSR_SCDISVBR; 1808 else 1809 scdi = (vc->cbr_scd - NS_FRSCD) / NS_FRSCD_SIZE; 1810 scqi = scq->next - scq->base; 1811 tsr.word_2 = ns_tsr_mkword_2(scdi, scqi); 1812 tsr.word_3 = 0x00000000; 1813 tsr.word_4 = 0x00000000; 1814 1815 *scq->next = tsr; 1816 index = (int)scqi; 1817 scq->skb[index] = NULL; 1818 XPRINTK 1819 ("nicstar%d: TSR written:\n0x%x\n0x%x\n0x%x\n0x%x\n at 0x%p.\n", 1820 card->index, le32_to_cpu(tsr.word_1), 1821 le32_to_cpu(tsr.word_2), le32_to_cpu(tsr.word_3), 1822 le32_to_cpu(tsr.word_4), scq->next); 1823 if (scq->next == scq->last) 1824 scq->next = scq->base; 1825 else 1826 scq->next++; 1827 vc->tbd_count = 0; 1828 scq->tbd_count = 0; 1829 } else 1830 PRINTK("nicstar%d: Timeout pushing TSR.\n", 1831 card->index); 1832 } 1833 data = scq_virt_to_bus(scq, scq->next); 1834 ns_write_sram(card, scq->scd, &data, 1); 1835 1836 spin_unlock_irqrestore(&scq->lock, flags); 1837 1838 return 0; 1839 } 1840 1841 static void process_tsq(ns_dev * card) 1842 { 1843 u32 scdi; 1844 scq_info *scq; 1845 ns_tsi *previous = NULL, *one_ahead, *two_ahead; 1846 int serviced_entries; /* flag indicating at least on entry was serviced */ 1847 1848 serviced_entries = 0; 1849 1850 if (card->tsq.next == card->tsq.last) 1851 one_ahead = card->tsq.base; 1852 else 1853 one_ahead = card->tsq.next + 1; 1854 1855 if (one_ahead == card->tsq.last) 1856 two_ahead = card->tsq.base; 1857 else 1858 two_ahead = one_ahead + 1; 1859 1860 while (!ns_tsi_isempty(card->tsq.next) || !ns_tsi_isempty(one_ahead) || 1861 !ns_tsi_isempty(two_ahead)) 1862 /* At most two empty, as stated in the 77201 errata */ 1863 { 1864 serviced_entries = 1; 1865 1866 /* Skip the one or two possible empty entries */ 1867 while (ns_tsi_isempty(card->tsq.next)) { 1868 if (card->tsq.next == card->tsq.last) 1869 card->tsq.next = card->tsq.base; 1870 else 1871 card->tsq.next++; 1872 } 1873 1874 if (!ns_tsi_tmrof(card->tsq.next)) { 1875 scdi = ns_tsi_getscdindex(card->tsq.next); 1876 if (scdi == NS_TSI_SCDISVBR) 1877 scq = card->scq0; 1878 else { 1879 if (card->scd2vc[scdi] == NULL) { 1880 printk 1881 ("nicstar%d: could not find VC from SCD index.\n", 1882 card->index); 1883 ns_tsi_init(card->tsq.next); 1884 return; 1885 } 1886 scq = card->scd2vc[scdi]->scq; 1887 } 1888 drain_scq(card, scq, ns_tsi_getscqpos(card->tsq.next)); 1889 scq->full = 0; 1890 wake_up_interruptible(&(scq->scqfull_waitq)); 1891 } 1892 1893 ns_tsi_init(card->tsq.next); 1894 previous = card->tsq.next; 1895 if (card->tsq.next == card->tsq.last) 1896 card->tsq.next = card->tsq.base; 1897 else 1898 card->tsq.next++; 1899 1900 if (card->tsq.next == card->tsq.last) 1901 one_ahead = card->tsq.base; 1902 else 1903 one_ahead = card->tsq.next + 1; 1904 1905 if (one_ahead == card->tsq.last) 1906 two_ahead = card->tsq.base; 1907 else 1908 two_ahead = one_ahead + 1; 1909 } 1910 1911 if (serviced_entries) 1912 writel(PTR_DIFF(previous, card->tsq.base), 1913 card->membase + TSQH); 1914 } 1915 1916 static void drain_scq(ns_dev * card, scq_info * scq, int pos) 1917 { 1918 struct atm_vcc *vcc; 1919 struct sk_buff *skb; 1920 int i; 1921 unsigned long flags; 1922 1923 XPRINTK("nicstar%d: drain_scq() called, scq at 0x%p, pos %d.\n", 1924 card->index, scq, pos); 1925 if (pos >= scq->num_entries) { 1926 printk("nicstar%d: Bad index on drain_scq().\n", card->index); 1927 return; 1928 } 1929 1930 spin_lock_irqsave(&scq->lock, flags); 1931 i = (int)(scq->tail - scq->base); 1932 if (++i == scq->num_entries) 1933 i = 0; 1934 while (i != pos) { 1935 skb = scq->skb[i]; 1936 XPRINTK("nicstar%d: freeing skb at 0x%p (index %d).\n", 1937 card->index, skb, i); 1938 if (skb != NULL) { 1939 dma_unmap_single(&card->pcidev->dev, 1940 NS_PRV_DMA(skb), 1941 skb->len, 1942 DMA_TO_DEVICE); 1943 vcc = ATM_SKB(skb)->vcc; 1944 if (vcc && vcc->pop != NULL) { 1945 vcc->pop(vcc, skb); 1946 } else { 1947 dev_kfree_skb_irq(skb); 1948 } 1949 scq->skb[i] = NULL; 1950 } 1951 if (++i == scq->num_entries) 1952 i = 0; 1953 } 1954 scq->tail = scq->base + pos; 1955 spin_unlock_irqrestore(&scq->lock, flags); 1956 } 1957 1958 static void process_rsq(ns_dev * card) 1959 { 1960 ns_rsqe *previous; 1961 1962 if (!ns_rsqe_valid(card->rsq.next)) 1963 return; 1964 do { 1965 dequeue_rx(card, card->rsq.next); 1966 ns_rsqe_init(card->rsq.next); 1967 previous = card->rsq.next; 1968 if (card->rsq.next == card->rsq.last) 1969 card->rsq.next = card->rsq.base; 1970 else 1971 card->rsq.next++; 1972 } while (ns_rsqe_valid(card->rsq.next)); 1973 writel(PTR_DIFF(previous, card->rsq.base), card->membase + RSQH); 1974 } 1975 1976 static void dequeue_rx(ns_dev * card, ns_rsqe * rsqe) 1977 { 1978 u32 vpi, vci; 1979 vc_map *vc; 1980 struct sk_buff *iovb; 1981 struct iovec *iov; 1982 struct atm_vcc *vcc; 1983 struct sk_buff *skb; 1984 unsigned short aal5_len; 1985 int len; 1986 u32 stat; 1987 u32 id; 1988 1989 stat = readl(card->membase + STAT); 1990 card->sbfqc = ns_stat_sfbqc_get(stat); 1991 card->lbfqc = ns_stat_lfbqc_get(stat); 1992 1993 id = le32_to_cpu(rsqe->buffer_handle); 1994 skb = idr_remove(&card->idr, id); 1995 if (!skb) { 1996 RXPRINTK(KERN_ERR 1997 "nicstar%d: skb not found!\n", card->index); 1998 return; 1999 } 2000 dma_sync_single_for_cpu(&card->pcidev->dev, 2001 NS_PRV_DMA(skb), 2002 (NS_PRV_BUFTYPE(skb) == BUF_SM 2003 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 2004 DMA_FROM_DEVICE); 2005 dma_unmap_single(&card->pcidev->dev, 2006 NS_PRV_DMA(skb), 2007 (NS_PRV_BUFTYPE(skb) == BUF_SM 2008 ? NS_SMSKBSIZE : NS_LGSKBSIZE), 2009 DMA_FROM_DEVICE); 2010 vpi = ns_rsqe_vpi(rsqe); 2011 vci = ns_rsqe_vci(rsqe); 2012 if (vpi >= 1UL << card->vpibits || vci >= 1UL << card->vcibits) { 2013 printk("nicstar%d: SDU received for out-of-range vc %d.%d.\n", 2014 card->index, vpi, vci); 2015 recycle_rx_buf(card, skb); 2016 return; 2017 } 2018 2019 vc = &(card->vcmap[vpi << card->vcibits | vci]); 2020 if (!vc->rx) { 2021 RXPRINTK("nicstar%d: SDU received on non-rx vc %d.%d.\n", 2022 card->index, vpi, vci); 2023 recycle_rx_buf(card, skb); 2024 return; 2025 } 2026 2027 vcc = vc->rx_vcc; 2028 2029 if (vcc->qos.aal == ATM_AAL0) { 2030 struct sk_buff *sb; 2031 unsigned char *cell; 2032 int i; 2033 2034 cell = skb->data; 2035 for (i = ns_rsqe_cellcount(rsqe); i; i--) { 2036 sb = dev_alloc_skb(NS_SMSKBSIZE); 2037 if (!sb) { 2038 printk 2039 ("nicstar%d: Can't allocate buffers for aal0.\n", 2040 card->index); 2041 atomic_add(i, &vcc->stats->rx_drop); 2042 break; 2043 } 2044 if (!atm_charge(vcc, sb->truesize)) { 2045 RXPRINTK 2046 ("nicstar%d: atm_charge() dropped aal0 packets.\n", 2047 card->index); 2048 atomic_add(i - 1, &vcc->stats->rx_drop); /* already increased by 1 */ 2049 dev_kfree_skb_any(sb); 2050 break; 2051 } 2052 /* Rebuild the header */ 2053 *((u32 *) sb->data) = le32_to_cpu(rsqe->word_1) << 4 | 2054 (ns_rsqe_clp(rsqe) ? 0x00000001 : 0x00000000); 2055 if (i == 1 && ns_rsqe_eopdu(rsqe)) 2056 *((u32 *) sb->data) |= 0x00000002; 2057 skb_put(sb, NS_AAL0_HEADER); 2058 memcpy(skb_tail_pointer(sb), cell, ATM_CELL_PAYLOAD); 2059 skb_put(sb, ATM_CELL_PAYLOAD); 2060 ATM_SKB(sb)->vcc = vcc; 2061 __net_timestamp(sb); 2062 vcc->push(vcc, sb); 2063 atomic_inc(&vcc->stats->rx); 2064 cell += ATM_CELL_PAYLOAD; 2065 } 2066 2067 recycle_rx_buf(card, skb); 2068 return; 2069 } 2070 2071 /* To reach this point, the AAL layer can only be AAL5 */ 2072 2073 if ((iovb = vc->rx_iov) == NULL) { 2074 iovb = skb_dequeue(&(card->iovpool.queue)); 2075 if (iovb == NULL) { /* No buffers in the queue */ 2076 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC); 2077 if (iovb == NULL) { 2078 printk("nicstar%d: Out of iovec buffers.\n", 2079 card->index); 2080 atomic_inc(&vcc->stats->rx_drop); 2081 recycle_rx_buf(card, skb); 2082 return; 2083 } 2084 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2085 } else if (--card->iovpool.count < card->iovnr.min) { 2086 struct sk_buff *new_iovb; 2087 if ((new_iovb = 2088 alloc_skb(NS_IOVBUFSIZE, GFP_ATOMIC)) != NULL) { 2089 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2090 skb_queue_tail(&card->iovpool.queue, new_iovb); 2091 card->iovpool.count++; 2092 } 2093 } 2094 vc->rx_iov = iovb; 2095 NS_PRV_IOVCNT(iovb) = 0; 2096 iovb->len = 0; 2097 iovb->data = iovb->head; 2098 skb_reset_tail_pointer(iovb); 2099 /* IMPORTANT: a pointer to the sk_buff containing the small or large 2100 buffer is stored as iovec base, NOT a pointer to the 2101 small or large buffer itself. */ 2102 } else if (NS_PRV_IOVCNT(iovb) >= NS_MAX_IOVECS) { 2103 printk("nicstar%d: received too big AAL5 SDU.\n", card->index); 2104 atomic_inc(&vcc->stats->rx_err); 2105 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2106 NS_MAX_IOVECS); 2107 NS_PRV_IOVCNT(iovb) = 0; 2108 iovb->len = 0; 2109 iovb->data = iovb->head; 2110 skb_reset_tail_pointer(iovb); 2111 } 2112 iov = &((struct iovec *)iovb->data)[NS_PRV_IOVCNT(iovb)++]; 2113 iov->iov_base = (void *)skb; 2114 iov->iov_len = ns_rsqe_cellcount(rsqe) * 48; 2115 iovb->len += iov->iov_len; 2116 2117 #ifdef EXTRA_DEBUG 2118 if (NS_PRV_IOVCNT(iovb) == 1) { 2119 if (NS_PRV_BUFTYPE(skb) != BUF_SM) { 2120 printk 2121 ("nicstar%d: Expected a small buffer, and this is not one.\n", 2122 card->index); 2123 which_list(card, skb); 2124 atomic_inc(&vcc->stats->rx_err); 2125 recycle_rx_buf(card, skb); 2126 vc->rx_iov = NULL; 2127 recycle_iov_buf(card, iovb); 2128 return; 2129 } 2130 } else { /* NS_PRV_IOVCNT(iovb) >= 2 */ 2131 2132 if (NS_PRV_BUFTYPE(skb) != BUF_LG) { 2133 printk 2134 ("nicstar%d: Expected a large buffer, and this is not one.\n", 2135 card->index); 2136 which_list(card, skb); 2137 atomic_inc(&vcc->stats->rx_err); 2138 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2139 NS_PRV_IOVCNT(iovb)); 2140 vc->rx_iov = NULL; 2141 recycle_iov_buf(card, iovb); 2142 return; 2143 } 2144 } 2145 #endif /* EXTRA_DEBUG */ 2146 2147 if (ns_rsqe_eopdu(rsqe)) { 2148 /* This works correctly regardless of the endianness of the host */ 2149 unsigned char *L1L2 = (unsigned char *) 2150 (skb->data + iov->iov_len - 6); 2151 aal5_len = L1L2[0] << 8 | L1L2[1]; 2152 len = (aal5_len == 0x0000) ? 0x10000 : aal5_len; 2153 if (ns_rsqe_crcerr(rsqe) || 2154 len + 8 > iovb->len || len + (47 + 8) < iovb->len) { 2155 printk("nicstar%d: AAL5 CRC error", card->index); 2156 if (len + 8 > iovb->len || len + (47 + 8) < iovb->len) 2157 printk(" - PDU size mismatch.\n"); 2158 else 2159 printk(".\n"); 2160 atomic_inc(&vcc->stats->rx_err); 2161 recycle_iovec_rx_bufs(card, (struct iovec *)iovb->data, 2162 NS_PRV_IOVCNT(iovb)); 2163 vc->rx_iov = NULL; 2164 recycle_iov_buf(card, iovb); 2165 return; 2166 } 2167 2168 /* By this point we (hopefully) have a complete SDU without errors. */ 2169 2170 if (NS_PRV_IOVCNT(iovb) == 1) { /* Just a small buffer */ 2171 /* skb points to a small buffer */ 2172 if (!atm_charge(vcc, skb->truesize)) { 2173 push_rxbufs(card, skb); 2174 atomic_inc(&vcc->stats->rx_drop); 2175 } else { 2176 skb_put(skb, len); 2177 dequeue_sm_buf(card, skb); 2178 ATM_SKB(skb)->vcc = vcc; 2179 __net_timestamp(skb); 2180 vcc->push(vcc, skb); 2181 atomic_inc(&vcc->stats->rx); 2182 } 2183 } else if (NS_PRV_IOVCNT(iovb) == 2) { /* One small plus one large buffer */ 2184 struct sk_buff *sb; 2185 2186 sb = (struct sk_buff *)(iov - 1)->iov_base; 2187 /* skb points to a large buffer */ 2188 2189 if (len <= NS_SMBUFSIZE) { 2190 if (!atm_charge(vcc, sb->truesize)) { 2191 push_rxbufs(card, sb); 2192 atomic_inc(&vcc->stats->rx_drop); 2193 } else { 2194 skb_put(sb, len); 2195 dequeue_sm_buf(card, sb); 2196 ATM_SKB(sb)->vcc = vcc; 2197 __net_timestamp(sb); 2198 vcc->push(vcc, sb); 2199 atomic_inc(&vcc->stats->rx); 2200 } 2201 2202 push_rxbufs(card, skb); 2203 2204 } else { /* len > NS_SMBUFSIZE, the usual case */ 2205 2206 if (!atm_charge(vcc, skb->truesize)) { 2207 push_rxbufs(card, skb); 2208 atomic_inc(&vcc->stats->rx_drop); 2209 } else { 2210 dequeue_lg_buf(card, skb); 2211 skb_push(skb, NS_SMBUFSIZE); 2212 skb_copy_from_linear_data(sb, skb->data, 2213 NS_SMBUFSIZE); 2214 skb_put(skb, len - NS_SMBUFSIZE); 2215 ATM_SKB(skb)->vcc = vcc; 2216 __net_timestamp(skb); 2217 vcc->push(vcc, skb); 2218 atomic_inc(&vcc->stats->rx); 2219 } 2220 2221 push_rxbufs(card, sb); 2222 2223 } 2224 2225 } else { /* Must push a huge buffer */ 2226 2227 struct sk_buff *hb, *sb, *lb; 2228 int remaining, tocopy; 2229 int j; 2230 2231 hb = skb_dequeue(&(card->hbpool.queue)); 2232 if (hb == NULL) { /* No buffers in the queue */ 2233 2234 hb = dev_alloc_skb(NS_HBUFSIZE); 2235 if (hb == NULL) { 2236 printk 2237 ("nicstar%d: Out of huge buffers.\n", 2238 card->index); 2239 atomic_inc(&vcc->stats->rx_drop); 2240 recycle_iovec_rx_bufs(card, 2241 (struct iovec *) 2242 iovb->data, 2243 NS_PRV_IOVCNT(iovb)); 2244 vc->rx_iov = NULL; 2245 recycle_iov_buf(card, iovb); 2246 return; 2247 } else if (card->hbpool.count < card->hbnr.min) { 2248 struct sk_buff *new_hb; 2249 if ((new_hb = 2250 dev_alloc_skb(NS_HBUFSIZE)) != 2251 NULL) { 2252 skb_queue_tail(&card->hbpool. 2253 queue, new_hb); 2254 card->hbpool.count++; 2255 } 2256 } 2257 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2258 } else if (--card->hbpool.count < card->hbnr.min) { 2259 struct sk_buff *new_hb; 2260 if ((new_hb = 2261 dev_alloc_skb(NS_HBUFSIZE)) != NULL) { 2262 NS_PRV_BUFTYPE(new_hb) = BUF_NONE; 2263 skb_queue_tail(&card->hbpool.queue, 2264 new_hb); 2265 card->hbpool.count++; 2266 } 2267 if (card->hbpool.count < card->hbnr.min) { 2268 if ((new_hb = 2269 dev_alloc_skb(NS_HBUFSIZE)) != 2270 NULL) { 2271 NS_PRV_BUFTYPE(new_hb) = 2272 BUF_NONE; 2273 skb_queue_tail(&card->hbpool. 2274 queue, new_hb); 2275 card->hbpool.count++; 2276 } 2277 } 2278 } 2279 2280 iov = (struct iovec *)iovb->data; 2281 2282 if (!atm_charge(vcc, hb->truesize)) { 2283 recycle_iovec_rx_bufs(card, iov, 2284 NS_PRV_IOVCNT(iovb)); 2285 if (card->hbpool.count < card->hbnr.max) { 2286 skb_queue_tail(&card->hbpool.queue, hb); 2287 card->hbpool.count++; 2288 } else 2289 dev_kfree_skb_any(hb); 2290 atomic_inc(&vcc->stats->rx_drop); 2291 } else { 2292 /* Copy the small buffer to the huge buffer */ 2293 sb = (struct sk_buff *)iov->iov_base; 2294 skb_copy_from_linear_data(sb, hb->data, 2295 iov->iov_len); 2296 skb_put(hb, iov->iov_len); 2297 remaining = len - iov->iov_len; 2298 iov++; 2299 /* Free the small buffer */ 2300 push_rxbufs(card, sb); 2301 2302 /* Copy all large buffers to the huge buffer and free them */ 2303 for (j = 1; j < NS_PRV_IOVCNT(iovb); j++) { 2304 lb = (struct sk_buff *)iov->iov_base; 2305 tocopy = 2306 min_t(int, remaining, iov->iov_len); 2307 skb_copy_from_linear_data(lb, 2308 skb_tail_pointer 2309 (hb), tocopy); 2310 skb_put(hb, tocopy); 2311 iov++; 2312 remaining -= tocopy; 2313 push_rxbufs(card, lb); 2314 } 2315 #ifdef EXTRA_DEBUG 2316 if (remaining != 0 || hb->len != len) 2317 printk 2318 ("nicstar%d: Huge buffer len mismatch.\n", 2319 card->index); 2320 #endif /* EXTRA_DEBUG */ 2321 ATM_SKB(hb)->vcc = vcc; 2322 __net_timestamp(hb); 2323 vcc->push(vcc, hb); 2324 atomic_inc(&vcc->stats->rx); 2325 } 2326 } 2327 2328 vc->rx_iov = NULL; 2329 recycle_iov_buf(card, iovb); 2330 } 2331 2332 } 2333 2334 static void recycle_rx_buf(ns_dev * card, struct sk_buff *skb) 2335 { 2336 if (unlikely(NS_PRV_BUFTYPE(skb) == BUF_NONE)) { 2337 printk("nicstar%d: What kind of rx buffer is this?\n", 2338 card->index); 2339 dev_kfree_skb_any(skb); 2340 } else 2341 push_rxbufs(card, skb); 2342 } 2343 2344 static void recycle_iovec_rx_bufs(ns_dev * card, struct iovec *iov, int count) 2345 { 2346 while (count-- > 0) 2347 recycle_rx_buf(card, (struct sk_buff *)(iov++)->iov_base); 2348 } 2349 2350 static void recycle_iov_buf(ns_dev * card, struct sk_buff *iovb) 2351 { 2352 if (card->iovpool.count < card->iovnr.max) { 2353 skb_queue_tail(&card->iovpool.queue, iovb); 2354 card->iovpool.count++; 2355 } else 2356 dev_kfree_skb_any(iovb); 2357 } 2358 2359 static void dequeue_sm_buf(ns_dev * card, struct sk_buff *sb) 2360 { 2361 skb_unlink(sb, &card->sbpool.queue); 2362 if (card->sbfqc < card->sbnr.init) { 2363 struct sk_buff *new_sb; 2364 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) { 2365 NS_PRV_BUFTYPE(new_sb) = BUF_SM; 2366 skb_queue_tail(&card->sbpool.queue, new_sb); 2367 skb_reserve(new_sb, NS_AAL0_HEADER); 2368 push_rxbufs(card, new_sb); 2369 } 2370 } 2371 if (card->sbfqc < card->sbnr.init) 2372 { 2373 struct sk_buff *new_sb; 2374 if ((new_sb = dev_alloc_skb(NS_SMSKBSIZE)) != NULL) { 2375 NS_PRV_BUFTYPE(new_sb) = BUF_SM; 2376 skb_queue_tail(&card->sbpool.queue, new_sb); 2377 skb_reserve(new_sb, NS_AAL0_HEADER); 2378 push_rxbufs(card, new_sb); 2379 } 2380 } 2381 } 2382 2383 static void dequeue_lg_buf(ns_dev * card, struct sk_buff *lb) 2384 { 2385 skb_unlink(lb, &card->lbpool.queue); 2386 if (card->lbfqc < card->lbnr.init) { 2387 struct sk_buff *new_lb; 2388 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) { 2389 NS_PRV_BUFTYPE(new_lb) = BUF_LG; 2390 skb_queue_tail(&card->lbpool.queue, new_lb); 2391 skb_reserve(new_lb, NS_SMBUFSIZE); 2392 push_rxbufs(card, new_lb); 2393 } 2394 } 2395 if (card->lbfqc < card->lbnr.init) 2396 { 2397 struct sk_buff *new_lb; 2398 if ((new_lb = dev_alloc_skb(NS_LGSKBSIZE)) != NULL) { 2399 NS_PRV_BUFTYPE(new_lb) = BUF_LG; 2400 skb_queue_tail(&card->lbpool.queue, new_lb); 2401 skb_reserve(new_lb, NS_SMBUFSIZE); 2402 push_rxbufs(card, new_lb); 2403 } 2404 } 2405 } 2406 2407 static int ns_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2408 { 2409 u32 stat; 2410 ns_dev *card; 2411 int left; 2412 2413 left = (int)*pos; 2414 card = (ns_dev *) dev->dev_data; 2415 stat = readl(card->membase + STAT); 2416 if (!left--) 2417 return sprintf(page, "Pool count min init max \n"); 2418 if (!left--) 2419 return sprintf(page, "Small %5d %5d %5d %5d \n", 2420 ns_stat_sfbqc_get(stat), card->sbnr.min, 2421 card->sbnr.init, card->sbnr.max); 2422 if (!left--) 2423 return sprintf(page, "Large %5d %5d %5d %5d \n", 2424 ns_stat_lfbqc_get(stat), card->lbnr.min, 2425 card->lbnr.init, card->lbnr.max); 2426 if (!left--) 2427 return sprintf(page, "Huge %5d %5d %5d %5d \n", 2428 card->hbpool.count, card->hbnr.min, 2429 card->hbnr.init, card->hbnr.max); 2430 if (!left--) 2431 return sprintf(page, "Iovec %5d %5d %5d %5d \n", 2432 card->iovpool.count, card->iovnr.min, 2433 card->iovnr.init, card->iovnr.max); 2434 if (!left--) { 2435 int retval; 2436 retval = 2437 sprintf(page, "Interrupt counter: %u \n", card->intcnt); 2438 card->intcnt = 0; 2439 return retval; 2440 } 2441 #if 0 2442 /* Dump 25.6 Mbps PHY registers */ 2443 /* Now there's a 25.6 Mbps PHY driver this code isn't needed. I left it 2444 here just in case it's needed for debugging. */ 2445 if (card->max_pcr == ATM_25_PCR && !left--) { 2446 u32 phy_regs[4]; 2447 u32 i; 2448 2449 for (i = 0; i < 4; i++) { 2450 while (CMD_BUSY(card)) ; 2451 writel(NS_CMD_READ_UTILITY | 0x00000200 | i, 2452 card->membase + CMD); 2453 while (CMD_BUSY(card)) ; 2454 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF; 2455 } 2456 2457 return sprintf(page, "PHY regs: 0x%02X 0x%02X 0x%02X 0x%02X \n", 2458 phy_regs[0], phy_regs[1], phy_regs[2], 2459 phy_regs[3]); 2460 } 2461 #endif /* 0 - Dump 25.6 Mbps PHY registers */ 2462 #if 0 2463 /* Dump TST */ 2464 if (left-- < NS_TST_NUM_ENTRIES) { 2465 if (card->tste2vc[left + 1] == NULL) 2466 return sprintf(page, "%5d - VBR/UBR \n", left + 1); 2467 else 2468 return sprintf(page, "%5d - %d %d \n", left + 1, 2469 card->tste2vc[left + 1]->tx_vcc->vpi, 2470 card->tste2vc[left + 1]->tx_vcc->vci); 2471 } 2472 #endif /* 0 */ 2473 return 0; 2474 } 2475 2476 static int ns_ioctl(struct atm_dev *dev, unsigned int cmd, void __user * arg) 2477 { 2478 ns_dev *card; 2479 pool_levels pl; 2480 long btype; 2481 unsigned long flags; 2482 2483 card = dev->dev_data; 2484 switch (cmd) { 2485 case NS_GETPSTAT: 2486 if (get_user 2487 (pl.buftype, &((pool_levels __user *) arg)->buftype)) 2488 return -EFAULT; 2489 switch (pl.buftype) { 2490 case NS_BUFTYPE_SMALL: 2491 pl.count = 2492 ns_stat_sfbqc_get(readl(card->membase + STAT)); 2493 pl.level.min = card->sbnr.min; 2494 pl.level.init = card->sbnr.init; 2495 pl.level.max = card->sbnr.max; 2496 break; 2497 2498 case NS_BUFTYPE_LARGE: 2499 pl.count = 2500 ns_stat_lfbqc_get(readl(card->membase + STAT)); 2501 pl.level.min = card->lbnr.min; 2502 pl.level.init = card->lbnr.init; 2503 pl.level.max = card->lbnr.max; 2504 break; 2505 2506 case NS_BUFTYPE_HUGE: 2507 pl.count = card->hbpool.count; 2508 pl.level.min = card->hbnr.min; 2509 pl.level.init = card->hbnr.init; 2510 pl.level.max = card->hbnr.max; 2511 break; 2512 2513 case NS_BUFTYPE_IOVEC: 2514 pl.count = card->iovpool.count; 2515 pl.level.min = card->iovnr.min; 2516 pl.level.init = card->iovnr.init; 2517 pl.level.max = card->iovnr.max; 2518 break; 2519 2520 default: 2521 return -ENOIOCTLCMD; 2522 2523 } 2524 if (!copy_to_user((pool_levels __user *) arg, &pl, sizeof(pl))) 2525 return (sizeof(pl)); 2526 else 2527 return -EFAULT; 2528 2529 case NS_SETBUFLEV: 2530 if (!capable(CAP_NET_ADMIN)) 2531 return -EPERM; 2532 if (copy_from_user(&pl, (pool_levels __user *) arg, sizeof(pl))) 2533 return -EFAULT; 2534 if (pl.level.min >= pl.level.init 2535 || pl.level.init >= pl.level.max) 2536 return -EINVAL; 2537 if (pl.level.min == 0) 2538 return -EINVAL; 2539 switch (pl.buftype) { 2540 case NS_BUFTYPE_SMALL: 2541 if (pl.level.max > TOP_SB) 2542 return -EINVAL; 2543 card->sbnr.min = pl.level.min; 2544 card->sbnr.init = pl.level.init; 2545 card->sbnr.max = pl.level.max; 2546 break; 2547 2548 case NS_BUFTYPE_LARGE: 2549 if (pl.level.max > TOP_LB) 2550 return -EINVAL; 2551 card->lbnr.min = pl.level.min; 2552 card->lbnr.init = pl.level.init; 2553 card->lbnr.max = pl.level.max; 2554 break; 2555 2556 case NS_BUFTYPE_HUGE: 2557 if (pl.level.max > TOP_HB) 2558 return -EINVAL; 2559 card->hbnr.min = pl.level.min; 2560 card->hbnr.init = pl.level.init; 2561 card->hbnr.max = pl.level.max; 2562 break; 2563 2564 case NS_BUFTYPE_IOVEC: 2565 if (pl.level.max > TOP_IOVB) 2566 return -EINVAL; 2567 card->iovnr.min = pl.level.min; 2568 card->iovnr.init = pl.level.init; 2569 card->iovnr.max = pl.level.max; 2570 break; 2571 2572 default: 2573 return -EINVAL; 2574 2575 } 2576 return 0; 2577 2578 case NS_ADJBUFLEV: 2579 if (!capable(CAP_NET_ADMIN)) 2580 return -EPERM; 2581 btype = (long)arg; /* a long is the same size as a pointer or bigger */ 2582 switch (btype) { 2583 case NS_BUFTYPE_SMALL: 2584 while (card->sbfqc < card->sbnr.init) { 2585 struct sk_buff *sb; 2586 2587 sb = __dev_alloc_skb(NS_SMSKBSIZE, GFP_KERNEL); 2588 if (sb == NULL) 2589 return -ENOMEM; 2590 NS_PRV_BUFTYPE(sb) = BUF_SM; 2591 skb_queue_tail(&card->sbpool.queue, sb); 2592 skb_reserve(sb, NS_AAL0_HEADER); 2593 push_rxbufs(card, sb); 2594 } 2595 break; 2596 2597 case NS_BUFTYPE_LARGE: 2598 while (card->lbfqc < card->lbnr.init) { 2599 struct sk_buff *lb; 2600 2601 lb = __dev_alloc_skb(NS_LGSKBSIZE, GFP_KERNEL); 2602 if (lb == NULL) 2603 return -ENOMEM; 2604 NS_PRV_BUFTYPE(lb) = BUF_LG; 2605 skb_queue_tail(&card->lbpool.queue, lb); 2606 skb_reserve(lb, NS_SMBUFSIZE); 2607 push_rxbufs(card, lb); 2608 } 2609 break; 2610 2611 case NS_BUFTYPE_HUGE: 2612 while (card->hbpool.count > card->hbnr.init) { 2613 struct sk_buff *hb; 2614 2615 spin_lock_irqsave(&card->int_lock, flags); 2616 hb = skb_dequeue(&card->hbpool.queue); 2617 card->hbpool.count--; 2618 spin_unlock_irqrestore(&card->int_lock, flags); 2619 if (hb == NULL) 2620 printk 2621 ("nicstar%d: huge buffer count inconsistent.\n", 2622 card->index); 2623 else 2624 dev_kfree_skb_any(hb); 2625 2626 } 2627 while (card->hbpool.count < card->hbnr.init) { 2628 struct sk_buff *hb; 2629 2630 hb = __dev_alloc_skb(NS_HBUFSIZE, GFP_KERNEL); 2631 if (hb == NULL) 2632 return -ENOMEM; 2633 NS_PRV_BUFTYPE(hb) = BUF_NONE; 2634 spin_lock_irqsave(&card->int_lock, flags); 2635 skb_queue_tail(&card->hbpool.queue, hb); 2636 card->hbpool.count++; 2637 spin_unlock_irqrestore(&card->int_lock, flags); 2638 } 2639 break; 2640 2641 case NS_BUFTYPE_IOVEC: 2642 while (card->iovpool.count > card->iovnr.init) { 2643 struct sk_buff *iovb; 2644 2645 spin_lock_irqsave(&card->int_lock, flags); 2646 iovb = skb_dequeue(&card->iovpool.queue); 2647 card->iovpool.count--; 2648 spin_unlock_irqrestore(&card->int_lock, flags); 2649 if (iovb == NULL) 2650 printk 2651 ("nicstar%d: iovec buffer count inconsistent.\n", 2652 card->index); 2653 else 2654 dev_kfree_skb_any(iovb); 2655 2656 } 2657 while (card->iovpool.count < card->iovnr.init) { 2658 struct sk_buff *iovb; 2659 2660 iovb = alloc_skb(NS_IOVBUFSIZE, GFP_KERNEL); 2661 if (iovb == NULL) 2662 return -ENOMEM; 2663 NS_PRV_BUFTYPE(iovb) = BUF_NONE; 2664 spin_lock_irqsave(&card->int_lock, flags); 2665 skb_queue_tail(&card->iovpool.queue, iovb); 2666 card->iovpool.count++; 2667 spin_unlock_irqrestore(&card->int_lock, flags); 2668 } 2669 break; 2670 2671 default: 2672 return -EINVAL; 2673 2674 } 2675 return 0; 2676 2677 default: 2678 if (dev->phy && dev->phy->ioctl) { 2679 return dev->phy->ioctl(dev, cmd, arg); 2680 } else { 2681 printk("nicstar%d: %s == NULL \n", card->index, 2682 dev->phy ? "dev->phy->ioctl" : "dev->phy"); 2683 return -ENOIOCTLCMD; 2684 } 2685 } 2686 } 2687 2688 #ifdef EXTRA_DEBUG 2689 static void which_list(ns_dev * card, struct sk_buff *skb) 2690 { 2691 printk("skb buf_type: 0x%08x\n", NS_PRV_BUFTYPE(skb)); 2692 } 2693 #endif /* EXTRA_DEBUG */ 2694 2695 static void ns_poll(struct timer_list *unused) 2696 { 2697 int i; 2698 ns_dev *card; 2699 unsigned long flags; 2700 u32 stat_r, stat_w; 2701 2702 PRINTK("nicstar: Entering ns_poll().\n"); 2703 for (i = 0; i < num_cards; i++) { 2704 card = cards[i]; 2705 if (!spin_trylock_irqsave(&card->int_lock, flags)) { 2706 /* Probably it isn't worth spinning */ 2707 continue; 2708 } 2709 2710 stat_w = 0; 2711 stat_r = readl(card->membase + STAT); 2712 if (stat_r & NS_STAT_TSIF) 2713 stat_w |= NS_STAT_TSIF; 2714 if (stat_r & NS_STAT_EOPDU) 2715 stat_w |= NS_STAT_EOPDU; 2716 2717 process_tsq(card); 2718 process_rsq(card); 2719 2720 writel(stat_w, card->membase + STAT); 2721 spin_unlock_irqrestore(&card->int_lock, flags); 2722 } 2723 mod_timer(&ns_timer, jiffies + NS_POLL_PERIOD); 2724 PRINTK("nicstar: Leaving ns_poll().\n"); 2725 } 2726 2727 static void ns_phy_put(struct atm_dev *dev, unsigned char value, 2728 unsigned long addr) 2729 { 2730 ns_dev *card; 2731 unsigned long flags; 2732 2733 card = dev->dev_data; 2734 spin_lock_irqsave(&card->res_lock, flags); 2735 while (CMD_BUSY(card)) ; 2736 writel((u32) value, card->membase + DR0); 2737 writel(NS_CMD_WRITE_UTILITY | 0x00000200 | (addr & 0x000000FF), 2738 card->membase + CMD); 2739 spin_unlock_irqrestore(&card->res_lock, flags); 2740 } 2741 2742 static unsigned char ns_phy_get(struct atm_dev *dev, unsigned long addr) 2743 { 2744 ns_dev *card; 2745 unsigned long flags; 2746 u32 data; 2747 2748 card = dev->dev_data; 2749 spin_lock_irqsave(&card->res_lock, flags); 2750 while (CMD_BUSY(card)) ; 2751 writel(NS_CMD_READ_UTILITY | 0x00000200 | (addr & 0x000000FF), 2752 card->membase + CMD); 2753 while (CMD_BUSY(card)) ; 2754 data = readl(card->membase + DR0) & 0x000000FF; 2755 spin_unlock_irqrestore(&card->res_lock, flags); 2756 return (unsigned char)data; 2757 } 2758 2759 module_init(nicstar_init); 2760 module_exit(nicstar_cleanup); 2761