1 /* lanai.c -- Copyright 1999-2003 by Mitchell Blank Jr <mitch@sfgoth.com> 2 * 3 * This program is free software; you can redistribute it and/or 4 * modify it under the terms of the GNU General Public License 5 * as published by the Free Software Foundation; either version 6 * 2 of the License, or (at your option) any later version. 7 * 8 * This driver supports ATM cards based on the Efficient "Lanai" 9 * chipset such as the Speedstream 3010 and the ENI-25p. The 10 * Speedstream 3060 is currently not supported since we don't 11 * have the code to drive the on-board Alcatel DSL chipset (yet). 12 * 13 * Thanks to Efficient for supporting this project with hardware, 14 * documentation, and by answering my questions. 15 * 16 * Things not working yet: 17 * 18 * o We don't support the Speedstream 3060 yet - this card has 19 * an on-board DSL modem chip by Alcatel and the driver will 20 * need some extra code added to handle it 21 * 22 * o Note that due to limitations of the Lanai only one VCC can be 23 * in CBR at once 24 * 25 * o We don't currently parse the EEPROM at all. The code is all 26 * there as per the spec, but it doesn't actually work. I think 27 * there may be some issues with the docs. Anyway, do NOT 28 * enable it yet - bugs in that code may actually damage your 29 * hardware! Because of this you should hardware an ESI before 30 * trying to use this in a LANE or MPOA environment. 31 * 32 * o AAL0 is stubbed in but the actual rx/tx path isn't written yet: 33 * vcc_tx_aal0() needs to send or queue a SKB 34 * vcc_tx_unqueue_aal0() needs to attempt to send queued SKBs 35 * vcc_rx_aal0() needs to handle AAL0 interrupts 36 * This isn't too much work - I just wanted to get other things 37 * done first. 38 * 39 * o lanai_change_qos() isn't written yet 40 * 41 * o There aren't any ioctl's yet -- I'd like to eventually support 42 * setting loopback and LED modes that way. 43 * 44 * o If the segmentation engine or DMA gets shut down we should restart 45 * card as per section 17.0i. (see lanai_reset) 46 * 47 * o setsockopt(SO_CIRANGE) isn't done (although despite what the 48 * API says it isn't exactly commonly implemented) 49 */ 50 51 /* Version history: 52 * v.1.00 -- 26-JUL-2003 -- PCI/DMA updates 53 * v.0.02 -- 11-JAN-2000 -- Endian fixes 54 * v.0.01 -- 30-NOV-1999 -- Initial release 55 */ 56 57 #include <linux/module.h> 58 #include <linux/slab.h> 59 #include <linux/mm.h> 60 #include <linux/atmdev.h> 61 #include <asm/io.h> 62 #include <asm/byteorder.h> 63 #include <linux/spinlock.h> 64 #include <linux/pci.h> 65 #include <linux/dma-mapping.h> 66 #include <linux/init.h> 67 #include <linux/delay.h> 68 #include <linux/interrupt.h> 69 70 /* -------------------- TUNABLE PARAMATERS: */ 71 72 /* 73 * Maximum number of VCIs per card. Setting it lower could theoretically 74 * save some memory, but since we allocate our vcc list with get_free_pages, 75 * it's not really likely for most architectures 76 */ 77 #define NUM_VCI (1024) 78 79 /* 80 * Enable extra debugging 81 */ 82 #define DEBUG 83 /* 84 * Debug _all_ register operations with card, except the memory test. 85 * Also disables the timed poll to prevent extra chattiness. This 86 * isn't for normal use 87 */ 88 #undef DEBUG_RW 89 90 /* 91 * The programming guide specifies a full test of the on-board SRAM 92 * at initialization time. Undefine to remove this 93 */ 94 #define FULL_MEMORY_TEST 95 96 /* 97 * This is the number of (4 byte) service entries that we will 98 * try to allocate at startup. Note that we will end up with 99 * one PAGE_SIZE's worth regardless of what this is set to 100 */ 101 #define SERVICE_ENTRIES (1024) 102 /* TODO: make above a module load-time option */ 103 104 /* 105 * We normally read the onboard EEPROM in order to discover our MAC 106 * address. Undefine to _not_ do this 107 */ 108 /* #define READ_EEPROM */ /* ***DONT ENABLE YET*** */ 109 /* TODO: make above a module load-time option (also) */ 110 111 /* 112 * Depth of TX fifo (in 128 byte units; range 2-31) 113 * Smaller numbers are better for network latency 114 * Larger numbers are better for PCI latency 115 * I'm really sure where the best tradeoff is, but the BSD driver uses 116 * 7 and it seems to work ok. 117 */ 118 #define TX_FIFO_DEPTH (7) 119 /* TODO: make above a module load-time option */ 120 121 /* 122 * How often (in jiffies) we will try to unstick stuck connections - 123 * shouldn't need to happen much 124 */ 125 #define LANAI_POLL_PERIOD (10*HZ) 126 /* TODO: make above a module load-time option */ 127 128 /* 129 * When allocating an AAL5 receiving buffer, try to make it at least 130 * large enough to hold this many max_sdu sized PDUs 131 */ 132 #define AAL5_RX_MULTIPLIER (3) 133 /* TODO: make above a module load-time option */ 134 135 /* 136 * Same for transmitting buffer 137 */ 138 #define AAL5_TX_MULTIPLIER (3) 139 /* TODO: make above a module load-time option */ 140 141 /* 142 * When allocating an AAL0 transmiting buffer, how many cells should fit. 143 * Remember we'll end up with a PAGE_SIZE of them anyway, so this isn't 144 * really critical 145 */ 146 #define AAL0_TX_MULTIPLIER (40) 147 /* TODO: make above a module load-time option */ 148 149 /* 150 * How large should we make the AAL0 receiving buffer. Remember that this 151 * is shared between all AAL0 VC's 152 */ 153 #define AAL0_RX_BUFFER_SIZE (PAGE_SIZE) 154 /* TODO: make above a module load-time option */ 155 156 /* 157 * Should we use Lanai's "powerdown" feature when no vcc's are bound? 158 */ 159 /* #define USE_POWERDOWN */ 160 /* TODO: make above a module load-time option (also) */ 161 162 /* -------------------- DEBUGGING AIDS: */ 163 164 #define DEV_LABEL "lanai" 165 166 #ifdef DEBUG 167 168 #define DPRINTK(format, args...) \ 169 printk(KERN_DEBUG DEV_LABEL ": " format, ##args) 170 #define APRINTK(truth, format, args...) \ 171 do { \ 172 if (unlikely(!(truth))) \ 173 printk(KERN_ERR DEV_LABEL ": " format, ##args); \ 174 } while (0) 175 176 #else /* !DEBUG */ 177 178 #define DPRINTK(format, args...) 179 #define APRINTK(truth, format, args...) 180 181 #endif /* DEBUG */ 182 183 #ifdef DEBUG_RW 184 #define RWDEBUG(format, args...) \ 185 printk(KERN_DEBUG DEV_LABEL ": " format, ##args) 186 #else /* !DEBUG_RW */ 187 #define RWDEBUG(format, args...) 188 #endif 189 190 /* -------------------- DATA DEFINITIONS: */ 191 192 #define LANAI_MAPPING_SIZE (0x40000) 193 #define LANAI_EEPROM_SIZE (128) 194 195 typedef int vci_t; 196 typedef void __iomem *bus_addr_t; 197 198 /* DMA buffer in host memory for TX, RX, or service list. */ 199 struct lanai_buffer { 200 u32 *start; /* From get_free_pages */ 201 u32 *end; /* One past last byte */ 202 u32 *ptr; /* Pointer to current host location */ 203 dma_addr_t dmaaddr; 204 }; 205 206 struct lanai_vcc_stats { 207 unsigned rx_nomem; 208 union { 209 struct { 210 unsigned rx_badlen; 211 unsigned service_trash; 212 unsigned service_stream; 213 unsigned service_rxcrc; 214 } aal5; 215 struct { 216 } aal0; 217 } x; 218 }; 219 220 struct lanai_dev; /* Forward declaration */ 221 222 /* 223 * This is the card-specific per-vcc data. Note that unlike some other 224 * drivers there is NOT a 1-to-1 correspondance between these and 225 * atm_vcc's - each one of these represents an actual 2-way vcc, but 226 * an atm_vcc can be 1-way and share with a 1-way vcc in the other 227 * direction. To make it weirder, there can even be 0-way vccs 228 * bound to us, waiting to do a change_qos 229 */ 230 struct lanai_vcc { 231 bus_addr_t vbase; /* Base of VCC's registers */ 232 struct lanai_vcc_stats stats; 233 int nref; /* # of atm_vcc's who reference us */ 234 vci_t vci; 235 struct { 236 struct lanai_buffer buf; 237 struct atm_vcc *atmvcc; /* atm_vcc who is receiver */ 238 } rx; 239 struct { 240 struct lanai_buffer buf; 241 struct atm_vcc *atmvcc; /* atm_vcc who is transmitter */ 242 int endptr; /* last endptr from service entry */ 243 struct sk_buff_head backlog; 244 void (*unqueue)(struct lanai_dev *, struct lanai_vcc *, int); 245 } tx; 246 }; 247 248 enum lanai_type { 249 lanai2 = PCI_DEVICE_ID_EF_ATM_LANAI2, 250 lanaihb = PCI_DEVICE_ID_EF_ATM_LANAIHB 251 }; 252 253 struct lanai_dev_stats { 254 unsigned ovfl_trash; /* # of cells dropped - buffer overflow */ 255 unsigned vci_trash; /* # of cells dropped - closed vci */ 256 unsigned hec_err; /* # of cells dropped - bad HEC */ 257 unsigned atm_ovfl; /* # of cells dropped - rx fifo overflow */ 258 unsigned pcierr_parity_detect; 259 unsigned pcierr_serr_set; 260 unsigned pcierr_master_abort; 261 unsigned pcierr_m_target_abort; 262 unsigned pcierr_s_target_abort; 263 unsigned pcierr_master_parity; 264 unsigned service_notx; 265 unsigned service_norx; 266 unsigned service_rxnotaal5; 267 unsigned dma_reenable; 268 unsigned card_reset; 269 }; 270 271 struct lanai_dev { 272 bus_addr_t base; 273 struct lanai_dev_stats stats; 274 struct lanai_buffer service; 275 struct lanai_vcc **vccs; 276 #ifdef USE_POWERDOWN 277 int nbound; /* number of bound vccs */ 278 #endif 279 enum lanai_type type; 280 vci_t num_vci; /* Currently just NUM_VCI */ 281 u8 eeprom[LANAI_EEPROM_SIZE]; 282 u32 serialno, magicno; 283 struct pci_dev *pci; 284 DECLARE_BITMAP(backlog_vccs, NUM_VCI); /* VCCs with tx backlog */ 285 DECLARE_BITMAP(transmit_ready, NUM_VCI); /* VCCs with transmit space */ 286 struct timer_list timer; 287 int naal0; 288 struct lanai_buffer aal0buf; /* AAL0 RX buffers */ 289 u32 conf1, conf2; /* CONFIG[12] registers */ 290 u32 status; /* STATUS register */ 291 spinlock_t endtxlock; 292 spinlock_t servicelock; 293 struct atm_vcc *cbrvcc; 294 int number; 295 int board_rev; 296 /* TODO - look at race conditions with maintence of conf1/conf2 */ 297 /* TODO - transmit locking: should we use _irq not _irqsave? */ 298 /* TODO - organize above in some rational fashion (see <asm/cache.h>) */ 299 }; 300 301 /* 302 * Each device has two bitmaps for each VCC (baclog_vccs and transmit_ready) 303 * This function iterates one of these, calling a given function for each 304 * vci with their bit set 305 */ 306 static void vci_bitfield_iterate(struct lanai_dev *lanai, 307 const unsigned long *lp, 308 void (*func)(struct lanai_dev *,vci_t vci)) 309 { 310 vci_t vci; 311 312 for_each_set_bit(vci, lp, NUM_VCI) 313 func(lanai, vci); 314 } 315 316 /* -------------------- BUFFER UTILITIES: */ 317 318 /* 319 * Lanai needs DMA buffers aligned to 256 bytes of at least 1024 bytes - 320 * usually any page allocation will do. Just to be safe in case 321 * PAGE_SIZE is insanely tiny, though... 322 */ 323 #define LANAI_PAGE_SIZE ((PAGE_SIZE >= 1024) ? PAGE_SIZE : 1024) 324 325 /* 326 * Allocate a buffer in host RAM for service list, RX, or TX 327 * Returns buf->start==NULL if no memory 328 * Note that the size will be rounded up 2^n bytes, and 329 * if we can't allocate that we'll settle for something smaller 330 * until minbytes 331 */ 332 static void lanai_buf_allocate(struct lanai_buffer *buf, 333 size_t bytes, size_t minbytes, struct pci_dev *pci) 334 { 335 int size; 336 337 if (bytes > (128 * 1024)) /* max lanai buffer size */ 338 bytes = 128 * 1024; 339 for (size = LANAI_PAGE_SIZE; size < bytes; size *= 2) 340 ; 341 if (minbytes < LANAI_PAGE_SIZE) 342 minbytes = LANAI_PAGE_SIZE; 343 do { 344 /* 345 * Technically we could use non-consistent mappings for 346 * everything, but the way the lanai uses DMA memory would 347 * make that a terrific pain. This is much simpler. 348 */ 349 buf->start = pci_alloc_consistent(pci, size, &buf->dmaaddr); 350 if (buf->start != NULL) { /* Success */ 351 /* Lanai requires 256-byte alignment of DMA bufs */ 352 APRINTK((buf->dmaaddr & ~0xFFFFFF00) == 0, 353 "bad dmaaddr: 0x%lx\n", 354 (unsigned long) buf->dmaaddr); 355 buf->ptr = buf->start; 356 buf->end = (u32 *) 357 (&((unsigned char *) buf->start)[size]); 358 memset(buf->start, 0, size); 359 break; 360 } 361 size /= 2; 362 } while (size >= minbytes); 363 } 364 365 /* size of buffer in bytes */ 366 static inline size_t lanai_buf_size(const struct lanai_buffer *buf) 367 { 368 return ((unsigned long) buf->end) - ((unsigned long) buf->start); 369 } 370 371 static void lanai_buf_deallocate(struct lanai_buffer *buf, 372 struct pci_dev *pci) 373 { 374 if (buf->start != NULL) { 375 pci_free_consistent(pci, lanai_buf_size(buf), 376 buf->start, buf->dmaaddr); 377 buf->start = buf->end = buf->ptr = NULL; 378 } 379 } 380 381 /* size of buffer as "card order" (0=1k .. 7=128k) */ 382 static int lanai_buf_size_cardorder(const struct lanai_buffer *buf) 383 { 384 int order = get_order(lanai_buf_size(buf)) + (PAGE_SHIFT - 10); 385 386 /* This can only happen if PAGE_SIZE is gigantic, but just in case */ 387 if (order > 7) 388 order = 7; 389 return order; 390 } 391 392 /* -------------------- PORT I/O UTILITIES: */ 393 394 /* Registers (and their bit-fields) */ 395 enum lanai_register { 396 Reset_Reg = 0x00, /* Reset; read for chip type; bits: */ 397 #define RESET_GET_BOARD_REV(x) (((x)>> 0)&0x03) /* Board revision */ 398 #define RESET_GET_BOARD_ID(x) (((x)>> 2)&0x03) /* Board ID */ 399 #define BOARD_ID_LANAI256 (0) /* 25.6M adapter card */ 400 Endian_Reg = 0x04, /* Endian setting */ 401 IntStatus_Reg = 0x08, /* Interrupt status */ 402 IntStatusMasked_Reg = 0x0C, /* Interrupt status (masked) */ 403 IntAck_Reg = 0x10, /* Interrupt acknowledge */ 404 IntAckMasked_Reg = 0x14, /* Interrupt acknowledge (masked) */ 405 IntStatusSet_Reg = 0x18, /* Get status + enable/disable */ 406 IntStatusSetMasked_Reg = 0x1C, /* Get status + en/di (masked) */ 407 IntControlEna_Reg = 0x20, /* Interrupt control enable */ 408 IntControlDis_Reg = 0x24, /* Interrupt control disable */ 409 Status_Reg = 0x28, /* Status */ 410 #define STATUS_PROMDATA (0x00000001) /* PROM_DATA pin */ 411 #define STATUS_WAITING (0x00000002) /* Interrupt being delayed */ 412 #define STATUS_SOOL (0x00000004) /* SOOL alarm */ 413 #define STATUS_LOCD (0x00000008) /* LOCD alarm */ 414 #define STATUS_LED (0x00000010) /* LED (HAPPI) output */ 415 #define STATUS_GPIN (0x00000020) /* GPIN pin */ 416 #define STATUS_BUTTBUSY (0x00000040) /* Butt register is pending */ 417 Config1_Reg = 0x2C, /* Config word 1; bits: */ 418 #define CONFIG1_PROMDATA (0x00000001) /* PROM_DATA pin */ 419 #define CONFIG1_PROMCLK (0x00000002) /* PROM_CLK pin */ 420 #define CONFIG1_SET_READMODE(x) ((x)*0x004) /* PCI BM reads; values: */ 421 #define READMODE_PLAIN (0) /* Plain memory read */ 422 #define READMODE_LINE (2) /* Memory read line */ 423 #define READMODE_MULTIPLE (3) /* Memory read multiple */ 424 #define CONFIG1_DMA_ENABLE (0x00000010) /* Turn on DMA */ 425 #define CONFIG1_POWERDOWN (0x00000020) /* Turn off clocks */ 426 #define CONFIG1_SET_LOOPMODE(x) ((x)*0x080) /* Clock&loop mode; values: */ 427 #define LOOPMODE_NORMAL (0) /* Normal - no loop */ 428 #define LOOPMODE_TIME (1) 429 #define LOOPMODE_DIAG (2) 430 #define LOOPMODE_LINE (3) 431 #define CONFIG1_MASK_LOOPMODE (0x00000180) 432 #define CONFIG1_SET_LEDMODE(x) ((x)*0x0200) /* Mode of LED; values: */ 433 #define LEDMODE_NOT_SOOL (0) /* !SOOL */ 434 #define LEDMODE_OFF (1) /* 0 */ 435 #define LEDMODE_ON (2) /* 1 */ 436 #define LEDMODE_NOT_LOCD (3) /* !LOCD */ 437 #define LEDMORE_GPIN (4) /* GPIN */ 438 #define LEDMODE_NOT_GPIN (7) /* !GPIN */ 439 #define CONFIG1_MASK_LEDMODE (0x00000E00) 440 #define CONFIG1_GPOUT1 (0x00001000) /* Toggle for reset */ 441 #define CONFIG1_GPOUT2 (0x00002000) /* Loopback PHY */ 442 #define CONFIG1_GPOUT3 (0x00004000) /* Loopback lanai */ 443 Config2_Reg = 0x30, /* Config word 2; bits: */ 444 #define CONFIG2_HOWMANY (0x00000001) /* >512 VCIs? */ 445 #define CONFIG2_PTI7_MODE (0x00000002) /* Make PTI=7 RM, not OAM */ 446 #define CONFIG2_VPI_CHK_DIS (0x00000004) /* Ignore RX VPI value */ 447 #define CONFIG2_HEC_DROP (0x00000008) /* Drop cells w/ HEC errors */ 448 #define CONFIG2_VCI0_NORMAL (0x00000010) /* Treat VCI=0 normally */ 449 #define CONFIG2_CBR_ENABLE (0x00000020) /* Deal with CBR traffic */ 450 #define CONFIG2_TRASH_ALL (0x00000040) /* Trashing incoming cells */ 451 #define CONFIG2_TX_DISABLE (0x00000080) /* Trashing outgoing cells */ 452 #define CONFIG2_SET_TRASH (0x00000100) /* Turn trashing on */ 453 Statistics_Reg = 0x34, /* Statistics; bits: */ 454 #define STATS_GET_FIFO_OVFL(x) (((x)>> 0)&0xFF) /* FIFO overflowed */ 455 #define STATS_GET_HEC_ERR(x) (((x)>> 8)&0xFF) /* HEC was bad */ 456 #define STATS_GET_BAD_VCI(x) (((x)>>16)&0xFF) /* VCI not open */ 457 #define STATS_GET_BUF_OVFL(x) (((x)>>24)&0xFF) /* VCC buffer full */ 458 ServiceStuff_Reg = 0x38, /* Service stuff; bits: */ 459 #define SSTUFF_SET_SIZE(x) ((x)*0x20000000) /* size of service buffer */ 460 #define SSTUFF_SET_ADDR(x) ((x)>>8) /* set address of buffer */ 461 ServWrite_Reg = 0x3C, /* ServWrite Pointer */ 462 ServRead_Reg = 0x40, /* ServRead Pointer */ 463 TxDepth_Reg = 0x44, /* FIFO Transmit Depth */ 464 Butt_Reg = 0x48, /* Butt register */ 465 CBR_ICG_Reg = 0x50, 466 CBR_PTR_Reg = 0x54, 467 PingCount_Reg = 0x58, /* Ping count */ 468 DMA_Addr_Reg = 0x5C /* DMA address */ 469 }; 470 471 static inline bus_addr_t reg_addr(const struct lanai_dev *lanai, 472 enum lanai_register reg) 473 { 474 return lanai->base + reg; 475 } 476 477 static inline u32 reg_read(const struct lanai_dev *lanai, 478 enum lanai_register reg) 479 { 480 u32 t; 481 t = readl(reg_addr(lanai, reg)); 482 RWDEBUG("R [0x%08X] 0x%02X = 0x%08X\n", (unsigned int) lanai->base, 483 (int) reg, t); 484 return t; 485 } 486 487 static inline void reg_write(const struct lanai_dev *lanai, u32 val, 488 enum lanai_register reg) 489 { 490 RWDEBUG("W [0x%08X] 0x%02X < 0x%08X\n", (unsigned int) lanai->base, 491 (int) reg, val); 492 writel(val, reg_addr(lanai, reg)); 493 } 494 495 static inline void conf1_write(const struct lanai_dev *lanai) 496 { 497 reg_write(lanai, lanai->conf1, Config1_Reg); 498 } 499 500 static inline void conf2_write(const struct lanai_dev *lanai) 501 { 502 reg_write(lanai, lanai->conf2, Config2_Reg); 503 } 504 505 /* Same as conf2_write(), but defers I/O if we're powered down */ 506 static inline void conf2_write_if_powerup(const struct lanai_dev *lanai) 507 { 508 #ifdef USE_POWERDOWN 509 if (unlikely((lanai->conf1 & CONFIG1_POWERDOWN) != 0)) 510 return; 511 #endif /* USE_POWERDOWN */ 512 conf2_write(lanai); 513 } 514 515 static inline void reset_board(const struct lanai_dev *lanai) 516 { 517 DPRINTK("about to reset board\n"); 518 reg_write(lanai, 0, Reset_Reg); 519 /* 520 * If we don't delay a little while here then we can end up 521 * leaving the card in a VERY weird state and lock up the 522 * PCI bus. This isn't documented anywhere but I've convinced 523 * myself after a lot of painful experimentation 524 */ 525 udelay(5); 526 } 527 528 /* -------------------- CARD SRAM UTILITIES: */ 529 530 /* The SRAM is mapped into normal PCI memory space - the only catch is 531 * that it is only 16-bits wide but must be accessed as 32-bit. The 532 * 16 high bits will be zero. We don't hide this, since they get 533 * programmed mostly like discrete registers anyway 534 */ 535 #define SRAM_START (0x20000) 536 #define SRAM_BYTES (0x20000) /* Again, half don't really exist */ 537 538 static inline bus_addr_t sram_addr(const struct lanai_dev *lanai, int offset) 539 { 540 return lanai->base + SRAM_START + offset; 541 } 542 543 static inline u32 sram_read(const struct lanai_dev *lanai, int offset) 544 { 545 return readl(sram_addr(lanai, offset)); 546 } 547 548 static inline void sram_write(const struct lanai_dev *lanai, 549 u32 val, int offset) 550 { 551 writel(val, sram_addr(lanai, offset)); 552 } 553 554 static int __devinit sram_test_word(const struct lanai_dev *lanai, 555 int offset, u32 pattern) 556 { 557 u32 readback; 558 sram_write(lanai, pattern, offset); 559 readback = sram_read(lanai, offset); 560 if (likely(readback == pattern)) 561 return 0; 562 printk(KERN_ERR DEV_LABEL 563 "(itf %d): SRAM word at %d bad: wrote 0x%X, read 0x%X\n", 564 lanai->number, offset, 565 (unsigned int) pattern, (unsigned int) readback); 566 return -EIO; 567 } 568 569 static int __devinit sram_test_pass(const struct lanai_dev *lanai, u32 pattern) 570 { 571 int offset, result = 0; 572 for (offset = 0; offset < SRAM_BYTES && result == 0; offset += 4) 573 result = sram_test_word(lanai, offset, pattern); 574 return result; 575 } 576 577 static int __devinit sram_test_and_clear(const struct lanai_dev *lanai) 578 { 579 #ifdef FULL_MEMORY_TEST 580 int result; 581 DPRINTK("testing SRAM\n"); 582 if ((result = sram_test_pass(lanai, 0x5555)) != 0) 583 return result; 584 if ((result = sram_test_pass(lanai, 0xAAAA)) != 0) 585 return result; 586 #endif 587 DPRINTK("clearing SRAM\n"); 588 return sram_test_pass(lanai, 0x0000); 589 } 590 591 /* -------------------- CARD-BASED VCC TABLE UTILITIES: */ 592 593 /* vcc table */ 594 enum lanai_vcc_offset { 595 vcc_rxaddr1 = 0x00, /* Location1, plus bits: */ 596 #define RXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of RX buffer */ 597 #define RXADDR1_SET_RMMODE(x) ((x)*0x00800) /* RM cell action; values: */ 598 #define RMMODE_TRASH (0) /* discard */ 599 #define RMMODE_PRESERVE (1) /* input as AAL0 */ 600 #define RMMODE_PIPE (2) /* pipe to coscheduler */ 601 #define RMMODE_PIPEALL (3) /* pipe non-RM too */ 602 #define RXADDR1_OAM_PRESERVE (0x00002000) /* Input OAM cells as AAL0 */ 603 #define RXADDR1_SET_MODE(x) ((x)*0x0004000) /* Reassembly mode */ 604 #define RXMODE_TRASH (0) /* discard */ 605 #define RXMODE_AAL0 (1) /* non-AAL5 mode */ 606 #define RXMODE_AAL5 (2) /* AAL5, intr. each PDU */ 607 #define RXMODE_AAL5_STREAM (3) /* AAL5 w/o per-PDU intr */ 608 vcc_rxaddr2 = 0x04, /* Location2 */ 609 vcc_rxcrc1 = 0x08, /* RX CRC claculation space */ 610 vcc_rxcrc2 = 0x0C, 611 vcc_rxwriteptr = 0x10, /* RX writeptr, plus bits: */ 612 #define RXWRITEPTR_LASTEFCI (0x00002000) /* Last PDU had EFCI bit */ 613 #define RXWRITEPTR_DROPPING (0x00004000) /* Had error, dropping */ 614 #define RXWRITEPTR_TRASHING (0x00008000) /* Trashing */ 615 vcc_rxbufstart = 0x14, /* RX bufstart, plus bits: */ 616 #define RXBUFSTART_CLP (0x00004000) 617 #define RXBUFSTART_CI (0x00008000) 618 vcc_rxreadptr = 0x18, /* RX readptr */ 619 vcc_txicg = 0x1C, /* TX ICG */ 620 vcc_txaddr1 = 0x20, /* Location1, plus bits: */ 621 #define TXADDR1_SET_SIZE(x) ((x)*0x0000100) /* size of TX buffer */ 622 #define TXADDR1_ABR (0x00008000) /* use ABR (doesn't work) */ 623 vcc_txaddr2 = 0x24, /* Location2 */ 624 vcc_txcrc1 = 0x28, /* TX CRC claculation space */ 625 vcc_txcrc2 = 0x2C, 626 vcc_txreadptr = 0x30, /* TX Readptr, plus bits: */ 627 #define TXREADPTR_GET_PTR(x) ((x)&0x01FFF) 628 #define TXREADPTR_MASK_DELTA (0x0000E000) /* ? */ 629 vcc_txendptr = 0x34, /* TX Endptr, plus bits: */ 630 #define TXENDPTR_CLP (0x00002000) 631 #define TXENDPTR_MASK_PDUMODE (0x0000C000) /* PDU mode; values: */ 632 #define PDUMODE_AAL0 (0*0x04000) 633 #define PDUMODE_AAL5 (2*0x04000) 634 #define PDUMODE_AAL5STREAM (3*0x04000) 635 vcc_txwriteptr = 0x38, /* TX Writeptr */ 636 #define TXWRITEPTR_GET_PTR(x) ((x)&0x1FFF) 637 vcc_txcbr_next = 0x3C /* # of next CBR VCI in ring */ 638 #define TXCBR_NEXT_BOZO (0x00008000) /* "bozo bit" */ 639 }; 640 641 #define CARDVCC_SIZE (0x40) 642 643 static inline bus_addr_t cardvcc_addr(const struct lanai_dev *lanai, 644 vci_t vci) 645 { 646 return sram_addr(lanai, vci * CARDVCC_SIZE); 647 } 648 649 static inline u32 cardvcc_read(const struct lanai_vcc *lvcc, 650 enum lanai_vcc_offset offset) 651 { 652 u32 val; 653 APRINTK(lvcc->vbase != NULL, "cardvcc_read: unbound vcc!\n"); 654 val= readl(lvcc->vbase + offset); 655 RWDEBUG("VR vci=%04d 0x%02X = 0x%08X\n", 656 lvcc->vci, (int) offset, val); 657 return val; 658 } 659 660 static inline void cardvcc_write(const struct lanai_vcc *lvcc, 661 u32 val, enum lanai_vcc_offset offset) 662 { 663 APRINTK(lvcc->vbase != NULL, "cardvcc_write: unbound vcc!\n"); 664 APRINTK((val & ~0xFFFF) == 0, 665 "cardvcc_write: bad val 0x%X (vci=%d, addr=0x%02X)\n", 666 (unsigned int) val, lvcc->vci, (unsigned int) offset); 667 RWDEBUG("VW vci=%04d 0x%02X > 0x%08X\n", 668 lvcc->vci, (unsigned int) offset, (unsigned int) val); 669 writel(val, lvcc->vbase + offset); 670 } 671 672 /* -------------------- COMPUTE SIZE OF AN AAL5 PDU: */ 673 674 /* How many bytes will an AAL5 PDU take to transmit - remember that: 675 * o we need to add 8 bytes for length, CPI, UU, and CRC 676 * o we need to round up to 48 bytes for cells 677 */ 678 static inline int aal5_size(int size) 679 { 680 int cells = (size + 8 + 47) / 48; 681 return cells * 48; 682 } 683 684 /* How many bytes can we send if we have "space" space, assuming we have 685 * to send full cells 686 */ 687 static inline int aal5_spacefor(int space) 688 { 689 int cells = space / 48; 690 return cells * 48; 691 } 692 693 /* -------------------- FREE AN ATM SKB: */ 694 695 static inline void lanai_free_skb(struct atm_vcc *atmvcc, struct sk_buff *skb) 696 { 697 if (atmvcc->pop != NULL) 698 atmvcc->pop(atmvcc, skb); 699 else 700 dev_kfree_skb_any(skb); 701 } 702 703 /* -------------------- TURN VCCS ON AND OFF: */ 704 705 static void host_vcc_start_rx(const struct lanai_vcc *lvcc) 706 { 707 u32 addr1; 708 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) { 709 dma_addr_t dmaaddr = lvcc->rx.buf.dmaaddr; 710 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc1); 711 cardvcc_write(lvcc, 0xFFFF, vcc_rxcrc2); 712 cardvcc_write(lvcc, 0, vcc_rxwriteptr); 713 cardvcc_write(lvcc, 0, vcc_rxbufstart); 714 cardvcc_write(lvcc, 0, vcc_rxreadptr); 715 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_rxaddr2); 716 addr1 = ((dmaaddr >> 8) & 0xFF) | 717 RXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->rx.buf))| 718 RXADDR1_SET_RMMODE(RMMODE_TRASH) | /* ??? */ 719 /* RXADDR1_OAM_PRESERVE | --- no OAM support yet */ 720 RXADDR1_SET_MODE(RXMODE_AAL5); 721 } else 722 addr1 = RXADDR1_SET_RMMODE(RMMODE_PRESERVE) | /* ??? */ 723 RXADDR1_OAM_PRESERVE | /* ??? */ 724 RXADDR1_SET_MODE(RXMODE_AAL0); 725 /* This one must be last! */ 726 cardvcc_write(lvcc, addr1, vcc_rxaddr1); 727 } 728 729 static void host_vcc_start_tx(const struct lanai_vcc *lvcc) 730 { 731 dma_addr_t dmaaddr = lvcc->tx.buf.dmaaddr; 732 cardvcc_write(lvcc, 0, vcc_txicg); 733 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc1); 734 cardvcc_write(lvcc, 0xFFFF, vcc_txcrc2); 735 cardvcc_write(lvcc, 0, vcc_txreadptr); 736 cardvcc_write(lvcc, 0, vcc_txendptr); 737 cardvcc_write(lvcc, 0, vcc_txwriteptr); 738 cardvcc_write(lvcc, 739 (lvcc->tx.atmvcc->qos.txtp.traffic_class == ATM_CBR) ? 740 TXCBR_NEXT_BOZO | lvcc->vci : 0, vcc_txcbr_next); 741 cardvcc_write(lvcc, (dmaaddr >> 16) & 0xFFFF, vcc_txaddr2); 742 cardvcc_write(lvcc, 743 ((dmaaddr >> 8) & 0xFF) | 744 TXADDR1_SET_SIZE(lanai_buf_size_cardorder(&lvcc->tx.buf)), 745 vcc_txaddr1); 746 } 747 748 /* Shutdown receiving on card */ 749 static void lanai_shutdown_rx_vci(const struct lanai_vcc *lvcc) 750 { 751 if (lvcc->vbase == NULL) /* We were never bound to a VCI */ 752 return; 753 /* 15.1.1 - set to trashing, wait one cell time (15us) */ 754 cardvcc_write(lvcc, 755 RXADDR1_SET_RMMODE(RMMODE_TRASH) | 756 RXADDR1_SET_MODE(RXMODE_TRASH), vcc_rxaddr1); 757 udelay(15); 758 /* 15.1.2 - clear rest of entries */ 759 cardvcc_write(lvcc, 0, vcc_rxaddr2); 760 cardvcc_write(lvcc, 0, vcc_rxcrc1); 761 cardvcc_write(lvcc, 0, vcc_rxcrc2); 762 cardvcc_write(lvcc, 0, vcc_rxwriteptr); 763 cardvcc_write(lvcc, 0, vcc_rxbufstart); 764 cardvcc_write(lvcc, 0, vcc_rxreadptr); 765 } 766 767 /* Shutdown transmitting on card. 768 * Unfortunately the lanai needs us to wait until all the data 769 * drains out of the buffer before we can dealloc it, so this 770 * can take awhile -- up to 370ms for a full 128KB buffer 771 * assuming everone else is quiet. In theory the time is 772 * boundless if there's a CBR VCC holding things up. 773 */ 774 static void lanai_shutdown_tx_vci(struct lanai_dev *lanai, 775 struct lanai_vcc *lvcc) 776 { 777 struct sk_buff *skb; 778 unsigned long flags, timeout; 779 int read, write, lastread = -1; 780 APRINTK(!in_interrupt(), 781 "lanai_shutdown_tx_vci called w/o process context!\n"); 782 if (lvcc->vbase == NULL) /* We were never bound to a VCI */ 783 return; 784 /* 15.2.1 - wait for queue to drain */ 785 while ((skb = skb_dequeue(&lvcc->tx.backlog)) != NULL) 786 lanai_free_skb(lvcc->tx.atmvcc, skb); 787 read_lock_irqsave(&vcc_sklist_lock, flags); 788 __clear_bit(lvcc->vci, lanai->backlog_vccs); 789 read_unlock_irqrestore(&vcc_sklist_lock, flags); 790 /* 791 * We need to wait for the VCC to drain but don't wait forever. We 792 * give each 1K of buffer size 1/128th of a second to clear out. 793 * TODO: maybe disable CBR if we're about to timeout? 794 */ 795 timeout = jiffies + 796 (((lanai_buf_size(&lvcc->tx.buf) / 1024) * HZ) >> 7); 797 write = TXWRITEPTR_GET_PTR(cardvcc_read(lvcc, vcc_txwriteptr)); 798 for (;;) { 799 read = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); 800 if (read == write && /* Is TX buffer empty? */ 801 (lvcc->tx.atmvcc->qos.txtp.traffic_class != ATM_CBR || 802 (cardvcc_read(lvcc, vcc_txcbr_next) & 803 TXCBR_NEXT_BOZO) == 0)) 804 break; 805 if (read != lastread) { /* Has there been any progress? */ 806 lastread = read; 807 timeout += HZ / 10; 808 } 809 if (unlikely(time_after(jiffies, timeout))) { 810 printk(KERN_ERR DEV_LABEL "(itf %d): Timed out on " 811 "backlog closing vci %d\n", 812 lvcc->tx.atmvcc->dev->number, lvcc->vci); 813 DPRINTK("read, write = %d, %d\n", read, write); 814 break; 815 } 816 msleep(40); 817 } 818 /* 15.2.2 - clear out all tx registers */ 819 cardvcc_write(lvcc, 0, vcc_txreadptr); 820 cardvcc_write(lvcc, 0, vcc_txwriteptr); 821 cardvcc_write(lvcc, 0, vcc_txendptr); 822 cardvcc_write(lvcc, 0, vcc_txcrc1); 823 cardvcc_write(lvcc, 0, vcc_txcrc2); 824 cardvcc_write(lvcc, 0, vcc_txaddr2); 825 cardvcc_write(lvcc, 0, vcc_txaddr1); 826 } 827 828 /* -------------------- MANAGING AAL0 RX BUFFER: */ 829 830 static inline int aal0_buffer_allocate(struct lanai_dev *lanai) 831 { 832 DPRINTK("aal0_buffer_allocate: allocating AAL0 RX buffer\n"); 833 lanai_buf_allocate(&lanai->aal0buf, AAL0_RX_BUFFER_SIZE, 80, 834 lanai->pci); 835 return (lanai->aal0buf.start == NULL) ? -ENOMEM : 0; 836 } 837 838 static inline void aal0_buffer_free(struct lanai_dev *lanai) 839 { 840 DPRINTK("aal0_buffer_allocate: freeing AAL0 RX buffer\n"); 841 lanai_buf_deallocate(&lanai->aal0buf, lanai->pci); 842 } 843 844 /* -------------------- EEPROM UTILITIES: */ 845 846 /* Offsets of data in the EEPROM */ 847 #define EEPROM_COPYRIGHT (0) 848 #define EEPROM_COPYRIGHT_LEN (44) 849 #define EEPROM_CHECKSUM (62) 850 #define EEPROM_CHECKSUM_REV (63) 851 #define EEPROM_MAC (64) 852 #define EEPROM_MAC_REV (70) 853 #define EEPROM_SERIAL (112) 854 #define EEPROM_SERIAL_REV (116) 855 #define EEPROM_MAGIC (120) 856 #define EEPROM_MAGIC_REV (124) 857 858 #define EEPROM_MAGIC_VALUE (0x5AB478D2) 859 860 #ifndef READ_EEPROM 861 862 /* Stub functions to use if EEPROM reading is disabled */ 863 static int __devinit eeprom_read(struct lanai_dev *lanai) 864 { 865 printk(KERN_INFO DEV_LABEL "(itf %d): *NOT* reading EEPROM\n", 866 lanai->number); 867 memset(&lanai->eeprom[EEPROM_MAC], 0, 6); 868 return 0; 869 } 870 871 static int __devinit eeprom_validate(struct lanai_dev *lanai) 872 { 873 lanai->serialno = 0; 874 lanai->magicno = EEPROM_MAGIC_VALUE; 875 return 0; 876 } 877 878 #else /* READ_EEPROM */ 879 880 static int __devinit eeprom_read(struct lanai_dev *lanai) 881 { 882 int i, address; 883 u8 data; 884 u32 tmp; 885 #define set_config1(x) do { lanai->conf1 = x; conf1_write(lanai); \ 886 } while (0) 887 #define clock_h() set_config1(lanai->conf1 | CONFIG1_PROMCLK) 888 #define clock_l() set_config1(lanai->conf1 &~ CONFIG1_PROMCLK) 889 #define data_h() set_config1(lanai->conf1 | CONFIG1_PROMDATA) 890 #define data_l() set_config1(lanai->conf1 &~ CONFIG1_PROMDATA) 891 #define pre_read() do { data_h(); clock_h(); udelay(5); } while (0) 892 #define read_pin() (reg_read(lanai, Status_Reg) & STATUS_PROMDATA) 893 #define send_stop() do { data_l(); udelay(5); clock_h(); udelay(5); \ 894 data_h(); udelay(5); } while (0) 895 /* start with both clock and data high */ 896 data_h(); clock_h(); udelay(5); 897 for (address = 0; address < LANAI_EEPROM_SIZE; address++) { 898 data = (address << 1) | 1; /* Command=read + address */ 899 /* send start bit */ 900 data_l(); udelay(5); 901 clock_l(); udelay(5); 902 for (i = 128; i != 0; i >>= 1) { /* write command out */ 903 tmp = (lanai->conf1 & ~CONFIG1_PROMDATA) | 904 ((data & i) ? CONFIG1_PROMDATA : 0); 905 if (lanai->conf1 != tmp) { 906 set_config1(tmp); 907 udelay(5); /* Let new data settle */ 908 } 909 clock_h(); udelay(5); clock_l(); udelay(5); 910 } 911 /* look for ack */ 912 data_h(); clock_h(); udelay(5); 913 if (read_pin() != 0) 914 goto error; /* No ack seen */ 915 clock_l(); udelay(5); 916 /* read back result */ 917 for (data = 0, i = 7; i >= 0; i--) { 918 data_h(); clock_h(); udelay(5); 919 data = (data << 1) | !!read_pin(); 920 clock_l(); udelay(5); 921 } 922 /* look again for ack */ 923 data_h(); clock_h(); udelay(5); 924 if (read_pin() == 0) 925 goto error; /* Spurious ack */ 926 clock_l(); udelay(5); 927 send_stop(); 928 lanai->eeprom[address] = data; 929 DPRINTK("EEPROM 0x%04X %02X\n", 930 (unsigned int) address, (unsigned int) data); 931 } 932 return 0; 933 error: 934 clock_l(); udelay(5); /* finish read */ 935 send_stop(); 936 printk(KERN_ERR DEV_LABEL "(itf %d): error reading EEPROM byte %d\n", 937 lanai->number, address); 938 return -EIO; 939 #undef set_config1 940 #undef clock_h 941 #undef clock_l 942 #undef data_h 943 #undef data_l 944 #undef pre_read 945 #undef read_pin 946 #undef send_stop 947 } 948 949 /* read a big-endian 4-byte value out of eeprom */ 950 static inline u32 eeprom_be4(const struct lanai_dev *lanai, int address) 951 { 952 return be32_to_cpup((const u32 *) &lanai->eeprom[address]); 953 } 954 955 /* Checksum/validate EEPROM contents */ 956 static int __devinit eeprom_validate(struct lanai_dev *lanai) 957 { 958 int i, s; 959 u32 v; 960 const u8 *e = lanai->eeprom; 961 #ifdef DEBUG 962 /* First, see if we can get an ASCIIZ string out of the copyright */ 963 for (i = EEPROM_COPYRIGHT; 964 i < (EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN); i++) 965 if (e[i] < 0x20 || e[i] > 0x7E) 966 break; 967 if ( i != EEPROM_COPYRIGHT && 968 i != EEPROM_COPYRIGHT + EEPROM_COPYRIGHT_LEN && e[i] == '\0') 969 DPRINTK("eeprom: copyright = \"%s\"\n", 970 (char *) &e[EEPROM_COPYRIGHT]); 971 else 972 DPRINTK("eeprom: copyright not found\n"); 973 #endif 974 /* Validate checksum */ 975 for (i = s = 0; i < EEPROM_CHECKSUM; i++) 976 s += e[i]; 977 s &= 0xFF; 978 if (s != e[EEPROM_CHECKSUM]) { 979 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM checksum bad " 980 "(wanted 0x%02X, got 0x%02X)\n", lanai->number, 981 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM]); 982 return -EIO; 983 } 984 s ^= 0xFF; 985 if (s != e[EEPROM_CHECKSUM_REV]) { 986 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM inverse checksum " 987 "bad (wanted 0x%02X, got 0x%02X)\n", lanai->number, 988 (unsigned int) s, (unsigned int) e[EEPROM_CHECKSUM_REV]); 989 return -EIO; 990 } 991 /* Verify MAC address */ 992 for (i = 0; i < 6; i++) 993 if ((e[EEPROM_MAC + i] ^ e[EEPROM_MAC_REV + i]) != 0xFF) { 994 printk(KERN_ERR DEV_LABEL 995 "(itf %d) : EEPROM MAC addresses don't match " 996 "(0x%02X, inverse 0x%02X)\n", lanai->number, 997 (unsigned int) e[EEPROM_MAC + i], 998 (unsigned int) e[EEPROM_MAC_REV + i]); 999 return -EIO; 1000 } 1001 DPRINTK("eeprom: MAC address = %pM\n", &e[EEPROM_MAC]); 1002 /* Verify serial number */ 1003 lanai->serialno = eeprom_be4(lanai, EEPROM_SERIAL); 1004 v = eeprom_be4(lanai, EEPROM_SERIAL_REV); 1005 if ((lanai->serialno ^ v) != 0xFFFFFFFF) { 1006 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM serial numbers " 1007 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, 1008 (unsigned int) lanai->serialno, (unsigned int) v); 1009 return -EIO; 1010 } 1011 DPRINTK("eeprom: Serial number = %d\n", (unsigned int) lanai->serialno); 1012 /* Verify magic number */ 1013 lanai->magicno = eeprom_be4(lanai, EEPROM_MAGIC); 1014 v = eeprom_be4(lanai, EEPROM_MAGIC_REV); 1015 if ((lanai->magicno ^ v) != 0xFFFFFFFF) { 1016 printk(KERN_ERR DEV_LABEL "(itf %d): EEPROM magic numbers " 1017 "don't match (0x%08X, inverse 0x%08X)\n", lanai->number, 1018 lanai->magicno, v); 1019 return -EIO; 1020 } 1021 DPRINTK("eeprom: Magic number = 0x%08X\n", lanai->magicno); 1022 if (lanai->magicno != EEPROM_MAGIC_VALUE) 1023 printk(KERN_WARNING DEV_LABEL "(itf %d): warning - EEPROM " 1024 "magic not what expected (got 0x%08X, not 0x%08X)\n", 1025 lanai->number, (unsigned int) lanai->magicno, 1026 (unsigned int) EEPROM_MAGIC_VALUE); 1027 return 0; 1028 } 1029 1030 #endif /* READ_EEPROM */ 1031 1032 static inline const u8 *eeprom_mac(const struct lanai_dev *lanai) 1033 { 1034 return &lanai->eeprom[EEPROM_MAC]; 1035 } 1036 1037 /* -------------------- INTERRUPT HANDLING UTILITIES: */ 1038 1039 /* Interrupt types */ 1040 #define INT_STATS (0x00000002) /* Statistics counter overflow */ 1041 #define INT_SOOL (0x00000004) /* SOOL changed state */ 1042 #define INT_LOCD (0x00000008) /* LOCD changed state */ 1043 #define INT_LED (0x00000010) /* LED (HAPPI) changed state */ 1044 #define INT_GPIN (0x00000020) /* GPIN changed state */ 1045 #define INT_PING (0x00000040) /* PING_COUNT fulfilled */ 1046 #define INT_WAKE (0x00000080) /* Lanai wants bus */ 1047 #define INT_CBR0 (0x00000100) /* CBR sched hit VCI 0 */ 1048 #define INT_LOCK (0x00000200) /* Service list overflow */ 1049 #define INT_MISMATCH (0x00000400) /* TX magic list mismatch */ 1050 #define INT_AAL0_STR (0x00000800) /* Non-AAL5 buffer half filled */ 1051 #define INT_AAL0 (0x00001000) /* Non-AAL5 data available */ 1052 #define INT_SERVICE (0x00002000) /* Service list entries available */ 1053 #define INT_TABORTSENT (0x00004000) /* Target abort sent by lanai */ 1054 #define INT_TABORTBM (0x00008000) /* Abort rcv'd as bus master */ 1055 #define INT_TIMEOUTBM (0x00010000) /* No response to bus master */ 1056 #define INT_PCIPARITY (0x00020000) /* Parity error on PCI */ 1057 1058 /* Sets of the above */ 1059 #define INT_ALL (0x0003FFFE) /* All interrupts */ 1060 #define INT_STATUS (0x0000003C) /* Some status pin changed */ 1061 #define INT_DMASHUT (0x00038000) /* DMA engine got shut down */ 1062 #define INT_SEGSHUT (0x00000700) /* Segmentation got shut down */ 1063 1064 static inline u32 intr_pending(const struct lanai_dev *lanai) 1065 { 1066 return reg_read(lanai, IntStatusMasked_Reg); 1067 } 1068 1069 static inline void intr_enable(const struct lanai_dev *lanai, u32 i) 1070 { 1071 reg_write(lanai, i, IntControlEna_Reg); 1072 } 1073 1074 static inline void intr_disable(const struct lanai_dev *lanai, u32 i) 1075 { 1076 reg_write(lanai, i, IntControlDis_Reg); 1077 } 1078 1079 /* -------------------- CARD/PCI STATUS: */ 1080 1081 static void status_message(int itf, const char *name, int status) 1082 { 1083 static const char *onoff[2] = { "off to on", "on to off" }; 1084 printk(KERN_INFO DEV_LABEL "(itf %d): %s changed from %s\n", 1085 itf, name, onoff[!status]); 1086 } 1087 1088 static void lanai_check_status(struct lanai_dev *lanai) 1089 { 1090 u32 new = reg_read(lanai, Status_Reg); 1091 u32 changes = new ^ lanai->status; 1092 lanai->status = new; 1093 #define e(flag, name) \ 1094 if (changes & flag) \ 1095 status_message(lanai->number, name, new & flag) 1096 e(STATUS_SOOL, "SOOL"); 1097 e(STATUS_LOCD, "LOCD"); 1098 e(STATUS_LED, "LED"); 1099 e(STATUS_GPIN, "GPIN"); 1100 #undef e 1101 } 1102 1103 static void pcistatus_got(int itf, const char *name) 1104 { 1105 printk(KERN_INFO DEV_LABEL "(itf %d): PCI got %s error\n", itf, name); 1106 } 1107 1108 static void pcistatus_check(struct lanai_dev *lanai, int clearonly) 1109 { 1110 u16 s; 1111 int result; 1112 result = pci_read_config_word(lanai->pci, PCI_STATUS, &s); 1113 if (result != PCIBIOS_SUCCESSFUL) { 1114 printk(KERN_ERR DEV_LABEL "(itf %d): can't read PCI_STATUS: " 1115 "%d\n", lanai->number, result); 1116 return; 1117 } 1118 s &= PCI_STATUS_DETECTED_PARITY | PCI_STATUS_SIG_SYSTEM_ERROR | 1119 PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT | 1120 PCI_STATUS_SIG_TARGET_ABORT | PCI_STATUS_PARITY; 1121 if (s == 0) 1122 return; 1123 result = pci_write_config_word(lanai->pci, PCI_STATUS, s); 1124 if (result != PCIBIOS_SUCCESSFUL) 1125 printk(KERN_ERR DEV_LABEL "(itf %d): can't write PCI_STATUS: " 1126 "%d\n", lanai->number, result); 1127 if (clearonly) 1128 return; 1129 #define e(flag, name, stat) \ 1130 if (s & flag) { \ 1131 pcistatus_got(lanai->number, name); \ 1132 ++lanai->stats.pcierr_##stat; \ 1133 } 1134 e(PCI_STATUS_DETECTED_PARITY, "parity", parity_detect); 1135 e(PCI_STATUS_SIG_SYSTEM_ERROR, "signalled system", serr_set); 1136 e(PCI_STATUS_REC_MASTER_ABORT, "master", master_abort); 1137 e(PCI_STATUS_REC_TARGET_ABORT, "master target", m_target_abort); 1138 e(PCI_STATUS_SIG_TARGET_ABORT, "slave", s_target_abort); 1139 e(PCI_STATUS_PARITY, "master parity", master_parity); 1140 #undef e 1141 } 1142 1143 /* -------------------- VCC TX BUFFER UTILITIES: */ 1144 1145 /* space left in tx buffer in bytes */ 1146 static inline int vcc_tx_space(const struct lanai_vcc *lvcc, int endptr) 1147 { 1148 int r; 1149 r = endptr * 16; 1150 r -= ((unsigned long) lvcc->tx.buf.ptr) - 1151 ((unsigned long) lvcc->tx.buf.start); 1152 r -= 16; /* Leave "bubble" - if start==end it looks empty */ 1153 if (r < 0) 1154 r += lanai_buf_size(&lvcc->tx.buf); 1155 return r; 1156 } 1157 1158 /* test if VCC is currently backlogged */ 1159 static inline int vcc_is_backlogged(const struct lanai_vcc *lvcc) 1160 { 1161 return !skb_queue_empty(&lvcc->tx.backlog); 1162 } 1163 1164 /* Bit fields in the segmentation buffer descriptor */ 1165 #define DESCRIPTOR_MAGIC (0xD0000000) 1166 #define DESCRIPTOR_AAL5 (0x00008000) 1167 #define DESCRIPTOR_AAL5_STREAM (0x00004000) 1168 #define DESCRIPTOR_CLP (0x00002000) 1169 1170 /* Add 32-bit descriptor with its padding */ 1171 static inline void vcc_tx_add_aal5_descriptor(struct lanai_vcc *lvcc, 1172 u32 flags, int len) 1173 { 1174 int pos; 1175 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 0, 1176 "vcc_tx_add_aal5_descriptor: bad ptr=%p\n", lvcc->tx.buf.ptr); 1177 lvcc->tx.buf.ptr += 4; /* Hope the values REALLY don't matter */ 1178 pos = ((unsigned char *) lvcc->tx.buf.ptr) - 1179 (unsigned char *) lvcc->tx.buf.start; 1180 APRINTK((pos & ~0x0001FFF0) == 0, 1181 "vcc_tx_add_aal5_descriptor: bad pos (%d) before, vci=%d, " 1182 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, 1183 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); 1184 pos = (pos + len) & (lanai_buf_size(&lvcc->tx.buf) - 1); 1185 APRINTK((pos & ~0x0001FFF0) == 0, 1186 "vcc_tx_add_aal5_descriptor: bad pos (%d) after, vci=%d, " 1187 "start,ptr,end=%p,%p,%p\n", pos, lvcc->vci, 1188 lvcc->tx.buf.start, lvcc->tx.buf.ptr, lvcc->tx.buf.end); 1189 lvcc->tx.buf.ptr[-1] = 1190 cpu_to_le32(DESCRIPTOR_MAGIC | DESCRIPTOR_AAL5 | 1191 ((lvcc->tx.atmvcc->atm_options & ATM_ATMOPT_CLP) ? 1192 DESCRIPTOR_CLP : 0) | flags | pos >> 4); 1193 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) 1194 lvcc->tx.buf.ptr = lvcc->tx.buf.start; 1195 } 1196 1197 /* Add 32-bit AAL5 trailer and leave room for its CRC */ 1198 static inline void vcc_tx_add_aal5_trailer(struct lanai_vcc *lvcc, 1199 int len, int cpi, int uu) 1200 { 1201 APRINTK((((unsigned long) lvcc->tx.buf.ptr) & 15) == 8, 1202 "vcc_tx_add_aal5_trailer: bad ptr=%p\n", lvcc->tx.buf.ptr); 1203 lvcc->tx.buf.ptr += 2; 1204 lvcc->tx.buf.ptr[-2] = cpu_to_be32((uu << 24) | (cpi << 16) | len); 1205 if (lvcc->tx.buf.ptr >= lvcc->tx.buf.end) 1206 lvcc->tx.buf.ptr = lvcc->tx.buf.start; 1207 } 1208 1209 static inline void vcc_tx_memcpy(struct lanai_vcc *lvcc, 1210 const unsigned char *src, int n) 1211 { 1212 unsigned char *e; 1213 int m; 1214 e = ((unsigned char *) lvcc->tx.buf.ptr) + n; 1215 m = e - (unsigned char *) lvcc->tx.buf.end; 1216 if (m < 0) 1217 m = 0; 1218 memcpy(lvcc->tx.buf.ptr, src, n - m); 1219 if (m != 0) { 1220 memcpy(lvcc->tx.buf.start, src + n - m, m); 1221 e = ((unsigned char *) lvcc->tx.buf.start) + m; 1222 } 1223 lvcc->tx.buf.ptr = (u32 *) e; 1224 } 1225 1226 static inline void vcc_tx_memzero(struct lanai_vcc *lvcc, int n) 1227 { 1228 unsigned char *e; 1229 int m; 1230 if (n == 0) 1231 return; 1232 e = ((unsigned char *) lvcc->tx.buf.ptr) + n; 1233 m = e - (unsigned char *) lvcc->tx.buf.end; 1234 if (m < 0) 1235 m = 0; 1236 memset(lvcc->tx.buf.ptr, 0, n - m); 1237 if (m != 0) { 1238 memset(lvcc->tx.buf.start, 0, m); 1239 e = ((unsigned char *) lvcc->tx.buf.start) + m; 1240 } 1241 lvcc->tx.buf.ptr = (u32 *) e; 1242 } 1243 1244 /* Update "butt" register to specify new WritePtr */ 1245 static inline void lanai_endtx(struct lanai_dev *lanai, 1246 const struct lanai_vcc *lvcc) 1247 { 1248 int i, ptr = ((unsigned char *) lvcc->tx.buf.ptr) - 1249 (unsigned char *) lvcc->tx.buf.start; 1250 APRINTK((ptr & ~0x0001FFF0) == 0, 1251 "lanai_endtx: bad ptr (%d), vci=%d, start,ptr,end=%p,%p,%p\n", 1252 ptr, lvcc->vci, lvcc->tx.buf.start, lvcc->tx.buf.ptr, 1253 lvcc->tx.buf.end); 1254 1255 /* 1256 * Since the "butt register" is a shared resounce on the card we 1257 * serialize all accesses to it through this spinlock. This is 1258 * mostly just paranoia sicne the register is rarely "busy" anyway 1259 * but is needed for correctness. 1260 */ 1261 spin_lock(&lanai->endtxlock); 1262 /* 1263 * We need to check if the "butt busy" bit is set before 1264 * updating the butt register. In theory this should 1265 * never happen because the ATM card is plenty fast at 1266 * updating the register. Still, we should make sure 1267 */ 1268 for (i = 0; reg_read(lanai, Status_Reg) & STATUS_BUTTBUSY; i++) { 1269 if (unlikely(i > 50)) { 1270 printk(KERN_ERR DEV_LABEL "(itf %d): butt register " 1271 "always busy!\n", lanai->number); 1272 break; 1273 } 1274 udelay(5); 1275 } 1276 /* 1277 * Before we tall the card to start work we need to be sure 100% of 1278 * the info in the service buffer has been written before we tell 1279 * the card about it 1280 */ 1281 wmb(); 1282 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); 1283 spin_unlock(&lanai->endtxlock); 1284 } 1285 1286 /* 1287 * Add one AAL5 PDU to lvcc's transmit buffer. Caller garauntees there's 1288 * space available. "pdusize" is the number of bytes the PDU will take 1289 */ 1290 static void lanai_send_one_aal5(struct lanai_dev *lanai, 1291 struct lanai_vcc *lvcc, struct sk_buff *skb, int pdusize) 1292 { 1293 int pad; 1294 APRINTK(pdusize == aal5_size(skb->len), 1295 "lanai_send_one_aal5: wrong size packet (%d != %d)\n", 1296 pdusize, aal5_size(skb->len)); 1297 vcc_tx_add_aal5_descriptor(lvcc, 0, pdusize); 1298 pad = pdusize - skb->len - 8; 1299 APRINTK(pad >= 0, "pad is negative (%d)\n", pad); 1300 APRINTK(pad < 48, "pad is too big (%d)\n", pad); 1301 vcc_tx_memcpy(lvcc, skb->data, skb->len); 1302 vcc_tx_memzero(lvcc, pad); 1303 vcc_tx_add_aal5_trailer(lvcc, skb->len, 0, 0); 1304 lanai_endtx(lanai, lvcc); 1305 lanai_free_skb(lvcc->tx.atmvcc, skb); 1306 atomic_inc(&lvcc->tx.atmvcc->stats->tx); 1307 } 1308 1309 /* Try to fill the buffer - don't call unless there is backlog */ 1310 static void vcc_tx_unqueue_aal5(struct lanai_dev *lanai, 1311 struct lanai_vcc *lvcc, int endptr) 1312 { 1313 int n; 1314 struct sk_buff *skb; 1315 int space = vcc_tx_space(lvcc, endptr); 1316 APRINTK(vcc_is_backlogged(lvcc), 1317 "vcc_tx_unqueue() called with empty backlog (vci=%d)\n", 1318 lvcc->vci); 1319 while (space >= 64) { 1320 skb = skb_dequeue(&lvcc->tx.backlog); 1321 if (skb == NULL) 1322 goto no_backlog; 1323 n = aal5_size(skb->len); 1324 if (n + 16 > space) { 1325 /* No room for this packet - put it back on queue */ 1326 skb_queue_head(&lvcc->tx.backlog, skb); 1327 return; 1328 } 1329 lanai_send_one_aal5(lanai, lvcc, skb, n); 1330 space -= n + 16; 1331 } 1332 if (!vcc_is_backlogged(lvcc)) { 1333 no_backlog: 1334 __clear_bit(lvcc->vci, lanai->backlog_vccs); 1335 } 1336 } 1337 1338 /* Given an skb that we want to transmit either send it now or queue */ 1339 static void vcc_tx_aal5(struct lanai_dev *lanai, struct lanai_vcc *lvcc, 1340 struct sk_buff *skb) 1341 { 1342 int space, n; 1343 if (vcc_is_backlogged(lvcc)) /* Already backlogged */ 1344 goto queue_it; 1345 space = vcc_tx_space(lvcc, 1346 TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr))); 1347 n = aal5_size(skb->len); 1348 APRINTK(n + 16 >= 64, "vcc_tx_aal5: n too small (%d)\n", n); 1349 if (space < n + 16) { /* No space for this PDU */ 1350 __set_bit(lvcc->vci, lanai->backlog_vccs); 1351 queue_it: 1352 skb_queue_tail(&lvcc->tx.backlog, skb); 1353 return; 1354 } 1355 lanai_send_one_aal5(lanai, lvcc, skb, n); 1356 } 1357 1358 static void vcc_tx_unqueue_aal0(struct lanai_dev *lanai, 1359 struct lanai_vcc *lvcc, int endptr) 1360 { 1361 printk(KERN_INFO DEV_LABEL 1362 ": vcc_tx_unqueue_aal0: not implemented\n"); 1363 } 1364 1365 static void vcc_tx_aal0(struct lanai_dev *lanai, struct lanai_vcc *lvcc, 1366 struct sk_buff *skb) 1367 { 1368 printk(KERN_INFO DEV_LABEL ": vcc_tx_aal0: not implemented\n"); 1369 /* Remember to increment lvcc->tx.atmvcc->stats->tx */ 1370 lanai_free_skb(lvcc->tx.atmvcc, skb); 1371 } 1372 1373 /* -------------------- VCC RX BUFFER UTILITIES: */ 1374 1375 /* unlike the _tx_ cousins, this doesn't update ptr */ 1376 static inline void vcc_rx_memcpy(unsigned char *dest, 1377 const struct lanai_vcc *lvcc, int n) 1378 { 1379 int m = ((const unsigned char *) lvcc->rx.buf.ptr) + n - 1380 ((const unsigned char *) (lvcc->rx.buf.end)); 1381 if (m < 0) 1382 m = 0; 1383 memcpy(dest, lvcc->rx.buf.ptr, n - m); 1384 memcpy(dest + n - m, lvcc->rx.buf.start, m); 1385 /* Make sure that these copies don't get reordered */ 1386 barrier(); 1387 } 1388 1389 /* Receive AAL5 data on a VCC with a particular endptr */ 1390 static void vcc_rx_aal5(struct lanai_vcc *lvcc, int endptr) 1391 { 1392 int size; 1393 struct sk_buff *skb; 1394 const u32 *x; 1395 u32 *end = &lvcc->rx.buf.start[endptr * 4]; 1396 int n = ((unsigned long) end) - ((unsigned long) lvcc->rx.buf.ptr); 1397 if (n < 0) 1398 n += lanai_buf_size(&lvcc->rx.buf); 1399 APRINTK(n >= 0 && n < lanai_buf_size(&lvcc->rx.buf) && !(n & 15), 1400 "vcc_rx_aal5: n out of range (%d/%Zu)\n", 1401 n, lanai_buf_size(&lvcc->rx.buf)); 1402 /* Recover the second-to-last word to get true pdu length */ 1403 if ((x = &end[-2]) < lvcc->rx.buf.start) 1404 x = &lvcc->rx.buf.end[-2]; 1405 /* 1406 * Before we actually read from the buffer, make sure the memory 1407 * changes have arrived 1408 */ 1409 rmb(); 1410 size = be32_to_cpup(x) & 0xffff; 1411 if (unlikely(n != aal5_size(size))) { 1412 /* Make sure size matches padding */ 1413 printk(KERN_INFO DEV_LABEL "(itf %d): Got bad AAL5 length " 1414 "on vci=%d - size=%d n=%d\n", 1415 lvcc->rx.atmvcc->dev->number, lvcc->vci, size, n); 1416 lvcc->stats.x.aal5.rx_badlen++; 1417 goto out; 1418 } 1419 skb = atm_alloc_charge(lvcc->rx.atmvcc, size, GFP_ATOMIC); 1420 if (unlikely(skb == NULL)) { 1421 lvcc->stats.rx_nomem++; 1422 goto out; 1423 } 1424 skb_put(skb, size); 1425 vcc_rx_memcpy(skb->data, lvcc, size); 1426 ATM_SKB(skb)->vcc = lvcc->rx.atmvcc; 1427 __net_timestamp(skb); 1428 lvcc->rx.atmvcc->push(lvcc->rx.atmvcc, skb); 1429 atomic_inc(&lvcc->rx.atmvcc->stats->rx); 1430 out: 1431 lvcc->rx.buf.ptr = end; 1432 cardvcc_write(lvcc, endptr, vcc_rxreadptr); 1433 } 1434 1435 static void vcc_rx_aal0(struct lanai_dev *lanai) 1436 { 1437 printk(KERN_INFO DEV_LABEL ": vcc_rx_aal0: not implemented\n"); 1438 /* Remember to get read_lock(&vcc_sklist_lock) while looking up VC */ 1439 /* Remember to increment lvcc->rx.atmvcc->stats->rx */ 1440 } 1441 1442 /* -------------------- MANAGING HOST-BASED VCC TABLE: */ 1443 1444 /* Decide whether to use vmalloc or get_zeroed_page for VCC table */ 1445 #if (NUM_VCI * BITS_PER_LONG) <= PAGE_SIZE 1446 #define VCCTABLE_GETFREEPAGE 1447 #else 1448 #include <linux/vmalloc.h> 1449 #endif 1450 1451 static int __devinit vcc_table_allocate(struct lanai_dev *lanai) 1452 { 1453 #ifdef VCCTABLE_GETFREEPAGE 1454 APRINTK((lanai->num_vci) * sizeof(struct lanai_vcc *) <= PAGE_SIZE, 1455 "vcc table > PAGE_SIZE!"); 1456 lanai->vccs = (struct lanai_vcc **) get_zeroed_page(GFP_KERNEL); 1457 return (lanai->vccs == NULL) ? -ENOMEM : 0; 1458 #else 1459 int bytes = (lanai->num_vci) * sizeof(struct lanai_vcc *); 1460 lanai->vccs = (struct lanai_vcc **) vmalloc(bytes); 1461 if (unlikely(lanai->vccs == NULL)) 1462 return -ENOMEM; 1463 memset(lanai->vccs, 0, bytes); 1464 return 0; 1465 #endif 1466 } 1467 1468 static inline void vcc_table_deallocate(const struct lanai_dev *lanai) 1469 { 1470 #ifdef VCCTABLE_GETFREEPAGE 1471 free_page((unsigned long) lanai->vccs); 1472 #else 1473 vfree(lanai->vccs); 1474 #endif 1475 } 1476 1477 /* Allocate a fresh lanai_vcc, with the appropriate things cleared */ 1478 static inline struct lanai_vcc *new_lanai_vcc(void) 1479 { 1480 struct lanai_vcc *lvcc; 1481 lvcc = kzalloc(sizeof(*lvcc), GFP_KERNEL); 1482 if (likely(lvcc != NULL)) { 1483 skb_queue_head_init(&lvcc->tx.backlog); 1484 #ifdef DEBUG 1485 lvcc->vci = -1; 1486 #endif 1487 } 1488 return lvcc; 1489 } 1490 1491 static int lanai_get_sized_buffer(struct lanai_dev *lanai, 1492 struct lanai_buffer *buf, int max_sdu, int multiplier, 1493 const char *name) 1494 { 1495 int size; 1496 if (unlikely(max_sdu < 1)) 1497 max_sdu = 1; 1498 max_sdu = aal5_size(max_sdu); 1499 size = (max_sdu + 16) * multiplier + 16; 1500 lanai_buf_allocate(buf, size, max_sdu + 32, lanai->pci); 1501 if (unlikely(buf->start == NULL)) 1502 return -ENOMEM; 1503 if (unlikely(lanai_buf_size(buf) < size)) 1504 printk(KERN_WARNING DEV_LABEL "(itf %d): wanted %d bytes " 1505 "for %s buffer, got only %Zu\n", lanai->number, size, 1506 name, lanai_buf_size(buf)); 1507 DPRINTK("Allocated %Zu byte %s buffer\n", lanai_buf_size(buf), name); 1508 return 0; 1509 } 1510 1511 /* Setup a RX buffer for a currently unbound AAL5 vci */ 1512 static inline int lanai_setup_rx_vci_aal5(struct lanai_dev *lanai, 1513 struct lanai_vcc *lvcc, const struct atm_qos *qos) 1514 { 1515 return lanai_get_sized_buffer(lanai, &lvcc->rx.buf, 1516 qos->rxtp.max_sdu, AAL5_RX_MULTIPLIER, "RX"); 1517 } 1518 1519 /* Setup a TX buffer for a currently unbound AAL5 vci */ 1520 static int lanai_setup_tx_vci(struct lanai_dev *lanai, struct lanai_vcc *lvcc, 1521 const struct atm_qos *qos) 1522 { 1523 int max_sdu, multiplier; 1524 if (qos->aal == ATM_AAL0) { 1525 lvcc->tx.unqueue = vcc_tx_unqueue_aal0; 1526 max_sdu = ATM_CELL_SIZE - 1; 1527 multiplier = AAL0_TX_MULTIPLIER; 1528 } else { 1529 lvcc->tx.unqueue = vcc_tx_unqueue_aal5; 1530 max_sdu = qos->txtp.max_sdu; 1531 multiplier = AAL5_TX_MULTIPLIER; 1532 } 1533 return lanai_get_sized_buffer(lanai, &lvcc->tx.buf, max_sdu, 1534 multiplier, "TX"); 1535 } 1536 1537 static inline void host_vcc_bind(struct lanai_dev *lanai, 1538 struct lanai_vcc *lvcc, vci_t vci) 1539 { 1540 if (lvcc->vbase != NULL) 1541 return; /* We already were bound in the other direction */ 1542 DPRINTK("Binding vci %d\n", vci); 1543 #ifdef USE_POWERDOWN 1544 if (lanai->nbound++ == 0) { 1545 DPRINTK("Coming out of powerdown\n"); 1546 lanai->conf1 &= ~CONFIG1_POWERDOWN; 1547 conf1_write(lanai); 1548 conf2_write(lanai); 1549 } 1550 #endif 1551 lvcc->vbase = cardvcc_addr(lanai, vci); 1552 lanai->vccs[lvcc->vci = vci] = lvcc; 1553 } 1554 1555 static inline void host_vcc_unbind(struct lanai_dev *lanai, 1556 struct lanai_vcc *lvcc) 1557 { 1558 if (lvcc->vbase == NULL) 1559 return; /* This vcc was never bound */ 1560 DPRINTK("Unbinding vci %d\n", lvcc->vci); 1561 lvcc->vbase = NULL; 1562 lanai->vccs[lvcc->vci] = NULL; 1563 #ifdef USE_POWERDOWN 1564 if (--lanai->nbound == 0) { 1565 DPRINTK("Going into powerdown\n"); 1566 lanai->conf1 |= CONFIG1_POWERDOWN; 1567 conf1_write(lanai); 1568 } 1569 #endif 1570 } 1571 1572 /* -------------------- RESET CARD: */ 1573 1574 static void lanai_reset(struct lanai_dev *lanai) 1575 { 1576 printk(KERN_CRIT DEV_LABEL "(itf %d): *NOT* reseting - not " 1577 "implemented\n", lanai->number); 1578 /* TODO */ 1579 /* The following is just a hack until we write the real 1580 * resetter - at least ack whatever interrupt sent us 1581 * here 1582 */ 1583 reg_write(lanai, INT_ALL, IntAck_Reg); 1584 lanai->stats.card_reset++; 1585 } 1586 1587 /* -------------------- SERVICE LIST UTILITIES: */ 1588 1589 /* 1590 * Allocate service buffer and tell card about it 1591 */ 1592 static int __devinit service_buffer_allocate(struct lanai_dev *lanai) 1593 { 1594 lanai_buf_allocate(&lanai->service, SERVICE_ENTRIES * 4, 8, 1595 lanai->pci); 1596 if (unlikely(lanai->service.start == NULL)) 1597 return -ENOMEM; 1598 DPRINTK("allocated service buffer at 0x%08lX, size %Zu(%d)\n", 1599 (unsigned long) lanai->service.start, 1600 lanai_buf_size(&lanai->service), 1601 lanai_buf_size_cardorder(&lanai->service)); 1602 /* Clear ServWrite register to be safe */ 1603 reg_write(lanai, 0, ServWrite_Reg); 1604 /* ServiceStuff register contains size and address of buffer */ 1605 reg_write(lanai, 1606 SSTUFF_SET_SIZE(lanai_buf_size_cardorder(&lanai->service)) | 1607 SSTUFF_SET_ADDR(lanai->service.dmaaddr), 1608 ServiceStuff_Reg); 1609 return 0; 1610 } 1611 1612 static inline void service_buffer_deallocate(struct lanai_dev *lanai) 1613 { 1614 lanai_buf_deallocate(&lanai->service, lanai->pci); 1615 } 1616 1617 /* Bitfields in service list */ 1618 #define SERVICE_TX (0x80000000) /* Was from transmission */ 1619 #define SERVICE_TRASH (0x40000000) /* RXed PDU was trashed */ 1620 #define SERVICE_CRCERR (0x20000000) /* RXed PDU had CRC error */ 1621 #define SERVICE_CI (0x10000000) /* RXed PDU had CI set */ 1622 #define SERVICE_CLP (0x08000000) /* RXed PDU had CLP set */ 1623 #define SERVICE_STREAM (0x04000000) /* RX Stream mode */ 1624 #define SERVICE_GET_VCI(x) (((x)>>16)&0x3FF) 1625 #define SERVICE_GET_END(x) ((x)&0x1FFF) 1626 1627 /* Handle one thing from the service list - returns true if it marked a 1628 * VCC ready for xmit 1629 */ 1630 static int handle_service(struct lanai_dev *lanai, u32 s) 1631 { 1632 vci_t vci = SERVICE_GET_VCI(s); 1633 struct lanai_vcc *lvcc; 1634 read_lock(&vcc_sklist_lock); 1635 lvcc = lanai->vccs[vci]; 1636 if (unlikely(lvcc == NULL)) { 1637 read_unlock(&vcc_sklist_lock); 1638 DPRINTK("(itf %d) got service entry 0x%X for nonexistent " 1639 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1640 if (s & SERVICE_TX) 1641 lanai->stats.service_notx++; 1642 else 1643 lanai->stats.service_norx++; 1644 return 0; 1645 } 1646 if (s & SERVICE_TX) { /* segmentation interrupt */ 1647 if (unlikely(lvcc->tx.atmvcc == NULL)) { 1648 read_unlock(&vcc_sklist_lock); 1649 DPRINTK("(itf %d) got service entry 0x%X for non-TX " 1650 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1651 lanai->stats.service_notx++; 1652 return 0; 1653 } 1654 __set_bit(vci, lanai->transmit_ready); 1655 lvcc->tx.endptr = SERVICE_GET_END(s); 1656 read_unlock(&vcc_sklist_lock); 1657 return 1; 1658 } 1659 if (unlikely(lvcc->rx.atmvcc == NULL)) { 1660 read_unlock(&vcc_sklist_lock); 1661 DPRINTK("(itf %d) got service entry 0x%X for non-RX " 1662 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1663 lanai->stats.service_norx++; 1664 return 0; 1665 } 1666 if (unlikely(lvcc->rx.atmvcc->qos.aal != ATM_AAL5)) { 1667 read_unlock(&vcc_sklist_lock); 1668 DPRINTK("(itf %d) got RX service entry 0x%X for non-AAL5 " 1669 "vcc %d\n", lanai->number, (unsigned int) s, vci); 1670 lanai->stats.service_rxnotaal5++; 1671 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1672 return 0; 1673 } 1674 if (likely(!(s & (SERVICE_TRASH | SERVICE_STREAM | SERVICE_CRCERR)))) { 1675 vcc_rx_aal5(lvcc, SERVICE_GET_END(s)); 1676 read_unlock(&vcc_sklist_lock); 1677 return 0; 1678 } 1679 if (s & SERVICE_TRASH) { 1680 int bytes; 1681 read_unlock(&vcc_sklist_lock); 1682 DPRINTK("got trashed rx pdu on vci %d\n", vci); 1683 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1684 lvcc->stats.x.aal5.service_trash++; 1685 bytes = (SERVICE_GET_END(s) * 16) - 1686 (((unsigned long) lvcc->rx.buf.ptr) - 1687 ((unsigned long) lvcc->rx.buf.start)) + 47; 1688 if (bytes < 0) 1689 bytes += lanai_buf_size(&lvcc->rx.buf); 1690 lanai->stats.ovfl_trash += (bytes / 48); 1691 return 0; 1692 } 1693 if (s & SERVICE_STREAM) { 1694 read_unlock(&vcc_sklist_lock); 1695 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1696 lvcc->stats.x.aal5.service_stream++; 1697 printk(KERN_ERR DEV_LABEL "(itf %d): Got AAL5 stream " 1698 "PDU on VCI %d!\n", lanai->number, vci); 1699 lanai_reset(lanai); 1700 return 0; 1701 } 1702 DPRINTK("got rx crc error on vci %d\n", vci); 1703 atomic_inc(&lvcc->rx.atmvcc->stats->rx_err); 1704 lvcc->stats.x.aal5.service_rxcrc++; 1705 lvcc->rx.buf.ptr = &lvcc->rx.buf.start[SERVICE_GET_END(s) * 4]; 1706 cardvcc_write(lvcc, SERVICE_GET_END(s), vcc_rxreadptr); 1707 read_unlock(&vcc_sklist_lock); 1708 return 0; 1709 } 1710 1711 /* Try transmitting on all VCIs that we marked ready to serve */ 1712 static void iter_transmit(struct lanai_dev *lanai, vci_t vci) 1713 { 1714 struct lanai_vcc *lvcc = lanai->vccs[vci]; 1715 if (vcc_is_backlogged(lvcc)) 1716 lvcc->tx.unqueue(lanai, lvcc, lvcc->tx.endptr); 1717 } 1718 1719 /* Run service queue -- called from interrupt context or with 1720 * interrupts otherwise disabled and with the lanai->servicelock 1721 * lock held 1722 */ 1723 static void run_service(struct lanai_dev *lanai) 1724 { 1725 int ntx = 0; 1726 u32 wreg = reg_read(lanai, ServWrite_Reg); 1727 const u32 *end = lanai->service.start + wreg; 1728 while (lanai->service.ptr != end) { 1729 ntx += handle_service(lanai, 1730 le32_to_cpup(lanai->service.ptr++)); 1731 if (lanai->service.ptr >= lanai->service.end) 1732 lanai->service.ptr = lanai->service.start; 1733 } 1734 reg_write(lanai, wreg, ServRead_Reg); 1735 if (ntx != 0) { 1736 read_lock(&vcc_sklist_lock); 1737 vci_bitfield_iterate(lanai, lanai->transmit_ready, 1738 iter_transmit); 1739 bitmap_zero(lanai->transmit_ready, NUM_VCI); 1740 read_unlock(&vcc_sklist_lock); 1741 } 1742 } 1743 1744 /* -------------------- GATHER STATISTICS: */ 1745 1746 static void get_statistics(struct lanai_dev *lanai) 1747 { 1748 u32 statreg = reg_read(lanai, Statistics_Reg); 1749 lanai->stats.atm_ovfl += STATS_GET_FIFO_OVFL(statreg); 1750 lanai->stats.hec_err += STATS_GET_HEC_ERR(statreg); 1751 lanai->stats.vci_trash += STATS_GET_BAD_VCI(statreg); 1752 lanai->stats.ovfl_trash += STATS_GET_BUF_OVFL(statreg); 1753 } 1754 1755 /* -------------------- POLLING TIMER: */ 1756 1757 #ifndef DEBUG_RW 1758 /* Try to undequeue 1 backlogged vcc */ 1759 static void iter_dequeue(struct lanai_dev *lanai, vci_t vci) 1760 { 1761 struct lanai_vcc *lvcc = lanai->vccs[vci]; 1762 int endptr; 1763 if (lvcc == NULL || lvcc->tx.atmvcc == NULL || 1764 !vcc_is_backlogged(lvcc)) { 1765 __clear_bit(vci, lanai->backlog_vccs); 1766 return; 1767 } 1768 endptr = TXREADPTR_GET_PTR(cardvcc_read(lvcc, vcc_txreadptr)); 1769 lvcc->tx.unqueue(lanai, lvcc, endptr); 1770 } 1771 #endif /* !DEBUG_RW */ 1772 1773 static void lanai_timed_poll(unsigned long arg) 1774 { 1775 struct lanai_dev *lanai = (struct lanai_dev *) arg; 1776 #ifndef DEBUG_RW 1777 unsigned long flags; 1778 #ifdef USE_POWERDOWN 1779 if (lanai->conf1 & CONFIG1_POWERDOWN) 1780 return; 1781 #endif /* USE_POWERDOWN */ 1782 local_irq_save(flags); 1783 /* If we can grab the spinlock, check if any services need to be run */ 1784 if (spin_trylock(&lanai->servicelock)) { 1785 run_service(lanai); 1786 spin_unlock(&lanai->servicelock); 1787 } 1788 /* ...and see if any backlogged VCs can make progress */ 1789 /* unfortunately linux has no read_trylock() currently */ 1790 read_lock(&vcc_sklist_lock); 1791 vci_bitfield_iterate(lanai, lanai->backlog_vccs, iter_dequeue); 1792 read_unlock(&vcc_sklist_lock); 1793 local_irq_restore(flags); 1794 1795 get_statistics(lanai); 1796 #endif /* !DEBUG_RW */ 1797 mod_timer(&lanai->timer, jiffies + LANAI_POLL_PERIOD); 1798 } 1799 1800 static inline void lanai_timed_poll_start(struct lanai_dev *lanai) 1801 { 1802 init_timer(&lanai->timer); 1803 lanai->timer.expires = jiffies + LANAI_POLL_PERIOD; 1804 lanai->timer.data = (unsigned long) lanai; 1805 lanai->timer.function = lanai_timed_poll; 1806 add_timer(&lanai->timer); 1807 } 1808 1809 static inline void lanai_timed_poll_stop(struct lanai_dev *lanai) 1810 { 1811 del_timer_sync(&lanai->timer); 1812 } 1813 1814 /* -------------------- INTERRUPT SERVICE: */ 1815 1816 static inline void lanai_int_1(struct lanai_dev *lanai, u32 reason) 1817 { 1818 u32 ack = 0; 1819 if (reason & INT_SERVICE) { 1820 ack = INT_SERVICE; 1821 spin_lock(&lanai->servicelock); 1822 run_service(lanai); 1823 spin_unlock(&lanai->servicelock); 1824 } 1825 if (reason & (INT_AAL0_STR | INT_AAL0)) { 1826 ack |= reason & (INT_AAL0_STR | INT_AAL0); 1827 vcc_rx_aal0(lanai); 1828 } 1829 /* The rest of the interrupts are pretty rare */ 1830 if (ack == reason) 1831 goto done; 1832 if (reason & INT_STATS) { 1833 reason &= ~INT_STATS; /* No need to ack */ 1834 get_statistics(lanai); 1835 } 1836 if (reason & INT_STATUS) { 1837 ack |= reason & INT_STATUS; 1838 lanai_check_status(lanai); 1839 } 1840 if (unlikely(reason & INT_DMASHUT)) { 1841 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - DMA " 1842 "shutdown, reason=0x%08X, address=0x%08X\n", 1843 lanai->number, (unsigned int) (reason & INT_DMASHUT), 1844 (unsigned int) reg_read(lanai, DMA_Addr_Reg)); 1845 if (reason & INT_TABORTBM) { 1846 lanai_reset(lanai); 1847 return; 1848 } 1849 ack |= (reason & INT_DMASHUT); 1850 printk(KERN_ERR DEV_LABEL "(itf %d): re-enabling DMA\n", 1851 lanai->number); 1852 conf1_write(lanai); 1853 lanai->stats.dma_reenable++; 1854 pcistatus_check(lanai, 0); 1855 } 1856 if (unlikely(reason & INT_TABORTSENT)) { 1857 ack |= (reason & INT_TABORTSENT); 1858 printk(KERN_ERR DEV_LABEL "(itf %d): sent PCI target abort\n", 1859 lanai->number); 1860 pcistatus_check(lanai, 0); 1861 } 1862 if (unlikely(reason & INT_SEGSHUT)) { 1863 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " 1864 "segmentation shutdown, reason=0x%08X\n", lanai->number, 1865 (unsigned int) (reason & INT_SEGSHUT)); 1866 lanai_reset(lanai); 1867 return; 1868 } 1869 if (unlikely(reason & (INT_PING | INT_WAKE))) { 1870 printk(KERN_ERR DEV_LABEL "(itf %d): driver error - " 1871 "unexpected interrupt 0x%08X, resetting\n", 1872 lanai->number, 1873 (unsigned int) (reason & (INT_PING | INT_WAKE))); 1874 lanai_reset(lanai); 1875 return; 1876 } 1877 #ifdef DEBUG 1878 if (unlikely(ack != reason)) { 1879 DPRINTK("unacked ints: 0x%08X\n", 1880 (unsigned int) (reason & ~ack)); 1881 ack = reason; 1882 } 1883 #endif 1884 done: 1885 if (ack != 0) 1886 reg_write(lanai, ack, IntAck_Reg); 1887 } 1888 1889 static irqreturn_t lanai_int(int irq, void *devid) 1890 { 1891 struct lanai_dev *lanai = devid; 1892 u32 reason; 1893 1894 #ifdef USE_POWERDOWN 1895 /* 1896 * If we're powered down we shouldn't be generating any interrupts - 1897 * so assume that this is a shared interrupt line and it's for someone 1898 * else 1899 */ 1900 if (unlikely(lanai->conf1 & CONFIG1_POWERDOWN)) 1901 return IRQ_NONE; 1902 #endif 1903 1904 reason = intr_pending(lanai); 1905 if (reason == 0) 1906 return IRQ_NONE; /* Must be for someone else */ 1907 1908 do { 1909 if (unlikely(reason == 0xFFFFFFFF)) 1910 break; /* Maybe we've been unplugged? */ 1911 lanai_int_1(lanai, reason); 1912 reason = intr_pending(lanai); 1913 } while (reason != 0); 1914 1915 return IRQ_HANDLED; 1916 } 1917 1918 /* TODO - it would be nice if we could use the "delayed interrupt" system 1919 * to some advantage 1920 */ 1921 1922 /* -------------------- CHECK BOARD ID/REV: */ 1923 1924 /* 1925 * The board id and revision are stored both in the reset register and 1926 * in the PCI configuration space - the documentation says to check 1927 * each of them. If revp!=NULL we store the revision there 1928 */ 1929 static int check_board_id_and_rev(const char *name, u32 val, int *revp) 1930 { 1931 DPRINTK("%s says board_id=%d, board_rev=%d\n", name, 1932 (int) RESET_GET_BOARD_ID(val), 1933 (int) RESET_GET_BOARD_REV(val)); 1934 if (RESET_GET_BOARD_ID(val) != BOARD_ID_LANAI256) { 1935 printk(KERN_ERR DEV_LABEL ": Found %s board-id %d -- not a " 1936 "Lanai 25.6\n", name, (int) RESET_GET_BOARD_ID(val)); 1937 return -ENODEV; 1938 } 1939 if (revp != NULL) 1940 *revp = RESET_GET_BOARD_REV(val); 1941 return 0; 1942 } 1943 1944 /* -------------------- PCI INITIALIZATION/SHUTDOWN: */ 1945 1946 static int __devinit lanai_pci_start(struct lanai_dev *lanai) 1947 { 1948 struct pci_dev *pci = lanai->pci; 1949 int result; 1950 u16 w; 1951 1952 if (pci_enable_device(pci) != 0) { 1953 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable " 1954 "PCI device", lanai->number); 1955 return -ENXIO; 1956 } 1957 pci_set_master(pci); 1958 if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) != 0) { 1959 printk(KERN_WARNING DEV_LABEL 1960 "(itf %d): No suitable DMA available.\n", lanai->number); 1961 return -EBUSY; 1962 } 1963 if (pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32)) != 0) { 1964 printk(KERN_WARNING DEV_LABEL 1965 "(itf %d): No suitable DMA available.\n", lanai->number); 1966 return -EBUSY; 1967 } 1968 result = pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &w); 1969 if (result != PCIBIOS_SUCCESSFUL) { 1970 printk(KERN_ERR DEV_LABEL "(itf %d): can't read " 1971 "PCI_SUBSYSTEM_ID: %d\n", lanai->number, result); 1972 return -EINVAL; 1973 } 1974 result = check_board_id_and_rev("PCI", w, NULL); 1975 if (result != 0) 1976 return result; 1977 /* Set latency timer to zero as per lanai docs */ 1978 result = pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0); 1979 if (result != PCIBIOS_SUCCESSFUL) { 1980 printk(KERN_ERR DEV_LABEL "(itf %d): can't write " 1981 "PCI_LATENCY_TIMER: %d\n", lanai->number, result); 1982 return -EINVAL; 1983 } 1984 pcistatus_check(lanai, 1); 1985 pcistatus_check(lanai, 0); 1986 return 0; 1987 } 1988 1989 /* -------------------- VPI/VCI ALLOCATION: */ 1990 1991 /* 1992 * We _can_ use VCI==0 for normal traffic, but only for UBR (or we'll 1993 * get a CBRZERO interrupt), and we can use it only if noone is receiving 1994 * AAL0 traffic (since they will use the same queue) - according to the 1995 * docs we shouldn't even use it for AAL0 traffic 1996 */ 1997 static inline int vci0_is_ok(struct lanai_dev *lanai, 1998 const struct atm_qos *qos) 1999 { 2000 if (qos->txtp.traffic_class == ATM_CBR || qos->aal == ATM_AAL0) 2001 return 0; 2002 if (qos->rxtp.traffic_class != ATM_NONE) { 2003 if (lanai->naal0 != 0) 2004 return 0; 2005 lanai->conf2 |= CONFIG2_VCI0_NORMAL; 2006 conf2_write_if_powerup(lanai); 2007 } 2008 return 1; 2009 } 2010 2011 /* return true if vci is currently unused, or if requested qos is 2012 * compatible 2013 */ 2014 static int vci_is_ok(struct lanai_dev *lanai, vci_t vci, 2015 const struct atm_vcc *atmvcc) 2016 { 2017 const struct atm_qos *qos = &atmvcc->qos; 2018 const struct lanai_vcc *lvcc = lanai->vccs[vci]; 2019 if (vci == 0 && !vci0_is_ok(lanai, qos)) 2020 return 0; 2021 if (unlikely(lvcc != NULL)) { 2022 if (qos->rxtp.traffic_class != ATM_NONE && 2023 lvcc->rx.atmvcc != NULL && lvcc->rx.atmvcc != atmvcc) 2024 return 0; 2025 if (qos->txtp.traffic_class != ATM_NONE && 2026 lvcc->tx.atmvcc != NULL && lvcc->tx.atmvcc != atmvcc) 2027 return 0; 2028 if (qos->txtp.traffic_class == ATM_CBR && 2029 lanai->cbrvcc != NULL && lanai->cbrvcc != atmvcc) 2030 return 0; 2031 } 2032 if (qos->aal == ATM_AAL0 && lanai->naal0 == 0 && 2033 qos->rxtp.traffic_class != ATM_NONE) { 2034 const struct lanai_vcc *vci0 = lanai->vccs[0]; 2035 if (vci0 != NULL && vci0->rx.atmvcc != NULL) 2036 return 0; 2037 lanai->conf2 &= ~CONFIG2_VCI0_NORMAL; 2038 conf2_write_if_powerup(lanai); 2039 } 2040 return 1; 2041 } 2042 2043 static int lanai_normalize_ci(struct lanai_dev *lanai, 2044 const struct atm_vcc *atmvcc, short *vpip, vci_t *vcip) 2045 { 2046 switch (*vpip) { 2047 case ATM_VPI_ANY: 2048 *vpip = 0; 2049 /* FALLTHROUGH */ 2050 case 0: 2051 break; 2052 default: 2053 return -EADDRINUSE; 2054 } 2055 switch (*vcip) { 2056 case ATM_VCI_ANY: 2057 for (*vcip = ATM_NOT_RSV_VCI; *vcip < lanai->num_vci; 2058 (*vcip)++) 2059 if (vci_is_ok(lanai, *vcip, atmvcc)) 2060 return 0; 2061 return -EADDRINUSE; 2062 default: 2063 if (*vcip >= lanai->num_vci || *vcip < 0 || 2064 !vci_is_ok(lanai, *vcip, atmvcc)) 2065 return -EADDRINUSE; 2066 } 2067 return 0; 2068 } 2069 2070 /* -------------------- MANAGE CBR: */ 2071 2072 /* 2073 * CBR ICG is stored as a fixed-point number with 4 fractional bits. 2074 * Note that storing a number greater than 2046.0 will result in 2075 * incorrect shaping 2076 */ 2077 #define CBRICG_FRAC_BITS (4) 2078 #define CBRICG_MAX (2046 << CBRICG_FRAC_BITS) 2079 2080 /* 2081 * ICG is related to PCR with the formula PCR = MAXPCR / (ICG + 1) 2082 * where MAXPCR is (according to the docs) 25600000/(54*8), 2083 * which is equal to (3125<<9)/27. 2084 * 2085 * Solving for ICG, we get: 2086 * ICG = MAXPCR/PCR - 1 2087 * ICG = (3125<<9)/(27*PCR) - 1 2088 * ICG = ((3125<<9) - (27*PCR)) / (27*PCR) 2089 * 2090 * The end result is supposed to be a fixed-point number with FRAC_BITS 2091 * bits of a fractional part, so we keep everything in the numerator 2092 * shifted by that much as we compute 2093 * 2094 */ 2095 static int pcr_to_cbricg(const struct atm_qos *qos) 2096 { 2097 int rounddown = 0; /* 1 = Round PCR down, i.e. round ICG _up_ */ 2098 int x, icg, pcr = atm_pcr_goal(&qos->txtp); 2099 if (pcr == 0) /* Use maximum bandwidth */ 2100 return 0; 2101 if (pcr < 0) { 2102 rounddown = 1; 2103 pcr = -pcr; 2104 } 2105 x = pcr * 27; 2106 icg = (3125 << (9 + CBRICG_FRAC_BITS)) - (x << CBRICG_FRAC_BITS); 2107 if (rounddown) 2108 icg += x - 1; 2109 icg /= x; 2110 if (icg > CBRICG_MAX) 2111 icg = CBRICG_MAX; 2112 DPRINTK("pcr_to_cbricg: pcr=%d rounddown=%c icg=%d\n", 2113 pcr, rounddown ? 'Y' : 'N', icg); 2114 return icg; 2115 } 2116 2117 static inline void lanai_cbr_setup(struct lanai_dev *lanai) 2118 { 2119 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg); 2120 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg); 2121 lanai->conf2 |= CONFIG2_CBR_ENABLE; 2122 conf2_write(lanai); 2123 } 2124 2125 static inline void lanai_cbr_shutdown(struct lanai_dev *lanai) 2126 { 2127 lanai->conf2 &= ~CONFIG2_CBR_ENABLE; 2128 conf2_write(lanai); 2129 } 2130 2131 /* -------------------- OPERATIONS: */ 2132 2133 /* setup a newly detected device */ 2134 static int __devinit lanai_dev_open(struct atm_dev *atmdev) 2135 { 2136 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; 2137 unsigned long raw_base; 2138 int result; 2139 2140 DPRINTK("In lanai_dev_open()\n"); 2141 /* Basic device fields */ 2142 lanai->number = atmdev->number; 2143 lanai->num_vci = NUM_VCI; 2144 bitmap_zero(lanai->backlog_vccs, NUM_VCI); 2145 bitmap_zero(lanai->transmit_ready, NUM_VCI); 2146 lanai->naal0 = 0; 2147 #ifdef USE_POWERDOWN 2148 lanai->nbound = 0; 2149 #endif 2150 lanai->cbrvcc = NULL; 2151 memset(&lanai->stats, 0, sizeof lanai->stats); 2152 spin_lock_init(&lanai->endtxlock); 2153 spin_lock_init(&lanai->servicelock); 2154 atmdev->ci_range.vpi_bits = 0; 2155 atmdev->ci_range.vci_bits = 0; 2156 while (1 << atmdev->ci_range.vci_bits < lanai->num_vci) 2157 atmdev->ci_range.vci_bits++; 2158 atmdev->link_rate = ATM_25_PCR; 2159 2160 /* 3.2: PCI initialization */ 2161 if ((result = lanai_pci_start(lanai)) != 0) 2162 goto error; 2163 raw_base = lanai->pci->resource[0].start; 2164 lanai->base = (bus_addr_t) ioremap(raw_base, LANAI_MAPPING_SIZE); 2165 if (lanai->base == NULL) { 2166 printk(KERN_ERR DEV_LABEL ": couldn't remap I/O space\n"); 2167 goto error_pci; 2168 } 2169 /* 3.3: Reset lanai and PHY */ 2170 reset_board(lanai); 2171 lanai->conf1 = reg_read(lanai, Config1_Reg); 2172 lanai->conf1 &= ~(CONFIG1_GPOUT1 | CONFIG1_POWERDOWN | 2173 CONFIG1_MASK_LEDMODE); 2174 lanai->conf1 |= CONFIG1_SET_LEDMODE(LEDMODE_NOT_SOOL); 2175 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); 2176 udelay(1000); 2177 conf1_write(lanai); 2178 2179 /* 2180 * 3.4: Turn on endian mode for big-endian hardware 2181 * We don't actually want to do this - the actual bit fields 2182 * in the endian register are not documented anywhere. 2183 * Instead we do the bit-flipping ourselves on big-endian 2184 * hardware. 2185 * 2186 * 3.5: get the board ID/rev by reading the reset register 2187 */ 2188 result = check_board_id_and_rev("register", 2189 reg_read(lanai, Reset_Reg), &lanai->board_rev); 2190 if (result != 0) 2191 goto error_unmap; 2192 2193 /* 3.6: read EEPROM */ 2194 if ((result = eeprom_read(lanai)) != 0) 2195 goto error_unmap; 2196 if ((result = eeprom_validate(lanai)) != 0) 2197 goto error_unmap; 2198 2199 /* 3.7: re-reset PHY, do loopback tests, setup PHY */ 2200 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); 2201 udelay(1000); 2202 conf1_write(lanai); 2203 /* TODO - loopback tests */ 2204 lanai->conf1 |= (CONFIG1_GPOUT2 | CONFIG1_GPOUT3 | CONFIG1_DMA_ENABLE); 2205 conf1_write(lanai); 2206 2207 /* 3.8/3.9: test and initialize card SRAM */ 2208 if ((result = sram_test_and_clear(lanai)) != 0) 2209 goto error_unmap; 2210 2211 /* 3.10: initialize lanai registers */ 2212 lanai->conf1 |= CONFIG1_DMA_ENABLE; 2213 conf1_write(lanai); 2214 if ((result = service_buffer_allocate(lanai)) != 0) 2215 goto error_unmap; 2216 if ((result = vcc_table_allocate(lanai)) != 0) 2217 goto error_service; 2218 lanai->conf2 = (lanai->num_vci >= 512 ? CONFIG2_HOWMANY : 0) | 2219 CONFIG2_HEC_DROP | /* ??? */ CONFIG2_PTI7_MODE; 2220 conf2_write(lanai); 2221 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg); 2222 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ 2223 if ((result = request_irq(lanai->pci->irq, lanai_int, IRQF_SHARED, 2224 DEV_LABEL, lanai)) != 0) { 2225 printk(KERN_ERR DEV_LABEL ": can't allocate interrupt\n"); 2226 goto error_vcctable; 2227 } 2228 mb(); /* Make sure that all that made it */ 2229 intr_enable(lanai, INT_ALL & ~(INT_PING | INT_WAKE)); 2230 /* 3.11: initialize loop mode (i.e. turn looping off) */ 2231 lanai->conf1 = (lanai->conf1 & ~CONFIG1_MASK_LOOPMODE) | 2232 CONFIG1_SET_LOOPMODE(LOOPMODE_NORMAL) | 2233 CONFIG1_GPOUT2 | CONFIG1_GPOUT3; 2234 conf1_write(lanai); 2235 lanai->status = reg_read(lanai, Status_Reg); 2236 /* We're now done initializing this card */ 2237 #ifdef USE_POWERDOWN 2238 lanai->conf1 |= CONFIG1_POWERDOWN; 2239 conf1_write(lanai); 2240 #endif 2241 memcpy(atmdev->esi, eeprom_mac(lanai), ESI_LEN); 2242 lanai_timed_poll_start(lanai); 2243 printk(KERN_NOTICE DEV_LABEL "(itf %d): rev.%d, base=0x%lx, irq=%u " 2244 "(%pMF)\n", lanai->number, (int) lanai->pci->revision, 2245 (unsigned long) lanai->base, lanai->pci->irq, atmdev->esi); 2246 printk(KERN_NOTICE DEV_LABEL "(itf %d): LANAI%s, serialno=%u(0x%X), " 2247 "board_rev=%d\n", lanai->number, 2248 lanai->type==lanai2 ? "2" : "HB", (unsigned int) lanai->serialno, 2249 (unsigned int) lanai->serialno, lanai->board_rev); 2250 return 0; 2251 2252 error_vcctable: 2253 vcc_table_deallocate(lanai); 2254 error_service: 2255 service_buffer_deallocate(lanai); 2256 error_unmap: 2257 reset_board(lanai); 2258 #ifdef USE_POWERDOWN 2259 lanai->conf1 = reg_read(lanai, Config1_Reg) | CONFIG1_POWERDOWN; 2260 conf1_write(lanai); 2261 #endif 2262 iounmap(lanai->base); 2263 error_pci: 2264 pci_disable_device(lanai->pci); 2265 error: 2266 return result; 2267 } 2268 2269 /* called when device is being shutdown, and all vcc's are gone - higher 2270 * levels will deallocate the atm device for us 2271 */ 2272 static void lanai_dev_close(struct atm_dev *atmdev) 2273 { 2274 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; 2275 printk(KERN_INFO DEV_LABEL "(itf %d): shutting down interface\n", 2276 lanai->number); 2277 lanai_timed_poll_stop(lanai); 2278 #ifdef USE_POWERDOWN 2279 lanai->conf1 = reg_read(lanai, Config1_Reg) & ~CONFIG1_POWERDOWN; 2280 conf1_write(lanai); 2281 #endif 2282 intr_disable(lanai, INT_ALL); 2283 free_irq(lanai->pci->irq, lanai); 2284 reset_board(lanai); 2285 #ifdef USE_POWERDOWN 2286 lanai->conf1 |= CONFIG1_POWERDOWN; 2287 conf1_write(lanai); 2288 #endif 2289 pci_disable_device(lanai->pci); 2290 vcc_table_deallocate(lanai); 2291 service_buffer_deallocate(lanai); 2292 iounmap(lanai->base); 2293 kfree(lanai); 2294 } 2295 2296 /* close a vcc */ 2297 static void lanai_close(struct atm_vcc *atmvcc) 2298 { 2299 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data; 2300 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data; 2301 if (lvcc == NULL) 2302 return; 2303 clear_bit(ATM_VF_READY, &atmvcc->flags); 2304 clear_bit(ATM_VF_PARTIAL, &atmvcc->flags); 2305 if (lvcc->rx.atmvcc == atmvcc) { 2306 lanai_shutdown_rx_vci(lvcc); 2307 if (atmvcc->qos.aal == ATM_AAL0) { 2308 if (--lanai->naal0 <= 0) 2309 aal0_buffer_free(lanai); 2310 } else 2311 lanai_buf_deallocate(&lvcc->rx.buf, lanai->pci); 2312 lvcc->rx.atmvcc = NULL; 2313 } 2314 if (lvcc->tx.atmvcc == atmvcc) { 2315 if (atmvcc == lanai->cbrvcc) { 2316 if (lvcc->vbase != NULL) 2317 lanai_cbr_shutdown(lanai); 2318 lanai->cbrvcc = NULL; 2319 } 2320 lanai_shutdown_tx_vci(lanai, lvcc); 2321 lanai_buf_deallocate(&lvcc->tx.buf, lanai->pci); 2322 lvcc->tx.atmvcc = NULL; 2323 } 2324 if (--lvcc->nref == 0) { 2325 host_vcc_unbind(lanai, lvcc); 2326 kfree(lvcc); 2327 } 2328 atmvcc->dev_data = NULL; 2329 clear_bit(ATM_VF_ADDR, &atmvcc->flags); 2330 } 2331 2332 /* open a vcc on the card to vpi/vci */ 2333 static int lanai_open(struct atm_vcc *atmvcc) 2334 { 2335 struct lanai_dev *lanai; 2336 struct lanai_vcc *lvcc; 2337 int result = 0; 2338 int vci = atmvcc->vci; 2339 short vpi = atmvcc->vpi; 2340 /* we don't support partial open - it's not really useful anyway */ 2341 if ((test_bit(ATM_VF_PARTIAL, &atmvcc->flags)) || 2342 (vpi == ATM_VPI_UNSPEC) || (vci == ATM_VCI_UNSPEC)) 2343 return -EINVAL; 2344 lanai = (struct lanai_dev *) atmvcc->dev->dev_data; 2345 result = lanai_normalize_ci(lanai, atmvcc, &vpi, &vci); 2346 if (unlikely(result != 0)) 2347 goto out; 2348 set_bit(ATM_VF_ADDR, &atmvcc->flags); 2349 if (atmvcc->qos.aal != ATM_AAL0 && atmvcc->qos.aal != ATM_AAL5) 2350 return -EINVAL; 2351 DPRINTK(DEV_LABEL "(itf %d): open %d.%d\n", lanai->number, 2352 (int) vpi, vci); 2353 lvcc = lanai->vccs[vci]; 2354 if (lvcc == NULL) { 2355 lvcc = new_lanai_vcc(); 2356 if (unlikely(lvcc == NULL)) 2357 return -ENOMEM; 2358 atmvcc->dev_data = lvcc; 2359 } 2360 lvcc->nref++; 2361 if (atmvcc->qos.rxtp.traffic_class != ATM_NONE) { 2362 APRINTK(lvcc->rx.atmvcc == NULL, "rx.atmvcc!=NULL, vci=%d\n", 2363 vci); 2364 if (atmvcc->qos.aal == ATM_AAL0) { 2365 if (lanai->naal0 == 0) 2366 result = aal0_buffer_allocate(lanai); 2367 } else 2368 result = lanai_setup_rx_vci_aal5( 2369 lanai, lvcc, &atmvcc->qos); 2370 if (unlikely(result != 0)) 2371 goto out_free; 2372 lvcc->rx.atmvcc = atmvcc; 2373 lvcc->stats.rx_nomem = 0; 2374 lvcc->stats.x.aal5.rx_badlen = 0; 2375 lvcc->stats.x.aal5.service_trash = 0; 2376 lvcc->stats.x.aal5.service_stream = 0; 2377 lvcc->stats.x.aal5.service_rxcrc = 0; 2378 if (atmvcc->qos.aal == ATM_AAL0) 2379 lanai->naal0++; 2380 } 2381 if (atmvcc->qos.txtp.traffic_class != ATM_NONE) { 2382 APRINTK(lvcc->tx.atmvcc == NULL, "tx.atmvcc!=NULL, vci=%d\n", 2383 vci); 2384 result = lanai_setup_tx_vci(lanai, lvcc, &atmvcc->qos); 2385 if (unlikely(result != 0)) 2386 goto out_free; 2387 lvcc->tx.atmvcc = atmvcc; 2388 if (atmvcc->qos.txtp.traffic_class == ATM_CBR) { 2389 APRINTK(lanai->cbrvcc == NULL, 2390 "cbrvcc!=NULL, vci=%d\n", vci); 2391 lanai->cbrvcc = atmvcc; 2392 } 2393 } 2394 host_vcc_bind(lanai, lvcc, vci); 2395 /* 2396 * Make sure everything made it to RAM before we tell the card about 2397 * the VCC 2398 */ 2399 wmb(); 2400 if (atmvcc == lvcc->rx.atmvcc) 2401 host_vcc_start_rx(lvcc); 2402 if (atmvcc == lvcc->tx.atmvcc) { 2403 host_vcc_start_tx(lvcc); 2404 if (lanai->cbrvcc == atmvcc) 2405 lanai_cbr_setup(lanai); 2406 } 2407 set_bit(ATM_VF_READY, &atmvcc->flags); 2408 return 0; 2409 out_free: 2410 lanai_close(atmvcc); 2411 out: 2412 return result; 2413 } 2414 2415 static int lanai_send(struct atm_vcc *atmvcc, struct sk_buff *skb) 2416 { 2417 struct lanai_vcc *lvcc = (struct lanai_vcc *) atmvcc->dev_data; 2418 struct lanai_dev *lanai = (struct lanai_dev *) atmvcc->dev->dev_data; 2419 unsigned long flags; 2420 if (unlikely(lvcc == NULL || lvcc->vbase == NULL || 2421 lvcc->tx.atmvcc != atmvcc)) 2422 goto einval; 2423 #ifdef DEBUG 2424 if (unlikely(skb == NULL)) { 2425 DPRINTK("lanai_send: skb==NULL for vci=%d\n", atmvcc->vci); 2426 goto einval; 2427 } 2428 if (unlikely(lanai == NULL)) { 2429 DPRINTK("lanai_send: lanai==NULL for vci=%d\n", atmvcc->vci); 2430 goto einval; 2431 } 2432 #endif 2433 ATM_SKB(skb)->vcc = atmvcc; 2434 switch (atmvcc->qos.aal) { 2435 case ATM_AAL5: 2436 read_lock_irqsave(&vcc_sklist_lock, flags); 2437 vcc_tx_aal5(lanai, lvcc, skb); 2438 read_unlock_irqrestore(&vcc_sklist_lock, flags); 2439 return 0; 2440 case ATM_AAL0: 2441 if (unlikely(skb->len != ATM_CELL_SIZE-1)) 2442 goto einval; 2443 /* NOTE - this next line is technically invalid - we haven't unshared skb */ 2444 cpu_to_be32s((u32 *) skb->data); 2445 read_lock_irqsave(&vcc_sklist_lock, flags); 2446 vcc_tx_aal0(lanai, lvcc, skb); 2447 read_unlock_irqrestore(&vcc_sklist_lock, flags); 2448 return 0; 2449 } 2450 DPRINTK("lanai_send: bad aal=%d on vci=%d\n", (int) atmvcc->qos.aal, 2451 atmvcc->vci); 2452 einval: 2453 lanai_free_skb(atmvcc, skb); 2454 return -EINVAL; 2455 } 2456 2457 static int lanai_change_qos(struct atm_vcc *atmvcc, 2458 /*const*/ struct atm_qos *qos, int flags) 2459 { 2460 return -EBUSY; /* TODO: need to write this */ 2461 } 2462 2463 #ifndef CONFIG_PROC_FS 2464 #define lanai_proc_read NULL 2465 #else 2466 static int lanai_proc_read(struct atm_dev *atmdev, loff_t *pos, char *page) 2467 { 2468 struct lanai_dev *lanai = (struct lanai_dev *) atmdev->dev_data; 2469 loff_t left = *pos; 2470 struct lanai_vcc *lvcc; 2471 if (left-- == 0) 2472 return sprintf(page, DEV_LABEL "(itf %d): chip=LANAI%s, " 2473 "serial=%u, magic=0x%08X, num_vci=%d\n", 2474 atmdev->number, lanai->type==lanai2 ? "2" : "HB", 2475 (unsigned int) lanai->serialno, 2476 (unsigned int) lanai->magicno, lanai->num_vci); 2477 if (left-- == 0) 2478 return sprintf(page, "revision: board=%d, pci_if=%d\n", 2479 lanai->board_rev, (int) lanai->pci->revision); 2480 if (left-- == 0) 2481 return sprintf(page, "EEPROM ESI: %pM\n", 2482 &lanai->eeprom[EEPROM_MAC]); 2483 if (left-- == 0) 2484 return sprintf(page, "status: SOOL=%d, LOCD=%d, LED=%d, " 2485 "GPIN=%d\n", (lanai->status & STATUS_SOOL) ? 1 : 0, 2486 (lanai->status & STATUS_LOCD) ? 1 : 0, 2487 (lanai->status & STATUS_LED) ? 1 : 0, 2488 (lanai->status & STATUS_GPIN) ? 1 : 0); 2489 if (left-- == 0) 2490 return sprintf(page, "global buffer sizes: service=%Zu, " 2491 "aal0_rx=%Zu\n", lanai_buf_size(&lanai->service), 2492 lanai->naal0 ? lanai_buf_size(&lanai->aal0buf) : 0); 2493 if (left-- == 0) { 2494 get_statistics(lanai); 2495 return sprintf(page, "cells in error: overflow=%u, " 2496 "closed_vci=%u, bad_HEC=%u, rx_fifo=%u\n", 2497 lanai->stats.ovfl_trash, lanai->stats.vci_trash, 2498 lanai->stats.hec_err, lanai->stats.atm_ovfl); 2499 } 2500 if (left-- == 0) 2501 return sprintf(page, "PCI errors: parity_detect=%u, " 2502 "master_abort=%u, master_target_abort=%u,\n", 2503 lanai->stats.pcierr_parity_detect, 2504 lanai->stats.pcierr_serr_set, 2505 lanai->stats.pcierr_m_target_abort); 2506 if (left-- == 0) 2507 return sprintf(page, " slave_target_abort=%u, " 2508 "master_parity=%u\n", lanai->stats.pcierr_s_target_abort, 2509 lanai->stats.pcierr_master_parity); 2510 if (left-- == 0) 2511 return sprintf(page, " no_tx=%u, " 2512 "no_rx=%u, bad_rx_aal=%u\n", lanai->stats.service_norx, 2513 lanai->stats.service_notx, 2514 lanai->stats.service_rxnotaal5); 2515 if (left-- == 0) 2516 return sprintf(page, "resets: dma=%u, card=%u\n", 2517 lanai->stats.dma_reenable, lanai->stats.card_reset); 2518 /* At this point, "left" should be the VCI we're looking for */ 2519 read_lock(&vcc_sklist_lock); 2520 for (; ; left++) { 2521 if (left >= NUM_VCI) { 2522 left = 0; 2523 goto out; 2524 } 2525 if ((lvcc = lanai->vccs[left]) != NULL) 2526 break; 2527 (*pos)++; 2528 } 2529 /* Note that we re-use "left" here since we're done with it */ 2530 left = sprintf(page, "VCI %4d: nref=%d, rx_nomem=%u", (vci_t) left, 2531 lvcc->nref, lvcc->stats.rx_nomem); 2532 if (lvcc->rx.atmvcc != NULL) { 2533 left += sprintf(&page[left], ",\n rx_AAL=%d", 2534 lvcc->rx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0); 2535 if (lvcc->rx.atmvcc->qos.aal == ATM_AAL5) 2536 left += sprintf(&page[left], ", rx_buf_size=%Zu, " 2537 "rx_bad_len=%u,\n rx_service_trash=%u, " 2538 "rx_service_stream=%u, rx_bad_crc=%u", 2539 lanai_buf_size(&lvcc->rx.buf), 2540 lvcc->stats.x.aal5.rx_badlen, 2541 lvcc->stats.x.aal5.service_trash, 2542 lvcc->stats.x.aal5.service_stream, 2543 lvcc->stats.x.aal5.service_rxcrc); 2544 } 2545 if (lvcc->tx.atmvcc != NULL) 2546 left += sprintf(&page[left], ",\n tx_AAL=%d, " 2547 "tx_buf_size=%Zu, tx_qos=%cBR, tx_backlogged=%c", 2548 lvcc->tx.atmvcc->qos.aal == ATM_AAL5 ? 5 : 0, 2549 lanai_buf_size(&lvcc->tx.buf), 2550 lvcc->tx.atmvcc == lanai->cbrvcc ? 'C' : 'U', 2551 vcc_is_backlogged(lvcc) ? 'Y' : 'N'); 2552 page[left++] = '\n'; 2553 page[left] = '\0'; 2554 out: 2555 read_unlock(&vcc_sklist_lock); 2556 return left; 2557 } 2558 #endif /* CONFIG_PROC_FS */ 2559 2560 /* -------------------- HOOKS: */ 2561 2562 static const struct atmdev_ops ops = { 2563 .dev_close = lanai_dev_close, 2564 .open = lanai_open, 2565 .close = lanai_close, 2566 .getsockopt = NULL, 2567 .setsockopt = NULL, 2568 .send = lanai_send, 2569 .phy_put = NULL, 2570 .phy_get = NULL, 2571 .change_qos = lanai_change_qos, 2572 .proc_read = lanai_proc_read, 2573 .owner = THIS_MODULE 2574 }; 2575 2576 /* initialize one probed card */ 2577 static int __devinit lanai_init_one(struct pci_dev *pci, 2578 const struct pci_device_id *ident) 2579 { 2580 struct lanai_dev *lanai; 2581 struct atm_dev *atmdev; 2582 int result; 2583 2584 lanai = kmalloc(sizeof(*lanai), GFP_KERNEL); 2585 if (lanai == NULL) { 2586 printk(KERN_ERR DEV_LABEL 2587 ": couldn't allocate dev_data structure!\n"); 2588 return -ENOMEM; 2589 } 2590 2591 atmdev = atm_dev_register(DEV_LABEL, &pci->dev, &ops, -1, NULL); 2592 if (atmdev == NULL) { 2593 printk(KERN_ERR DEV_LABEL 2594 ": couldn't register atm device!\n"); 2595 kfree(lanai); 2596 return -EBUSY; 2597 } 2598 2599 atmdev->dev_data = lanai; 2600 lanai->pci = pci; 2601 lanai->type = (enum lanai_type) ident->device; 2602 2603 result = lanai_dev_open(atmdev); 2604 if (result != 0) { 2605 DPRINTK("lanai_start() failed, err=%d\n", -result); 2606 atm_dev_deregister(atmdev); 2607 kfree(lanai); 2608 } 2609 return result; 2610 } 2611 2612 static struct pci_device_id lanai_pci_tbl[] = { 2613 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAI2) }, 2614 { PCI_VDEVICE(EF, PCI_DEVICE_ID_EF_ATM_LANAIHB) }, 2615 { 0, } /* terminal entry */ 2616 }; 2617 MODULE_DEVICE_TABLE(pci, lanai_pci_tbl); 2618 2619 static struct pci_driver lanai_driver = { 2620 .name = DEV_LABEL, 2621 .id_table = lanai_pci_tbl, 2622 .probe = lanai_init_one, 2623 }; 2624 2625 static int __init lanai_module_init(void) 2626 { 2627 int x; 2628 2629 x = pci_register_driver(&lanai_driver); 2630 if (x != 0) 2631 printk(KERN_ERR DEV_LABEL ": no adapter found\n"); 2632 return x; 2633 } 2634 2635 static void __exit lanai_module_exit(void) 2636 { 2637 /* We'll only get called when all the interfaces are already 2638 * gone, so there isn't much to do 2639 */ 2640 DPRINTK("cleanup_module()\n"); 2641 pci_unregister_driver(&lanai_driver); 2642 } 2643 2644 module_init(lanai_module_init); 2645 module_exit(lanai_module_exit); 2646 2647 MODULE_AUTHOR("Mitchell Blank Jr <mitch@sfgoth.com>"); 2648 MODULE_DESCRIPTION("Efficient Networks Speedstream 3010 driver"); 2649 MODULE_LICENSE("GPL"); 2650