1 /******************************************************************* 2 * 3 * Copyright (c) 2000 ATecoM GmbH 4 * 5 * The author may be reached at ecd@atecom.com. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 22 * 23 * You should have received a copy of the GNU General Public License along 24 * with this program; if not, write to the Free Software Foundation, Inc., 25 * 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 *******************************************************************/ 28 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/poison.h> 32 #include <linux/skbuff.h> 33 #include <linux/kernel.h> 34 #include <linux/vmalloc.h> 35 #include <linux/netdevice.h> 36 #include <linux/atmdev.h> 37 #include <linux/atm.h> 38 #include <linux/delay.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <linux/bitops.h> 42 #include <linux/wait.h> 43 #include <linux/jiffies.h> 44 #include <linux/mutex.h> 45 #include <linux/slab.h> 46 47 #include <asm/io.h> 48 #include <asm/uaccess.h> 49 #include <linux/atomic.h> 50 #include <asm/byteorder.h> 51 52 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 53 #include "suni.h" 54 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 55 56 57 #include "idt77252.h" 58 #include "idt77252_tables.h" 59 60 static unsigned int vpibits = 1; 61 62 63 #define ATM_IDT77252_SEND_IDLE 1 64 65 66 /* 67 * Debug HACKs. 68 */ 69 #define DEBUG_MODULE 1 70 #undef HAVE_EEPROM /* does not work, yet. */ 71 72 #ifdef CONFIG_ATM_IDT77252_DEBUG 73 static unsigned long debug = DBG_GENERAL; 74 #endif 75 76 77 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 78 79 80 /* 81 * SCQ Handling. 82 */ 83 static struct scq_info *alloc_scq(struct idt77252_dev *, int); 84 static void free_scq(struct idt77252_dev *, struct scq_info *); 85 static int queue_skb(struct idt77252_dev *, struct vc_map *, 86 struct sk_buff *, int oam); 87 static void drain_scq(struct idt77252_dev *, struct vc_map *); 88 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 89 static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 90 91 /* 92 * FBQ Handling. 93 */ 94 static int push_rx_skb(struct idt77252_dev *, 95 struct sk_buff *, int queue); 96 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 97 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 98 static void recycle_rx_pool_skb(struct idt77252_dev *, 99 struct rx_pool *); 100 static void add_rx_skb(struct idt77252_dev *, int queue, 101 unsigned int size, unsigned int count); 102 103 /* 104 * RSQ Handling. 105 */ 106 static int init_rsq(struct idt77252_dev *); 107 static void deinit_rsq(struct idt77252_dev *); 108 static void idt77252_rx(struct idt77252_dev *); 109 110 /* 111 * TSQ handling. 112 */ 113 static int init_tsq(struct idt77252_dev *); 114 static void deinit_tsq(struct idt77252_dev *); 115 static void idt77252_tx(struct idt77252_dev *); 116 117 118 /* 119 * ATM Interface. 120 */ 121 static void idt77252_dev_close(struct atm_dev *dev); 122 static int idt77252_open(struct atm_vcc *vcc); 123 static void idt77252_close(struct atm_vcc *vcc); 124 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 125 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 126 int flags); 127 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 128 unsigned long addr); 129 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 130 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 131 int flags); 132 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 133 char *page); 134 static void idt77252_softint(struct work_struct *work); 135 136 137 static struct atmdev_ops idt77252_ops = 138 { 139 .dev_close = idt77252_dev_close, 140 .open = idt77252_open, 141 .close = idt77252_close, 142 .send = idt77252_send, 143 .send_oam = idt77252_send_oam, 144 .phy_put = idt77252_phy_put, 145 .phy_get = idt77252_phy_get, 146 .change_qos = idt77252_change_qos, 147 .proc_read = idt77252_proc_read, 148 .owner = THIS_MODULE 149 }; 150 151 static struct idt77252_dev *idt77252_chain = NULL; 152 static unsigned int idt77252_sram_write_errors = 0; 153 154 /*****************************************************************************/ 155 /* */ 156 /* I/O and Utility Bus */ 157 /* */ 158 /*****************************************************************************/ 159 160 static void 161 waitfor_idle(struct idt77252_dev *card) 162 { 163 u32 stat; 164 165 stat = readl(SAR_REG_STAT); 166 while (stat & SAR_STAT_CMDBZ) 167 stat = readl(SAR_REG_STAT); 168 } 169 170 static u32 171 read_sram(struct idt77252_dev *card, unsigned long addr) 172 { 173 unsigned long flags; 174 u32 value; 175 176 spin_lock_irqsave(&card->cmd_lock, flags); 177 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 178 waitfor_idle(card); 179 value = readl(SAR_REG_DR0); 180 spin_unlock_irqrestore(&card->cmd_lock, flags); 181 return value; 182 } 183 184 static void 185 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 186 { 187 unsigned long flags; 188 189 if ((idt77252_sram_write_errors == 0) && 190 (((addr > card->tst[0] + card->tst_size - 2) && 191 (addr < card->tst[0] + card->tst_size)) || 192 ((addr > card->tst[1] + card->tst_size - 2) && 193 (addr < card->tst[1] + card->tst_size)))) { 194 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 195 card->name, addr, value); 196 } 197 198 spin_lock_irqsave(&card->cmd_lock, flags); 199 writel(value, SAR_REG_DR0); 200 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 201 waitfor_idle(card); 202 spin_unlock_irqrestore(&card->cmd_lock, flags); 203 } 204 205 static u8 206 read_utility(void *dev, unsigned long ubus_addr) 207 { 208 struct idt77252_dev *card = dev; 209 unsigned long flags; 210 u8 value; 211 212 if (!card) { 213 printk("Error: No such device.\n"); 214 return -1; 215 } 216 217 spin_lock_irqsave(&card->cmd_lock, flags); 218 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 219 waitfor_idle(card); 220 value = readl(SAR_REG_DR0); 221 spin_unlock_irqrestore(&card->cmd_lock, flags); 222 return value; 223 } 224 225 static void 226 write_utility(void *dev, unsigned long ubus_addr, u8 value) 227 { 228 struct idt77252_dev *card = dev; 229 unsigned long flags; 230 231 if (!card) { 232 printk("Error: No such device.\n"); 233 return; 234 } 235 236 spin_lock_irqsave(&card->cmd_lock, flags); 237 writel((u32) value, SAR_REG_DR0); 238 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 239 waitfor_idle(card); 240 spin_unlock_irqrestore(&card->cmd_lock, flags); 241 } 242 243 #ifdef HAVE_EEPROM 244 static u32 rdsrtab[] = 245 { 246 SAR_GP_EECS | SAR_GP_EESCLK, 247 0, 248 SAR_GP_EESCLK, /* 0 */ 249 0, 250 SAR_GP_EESCLK, /* 0 */ 251 0, 252 SAR_GP_EESCLK, /* 0 */ 253 0, 254 SAR_GP_EESCLK, /* 0 */ 255 0, 256 SAR_GP_EESCLK, /* 0 */ 257 SAR_GP_EEDO, 258 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 259 0, 260 SAR_GP_EESCLK, /* 0 */ 261 SAR_GP_EEDO, 262 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 263 }; 264 265 static u32 wrentab[] = 266 { 267 SAR_GP_EECS | SAR_GP_EESCLK, 268 0, 269 SAR_GP_EESCLK, /* 0 */ 270 0, 271 SAR_GP_EESCLK, /* 0 */ 272 0, 273 SAR_GP_EESCLK, /* 0 */ 274 0, 275 SAR_GP_EESCLK, /* 0 */ 276 SAR_GP_EEDO, 277 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 278 SAR_GP_EEDO, 279 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 280 0, 281 SAR_GP_EESCLK, /* 0 */ 282 0, 283 SAR_GP_EESCLK /* 0 */ 284 }; 285 286 static u32 rdtab[] = 287 { 288 SAR_GP_EECS | SAR_GP_EESCLK, 289 0, 290 SAR_GP_EESCLK, /* 0 */ 291 0, 292 SAR_GP_EESCLK, /* 0 */ 293 0, 294 SAR_GP_EESCLK, /* 0 */ 295 0, 296 SAR_GP_EESCLK, /* 0 */ 297 0, 298 SAR_GP_EESCLK, /* 0 */ 299 0, 300 SAR_GP_EESCLK, /* 0 */ 301 SAR_GP_EEDO, 302 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 303 SAR_GP_EEDO, 304 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 305 }; 306 307 static u32 wrtab[] = 308 { 309 SAR_GP_EECS | SAR_GP_EESCLK, 310 0, 311 SAR_GP_EESCLK, /* 0 */ 312 0, 313 SAR_GP_EESCLK, /* 0 */ 314 0, 315 SAR_GP_EESCLK, /* 0 */ 316 0, 317 SAR_GP_EESCLK, /* 0 */ 318 0, 319 SAR_GP_EESCLK, /* 0 */ 320 0, 321 SAR_GP_EESCLK, /* 0 */ 322 SAR_GP_EEDO, 323 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 324 0, 325 SAR_GP_EESCLK /* 0 */ 326 }; 327 328 static u32 clktab[] = 329 { 330 0, 331 SAR_GP_EESCLK, 332 0, 333 SAR_GP_EESCLK, 334 0, 335 SAR_GP_EESCLK, 336 0, 337 SAR_GP_EESCLK, 338 0, 339 SAR_GP_EESCLK, 340 0, 341 SAR_GP_EESCLK, 342 0, 343 SAR_GP_EESCLK, 344 0, 345 SAR_GP_EESCLK, 346 0 347 }; 348 349 static u32 350 idt77252_read_gp(struct idt77252_dev *card) 351 { 352 u32 gp; 353 354 gp = readl(SAR_REG_GP); 355 #if 0 356 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 357 #endif 358 return gp; 359 } 360 361 static void 362 idt77252_write_gp(struct idt77252_dev *card, u32 value) 363 { 364 unsigned long flags; 365 366 #if 0 367 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 368 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 369 value & SAR_GP_EEDO ? "1" : "0"); 370 #endif 371 372 spin_lock_irqsave(&card->cmd_lock, flags); 373 waitfor_idle(card); 374 writel(value, SAR_REG_GP); 375 spin_unlock_irqrestore(&card->cmd_lock, flags); 376 } 377 378 static u8 379 idt77252_eeprom_read_status(struct idt77252_dev *card) 380 { 381 u8 byte; 382 u32 gp; 383 int i, j; 384 385 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 386 387 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 388 idt77252_write_gp(card, gp | rdsrtab[i]); 389 udelay(5); 390 } 391 idt77252_write_gp(card, gp | SAR_GP_EECS); 392 udelay(5); 393 394 byte = 0; 395 for (i = 0, j = 0; i < 8; i++) { 396 byte <<= 1; 397 398 idt77252_write_gp(card, gp | clktab[j++]); 399 udelay(5); 400 401 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 402 403 idt77252_write_gp(card, gp | clktab[j++]); 404 udelay(5); 405 } 406 idt77252_write_gp(card, gp | SAR_GP_EECS); 407 udelay(5); 408 409 return byte; 410 } 411 412 static u8 413 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 414 { 415 u8 byte; 416 u32 gp; 417 int i, j; 418 419 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 420 421 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 422 idt77252_write_gp(card, gp | rdtab[i]); 423 udelay(5); 424 } 425 idt77252_write_gp(card, gp | SAR_GP_EECS); 426 udelay(5); 427 428 for (i = 0, j = 0; i < 8; i++) { 429 idt77252_write_gp(card, gp | clktab[j++] | 430 (offset & 1 ? SAR_GP_EEDO : 0)); 431 udelay(5); 432 433 idt77252_write_gp(card, gp | clktab[j++] | 434 (offset & 1 ? SAR_GP_EEDO : 0)); 435 udelay(5); 436 437 offset >>= 1; 438 } 439 idt77252_write_gp(card, gp | SAR_GP_EECS); 440 udelay(5); 441 442 byte = 0; 443 for (i = 0, j = 0; i < 8; i++) { 444 byte <<= 1; 445 446 idt77252_write_gp(card, gp | clktab[j++]); 447 udelay(5); 448 449 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 450 451 idt77252_write_gp(card, gp | clktab[j++]); 452 udelay(5); 453 } 454 idt77252_write_gp(card, gp | SAR_GP_EECS); 455 udelay(5); 456 457 return byte; 458 } 459 460 static void 461 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 462 { 463 u32 gp; 464 int i, j; 465 466 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 467 468 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 469 idt77252_write_gp(card, gp | wrentab[i]); 470 udelay(5); 471 } 472 idt77252_write_gp(card, gp | SAR_GP_EECS); 473 udelay(5); 474 475 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 476 idt77252_write_gp(card, gp | wrtab[i]); 477 udelay(5); 478 } 479 idt77252_write_gp(card, gp | SAR_GP_EECS); 480 udelay(5); 481 482 for (i = 0, j = 0; i < 8; i++) { 483 idt77252_write_gp(card, gp | clktab[j++] | 484 (offset & 1 ? SAR_GP_EEDO : 0)); 485 udelay(5); 486 487 idt77252_write_gp(card, gp | clktab[j++] | 488 (offset & 1 ? SAR_GP_EEDO : 0)); 489 udelay(5); 490 491 offset >>= 1; 492 } 493 idt77252_write_gp(card, gp | SAR_GP_EECS); 494 udelay(5); 495 496 for (i = 0, j = 0; i < 8; i++) { 497 idt77252_write_gp(card, gp | clktab[j++] | 498 (data & 1 ? SAR_GP_EEDO : 0)); 499 udelay(5); 500 501 idt77252_write_gp(card, gp | clktab[j++] | 502 (data & 1 ? SAR_GP_EEDO : 0)); 503 udelay(5); 504 505 data >>= 1; 506 } 507 idt77252_write_gp(card, gp | SAR_GP_EECS); 508 udelay(5); 509 } 510 511 static void 512 idt77252_eeprom_init(struct idt77252_dev *card) 513 { 514 u32 gp; 515 516 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 517 518 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 519 udelay(5); 520 idt77252_write_gp(card, gp | SAR_GP_EECS); 521 udelay(5); 522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 523 udelay(5); 524 idt77252_write_gp(card, gp | SAR_GP_EECS); 525 udelay(5); 526 } 527 #endif /* HAVE_EEPROM */ 528 529 530 #ifdef CONFIG_ATM_IDT77252_DEBUG 531 static void 532 dump_tct(struct idt77252_dev *card, int index) 533 { 534 unsigned long tct; 535 int i; 536 537 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 538 539 printk("%s: TCT %x:", card->name, index); 540 for (i = 0; i < 8; i++) { 541 printk(" %08x", read_sram(card, tct + i)); 542 } 543 printk("\n"); 544 } 545 546 static void 547 idt77252_tx_dump(struct idt77252_dev *card) 548 { 549 struct atm_vcc *vcc; 550 struct vc_map *vc; 551 int i; 552 553 printk("%s\n", __func__); 554 for (i = 0; i < card->tct_size; i++) { 555 vc = card->vcs[i]; 556 if (!vc) 557 continue; 558 559 vcc = NULL; 560 if (vc->rx_vcc) 561 vcc = vc->rx_vcc; 562 else if (vc->tx_vcc) 563 vcc = vc->tx_vcc; 564 565 if (!vcc) 566 continue; 567 568 printk("%s: Connection %d:\n", card->name, vc->index); 569 dump_tct(card, vc->index); 570 } 571 } 572 #endif 573 574 575 /*****************************************************************************/ 576 /* */ 577 /* SCQ Handling */ 578 /* */ 579 /*****************************************************************************/ 580 581 static int 582 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 583 { 584 struct sb_pool *pool = &card->sbpool[queue]; 585 int index; 586 587 index = pool->index; 588 while (pool->skb[index]) { 589 index = (index + 1) & FBQ_MASK; 590 if (index == pool->index) 591 return -ENOBUFS; 592 } 593 594 pool->skb[index] = skb; 595 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 596 597 pool->index = (index + 1) & FBQ_MASK; 598 return 0; 599 } 600 601 static void 602 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 603 { 604 unsigned int queue, index; 605 u32 handle; 606 607 handle = IDT77252_PRV_POOL(skb); 608 609 queue = POOL_QUEUE(handle); 610 if (queue > 3) 611 return; 612 613 index = POOL_INDEX(handle); 614 if (index > FBQ_SIZE - 1) 615 return; 616 617 card->sbpool[queue].skb[index] = NULL; 618 } 619 620 static struct sk_buff * 621 sb_pool_skb(struct idt77252_dev *card, u32 handle) 622 { 623 unsigned int queue, index; 624 625 queue = POOL_QUEUE(handle); 626 if (queue > 3) 627 return NULL; 628 629 index = POOL_INDEX(handle); 630 if (index > FBQ_SIZE - 1) 631 return NULL; 632 633 return card->sbpool[queue].skb[index]; 634 } 635 636 static struct scq_info * 637 alloc_scq(struct idt77252_dev *card, int class) 638 { 639 struct scq_info *scq; 640 641 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 642 if (!scq) 643 return NULL; 644 scq->base = dma_zalloc_coherent(&card->pcidev->dev, SCQ_SIZE, 645 &scq->paddr, GFP_KERNEL); 646 if (scq->base == NULL) { 647 kfree(scq); 648 return NULL; 649 } 650 651 scq->next = scq->base; 652 scq->last = scq->base + (SCQ_ENTRIES - 1); 653 atomic_set(&scq->used, 0); 654 655 spin_lock_init(&scq->lock); 656 spin_lock_init(&scq->skblock); 657 658 skb_queue_head_init(&scq->transmit); 659 skb_queue_head_init(&scq->pending); 660 661 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 662 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 663 664 return scq; 665 } 666 667 static void 668 free_scq(struct idt77252_dev *card, struct scq_info *scq) 669 { 670 struct sk_buff *skb; 671 struct atm_vcc *vcc; 672 673 dma_free_coherent(&card->pcidev->dev, SCQ_SIZE, 674 scq->base, scq->paddr); 675 676 while ((skb = skb_dequeue(&scq->transmit))) { 677 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 678 skb->len, DMA_TO_DEVICE); 679 680 vcc = ATM_SKB(skb)->vcc; 681 if (vcc->pop) 682 vcc->pop(vcc, skb); 683 else 684 dev_kfree_skb(skb); 685 } 686 687 while ((skb = skb_dequeue(&scq->pending))) { 688 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 689 skb->len, DMA_TO_DEVICE); 690 691 vcc = ATM_SKB(skb)->vcc; 692 if (vcc->pop) 693 vcc->pop(vcc, skb); 694 else 695 dev_kfree_skb(skb); 696 } 697 698 kfree(scq); 699 } 700 701 702 static int 703 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 704 { 705 struct scq_info *scq = vc->scq; 706 unsigned long flags; 707 struct scqe *tbd; 708 int entries; 709 710 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 711 712 atomic_inc(&scq->used); 713 entries = atomic_read(&scq->used); 714 if (entries > (SCQ_ENTRIES - 1)) { 715 atomic_dec(&scq->used); 716 goto out; 717 } 718 719 skb_queue_tail(&scq->transmit, skb); 720 721 spin_lock_irqsave(&vc->lock, flags); 722 if (vc->estimator) { 723 struct atm_vcc *vcc = vc->tx_vcc; 724 struct sock *sk = sk_atm(vcc); 725 726 vc->estimator->cells += (skb->len + 47) / 48; 727 if (atomic_read(&sk->sk_wmem_alloc) > 728 (sk->sk_sndbuf >> 1)) { 729 u32 cps = vc->estimator->maxcps; 730 731 vc->estimator->cps = cps; 732 vc->estimator->avcps = cps << 5; 733 if (vc->lacr < vc->init_er) { 734 vc->lacr = vc->init_er; 735 writel(TCMDQ_LACR | (vc->lacr << 16) | 736 vc->index, SAR_REG_TCMDQ); 737 } 738 } 739 } 740 spin_unlock_irqrestore(&vc->lock, flags); 741 742 tbd = &IDT77252_PRV_TBD(skb); 743 744 spin_lock_irqsave(&scq->lock, flags); 745 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 746 SAR_TBD_TSIF | SAR_TBD_GTSI); 747 scq->next->word_2 = cpu_to_le32(tbd->word_2); 748 scq->next->word_3 = cpu_to_le32(tbd->word_3); 749 scq->next->word_4 = cpu_to_le32(tbd->word_4); 750 751 if (scq->next == scq->last) 752 scq->next = scq->base; 753 else 754 scq->next++; 755 756 write_sram(card, scq->scd, 757 scq->paddr + 758 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 759 spin_unlock_irqrestore(&scq->lock, flags); 760 761 scq->trans_start = jiffies; 762 763 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 764 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 765 SAR_REG_TCMDQ); 766 } 767 768 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 769 770 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 771 card->name, atomic_read(&scq->used), 772 read_sram(card, scq->scd + 1), scq->next); 773 774 return 0; 775 776 out: 777 if (time_after(jiffies, scq->trans_start + HZ)) { 778 printk("%s: Error pushing TBD for %d.%d\n", 779 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 780 #ifdef CONFIG_ATM_IDT77252_DEBUG 781 idt77252_tx_dump(card); 782 #endif 783 scq->trans_start = jiffies; 784 } 785 786 return -ENOBUFS; 787 } 788 789 790 static void 791 drain_scq(struct idt77252_dev *card, struct vc_map *vc) 792 { 793 struct scq_info *scq = vc->scq; 794 struct sk_buff *skb; 795 struct atm_vcc *vcc; 796 797 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 798 card->name, atomic_read(&scq->used), scq->next); 799 800 skb = skb_dequeue(&scq->transmit); 801 if (skb) { 802 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 803 804 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 805 skb->len, DMA_TO_DEVICE); 806 807 vcc = ATM_SKB(skb)->vcc; 808 809 if (vcc->pop) 810 vcc->pop(vcc, skb); 811 else 812 dev_kfree_skb(skb); 813 814 atomic_inc(&vcc->stats->tx); 815 } 816 817 atomic_dec(&scq->used); 818 819 spin_lock(&scq->skblock); 820 while ((skb = skb_dequeue(&scq->pending))) { 821 if (push_on_scq(card, vc, skb)) { 822 skb_queue_head(&vc->scq->pending, skb); 823 break; 824 } 825 } 826 spin_unlock(&scq->skblock); 827 } 828 829 static int 830 queue_skb(struct idt77252_dev *card, struct vc_map *vc, 831 struct sk_buff *skb, int oam) 832 { 833 struct atm_vcc *vcc; 834 struct scqe *tbd; 835 unsigned long flags; 836 int error; 837 int aal; 838 839 if (skb->len == 0) { 840 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 841 return -EINVAL; 842 } 843 844 TXPRINTK("%s: Sending %d bytes of data.\n", 845 card->name, skb->len); 846 847 tbd = &IDT77252_PRV_TBD(skb); 848 vcc = ATM_SKB(skb)->vcc; 849 850 IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data, 851 skb->len, DMA_TO_DEVICE); 852 853 error = -EINVAL; 854 855 if (oam) { 856 if (skb->len != 52) 857 goto errout; 858 859 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 860 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 861 tbd->word_3 = 0x00000000; 862 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 863 (skb->data[2] << 8) | (skb->data[3] << 0); 864 865 if (test_bit(VCF_RSV, &vc->flags)) 866 vc = card->vcs[0]; 867 868 goto done; 869 } 870 871 if (test_bit(VCF_RSV, &vc->flags)) { 872 printk("%s: Trying to transmit on reserved VC\n", card->name); 873 goto errout; 874 } 875 876 aal = vcc->qos.aal; 877 878 switch (aal) { 879 case ATM_AAL0: 880 case ATM_AAL34: 881 if (skb->len > 52) 882 goto errout; 883 884 if (aal == ATM_AAL0) 885 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 886 ATM_CELL_PAYLOAD; 887 else 888 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 889 ATM_CELL_PAYLOAD; 890 891 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 892 tbd->word_3 = 0x00000000; 893 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 894 (skb->data[2] << 8) | (skb->data[3] << 0); 895 break; 896 897 case ATM_AAL5: 898 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 899 tbd->word_2 = IDT77252_PRV_PADDR(skb); 900 tbd->word_3 = skb->len; 901 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 902 (vcc->vci << SAR_TBD_VCI_SHIFT); 903 break; 904 905 case ATM_AAL1: 906 case ATM_AAL2: 907 default: 908 printk("%s: Traffic type not supported.\n", card->name); 909 error = -EPROTONOSUPPORT; 910 goto errout; 911 } 912 913 done: 914 spin_lock_irqsave(&vc->scq->skblock, flags); 915 skb_queue_tail(&vc->scq->pending, skb); 916 917 while ((skb = skb_dequeue(&vc->scq->pending))) { 918 if (push_on_scq(card, vc, skb)) { 919 skb_queue_head(&vc->scq->pending, skb); 920 break; 921 } 922 } 923 spin_unlock_irqrestore(&vc->scq->skblock, flags); 924 925 return 0; 926 927 errout: 928 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 929 skb->len, DMA_TO_DEVICE); 930 return error; 931 } 932 933 static unsigned long 934 get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 935 { 936 int i; 937 938 for (i = 0; i < card->scd_size; i++) { 939 if (!card->scd2vc[i]) { 940 card->scd2vc[i] = vc; 941 vc->scd_index = i; 942 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 943 } 944 } 945 return 0; 946 } 947 948 static void 949 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 950 { 951 write_sram(card, scq->scd, scq->paddr); 952 write_sram(card, scq->scd + 1, 0x00000000); 953 write_sram(card, scq->scd + 2, 0xffffffff); 954 write_sram(card, scq->scd + 3, 0x00000000); 955 } 956 957 static void 958 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 959 { 960 return; 961 } 962 963 /*****************************************************************************/ 964 /* */ 965 /* RSQ Handling */ 966 /* */ 967 /*****************************************************************************/ 968 969 static int 970 init_rsq(struct idt77252_dev *card) 971 { 972 struct rsq_entry *rsqe; 973 974 card->rsq.base = dma_zalloc_coherent(&card->pcidev->dev, RSQSIZE, 975 &card->rsq.paddr, GFP_KERNEL); 976 if (card->rsq.base == NULL) { 977 printk("%s: can't allocate RSQ.\n", card->name); 978 return -1; 979 } 980 981 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 982 card->rsq.next = card->rsq.last; 983 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 984 rsqe->word_4 = 0; 985 986 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 987 SAR_REG_RSQH); 988 writel(card->rsq.paddr, SAR_REG_RSQB); 989 990 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 991 (unsigned long) card->rsq.base, 992 readl(SAR_REG_RSQB)); 993 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 994 card->name, 995 readl(SAR_REG_RSQH), 996 readl(SAR_REG_RSQB), 997 readl(SAR_REG_RSQT)); 998 999 return 0; 1000 } 1001 1002 static void 1003 deinit_rsq(struct idt77252_dev *card) 1004 { 1005 dma_free_coherent(&card->pcidev->dev, RSQSIZE, 1006 card->rsq.base, card->rsq.paddr); 1007 } 1008 1009 static void 1010 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1011 { 1012 struct atm_vcc *vcc; 1013 struct sk_buff *skb; 1014 struct rx_pool *rpp; 1015 struct vc_map *vc; 1016 u32 header, vpi, vci; 1017 u32 stat; 1018 int i; 1019 1020 stat = le32_to_cpu(rsqe->word_4); 1021 1022 if (stat & SAR_RSQE_IDLE) { 1023 RXPRINTK("%s: message about inactive connection.\n", 1024 card->name); 1025 return; 1026 } 1027 1028 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1029 if (skb == NULL) { 1030 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1031 card->name, __func__, 1032 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1033 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1034 return; 1035 } 1036 1037 header = le32_to_cpu(rsqe->word_1); 1038 vpi = (header >> 16) & 0x00ff; 1039 vci = (header >> 0) & 0xffff; 1040 1041 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1042 card->name, vpi, vci, skb, skb->data); 1043 1044 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1045 printk("%s: SDU received for out-of-range vc %u.%u\n", 1046 card->name, vpi, vci); 1047 recycle_rx_skb(card, skb); 1048 return; 1049 } 1050 1051 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1052 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1053 printk("%s: SDU received on non RX vc %u.%u\n", 1054 card->name, vpi, vci); 1055 recycle_rx_skb(card, skb); 1056 return; 1057 } 1058 1059 vcc = vc->rx_vcc; 1060 1061 dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 1062 skb_end_pointer(skb) - skb->data, 1063 DMA_FROM_DEVICE); 1064 1065 if ((vcc->qos.aal == ATM_AAL0) || 1066 (vcc->qos.aal == ATM_AAL34)) { 1067 struct sk_buff *sb; 1068 unsigned char *cell; 1069 u32 aal0; 1070 1071 cell = skb->data; 1072 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1073 if ((sb = dev_alloc_skb(64)) == NULL) { 1074 printk("%s: Can't allocate buffers for aal0.\n", 1075 card->name); 1076 atomic_add(i, &vcc->stats->rx_drop); 1077 break; 1078 } 1079 if (!atm_charge(vcc, sb->truesize)) { 1080 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1081 card->name); 1082 atomic_add(i - 1, &vcc->stats->rx_drop); 1083 dev_kfree_skb(sb); 1084 break; 1085 } 1086 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1087 (vci << ATM_HDR_VCI_SHIFT); 1088 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1089 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1090 1091 *((u32 *) sb->data) = aal0; 1092 skb_put(sb, sizeof(u32)); 1093 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1094 cell, ATM_CELL_PAYLOAD); 1095 1096 ATM_SKB(sb)->vcc = vcc; 1097 __net_timestamp(sb); 1098 vcc->push(vcc, sb); 1099 atomic_inc(&vcc->stats->rx); 1100 1101 cell += ATM_CELL_PAYLOAD; 1102 } 1103 1104 recycle_rx_skb(card, skb); 1105 return; 1106 } 1107 if (vcc->qos.aal != ATM_AAL5) { 1108 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1109 card->name, vcc->qos.aal); 1110 recycle_rx_skb(card, skb); 1111 return; 1112 } 1113 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1114 1115 rpp = &vc->rcv.rx_pool; 1116 1117 __skb_queue_tail(&rpp->queue, skb); 1118 rpp->len += skb->len; 1119 1120 if (stat & SAR_RSQE_EPDU) { 1121 unsigned char *l1l2; 1122 unsigned int len; 1123 1124 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1125 1126 len = (l1l2[0] << 8) | l1l2[1]; 1127 len = len ? len : 0x10000; 1128 1129 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1130 1131 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1132 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1133 "(CDC: %08x)\n", 1134 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1135 recycle_rx_pool_skb(card, rpp); 1136 atomic_inc(&vcc->stats->rx_err); 1137 return; 1138 } 1139 if (stat & SAR_RSQE_CRC) { 1140 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1141 recycle_rx_pool_skb(card, rpp); 1142 atomic_inc(&vcc->stats->rx_err); 1143 return; 1144 } 1145 if (skb_queue_len(&rpp->queue) > 1) { 1146 struct sk_buff *sb; 1147 1148 skb = dev_alloc_skb(rpp->len); 1149 if (!skb) { 1150 RXPRINTK("%s: Can't alloc RX skb.\n", 1151 card->name); 1152 recycle_rx_pool_skb(card, rpp); 1153 atomic_inc(&vcc->stats->rx_err); 1154 return; 1155 } 1156 if (!atm_charge(vcc, skb->truesize)) { 1157 recycle_rx_pool_skb(card, rpp); 1158 dev_kfree_skb(skb); 1159 return; 1160 } 1161 skb_queue_walk(&rpp->queue, sb) 1162 memcpy(skb_put(skb, sb->len), 1163 sb->data, sb->len); 1164 1165 recycle_rx_pool_skb(card, rpp); 1166 1167 skb_trim(skb, len); 1168 ATM_SKB(skb)->vcc = vcc; 1169 __net_timestamp(skb); 1170 1171 vcc->push(vcc, skb); 1172 atomic_inc(&vcc->stats->rx); 1173 1174 return; 1175 } 1176 1177 flush_rx_pool(card, rpp); 1178 1179 if (!atm_charge(vcc, skb->truesize)) { 1180 recycle_rx_skb(card, skb); 1181 return; 1182 } 1183 1184 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 1185 skb_end_pointer(skb) - skb->data, 1186 DMA_FROM_DEVICE); 1187 sb_pool_remove(card, skb); 1188 1189 skb_trim(skb, len); 1190 ATM_SKB(skb)->vcc = vcc; 1191 __net_timestamp(skb); 1192 1193 vcc->push(vcc, skb); 1194 atomic_inc(&vcc->stats->rx); 1195 1196 if (skb->truesize > SAR_FB_SIZE_3) 1197 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1198 else if (skb->truesize > SAR_FB_SIZE_2) 1199 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1200 else if (skb->truesize > SAR_FB_SIZE_1) 1201 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1202 else 1203 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1204 return; 1205 } 1206 } 1207 1208 static void 1209 idt77252_rx(struct idt77252_dev *card) 1210 { 1211 struct rsq_entry *rsqe; 1212 1213 if (card->rsq.next == card->rsq.last) 1214 rsqe = card->rsq.base; 1215 else 1216 rsqe = card->rsq.next + 1; 1217 1218 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1219 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1220 return; 1221 } 1222 1223 do { 1224 dequeue_rx(card, rsqe); 1225 rsqe->word_4 = 0; 1226 card->rsq.next = rsqe; 1227 if (card->rsq.next == card->rsq.last) 1228 rsqe = card->rsq.base; 1229 else 1230 rsqe = card->rsq.next + 1; 1231 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1232 1233 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1234 SAR_REG_RSQH); 1235 } 1236 1237 static void 1238 idt77252_rx_raw(struct idt77252_dev *card) 1239 { 1240 struct sk_buff *queue; 1241 u32 head, tail; 1242 struct atm_vcc *vcc; 1243 struct vc_map *vc; 1244 struct sk_buff *sb; 1245 1246 if (card->raw_cell_head == NULL) { 1247 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1248 card->raw_cell_head = sb_pool_skb(card, handle); 1249 } 1250 1251 queue = card->raw_cell_head; 1252 if (!queue) 1253 return; 1254 1255 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1256 tail = readl(SAR_REG_RAWCT); 1257 1258 dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue), 1259 skb_end_offset(queue) - 16, 1260 DMA_FROM_DEVICE); 1261 1262 while (head != tail) { 1263 unsigned int vpi, vci; 1264 u32 header; 1265 1266 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1267 1268 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1269 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1270 1271 #ifdef CONFIG_ATM_IDT77252_DEBUG 1272 if (debug & DBG_RAW_CELL) { 1273 int i; 1274 1275 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1276 card->name, (header >> 28) & 0x000f, 1277 (header >> 20) & 0x00ff, 1278 (header >> 4) & 0xffff, 1279 (header >> 1) & 0x0007, 1280 (header >> 0) & 0x0001); 1281 for (i = 16; i < 64; i++) 1282 printk(" %02x", queue->data[i]); 1283 printk("\n"); 1284 } 1285 #endif 1286 1287 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1288 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1289 card->name, vpi, vci); 1290 goto drop; 1291 } 1292 1293 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1294 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1295 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1296 card->name, vpi, vci); 1297 goto drop; 1298 } 1299 1300 vcc = vc->rx_vcc; 1301 1302 if (vcc->qos.aal != ATM_AAL0) { 1303 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1304 card->name, vpi, vci); 1305 atomic_inc(&vcc->stats->rx_drop); 1306 goto drop; 1307 } 1308 1309 if ((sb = dev_alloc_skb(64)) == NULL) { 1310 printk("%s: Can't allocate buffers for AAL0.\n", 1311 card->name); 1312 atomic_inc(&vcc->stats->rx_err); 1313 goto drop; 1314 } 1315 1316 if (!atm_charge(vcc, sb->truesize)) { 1317 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1318 card->name); 1319 dev_kfree_skb(sb); 1320 goto drop; 1321 } 1322 1323 *((u32 *) sb->data) = header; 1324 skb_put(sb, sizeof(u32)); 1325 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1326 ATM_CELL_PAYLOAD); 1327 1328 ATM_SKB(sb)->vcc = vcc; 1329 __net_timestamp(sb); 1330 vcc->push(vcc, sb); 1331 atomic_inc(&vcc->stats->rx); 1332 1333 drop: 1334 skb_pull(queue, 64); 1335 1336 head = IDT77252_PRV_PADDR(queue) 1337 + (queue->data - queue->head - 16); 1338 1339 if (queue->len < 128) { 1340 struct sk_buff *next; 1341 u32 handle; 1342 1343 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1344 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1345 1346 next = sb_pool_skb(card, handle); 1347 recycle_rx_skb(card, queue); 1348 1349 if (next) { 1350 card->raw_cell_head = next; 1351 queue = card->raw_cell_head; 1352 dma_sync_single_for_cpu(&card->pcidev->dev, 1353 IDT77252_PRV_PADDR(queue), 1354 (skb_end_pointer(queue) - 1355 queue->data), 1356 DMA_FROM_DEVICE); 1357 } else { 1358 card->raw_cell_head = NULL; 1359 printk("%s: raw cell queue overrun\n", 1360 card->name); 1361 break; 1362 } 1363 } 1364 } 1365 } 1366 1367 1368 /*****************************************************************************/ 1369 /* */ 1370 /* TSQ Handling */ 1371 /* */ 1372 /*****************************************************************************/ 1373 1374 static int 1375 init_tsq(struct idt77252_dev *card) 1376 { 1377 struct tsq_entry *tsqe; 1378 1379 card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE, 1380 &card->tsq.paddr, GFP_KERNEL); 1381 if (card->tsq.base == NULL) { 1382 printk("%s: can't allocate TSQ.\n", card->name); 1383 return -1; 1384 } 1385 memset(card->tsq.base, 0, TSQSIZE); 1386 1387 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1388 card->tsq.next = card->tsq.last; 1389 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1390 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1391 1392 writel(card->tsq.paddr, SAR_REG_TSQB); 1393 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1394 SAR_REG_TSQH); 1395 1396 return 0; 1397 } 1398 1399 static void 1400 deinit_tsq(struct idt77252_dev *card) 1401 { 1402 dma_free_coherent(&card->pcidev->dev, TSQSIZE, 1403 card->tsq.base, card->tsq.paddr); 1404 } 1405 1406 static void 1407 idt77252_tx(struct idt77252_dev *card) 1408 { 1409 struct tsq_entry *tsqe; 1410 unsigned int vpi, vci; 1411 struct vc_map *vc; 1412 u32 conn, stat; 1413 1414 if (card->tsq.next == card->tsq.last) 1415 tsqe = card->tsq.base; 1416 else 1417 tsqe = card->tsq.next + 1; 1418 1419 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1420 card->tsq.base, card->tsq.next, card->tsq.last); 1421 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1422 readl(SAR_REG_TSQB), 1423 readl(SAR_REG_TSQT), 1424 readl(SAR_REG_TSQH)); 1425 1426 stat = le32_to_cpu(tsqe->word_2); 1427 1428 if (stat & SAR_TSQE_INVALID) 1429 return; 1430 1431 do { 1432 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1433 le32_to_cpu(tsqe->word_1), 1434 le32_to_cpu(tsqe->word_2)); 1435 1436 switch (stat & SAR_TSQE_TYPE) { 1437 case SAR_TSQE_TYPE_TIMER: 1438 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1439 break; 1440 1441 case SAR_TSQE_TYPE_IDLE: 1442 1443 conn = le32_to_cpu(tsqe->word_1); 1444 1445 if (SAR_TSQE_TAG(stat) == 0x10) { 1446 #ifdef NOTDEF 1447 printk("%s: Connection %d halted.\n", 1448 card->name, 1449 le32_to_cpu(tsqe->word_1) & 0x1fff); 1450 #endif 1451 break; 1452 } 1453 1454 vc = card->vcs[conn & 0x1fff]; 1455 if (!vc) { 1456 printk("%s: could not find VC from conn %d\n", 1457 card->name, conn & 0x1fff); 1458 break; 1459 } 1460 1461 printk("%s: Connection %d IDLE.\n", 1462 card->name, vc->index); 1463 1464 set_bit(VCF_IDLE, &vc->flags); 1465 break; 1466 1467 case SAR_TSQE_TYPE_TSR: 1468 1469 conn = le32_to_cpu(tsqe->word_1); 1470 1471 vc = card->vcs[conn & 0x1fff]; 1472 if (!vc) { 1473 printk("%s: no VC at index %d\n", 1474 card->name, 1475 le32_to_cpu(tsqe->word_1) & 0x1fff); 1476 break; 1477 } 1478 1479 drain_scq(card, vc); 1480 break; 1481 1482 case SAR_TSQE_TYPE_TBD_COMP: 1483 1484 conn = le32_to_cpu(tsqe->word_1); 1485 1486 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1487 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1488 1489 if (vpi >= (1 << card->vpibits) || 1490 vci >= (1 << card->vcibits)) { 1491 printk("%s: TBD complete: " 1492 "out of range VPI.VCI %u.%u\n", 1493 card->name, vpi, vci); 1494 break; 1495 } 1496 1497 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1498 if (!vc) { 1499 printk("%s: TBD complete: " 1500 "no VC at VPI.VCI %u.%u\n", 1501 card->name, vpi, vci); 1502 break; 1503 } 1504 1505 drain_scq(card, vc); 1506 break; 1507 } 1508 1509 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1510 1511 card->tsq.next = tsqe; 1512 if (card->tsq.next == card->tsq.last) 1513 tsqe = card->tsq.base; 1514 else 1515 tsqe = card->tsq.next + 1; 1516 1517 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1518 card->tsq.base, card->tsq.next, card->tsq.last); 1519 1520 stat = le32_to_cpu(tsqe->word_2); 1521 1522 } while (!(stat & SAR_TSQE_INVALID)); 1523 1524 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1525 SAR_REG_TSQH); 1526 1527 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1528 card->index, readl(SAR_REG_TSQH), 1529 readl(SAR_REG_TSQT), card->tsq.next); 1530 } 1531 1532 1533 static void 1534 tst_timer(unsigned long data) 1535 { 1536 struct idt77252_dev *card = (struct idt77252_dev *)data; 1537 unsigned long base, idle, jump; 1538 unsigned long flags; 1539 u32 pc; 1540 int e; 1541 1542 spin_lock_irqsave(&card->tst_lock, flags); 1543 1544 base = card->tst[card->tst_index]; 1545 idle = card->tst[card->tst_index ^ 1]; 1546 1547 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1548 jump = base + card->tst_size - 2; 1549 1550 pc = readl(SAR_REG_NOW) >> 2; 1551 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1552 mod_timer(&card->tst_timer, jiffies + 1); 1553 goto out; 1554 } 1555 1556 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1557 1558 card->tst_index ^= 1; 1559 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1560 1561 base = card->tst[card->tst_index]; 1562 idle = card->tst[card->tst_index ^ 1]; 1563 1564 for (e = 0; e < card->tst_size - 2; e++) { 1565 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1566 write_sram(card, idle + e, 1567 card->soft_tst[e].tste & TSTE_MASK); 1568 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1569 } 1570 } 1571 } 1572 1573 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1574 1575 for (e = 0; e < card->tst_size - 2; e++) { 1576 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1577 write_sram(card, idle + e, 1578 card->soft_tst[e].tste & TSTE_MASK); 1579 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1580 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1581 } 1582 } 1583 1584 jump = base + card->tst_size - 2; 1585 1586 write_sram(card, jump, TSTE_OPC_NULL); 1587 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1588 1589 mod_timer(&card->tst_timer, jiffies + 1); 1590 } 1591 1592 out: 1593 spin_unlock_irqrestore(&card->tst_lock, flags); 1594 } 1595 1596 static int 1597 __fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1598 int n, unsigned int opc) 1599 { 1600 unsigned long cl, avail; 1601 unsigned long idle; 1602 int e, r; 1603 u32 data; 1604 1605 avail = card->tst_size - 2; 1606 for (e = 0; e < avail; e++) { 1607 if (card->soft_tst[e].vc == NULL) 1608 break; 1609 } 1610 if (e >= avail) { 1611 printk("%s: No free TST entries found\n", card->name); 1612 return -1; 1613 } 1614 1615 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1616 card->name, vc ? vc->index : -1, e); 1617 1618 r = n; 1619 cl = avail; 1620 data = opc & TSTE_OPC_MASK; 1621 if (vc && (opc != TSTE_OPC_NULL)) 1622 data = opc | vc->index; 1623 1624 idle = card->tst[card->tst_index ^ 1]; 1625 1626 /* 1627 * Fill Soft TST. 1628 */ 1629 while (r > 0) { 1630 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1631 if (vc) 1632 card->soft_tst[e].vc = vc; 1633 else 1634 card->soft_tst[e].vc = (void *)-1; 1635 1636 card->soft_tst[e].tste = data; 1637 if (timer_pending(&card->tst_timer)) 1638 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1639 else { 1640 write_sram(card, idle + e, data); 1641 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1642 } 1643 1644 cl -= card->tst_size; 1645 r--; 1646 } 1647 1648 if (++e == avail) 1649 e = 0; 1650 cl += n; 1651 } 1652 1653 return 0; 1654 } 1655 1656 static int 1657 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1658 { 1659 unsigned long flags; 1660 int res; 1661 1662 spin_lock_irqsave(&card->tst_lock, flags); 1663 1664 res = __fill_tst(card, vc, n, opc); 1665 1666 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1667 if (!timer_pending(&card->tst_timer)) 1668 mod_timer(&card->tst_timer, jiffies + 1); 1669 1670 spin_unlock_irqrestore(&card->tst_lock, flags); 1671 return res; 1672 } 1673 1674 static int 1675 __clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1676 { 1677 unsigned long idle; 1678 int e; 1679 1680 idle = card->tst[card->tst_index ^ 1]; 1681 1682 for (e = 0; e < card->tst_size - 2; e++) { 1683 if (card->soft_tst[e].vc == vc) { 1684 card->soft_tst[e].vc = NULL; 1685 1686 card->soft_tst[e].tste = TSTE_OPC_VAR; 1687 if (timer_pending(&card->tst_timer)) 1688 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1689 else { 1690 write_sram(card, idle + e, TSTE_OPC_VAR); 1691 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1692 } 1693 } 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int 1700 clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1701 { 1702 unsigned long flags; 1703 int res; 1704 1705 spin_lock_irqsave(&card->tst_lock, flags); 1706 1707 res = __clear_tst(card, vc); 1708 1709 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1710 if (!timer_pending(&card->tst_timer)) 1711 mod_timer(&card->tst_timer, jiffies + 1); 1712 1713 spin_unlock_irqrestore(&card->tst_lock, flags); 1714 return res; 1715 } 1716 1717 static int 1718 change_tst(struct idt77252_dev *card, struct vc_map *vc, 1719 int n, unsigned int opc) 1720 { 1721 unsigned long flags; 1722 int res; 1723 1724 spin_lock_irqsave(&card->tst_lock, flags); 1725 1726 __clear_tst(card, vc); 1727 res = __fill_tst(card, vc, n, opc); 1728 1729 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1730 if (!timer_pending(&card->tst_timer)) 1731 mod_timer(&card->tst_timer, jiffies + 1); 1732 1733 spin_unlock_irqrestore(&card->tst_lock, flags); 1734 return res; 1735 } 1736 1737 1738 static int 1739 set_tct(struct idt77252_dev *card, struct vc_map *vc) 1740 { 1741 unsigned long tct; 1742 1743 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1744 1745 switch (vc->class) { 1746 case SCHED_CBR: 1747 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1748 card->name, tct, vc->scq->scd); 1749 1750 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1751 write_sram(card, tct + 1, 0); 1752 write_sram(card, tct + 2, 0); 1753 write_sram(card, tct + 3, 0); 1754 write_sram(card, tct + 4, 0); 1755 write_sram(card, tct + 5, 0); 1756 write_sram(card, tct + 6, 0); 1757 write_sram(card, tct + 7, 0); 1758 break; 1759 1760 case SCHED_UBR: 1761 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1762 card->name, tct, vc->scq->scd); 1763 1764 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1765 write_sram(card, tct + 1, 0); 1766 write_sram(card, tct + 2, TCT_TSIF); 1767 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1768 write_sram(card, tct + 4, 0); 1769 write_sram(card, tct + 5, vc->init_er); 1770 write_sram(card, tct + 6, 0); 1771 write_sram(card, tct + 7, TCT_FLAG_UBR); 1772 break; 1773 1774 case SCHED_VBR: 1775 case SCHED_ABR: 1776 default: 1777 return -ENOSYS; 1778 } 1779 1780 return 0; 1781 } 1782 1783 /*****************************************************************************/ 1784 /* */ 1785 /* FBQ Handling */ 1786 /* */ 1787 /*****************************************************************************/ 1788 1789 static __inline__ int 1790 idt77252_fbq_level(struct idt77252_dev *card, int queue) 1791 { 1792 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1793 } 1794 1795 static __inline__ int 1796 idt77252_fbq_full(struct idt77252_dev *card, int queue) 1797 { 1798 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1799 } 1800 1801 static int 1802 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1803 { 1804 unsigned long flags; 1805 u32 handle; 1806 u32 addr; 1807 1808 skb->data = skb->head; 1809 skb_reset_tail_pointer(skb); 1810 skb->len = 0; 1811 1812 skb_reserve(skb, 16); 1813 1814 switch (queue) { 1815 case 0: 1816 skb_put(skb, SAR_FB_SIZE_0); 1817 break; 1818 case 1: 1819 skb_put(skb, SAR_FB_SIZE_1); 1820 break; 1821 case 2: 1822 skb_put(skb, SAR_FB_SIZE_2); 1823 break; 1824 case 3: 1825 skb_put(skb, SAR_FB_SIZE_3); 1826 break; 1827 default: 1828 return -1; 1829 } 1830 1831 if (idt77252_fbq_full(card, queue)) 1832 return -1; 1833 1834 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1835 1836 handle = IDT77252_PRV_POOL(skb); 1837 addr = IDT77252_PRV_PADDR(skb); 1838 1839 spin_lock_irqsave(&card->cmd_lock, flags); 1840 writel(handle, card->fbq[queue]); 1841 writel(addr, card->fbq[queue]); 1842 spin_unlock_irqrestore(&card->cmd_lock, flags); 1843 1844 return 0; 1845 } 1846 1847 static void 1848 add_rx_skb(struct idt77252_dev *card, int queue, 1849 unsigned int size, unsigned int count) 1850 { 1851 struct sk_buff *skb; 1852 dma_addr_t paddr; 1853 u32 handle; 1854 1855 while (count--) { 1856 skb = dev_alloc_skb(size); 1857 if (!skb) 1858 return; 1859 1860 if (sb_pool_add(card, skb, queue)) { 1861 printk("%s: SB POOL full\n", __func__); 1862 goto outfree; 1863 } 1864 1865 paddr = dma_map_single(&card->pcidev->dev, skb->data, 1866 skb_end_pointer(skb) - skb->data, 1867 DMA_FROM_DEVICE); 1868 IDT77252_PRV_PADDR(skb) = paddr; 1869 1870 if (push_rx_skb(card, skb, queue)) { 1871 printk("%s: FB QUEUE full\n", __func__); 1872 goto outunmap; 1873 } 1874 } 1875 1876 return; 1877 1878 outunmap: 1879 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 1880 skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE); 1881 1882 handle = IDT77252_PRV_POOL(skb); 1883 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1884 1885 outfree: 1886 dev_kfree_skb(skb); 1887 } 1888 1889 1890 static void 1891 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1892 { 1893 u32 handle = IDT77252_PRV_POOL(skb); 1894 int err; 1895 1896 dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 1897 skb_end_pointer(skb) - skb->data, 1898 DMA_FROM_DEVICE); 1899 1900 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1901 if (err) { 1902 dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), 1903 skb_end_pointer(skb) - skb->data, 1904 DMA_FROM_DEVICE); 1905 sb_pool_remove(card, skb); 1906 dev_kfree_skb(skb); 1907 } 1908 } 1909 1910 static void 1911 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1912 { 1913 skb_queue_head_init(&rpp->queue); 1914 rpp->len = 0; 1915 } 1916 1917 static void 1918 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1919 { 1920 struct sk_buff *skb, *tmp; 1921 1922 skb_queue_walk_safe(&rpp->queue, skb, tmp) 1923 recycle_rx_skb(card, skb); 1924 1925 flush_rx_pool(card, rpp); 1926 } 1927 1928 /*****************************************************************************/ 1929 /* */ 1930 /* ATM Interface */ 1931 /* */ 1932 /*****************************************************************************/ 1933 1934 static void 1935 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1936 { 1937 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1938 } 1939 1940 static unsigned char 1941 idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1942 { 1943 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1944 } 1945 1946 static inline int 1947 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1948 { 1949 struct atm_dev *dev = vcc->dev; 1950 struct idt77252_dev *card = dev->dev_data; 1951 struct vc_map *vc = vcc->dev_data; 1952 int err; 1953 1954 if (vc == NULL) { 1955 printk("%s: NULL connection in send().\n", card->name); 1956 atomic_inc(&vcc->stats->tx_err); 1957 dev_kfree_skb(skb); 1958 return -EINVAL; 1959 } 1960 if (!test_bit(VCF_TX, &vc->flags)) { 1961 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1962 atomic_inc(&vcc->stats->tx_err); 1963 dev_kfree_skb(skb); 1964 return -EINVAL; 1965 } 1966 1967 switch (vcc->qos.aal) { 1968 case ATM_AAL0: 1969 case ATM_AAL1: 1970 case ATM_AAL5: 1971 break; 1972 default: 1973 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1974 atomic_inc(&vcc->stats->tx_err); 1975 dev_kfree_skb(skb); 1976 return -EINVAL; 1977 } 1978 1979 if (skb_shinfo(skb)->nr_frags != 0) { 1980 printk("%s: No scatter-gather yet.\n", card->name); 1981 atomic_inc(&vcc->stats->tx_err); 1982 dev_kfree_skb(skb); 1983 return -EINVAL; 1984 } 1985 ATM_SKB(skb)->vcc = vcc; 1986 1987 err = queue_skb(card, vc, skb, oam); 1988 if (err) { 1989 atomic_inc(&vcc->stats->tx_err); 1990 dev_kfree_skb(skb); 1991 return err; 1992 } 1993 1994 return 0; 1995 } 1996 1997 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 1998 { 1999 return idt77252_send_skb(vcc, skb, 0); 2000 } 2001 2002 static int 2003 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2004 { 2005 struct atm_dev *dev = vcc->dev; 2006 struct idt77252_dev *card = dev->dev_data; 2007 struct sk_buff *skb; 2008 2009 skb = dev_alloc_skb(64); 2010 if (!skb) { 2011 printk("%s: Out of memory in send_oam().\n", card->name); 2012 atomic_inc(&vcc->stats->tx_err); 2013 return -ENOMEM; 2014 } 2015 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2016 2017 memcpy(skb_put(skb, 52), cell, 52); 2018 2019 return idt77252_send_skb(vcc, skb, 1); 2020 } 2021 2022 static __inline__ unsigned int 2023 idt77252_fls(unsigned int x) 2024 { 2025 int r = 1; 2026 2027 if (x == 0) 2028 return 0; 2029 if (x & 0xffff0000) { 2030 x >>= 16; 2031 r += 16; 2032 } 2033 if (x & 0xff00) { 2034 x >>= 8; 2035 r += 8; 2036 } 2037 if (x & 0xf0) { 2038 x >>= 4; 2039 r += 4; 2040 } 2041 if (x & 0xc) { 2042 x >>= 2; 2043 r += 2; 2044 } 2045 if (x & 0x2) 2046 r += 1; 2047 return r; 2048 } 2049 2050 static u16 2051 idt77252_int_to_atmfp(unsigned int rate) 2052 { 2053 u16 m, e; 2054 2055 if (rate == 0) 2056 return 0; 2057 e = idt77252_fls(rate) - 1; 2058 if (e < 9) 2059 m = (rate - (1 << e)) << (9 - e); 2060 else if (e == 9) 2061 m = (rate - (1 << e)); 2062 else /* e > 9 */ 2063 m = (rate - (1 << e)) >> (e - 9); 2064 return 0x4000 | (e << 9) | m; 2065 } 2066 2067 static u8 2068 idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2069 { 2070 u16 afp; 2071 2072 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2073 if (pcr < 0) 2074 return rate_to_log[(afp >> 5) & 0x1ff]; 2075 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2076 } 2077 2078 static void 2079 idt77252_est_timer(unsigned long data) 2080 { 2081 struct vc_map *vc = (struct vc_map *)data; 2082 struct idt77252_dev *card = vc->card; 2083 struct rate_estimator *est; 2084 unsigned long flags; 2085 u32 rate, cps; 2086 u64 ncells; 2087 u8 lacr; 2088 2089 spin_lock_irqsave(&vc->lock, flags); 2090 est = vc->estimator; 2091 if (!est) 2092 goto out; 2093 2094 ncells = est->cells; 2095 2096 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2097 est->last_cells = ncells; 2098 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2099 est->cps = (est->avcps + 0x1f) >> 5; 2100 2101 cps = est->cps; 2102 if (cps < (est->maxcps >> 4)) 2103 cps = est->maxcps >> 4; 2104 2105 lacr = idt77252_rate_logindex(card, cps); 2106 if (lacr > vc->max_er) 2107 lacr = vc->max_er; 2108 2109 if (lacr != vc->lacr) { 2110 vc->lacr = lacr; 2111 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2112 } 2113 2114 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2115 add_timer(&est->timer); 2116 2117 out: 2118 spin_unlock_irqrestore(&vc->lock, flags); 2119 } 2120 2121 static struct rate_estimator * 2122 idt77252_init_est(struct vc_map *vc, int pcr) 2123 { 2124 struct rate_estimator *est; 2125 2126 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2127 if (!est) 2128 return NULL; 2129 est->maxcps = pcr < 0 ? -pcr : pcr; 2130 est->cps = est->maxcps; 2131 est->avcps = est->cps << 5; 2132 2133 est->interval = 2; /* XXX: make this configurable */ 2134 est->ewma_log = 2; /* XXX: make this configurable */ 2135 init_timer(&est->timer); 2136 est->timer.data = (unsigned long)vc; 2137 est->timer.function = idt77252_est_timer; 2138 2139 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2140 add_timer(&est->timer); 2141 2142 return est; 2143 } 2144 2145 static int 2146 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2147 struct atm_vcc *vcc, struct atm_qos *qos) 2148 { 2149 int tst_free, tst_used, tst_entries; 2150 unsigned long tmpl, modl; 2151 int tcr, tcra; 2152 2153 if ((qos->txtp.max_pcr == 0) && 2154 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2155 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2156 card->name); 2157 return -EINVAL; 2158 } 2159 2160 tst_used = 0; 2161 tst_free = card->tst_free; 2162 if (test_bit(VCF_TX, &vc->flags)) 2163 tst_used = vc->ntste; 2164 tst_free += tst_used; 2165 2166 tcr = atm_pcr_goal(&qos->txtp); 2167 tcra = tcr >= 0 ? tcr : -tcr; 2168 2169 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2170 2171 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2172 modl = tmpl % (unsigned long)card->utopia_pcr; 2173 2174 tst_entries = (int) (tmpl / card->utopia_pcr); 2175 if (tcr > 0) { 2176 if (modl > 0) 2177 tst_entries++; 2178 } else if (tcr == 0) { 2179 tst_entries = tst_free - SAR_TST_RESERVED; 2180 if (tst_entries <= 0) { 2181 printk("%s: no CBR bandwidth free.\n", card->name); 2182 return -ENOSR; 2183 } 2184 } 2185 2186 if (tst_entries == 0) { 2187 printk("%s: selected CBR bandwidth < granularity.\n", 2188 card->name); 2189 return -EINVAL; 2190 } 2191 2192 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2193 printk("%s: not enough CBR bandwidth free.\n", card->name); 2194 return -ENOSR; 2195 } 2196 2197 vc->ntste = tst_entries; 2198 2199 card->tst_free = tst_free - tst_entries; 2200 if (test_bit(VCF_TX, &vc->flags)) { 2201 if (tst_used == tst_entries) 2202 return 0; 2203 2204 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2205 card->name, tst_used, tst_entries); 2206 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2207 return 0; 2208 } 2209 2210 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2211 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2212 return 0; 2213 } 2214 2215 static int 2216 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2217 struct atm_vcc *vcc, struct atm_qos *qos) 2218 { 2219 unsigned long flags; 2220 int tcr; 2221 2222 spin_lock_irqsave(&vc->lock, flags); 2223 if (vc->estimator) { 2224 del_timer(&vc->estimator->timer); 2225 kfree(vc->estimator); 2226 vc->estimator = NULL; 2227 } 2228 spin_unlock_irqrestore(&vc->lock, flags); 2229 2230 tcr = atm_pcr_goal(&qos->txtp); 2231 if (tcr == 0) 2232 tcr = card->link_pcr; 2233 2234 vc->estimator = idt77252_init_est(vc, tcr); 2235 2236 vc->class = SCHED_UBR; 2237 vc->init_er = idt77252_rate_logindex(card, tcr); 2238 vc->lacr = vc->init_er; 2239 if (tcr < 0) 2240 vc->max_er = vc->init_er; 2241 else 2242 vc->max_er = 0xff; 2243 2244 return 0; 2245 } 2246 2247 static int 2248 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2249 struct atm_vcc *vcc, struct atm_qos *qos) 2250 { 2251 int error; 2252 2253 if (test_bit(VCF_TX, &vc->flags)) 2254 return -EBUSY; 2255 2256 switch (qos->txtp.traffic_class) { 2257 case ATM_CBR: 2258 vc->class = SCHED_CBR; 2259 break; 2260 2261 case ATM_UBR: 2262 vc->class = SCHED_UBR; 2263 break; 2264 2265 case ATM_VBR: 2266 case ATM_ABR: 2267 default: 2268 return -EPROTONOSUPPORT; 2269 } 2270 2271 vc->scq = alloc_scq(card, vc->class); 2272 if (!vc->scq) { 2273 printk("%s: can't get SCQ.\n", card->name); 2274 return -ENOMEM; 2275 } 2276 2277 vc->scq->scd = get_free_scd(card, vc); 2278 if (vc->scq->scd == 0) { 2279 printk("%s: no SCD available.\n", card->name); 2280 free_scq(card, vc->scq); 2281 return -ENOMEM; 2282 } 2283 2284 fill_scd(card, vc->scq, vc->class); 2285 2286 if (set_tct(card, vc)) { 2287 printk("%s: class %d not supported.\n", 2288 card->name, qos->txtp.traffic_class); 2289 2290 card->scd2vc[vc->scd_index] = NULL; 2291 free_scq(card, vc->scq); 2292 return -EPROTONOSUPPORT; 2293 } 2294 2295 switch (vc->class) { 2296 case SCHED_CBR: 2297 error = idt77252_init_cbr(card, vc, vcc, qos); 2298 if (error) { 2299 card->scd2vc[vc->scd_index] = NULL; 2300 free_scq(card, vc->scq); 2301 return error; 2302 } 2303 2304 clear_bit(VCF_IDLE, &vc->flags); 2305 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2306 break; 2307 2308 case SCHED_UBR: 2309 error = idt77252_init_ubr(card, vc, vcc, qos); 2310 if (error) { 2311 card->scd2vc[vc->scd_index] = NULL; 2312 free_scq(card, vc->scq); 2313 return error; 2314 } 2315 2316 set_bit(VCF_IDLE, &vc->flags); 2317 break; 2318 } 2319 2320 vc->tx_vcc = vcc; 2321 set_bit(VCF_TX, &vc->flags); 2322 return 0; 2323 } 2324 2325 static int 2326 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2327 struct atm_vcc *vcc, struct atm_qos *qos) 2328 { 2329 unsigned long flags; 2330 unsigned long addr; 2331 u32 rcte = 0; 2332 2333 if (test_bit(VCF_RX, &vc->flags)) 2334 return -EBUSY; 2335 2336 vc->rx_vcc = vcc; 2337 set_bit(VCF_RX, &vc->flags); 2338 2339 if ((vcc->vci == 3) || (vcc->vci == 4)) 2340 return 0; 2341 2342 flush_rx_pool(card, &vc->rcv.rx_pool); 2343 2344 rcte |= SAR_RCTE_CONNECTOPEN; 2345 rcte |= SAR_RCTE_RAWCELLINTEN; 2346 2347 switch (qos->aal) { 2348 case ATM_AAL0: 2349 rcte |= SAR_RCTE_RCQ; 2350 break; 2351 case ATM_AAL1: 2352 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2353 break; 2354 case ATM_AAL34: 2355 rcte |= SAR_RCTE_AAL34; 2356 break; 2357 case ATM_AAL5: 2358 rcte |= SAR_RCTE_AAL5; 2359 break; 2360 default: 2361 rcte |= SAR_RCTE_RCQ; 2362 break; 2363 } 2364 2365 if (qos->aal != ATM_AAL5) 2366 rcte |= SAR_RCTE_FBP_1; 2367 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2368 rcte |= SAR_RCTE_FBP_3; 2369 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2370 rcte |= SAR_RCTE_FBP_2; 2371 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2372 rcte |= SAR_RCTE_FBP_1; 2373 else 2374 rcte |= SAR_RCTE_FBP_01; 2375 2376 addr = card->rct_base + (vc->index << 2); 2377 2378 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2379 write_sram(card, addr, rcte); 2380 2381 spin_lock_irqsave(&card->cmd_lock, flags); 2382 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2383 waitfor_idle(card); 2384 spin_unlock_irqrestore(&card->cmd_lock, flags); 2385 2386 return 0; 2387 } 2388 2389 static int 2390 idt77252_open(struct atm_vcc *vcc) 2391 { 2392 struct atm_dev *dev = vcc->dev; 2393 struct idt77252_dev *card = dev->dev_data; 2394 struct vc_map *vc; 2395 unsigned int index; 2396 unsigned int inuse; 2397 int error; 2398 int vci = vcc->vci; 2399 short vpi = vcc->vpi; 2400 2401 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2402 return 0; 2403 2404 if (vpi >= (1 << card->vpibits)) { 2405 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2406 return -EINVAL; 2407 } 2408 2409 if (vci >= (1 << card->vcibits)) { 2410 printk("%s: unsupported VCI: %d\n", card->name, vci); 2411 return -EINVAL; 2412 } 2413 2414 set_bit(ATM_VF_ADDR, &vcc->flags); 2415 2416 mutex_lock(&card->mutex); 2417 2418 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2419 2420 switch (vcc->qos.aal) { 2421 case ATM_AAL0: 2422 case ATM_AAL1: 2423 case ATM_AAL5: 2424 break; 2425 default: 2426 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2427 mutex_unlock(&card->mutex); 2428 return -EPROTONOSUPPORT; 2429 } 2430 2431 index = VPCI2VC(card, vpi, vci); 2432 if (!card->vcs[index]) { 2433 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2434 if (!card->vcs[index]) { 2435 printk("%s: can't alloc vc in open()\n", card->name); 2436 mutex_unlock(&card->mutex); 2437 return -ENOMEM; 2438 } 2439 card->vcs[index]->card = card; 2440 card->vcs[index]->index = index; 2441 2442 spin_lock_init(&card->vcs[index]->lock); 2443 } 2444 vc = card->vcs[index]; 2445 2446 vcc->dev_data = vc; 2447 2448 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2449 card->name, vc->index, vcc->vpi, vcc->vci, 2450 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2451 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2452 vcc->qos.rxtp.max_sdu); 2453 2454 inuse = 0; 2455 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2456 test_bit(VCF_TX, &vc->flags)) 2457 inuse = 1; 2458 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2459 test_bit(VCF_RX, &vc->flags)) 2460 inuse += 2; 2461 2462 if (inuse) { 2463 printk("%s: %s vci already in use.\n", card->name, 2464 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2465 mutex_unlock(&card->mutex); 2466 return -EADDRINUSE; 2467 } 2468 2469 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2470 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2471 if (error) { 2472 mutex_unlock(&card->mutex); 2473 return error; 2474 } 2475 } 2476 2477 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2478 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2479 if (error) { 2480 mutex_unlock(&card->mutex); 2481 return error; 2482 } 2483 } 2484 2485 set_bit(ATM_VF_READY, &vcc->flags); 2486 2487 mutex_unlock(&card->mutex); 2488 return 0; 2489 } 2490 2491 static void 2492 idt77252_close(struct atm_vcc *vcc) 2493 { 2494 struct atm_dev *dev = vcc->dev; 2495 struct idt77252_dev *card = dev->dev_data; 2496 struct vc_map *vc = vcc->dev_data; 2497 unsigned long flags; 2498 unsigned long addr; 2499 unsigned long timeout; 2500 2501 mutex_lock(&card->mutex); 2502 2503 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2504 card->name, vc->index, vcc->vpi, vcc->vci); 2505 2506 clear_bit(ATM_VF_READY, &vcc->flags); 2507 2508 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2509 2510 spin_lock_irqsave(&vc->lock, flags); 2511 clear_bit(VCF_RX, &vc->flags); 2512 vc->rx_vcc = NULL; 2513 spin_unlock_irqrestore(&vc->lock, flags); 2514 2515 if ((vcc->vci == 3) || (vcc->vci == 4)) 2516 goto done; 2517 2518 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2519 2520 spin_lock_irqsave(&card->cmd_lock, flags); 2521 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2522 waitfor_idle(card); 2523 spin_unlock_irqrestore(&card->cmd_lock, flags); 2524 2525 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2526 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2527 card->name); 2528 2529 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2530 } 2531 } 2532 2533 done: 2534 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2535 2536 spin_lock_irqsave(&vc->lock, flags); 2537 clear_bit(VCF_TX, &vc->flags); 2538 clear_bit(VCF_IDLE, &vc->flags); 2539 clear_bit(VCF_RSV, &vc->flags); 2540 vc->tx_vcc = NULL; 2541 2542 if (vc->estimator) { 2543 del_timer(&vc->estimator->timer); 2544 kfree(vc->estimator); 2545 vc->estimator = NULL; 2546 } 2547 spin_unlock_irqrestore(&vc->lock, flags); 2548 2549 timeout = 5 * 1000; 2550 while (atomic_read(&vc->scq->used) > 0) { 2551 timeout = msleep_interruptible(timeout); 2552 if (!timeout) { 2553 pr_warn("%s: SCQ drain timeout: %u used\n", 2554 card->name, atomic_read(&vc->scq->used)); 2555 break; 2556 } 2557 } 2558 2559 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2560 clear_scd(card, vc->scq, vc->class); 2561 2562 if (vc->class == SCHED_CBR) { 2563 clear_tst(card, vc); 2564 card->tst_free += vc->ntste; 2565 vc->ntste = 0; 2566 } 2567 2568 card->scd2vc[vc->scd_index] = NULL; 2569 free_scq(card, vc->scq); 2570 } 2571 2572 mutex_unlock(&card->mutex); 2573 } 2574 2575 static int 2576 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2577 { 2578 struct atm_dev *dev = vcc->dev; 2579 struct idt77252_dev *card = dev->dev_data; 2580 struct vc_map *vc = vcc->dev_data; 2581 int error = 0; 2582 2583 mutex_lock(&card->mutex); 2584 2585 if (qos->txtp.traffic_class != ATM_NONE) { 2586 if (!test_bit(VCF_TX, &vc->flags)) { 2587 error = idt77252_init_tx(card, vc, vcc, qos); 2588 if (error) 2589 goto out; 2590 } else { 2591 switch (qos->txtp.traffic_class) { 2592 case ATM_CBR: 2593 error = idt77252_init_cbr(card, vc, vcc, qos); 2594 if (error) 2595 goto out; 2596 break; 2597 2598 case ATM_UBR: 2599 error = idt77252_init_ubr(card, vc, vcc, qos); 2600 if (error) 2601 goto out; 2602 2603 if (!test_bit(VCF_IDLE, &vc->flags)) { 2604 writel(TCMDQ_LACR | (vc->lacr << 16) | 2605 vc->index, SAR_REG_TCMDQ); 2606 } 2607 break; 2608 2609 case ATM_VBR: 2610 case ATM_ABR: 2611 error = -EOPNOTSUPP; 2612 goto out; 2613 } 2614 } 2615 } 2616 2617 if ((qos->rxtp.traffic_class != ATM_NONE) && 2618 !test_bit(VCF_RX, &vc->flags)) { 2619 error = idt77252_init_rx(card, vc, vcc, qos); 2620 if (error) 2621 goto out; 2622 } 2623 2624 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2625 2626 set_bit(ATM_VF_HASQOS, &vcc->flags); 2627 2628 out: 2629 mutex_unlock(&card->mutex); 2630 return error; 2631 } 2632 2633 static int 2634 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2635 { 2636 struct idt77252_dev *card = dev->dev_data; 2637 int i, left; 2638 2639 left = (int) *pos; 2640 if (!left--) 2641 return sprintf(page, "IDT77252 Interrupts:\n"); 2642 if (!left--) 2643 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2644 if (!left--) 2645 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2646 if (!left--) 2647 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2648 if (!left--) 2649 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2650 if (!left--) 2651 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2652 if (!left--) 2653 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2654 if (!left--) 2655 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2656 if (!left--) 2657 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2658 if (!left--) 2659 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2660 if (!left--) 2661 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2662 if (!left--) 2663 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2664 if (!left--) 2665 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2666 if (!left--) 2667 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2668 if (!left--) 2669 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2670 2671 for (i = 0; i < card->tct_size; i++) { 2672 unsigned long tct; 2673 struct atm_vcc *vcc; 2674 struct vc_map *vc; 2675 char *p; 2676 2677 vc = card->vcs[i]; 2678 if (!vc) 2679 continue; 2680 2681 vcc = NULL; 2682 if (vc->tx_vcc) 2683 vcc = vc->tx_vcc; 2684 if (!vcc) 2685 continue; 2686 if (left--) 2687 continue; 2688 2689 p = page; 2690 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2691 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2692 2693 for (i = 0; i < 8; i++) 2694 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2695 p += sprintf(p, "\n"); 2696 return p - page; 2697 } 2698 return 0; 2699 } 2700 2701 /*****************************************************************************/ 2702 /* */ 2703 /* Interrupt handler */ 2704 /* */ 2705 /*****************************************************************************/ 2706 2707 static void 2708 idt77252_collect_stat(struct idt77252_dev *card) 2709 { 2710 (void) readl(SAR_REG_CDC); 2711 (void) readl(SAR_REG_VPEC); 2712 (void) readl(SAR_REG_ICC); 2713 2714 } 2715 2716 static irqreturn_t 2717 idt77252_interrupt(int irq, void *dev_id) 2718 { 2719 struct idt77252_dev *card = dev_id; 2720 u32 stat; 2721 2722 stat = readl(SAR_REG_STAT) & 0xffff; 2723 if (!stat) /* no interrupt for us */ 2724 return IRQ_NONE; 2725 2726 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2727 printk("%s: Re-entering irq_handler()\n", card->name); 2728 goto out; 2729 } 2730 2731 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2732 2733 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2734 INTPRINTK("%s: TSIF\n", card->name); 2735 card->irqstat[15]++; 2736 idt77252_tx(card); 2737 } 2738 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2739 INTPRINTK("%s: TXICP\n", card->name); 2740 card->irqstat[14]++; 2741 #ifdef CONFIG_ATM_IDT77252_DEBUG 2742 idt77252_tx_dump(card); 2743 #endif 2744 } 2745 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2746 INTPRINTK("%s: TSQF\n", card->name); 2747 card->irqstat[12]++; 2748 idt77252_tx(card); 2749 } 2750 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2751 INTPRINTK("%s: TMROF\n", card->name); 2752 card->irqstat[11]++; 2753 idt77252_collect_stat(card); 2754 } 2755 2756 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2757 INTPRINTK("%s: EPDU\n", card->name); 2758 card->irqstat[5]++; 2759 idt77252_rx(card); 2760 } 2761 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2762 INTPRINTK("%s: RSQAF\n", card->name); 2763 card->irqstat[1]++; 2764 idt77252_rx(card); 2765 } 2766 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2767 INTPRINTK("%s: RSQF\n", card->name); 2768 card->irqstat[6]++; 2769 idt77252_rx(card); 2770 } 2771 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2772 INTPRINTK("%s: RAWCF\n", card->name); 2773 card->irqstat[4]++; 2774 idt77252_rx_raw(card); 2775 } 2776 2777 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2778 INTPRINTK("%s: PHYI", card->name); 2779 card->irqstat[10]++; 2780 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2781 card->atmdev->phy->interrupt(card->atmdev); 2782 } 2783 2784 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2785 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2786 2787 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2788 2789 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2790 2791 if (stat & SAR_STAT_FBQ0A) 2792 card->irqstat[2]++; 2793 if (stat & SAR_STAT_FBQ1A) 2794 card->irqstat[3]++; 2795 if (stat & SAR_STAT_FBQ2A) 2796 card->irqstat[7]++; 2797 if (stat & SAR_STAT_FBQ3A) 2798 card->irqstat[8]++; 2799 2800 schedule_work(&card->tqueue); 2801 } 2802 2803 out: 2804 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2805 return IRQ_HANDLED; 2806 } 2807 2808 static void 2809 idt77252_softint(struct work_struct *work) 2810 { 2811 struct idt77252_dev *card = 2812 container_of(work, struct idt77252_dev, tqueue); 2813 u32 stat; 2814 int done; 2815 2816 for (done = 1; ; done = 1) { 2817 stat = readl(SAR_REG_STAT) >> 16; 2818 2819 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2820 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2821 done = 0; 2822 } 2823 2824 stat >>= 4; 2825 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2826 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2827 done = 0; 2828 } 2829 2830 stat >>= 4; 2831 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2832 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2833 done = 0; 2834 } 2835 2836 stat >>= 4; 2837 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2838 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2839 done = 0; 2840 } 2841 2842 if (done) 2843 break; 2844 } 2845 2846 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2847 } 2848 2849 2850 static int 2851 open_card_oam(struct idt77252_dev *card) 2852 { 2853 unsigned long flags; 2854 unsigned long addr; 2855 struct vc_map *vc; 2856 int vpi, vci; 2857 int index; 2858 u32 rcte; 2859 2860 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2861 for (vci = 3; vci < 5; vci++) { 2862 index = VPCI2VC(card, vpi, vci); 2863 2864 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2865 if (!vc) { 2866 printk("%s: can't alloc vc\n", card->name); 2867 return -ENOMEM; 2868 } 2869 vc->index = index; 2870 card->vcs[index] = vc; 2871 2872 flush_rx_pool(card, &vc->rcv.rx_pool); 2873 2874 rcte = SAR_RCTE_CONNECTOPEN | 2875 SAR_RCTE_RAWCELLINTEN | 2876 SAR_RCTE_RCQ | 2877 SAR_RCTE_FBP_1; 2878 2879 addr = card->rct_base + (vc->index << 2); 2880 write_sram(card, addr, rcte); 2881 2882 spin_lock_irqsave(&card->cmd_lock, flags); 2883 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2884 SAR_REG_CMD); 2885 waitfor_idle(card); 2886 spin_unlock_irqrestore(&card->cmd_lock, flags); 2887 } 2888 } 2889 2890 return 0; 2891 } 2892 2893 static void 2894 close_card_oam(struct idt77252_dev *card) 2895 { 2896 unsigned long flags; 2897 unsigned long addr; 2898 struct vc_map *vc; 2899 int vpi, vci; 2900 int index; 2901 2902 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2903 for (vci = 3; vci < 5; vci++) { 2904 index = VPCI2VC(card, vpi, vci); 2905 vc = card->vcs[index]; 2906 2907 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2908 2909 spin_lock_irqsave(&card->cmd_lock, flags); 2910 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2911 SAR_REG_CMD); 2912 waitfor_idle(card); 2913 spin_unlock_irqrestore(&card->cmd_lock, flags); 2914 2915 if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { 2916 DPRINTK("%s: closing a VC " 2917 "with pending rx buffers.\n", 2918 card->name); 2919 2920 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2921 } 2922 } 2923 } 2924 } 2925 2926 static int 2927 open_card_ubr0(struct idt77252_dev *card) 2928 { 2929 struct vc_map *vc; 2930 2931 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2932 if (!vc) { 2933 printk("%s: can't alloc vc\n", card->name); 2934 return -ENOMEM; 2935 } 2936 card->vcs[0] = vc; 2937 vc->class = SCHED_UBR0; 2938 2939 vc->scq = alloc_scq(card, vc->class); 2940 if (!vc->scq) { 2941 printk("%s: can't get SCQ.\n", card->name); 2942 return -ENOMEM; 2943 } 2944 2945 card->scd2vc[0] = vc; 2946 vc->scd_index = 0; 2947 vc->scq->scd = card->scd_base; 2948 2949 fill_scd(card, vc->scq, vc->class); 2950 2951 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 2952 write_sram(card, card->tct_base + 1, 0); 2953 write_sram(card, card->tct_base + 2, 0); 2954 write_sram(card, card->tct_base + 3, 0); 2955 write_sram(card, card->tct_base + 4, 0); 2956 write_sram(card, card->tct_base + 5, 0); 2957 write_sram(card, card->tct_base + 6, 0); 2958 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 2959 2960 clear_bit(VCF_IDLE, &vc->flags); 2961 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 2962 return 0; 2963 } 2964 2965 static int 2966 idt77252_dev_open(struct idt77252_dev *card) 2967 { 2968 u32 conf; 2969 2970 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 2971 printk("%s: SAR not yet initialized.\n", card->name); 2972 return -1; 2973 } 2974 2975 conf = SAR_CFG_RXPTH| /* enable receive path */ 2976 SAR_RX_DELAY | /* interrupt on complete PDU */ 2977 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 2978 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 2979 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 2980 SAR_CFG_FBIE | /* interrupt on low free buffers */ 2981 SAR_CFG_TXEN | /* transmit operation enable */ 2982 SAR_CFG_TXINT | /* interrupt on transmit status */ 2983 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 2984 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 2985 SAR_CFG_PHYIE /* enable PHY interrupts */ 2986 ; 2987 2988 #ifdef CONFIG_ATM_IDT77252_RCV_ALL 2989 /* Test RAW cell receive. */ 2990 conf |= SAR_CFG_VPECA; 2991 #endif 2992 2993 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 2994 2995 if (open_card_oam(card)) { 2996 printk("%s: Error initializing OAM.\n", card->name); 2997 return -1; 2998 } 2999 3000 if (open_card_ubr0(card)) { 3001 printk("%s: Error initializing UBR0.\n", card->name); 3002 return -1; 3003 } 3004 3005 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3006 return 0; 3007 } 3008 3009 static void idt77252_dev_close(struct atm_dev *dev) 3010 { 3011 struct idt77252_dev *card = dev->dev_data; 3012 u32 conf; 3013 3014 close_card_oam(card); 3015 3016 conf = SAR_CFG_RXPTH | /* enable receive path */ 3017 SAR_RX_DELAY | /* interrupt on complete PDU */ 3018 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3019 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3020 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3021 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3022 SAR_CFG_TXEN | /* transmit operation enable */ 3023 SAR_CFG_TXINT | /* interrupt on transmit status */ 3024 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3025 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3026 ; 3027 3028 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3029 3030 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3031 } 3032 3033 3034 /*****************************************************************************/ 3035 /* */ 3036 /* Initialisation and Deinitialization of IDT77252 */ 3037 /* */ 3038 /*****************************************************************************/ 3039 3040 3041 static void 3042 deinit_card(struct idt77252_dev *card) 3043 { 3044 struct sk_buff *skb; 3045 int i, j; 3046 3047 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3048 printk("%s: SAR not yet initialized.\n", card->name); 3049 return; 3050 } 3051 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3052 3053 writel(0, SAR_REG_CFG); 3054 3055 if (card->atmdev) 3056 atm_dev_deregister(card->atmdev); 3057 3058 for (i = 0; i < 4; i++) { 3059 for (j = 0; j < FBQ_SIZE; j++) { 3060 skb = card->sbpool[i].skb[j]; 3061 if (skb) { 3062 dma_unmap_single(&card->pcidev->dev, 3063 IDT77252_PRV_PADDR(skb), 3064 (skb_end_pointer(skb) - 3065 skb->data), 3066 DMA_FROM_DEVICE); 3067 card->sbpool[i].skb[j] = NULL; 3068 dev_kfree_skb(skb); 3069 } 3070 } 3071 } 3072 3073 vfree(card->soft_tst); 3074 3075 vfree(card->scd2vc); 3076 3077 vfree(card->vcs); 3078 3079 if (card->raw_cell_hnd) { 3080 dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32), 3081 card->raw_cell_hnd, card->raw_cell_paddr); 3082 } 3083 3084 if (card->rsq.base) { 3085 DIPRINTK("%s: Release RSQ ...\n", card->name); 3086 deinit_rsq(card); 3087 } 3088 3089 if (card->tsq.base) { 3090 DIPRINTK("%s: Release TSQ ...\n", card->name); 3091 deinit_tsq(card); 3092 } 3093 3094 DIPRINTK("idt77252: Release IRQ.\n"); 3095 free_irq(card->pcidev->irq, card); 3096 3097 for (i = 0; i < 4; i++) { 3098 if (card->fbq[i]) 3099 iounmap(card->fbq[i]); 3100 } 3101 3102 if (card->membase) 3103 iounmap(card->membase); 3104 3105 clear_bit(IDT77252_BIT_INIT, &card->flags); 3106 DIPRINTK("%s: Card deinitialized.\n", card->name); 3107 } 3108 3109 3110 static void init_sram(struct idt77252_dev *card) 3111 { 3112 int i; 3113 3114 for (i = 0; i < card->sramsize; i += 4) 3115 write_sram(card, (i >> 2), 0); 3116 3117 /* set SRAM layout for THIS card */ 3118 if (card->sramsize == (512 * 1024)) { 3119 card->tct_base = SAR_SRAM_TCT_128_BASE; 3120 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3121 / SAR_SRAM_TCT_SIZE; 3122 card->rct_base = SAR_SRAM_RCT_128_BASE; 3123 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3124 / SAR_SRAM_RCT_SIZE; 3125 card->rt_base = SAR_SRAM_RT_128_BASE; 3126 card->scd_base = SAR_SRAM_SCD_128_BASE; 3127 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3128 / SAR_SRAM_SCD_SIZE; 3129 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3130 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3131 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3132 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3133 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3134 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3135 card->fifo_size = SAR_RXFD_SIZE_32K; 3136 } else { 3137 card->tct_base = SAR_SRAM_TCT_32_BASE; 3138 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3139 / SAR_SRAM_TCT_SIZE; 3140 card->rct_base = SAR_SRAM_RCT_32_BASE; 3141 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3142 / SAR_SRAM_RCT_SIZE; 3143 card->rt_base = SAR_SRAM_RT_32_BASE; 3144 card->scd_base = SAR_SRAM_SCD_32_BASE; 3145 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3146 / SAR_SRAM_SCD_SIZE; 3147 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3148 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3149 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3150 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3151 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3152 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3153 card->fifo_size = SAR_RXFD_SIZE_4K; 3154 } 3155 3156 /* Initialize TCT */ 3157 for (i = 0; i < card->tct_size; i++) { 3158 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3159 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3160 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3161 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3162 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3163 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3164 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3165 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3166 } 3167 3168 /* Initialize RCT */ 3169 for (i = 0; i < card->rct_size; i++) { 3170 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3171 (u32) SAR_RCTE_RAWCELLINTEN); 3172 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3173 (u32) 0); 3174 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3175 (u32) 0); 3176 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3177 (u32) 0xffffffff); 3178 } 3179 3180 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3181 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3182 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3183 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3184 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3185 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3186 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3187 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3188 3189 /* Initialize rate table */ 3190 for (i = 0; i < 256; i++) { 3191 write_sram(card, card->rt_base + i, log_to_rate[i]); 3192 } 3193 3194 for (i = 0; i < 128; i++) { 3195 unsigned int tmp; 3196 3197 tmp = rate_to_log[(i << 2) + 0] << 0; 3198 tmp |= rate_to_log[(i << 2) + 1] << 8; 3199 tmp |= rate_to_log[(i << 2) + 2] << 16; 3200 tmp |= rate_to_log[(i << 2) + 3] << 24; 3201 write_sram(card, card->rt_base + 256 + i, tmp); 3202 } 3203 3204 #if 0 /* Fill RDF and AIR tables. */ 3205 for (i = 0; i < 128; i++) { 3206 unsigned int tmp; 3207 3208 tmp = RDF[0][(i << 1) + 0] << 16; 3209 tmp |= RDF[0][(i << 1) + 1] << 0; 3210 write_sram(card, card->rt_base + 512 + i, tmp); 3211 } 3212 3213 for (i = 0; i < 128; i++) { 3214 unsigned int tmp; 3215 3216 tmp = AIR[0][(i << 1) + 0] << 16; 3217 tmp |= AIR[0][(i << 1) + 1] << 0; 3218 write_sram(card, card->rt_base + 640 + i, tmp); 3219 } 3220 #endif 3221 3222 IPRINTK("%s: initialize rate table ...\n", card->name); 3223 writel(card->rt_base << 2, SAR_REG_RTBL); 3224 3225 /* Initialize TSTs */ 3226 IPRINTK("%s: initialize TST ...\n", card->name); 3227 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3228 3229 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3230 write_sram(card, i, TSTE_OPC_VAR); 3231 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3232 idt77252_sram_write_errors = 1; 3233 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3234 idt77252_sram_write_errors = 0; 3235 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3236 write_sram(card, i, TSTE_OPC_VAR); 3237 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3238 idt77252_sram_write_errors = 1; 3239 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3240 idt77252_sram_write_errors = 0; 3241 3242 card->tst_index = 0; 3243 writel(card->tst[0] << 2, SAR_REG_TSTB); 3244 3245 /* Initialize ABRSTD and Receive FIFO */ 3246 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3247 writel(card->abrst_size | (card->abrst_base << 2), 3248 SAR_REG_ABRSTD); 3249 3250 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3251 writel(card->fifo_size | (card->fifo_base << 2), 3252 SAR_REG_RXFD); 3253 3254 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3255 } 3256 3257 static int init_card(struct atm_dev *dev) 3258 { 3259 struct idt77252_dev *card = dev->dev_data; 3260 struct pci_dev *pcidev = card->pcidev; 3261 unsigned long tmpl, modl; 3262 unsigned int linkrate, rsvdcr; 3263 unsigned int tst_entries; 3264 struct net_device *tmp; 3265 char tname[10]; 3266 3267 u32 size; 3268 u_char pci_byte; 3269 u32 conf; 3270 int i, k; 3271 3272 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3273 printk("Error: SAR already initialized.\n"); 3274 return -1; 3275 } 3276 3277 /*****************************************************************/ 3278 /* P C I C O N F I G U R A T I O N */ 3279 /*****************************************************************/ 3280 3281 /* Set PCI Retry-Timeout and TRDY timeout */ 3282 IPRINTK("%s: Checking PCI retries.\n", card->name); 3283 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3284 printk("%s: can't read PCI retry timeout.\n", card->name); 3285 deinit_card(card); 3286 return -1; 3287 } 3288 if (pci_byte != 0) { 3289 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3290 card->name, pci_byte); 3291 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3292 printk("%s: can't set PCI retry timeout.\n", 3293 card->name); 3294 deinit_card(card); 3295 return -1; 3296 } 3297 } 3298 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3299 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3300 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3301 deinit_card(card); 3302 return -1; 3303 } 3304 if (pci_byte != 0) { 3305 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3306 card->name, pci_byte); 3307 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3308 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3309 deinit_card(card); 3310 return -1; 3311 } 3312 } 3313 /* Reset Timer register */ 3314 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3315 printk("%s: resetting timer overflow.\n", card->name); 3316 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3317 } 3318 IPRINTK("%s: Request IRQ ... ", card->name); 3319 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED, 3320 card->name, card) != 0) { 3321 printk("%s: can't allocate IRQ.\n", card->name); 3322 deinit_card(card); 3323 return -1; 3324 } 3325 IPRINTK("got %d.\n", pcidev->irq); 3326 3327 /*****************************************************************/ 3328 /* C H E C K A N D I N I T S R A M */ 3329 /*****************************************************************/ 3330 3331 IPRINTK("%s: Initializing SRAM\n", card->name); 3332 3333 /* preset size of connecton table, so that init_sram() knows about it */ 3334 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3335 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3336 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3337 #ifndef ATM_IDT77252_SEND_IDLE 3338 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3339 #endif 3340 0; 3341 3342 if (card->sramsize == (512 * 1024)) 3343 conf |= SAR_CFG_CNTBL_1k; 3344 else 3345 conf |= SAR_CFG_CNTBL_512; 3346 3347 switch (vpibits) { 3348 case 0: 3349 conf |= SAR_CFG_VPVCS_0; 3350 break; 3351 default: 3352 case 1: 3353 conf |= SAR_CFG_VPVCS_1; 3354 break; 3355 case 2: 3356 conf |= SAR_CFG_VPVCS_2; 3357 break; 3358 case 8: 3359 conf |= SAR_CFG_VPVCS_8; 3360 break; 3361 } 3362 3363 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3364 3365 init_sram(card); 3366 3367 /********************************************************************/ 3368 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3369 /********************************************************************/ 3370 /* Initialize TSQ */ 3371 if (0 != init_tsq(card)) { 3372 deinit_card(card); 3373 return -1; 3374 } 3375 /* Initialize RSQ */ 3376 if (0 != init_rsq(card)) { 3377 deinit_card(card); 3378 return -1; 3379 } 3380 3381 card->vpibits = vpibits; 3382 if (card->sramsize == (512 * 1024)) { 3383 card->vcibits = 10 - card->vpibits; 3384 } else { 3385 card->vcibits = 9 - card->vpibits; 3386 } 3387 3388 card->vcimask = 0; 3389 for (k = 0, i = 1; k < card->vcibits; k++) { 3390 card->vcimask |= i; 3391 i <<= 1; 3392 } 3393 3394 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3395 writel(0, SAR_REG_VPM); 3396 3397 /* Little Endian Order */ 3398 writel(0, SAR_REG_GP); 3399 3400 /* Initialize RAW Cell Handle Register */ 3401 card->raw_cell_hnd = dma_zalloc_coherent(&card->pcidev->dev, 3402 2 * sizeof(u32), 3403 &card->raw_cell_paddr, 3404 GFP_KERNEL); 3405 if (!card->raw_cell_hnd) { 3406 printk("%s: memory allocation failure.\n", card->name); 3407 deinit_card(card); 3408 return -1; 3409 } 3410 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3411 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3412 card->raw_cell_hnd); 3413 3414 size = sizeof(struct vc_map *) * card->tct_size; 3415 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3416 card->vcs = vzalloc(size); 3417 if (!card->vcs) { 3418 printk("%s: memory allocation failure.\n", card->name); 3419 deinit_card(card); 3420 return -1; 3421 } 3422 3423 size = sizeof(struct vc_map *) * card->scd_size; 3424 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3425 card->name, size); 3426 card->scd2vc = vzalloc(size); 3427 if (!card->scd2vc) { 3428 printk("%s: memory allocation failure.\n", card->name); 3429 deinit_card(card); 3430 return -1; 3431 } 3432 3433 size = sizeof(struct tst_info) * (card->tst_size - 2); 3434 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3435 card->name, size); 3436 card->soft_tst = vmalloc(size); 3437 if (!card->soft_tst) { 3438 printk("%s: memory allocation failure.\n", card->name); 3439 deinit_card(card); 3440 return -1; 3441 } 3442 for (i = 0; i < card->tst_size - 2; i++) { 3443 card->soft_tst[i].tste = TSTE_OPC_VAR; 3444 card->soft_tst[i].vc = NULL; 3445 } 3446 3447 if (dev->phy == NULL) { 3448 printk("%s: No LT device defined.\n", card->name); 3449 deinit_card(card); 3450 return -1; 3451 } 3452 if (dev->phy->ioctl == NULL) { 3453 printk("%s: LT had no IOCTL function defined.\n", card->name); 3454 deinit_card(card); 3455 return -1; 3456 } 3457 3458 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3459 /* 3460 * this is a jhs hack to get around special functionality in the 3461 * phy driver for the atecom hardware; the functionality doesn't 3462 * exist in the linux atm suni driver 3463 * 3464 * it isn't the right way to do things, but as the guy from NIST 3465 * said, talking about their measurement of the fine structure 3466 * constant, "it's good enough for government work." 3467 */ 3468 linkrate = 149760000; 3469 #endif 3470 3471 card->link_pcr = (linkrate / 8 / 53); 3472 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3473 card->name, linkrate, card->link_pcr); 3474 3475 #ifdef ATM_IDT77252_SEND_IDLE 3476 card->utopia_pcr = card->link_pcr; 3477 #else 3478 card->utopia_pcr = (160000000 / 8 / 54); 3479 #endif 3480 3481 rsvdcr = 0; 3482 if (card->utopia_pcr > card->link_pcr) 3483 rsvdcr = card->utopia_pcr - card->link_pcr; 3484 3485 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3486 modl = tmpl % (unsigned long)card->utopia_pcr; 3487 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3488 if (modl) 3489 tst_entries++; 3490 card->tst_free -= tst_entries; 3491 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3492 3493 #ifdef HAVE_EEPROM 3494 idt77252_eeprom_init(card); 3495 printk("%s: EEPROM: %02x:", card->name, 3496 idt77252_eeprom_read_status(card)); 3497 3498 for (i = 0; i < 0x80; i++) { 3499 printk(" %02x", 3500 idt77252_eeprom_read_byte(card, i) 3501 ); 3502 } 3503 printk("\n"); 3504 #endif /* HAVE_EEPROM */ 3505 3506 /* 3507 * XXX: <hack> 3508 */ 3509 sprintf(tname, "eth%d", card->index); 3510 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ 3511 if (tmp) { 3512 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3513 dev_put(tmp); 3514 printk("%s: ESI %pM\n", card->name, card->atmdev->esi); 3515 } 3516 /* 3517 * XXX: </hack> 3518 */ 3519 3520 /* Set Maximum Deficit Count for now. */ 3521 writel(0xffff, SAR_REG_MDFCT); 3522 3523 set_bit(IDT77252_BIT_INIT, &card->flags); 3524 3525 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3526 return 0; 3527 } 3528 3529 3530 /*****************************************************************************/ 3531 /* */ 3532 /* Probing of IDT77252 ABR SAR */ 3533 /* */ 3534 /*****************************************************************************/ 3535 3536 3537 static int idt77252_preset(struct idt77252_dev *card) 3538 { 3539 u16 pci_command; 3540 3541 /*****************************************************************/ 3542 /* P C I C O N F I G U R A T I O N */ 3543 /*****************************************************************/ 3544 3545 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3546 card->name); 3547 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3548 printk("%s: can't read PCI_COMMAND.\n", card->name); 3549 deinit_card(card); 3550 return -1; 3551 } 3552 if (!(pci_command & PCI_COMMAND_IO)) { 3553 printk("%s: PCI_COMMAND: %04x (???)\n", 3554 card->name, pci_command); 3555 deinit_card(card); 3556 return (-1); 3557 } 3558 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3559 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3560 printk("%s: can't write PCI_COMMAND.\n", card->name); 3561 deinit_card(card); 3562 return -1; 3563 } 3564 /*****************************************************************/ 3565 /* G E N E R I C R E S E T */ 3566 /*****************************************************************/ 3567 3568 /* Software reset */ 3569 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3570 mdelay(1); 3571 writel(0, SAR_REG_CFG); 3572 3573 IPRINTK("%s: Software resetted.\n", card->name); 3574 return 0; 3575 } 3576 3577 3578 static unsigned long probe_sram(struct idt77252_dev *card) 3579 { 3580 u32 data, addr; 3581 3582 writel(0, SAR_REG_DR0); 3583 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3584 3585 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3586 writel(ATM_POISON, SAR_REG_DR0); 3587 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3588 3589 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3590 data = readl(SAR_REG_DR0); 3591 3592 if (data != 0) 3593 break; 3594 } 3595 3596 return addr * sizeof(u32); 3597 } 3598 3599 static int idt77252_init_one(struct pci_dev *pcidev, 3600 const struct pci_device_id *id) 3601 { 3602 static struct idt77252_dev **last = &idt77252_chain; 3603 static int index = 0; 3604 3605 unsigned long membase, srambase; 3606 struct idt77252_dev *card; 3607 struct atm_dev *dev; 3608 int i, err; 3609 3610 3611 if ((err = pci_enable_device(pcidev))) { 3612 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3613 return err; 3614 } 3615 3616 if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) { 3617 printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev)); 3618 return err; 3619 } 3620 3621 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3622 if (!card) { 3623 printk("idt77252-%d: can't allocate private data\n", index); 3624 err = -ENOMEM; 3625 goto err_out_disable_pdev; 3626 } 3627 card->revision = pcidev->revision; 3628 card->index = index; 3629 card->pcidev = pcidev; 3630 sprintf(card->name, "idt77252-%d", card->index); 3631 3632 INIT_WORK(&card->tqueue, idt77252_softint); 3633 3634 membase = pci_resource_start(pcidev, 1); 3635 srambase = pci_resource_start(pcidev, 2); 3636 3637 mutex_init(&card->mutex); 3638 spin_lock_init(&card->cmd_lock); 3639 spin_lock_init(&card->tst_lock); 3640 3641 init_timer(&card->tst_timer); 3642 card->tst_timer.data = (unsigned long)card; 3643 card->tst_timer.function = tst_timer; 3644 3645 /* Do the I/O remapping... */ 3646 card->membase = ioremap(membase, 1024); 3647 if (!card->membase) { 3648 printk("%s: can't ioremap() membase\n", card->name); 3649 err = -EIO; 3650 goto err_out_free_card; 3651 } 3652 3653 if (idt77252_preset(card)) { 3654 printk("%s: preset failed\n", card->name); 3655 err = -EIO; 3656 goto err_out_iounmap; 3657 } 3658 3659 dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1, 3660 NULL); 3661 if (!dev) { 3662 printk("%s: can't register atm device\n", card->name); 3663 err = -EIO; 3664 goto err_out_iounmap; 3665 } 3666 dev->dev_data = card; 3667 card->atmdev = dev; 3668 3669 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3670 suni_init(dev); 3671 if (!dev->phy) { 3672 printk("%s: can't init SUNI\n", card->name); 3673 err = -EIO; 3674 goto err_out_deinit_card; 3675 } 3676 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3677 3678 card->sramsize = probe_sram(card); 3679 3680 for (i = 0; i < 4; i++) { 3681 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3682 if (!card->fbq[i]) { 3683 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3684 err = -EIO; 3685 goto err_out_deinit_card; 3686 } 3687 } 3688 3689 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3690 card->name, ((card->revision > 1) && (card->revision < 25)) ? 3691 'A' + card->revision - 1 : '?', membase, srambase, 3692 card->sramsize / 1024); 3693 3694 if (init_card(dev)) { 3695 printk("%s: init_card failed\n", card->name); 3696 err = -EIO; 3697 goto err_out_deinit_card; 3698 } 3699 3700 dev->ci_range.vpi_bits = card->vpibits; 3701 dev->ci_range.vci_bits = card->vcibits; 3702 dev->link_rate = card->link_pcr; 3703 3704 if (dev->phy->start) 3705 dev->phy->start(dev); 3706 3707 if (idt77252_dev_open(card)) { 3708 printk("%s: dev_open failed\n", card->name); 3709 err = -EIO; 3710 goto err_out_stop; 3711 } 3712 3713 *last = card; 3714 last = &card->next; 3715 index++; 3716 3717 return 0; 3718 3719 err_out_stop: 3720 if (dev->phy->stop) 3721 dev->phy->stop(dev); 3722 3723 err_out_deinit_card: 3724 deinit_card(card); 3725 3726 err_out_iounmap: 3727 iounmap(card->membase); 3728 3729 err_out_free_card: 3730 kfree(card); 3731 3732 err_out_disable_pdev: 3733 pci_disable_device(pcidev); 3734 return err; 3735 } 3736 3737 static struct pci_device_id idt77252_pci_tbl[] = 3738 { 3739 { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 }, 3740 { 0, } 3741 }; 3742 3743 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3744 3745 static struct pci_driver idt77252_driver = { 3746 .name = "idt77252", 3747 .id_table = idt77252_pci_tbl, 3748 .probe = idt77252_init_one, 3749 }; 3750 3751 static int __init idt77252_init(void) 3752 { 3753 struct sk_buff *skb; 3754 3755 printk("%s: at %p\n", __func__, idt77252_init); 3756 3757 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3758 sizeof(struct idt77252_skb_prv)) { 3759 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3760 __func__, (unsigned long) sizeof(skb->cb), 3761 (unsigned long) sizeof(struct atm_skb_data) + 3762 sizeof(struct idt77252_skb_prv)); 3763 return -EIO; 3764 } 3765 3766 return pci_register_driver(&idt77252_driver); 3767 } 3768 3769 static void __exit idt77252_exit(void) 3770 { 3771 struct idt77252_dev *card; 3772 struct atm_dev *dev; 3773 3774 pci_unregister_driver(&idt77252_driver); 3775 3776 while (idt77252_chain) { 3777 card = idt77252_chain; 3778 dev = card->atmdev; 3779 idt77252_chain = card->next; 3780 3781 if (dev->phy->stop) 3782 dev->phy->stop(dev); 3783 deinit_card(card); 3784 pci_disable_device(card->pcidev); 3785 kfree(card); 3786 } 3787 3788 DIPRINTK("idt77252: finished cleanup-module().\n"); 3789 } 3790 3791 module_init(idt77252_init); 3792 module_exit(idt77252_exit); 3793 3794 MODULE_LICENSE("GPL"); 3795 3796 module_param(vpibits, uint, 0); 3797 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3798 #ifdef CONFIG_ATM_IDT77252_DEBUG 3799 module_param(debug, ulong, 0644); 3800 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3801 #endif 3802 3803 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3804 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3805