1 /******************************************************************* 2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $" 3 * 4 * $Author: ecd $ 5 * $Date: 2001/11/11 08:13:54 $ 6 * 7 * Copyright (c) 2000 ATecoM GmbH 8 * 9 * The author may be reached at ecd@atecom.com. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * You should have received a copy of the GNU General Public License along 28 * with this program; if not, write to the Free Software Foundation, Inc., 29 * 675 Mass Ave, Cambridge, MA 02139, USA. 30 * 31 *******************************************************************/ 32 static char const rcsid[] = 33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"; 34 35 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/poison.h> 39 #include <linux/skbuff.h> 40 #include <linux/kernel.h> 41 #include <linux/vmalloc.h> 42 #include <linux/netdevice.h> 43 #include <linux/atmdev.h> 44 #include <linux/atm.h> 45 #include <linux/delay.h> 46 #include <linux/init.h> 47 #include <linux/bitops.h> 48 #include <linux/wait.h> 49 #include <linux/jiffies.h> 50 #include <asm/semaphore.h> 51 #include <asm/io.h> 52 #include <asm/uaccess.h> 53 #include <asm/atomic.h> 54 #include <asm/byteorder.h> 55 56 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 57 #include "suni.h" 58 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 59 60 61 #include "idt77252.h" 62 #include "idt77252_tables.h" 63 64 static unsigned int vpibits = 1; 65 66 67 #define CONFIG_ATM_IDT77252_SEND_IDLE 1 68 69 70 /* 71 * Debug HACKs. 72 */ 73 #define DEBUG_MODULE 1 74 #undef HAVE_EEPROM /* does not work, yet. */ 75 76 #ifdef CONFIG_ATM_IDT77252_DEBUG 77 static unsigned long debug = DBG_GENERAL; 78 #endif 79 80 81 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) 82 83 84 /* 85 * SCQ Handling. 86 */ 87 static struct scq_info *alloc_scq(struct idt77252_dev *, int); 88 static void free_scq(struct idt77252_dev *, struct scq_info *); 89 static int queue_skb(struct idt77252_dev *, struct vc_map *, 90 struct sk_buff *, int oam); 91 static void drain_scq(struct idt77252_dev *, struct vc_map *); 92 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); 93 static void fill_scd(struct idt77252_dev *, struct scq_info *, int); 94 95 /* 96 * FBQ Handling. 97 */ 98 static int push_rx_skb(struct idt77252_dev *, 99 struct sk_buff *, int queue); 100 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); 101 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); 102 static void recycle_rx_pool_skb(struct idt77252_dev *, 103 struct rx_pool *); 104 static void add_rx_skb(struct idt77252_dev *, int queue, 105 unsigned int size, unsigned int count); 106 107 /* 108 * RSQ Handling. 109 */ 110 static int init_rsq(struct idt77252_dev *); 111 static void deinit_rsq(struct idt77252_dev *); 112 static void idt77252_rx(struct idt77252_dev *); 113 114 /* 115 * TSQ handling. 116 */ 117 static int init_tsq(struct idt77252_dev *); 118 static void deinit_tsq(struct idt77252_dev *); 119 static void idt77252_tx(struct idt77252_dev *); 120 121 122 /* 123 * ATM Interface. 124 */ 125 static void idt77252_dev_close(struct atm_dev *dev); 126 static int idt77252_open(struct atm_vcc *vcc); 127 static void idt77252_close(struct atm_vcc *vcc); 128 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); 129 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, 130 int flags); 131 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, 132 unsigned long addr); 133 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); 134 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, 135 int flags); 136 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, 137 char *page); 138 static void idt77252_softint(struct work_struct *work); 139 140 141 static struct atmdev_ops idt77252_ops = 142 { 143 .dev_close = idt77252_dev_close, 144 .open = idt77252_open, 145 .close = idt77252_close, 146 .send = idt77252_send, 147 .send_oam = idt77252_send_oam, 148 .phy_put = idt77252_phy_put, 149 .phy_get = idt77252_phy_get, 150 .change_qos = idt77252_change_qos, 151 .proc_read = idt77252_proc_read, 152 .owner = THIS_MODULE 153 }; 154 155 static struct idt77252_dev *idt77252_chain = NULL; 156 static unsigned int idt77252_sram_write_errors = 0; 157 158 /*****************************************************************************/ 159 /* */ 160 /* I/O and Utility Bus */ 161 /* */ 162 /*****************************************************************************/ 163 164 static void 165 waitfor_idle(struct idt77252_dev *card) 166 { 167 u32 stat; 168 169 stat = readl(SAR_REG_STAT); 170 while (stat & SAR_STAT_CMDBZ) 171 stat = readl(SAR_REG_STAT); 172 } 173 174 static u32 175 read_sram(struct idt77252_dev *card, unsigned long addr) 176 { 177 unsigned long flags; 178 u32 value; 179 180 spin_lock_irqsave(&card->cmd_lock, flags); 181 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); 182 waitfor_idle(card); 183 value = readl(SAR_REG_DR0); 184 spin_unlock_irqrestore(&card->cmd_lock, flags); 185 return value; 186 } 187 188 static void 189 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) 190 { 191 unsigned long flags; 192 193 if ((idt77252_sram_write_errors == 0) && 194 (((addr > card->tst[0] + card->tst_size - 2) && 195 (addr < card->tst[0] + card->tst_size)) || 196 ((addr > card->tst[1] + card->tst_size - 2) && 197 (addr < card->tst[1] + card->tst_size)))) { 198 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", 199 card->name, addr, value); 200 } 201 202 spin_lock_irqsave(&card->cmd_lock, flags); 203 writel(value, SAR_REG_DR0); 204 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 205 waitfor_idle(card); 206 spin_unlock_irqrestore(&card->cmd_lock, flags); 207 } 208 209 static u8 210 read_utility(void *dev, unsigned long ubus_addr) 211 { 212 struct idt77252_dev *card = dev; 213 unsigned long flags; 214 u8 value; 215 216 if (!card) { 217 printk("Error: No such device.\n"); 218 return -1; 219 } 220 221 spin_lock_irqsave(&card->cmd_lock, flags); 222 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); 223 waitfor_idle(card); 224 value = readl(SAR_REG_DR0); 225 spin_unlock_irqrestore(&card->cmd_lock, flags); 226 return value; 227 } 228 229 static void 230 write_utility(void *dev, unsigned long ubus_addr, u8 value) 231 { 232 struct idt77252_dev *card = dev; 233 unsigned long flags; 234 235 if (!card) { 236 printk("Error: No such device.\n"); 237 return; 238 } 239 240 spin_lock_irqsave(&card->cmd_lock, flags); 241 writel((u32) value, SAR_REG_DR0); 242 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); 243 waitfor_idle(card); 244 spin_unlock_irqrestore(&card->cmd_lock, flags); 245 } 246 247 #ifdef HAVE_EEPROM 248 static u32 rdsrtab[] = 249 { 250 SAR_GP_EECS | SAR_GP_EESCLK, 251 0, 252 SAR_GP_EESCLK, /* 0 */ 253 0, 254 SAR_GP_EESCLK, /* 0 */ 255 0, 256 SAR_GP_EESCLK, /* 0 */ 257 0, 258 SAR_GP_EESCLK, /* 0 */ 259 0, 260 SAR_GP_EESCLK, /* 0 */ 261 SAR_GP_EEDO, 262 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 263 0, 264 SAR_GP_EESCLK, /* 0 */ 265 SAR_GP_EEDO, 266 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 267 }; 268 269 static u32 wrentab[] = 270 { 271 SAR_GP_EECS | SAR_GP_EESCLK, 272 0, 273 SAR_GP_EESCLK, /* 0 */ 274 0, 275 SAR_GP_EESCLK, /* 0 */ 276 0, 277 SAR_GP_EESCLK, /* 0 */ 278 0, 279 SAR_GP_EESCLK, /* 0 */ 280 SAR_GP_EEDO, 281 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 282 SAR_GP_EEDO, 283 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 284 0, 285 SAR_GP_EESCLK, /* 0 */ 286 0, 287 SAR_GP_EESCLK /* 0 */ 288 }; 289 290 static u32 rdtab[] = 291 { 292 SAR_GP_EECS | SAR_GP_EESCLK, 293 0, 294 SAR_GP_EESCLK, /* 0 */ 295 0, 296 SAR_GP_EESCLK, /* 0 */ 297 0, 298 SAR_GP_EESCLK, /* 0 */ 299 0, 300 SAR_GP_EESCLK, /* 0 */ 301 0, 302 SAR_GP_EESCLK, /* 0 */ 303 0, 304 SAR_GP_EESCLK, /* 0 */ 305 SAR_GP_EEDO, 306 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 307 SAR_GP_EEDO, 308 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ 309 }; 310 311 static u32 wrtab[] = 312 { 313 SAR_GP_EECS | SAR_GP_EESCLK, 314 0, 315 SAR_GP_EESCLK, /* 0 */ 316 0, 317 SAR_GP_EESCLK, /* 0 */ 318 0, 319 SAR_GP_EESCLK, /* 0 */ 320 0, 321 SAR_GP_EESCLK, /* 0 */ 322 0, 323 SAR_GP_EESCLK, /* 0 */ 324 0, 325 SAR_GP_EESCLK, /* 0 */ 326 SAR_GP_EEDO, 327 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ 328 0, 329 SAR_GP_EESCLK /* 0 */ 330 }; 331 332 static u32 clktab[] = 333 { 334 0, 335 SAR_GP_EESCLK, 336 0, 337 SAR_GP_EESCLK, 338 0, 339 SAR_GP_EESCLK, 340 0, 341 SAR_GP_EESCLK, 342 0, 343 SAR_GP_EESCLK, 344 0, 345 SAR_GP_EESCLK, 346 0, 347 SAR_GP_EESCLK, 348 0, 349 SAR_GP_EESCLK, 350 0 351 }; 352 353 static u32 354 idt77252_read_gp(struct idt77252_dev *card) 355 { 356 u32 gp; 357 358 gp = readl(SAR_REG_GP); 359 #if 0 360 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); 361 #endif 362 return gp; 363 } 364 365 static void 366 idt77252_write_gp(struct idt77252_dev *card, u32 value) 367 { 368 unsigned long flags; 369 370 #if 0 371 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", 372 value & SAR_GP_EESCLK ? "HIGH" : "LOW ", 373 value & SAR_GP_EEDO ? "1" : "0"); 374 #endif 375 376 spin_lock_irqsave(&card->cmd_lock, flags); 377 waitfor_idle(card); 378 writel(value, SAR_REG_GP); 379 spin_unlock_irqrestore(&card->cmd_lock, flags); 380 } 381 382 static u8 383 idt77252_eeprom_read_status(struct idt77252_dev *card) 384 { 385 u8 byte; 386 u32 gp; 387 int i, j; 388 389 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 390 391 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { 392 idt77252_write_gp(card, gp | rdsrtab[i]); 393 udelay(5); 394 } 395 idt77252_write_gp(card, gp | SAR_GP_EECS); 396 udelay(5); 397 398 byte = 0; 399 for (i = 0, j = 0; i < 8; i++) { 400 byte <<= 1; 401 402 idt77252_write_gp(card, gp | clktab[j++]); 403 udelay(5); 404 405 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 406 407 idt77252_write_gp(card, gp | clktab[j++]); 408 udelay(5); 409 } 410 idt77252_write_gp(card, gp | SAR_GP_EECS); 411 udelay(5); 412 413 return byte; 414 } 415 416 static u8 417 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) 418 { 419 u8 byte; 420 u32 gp; 421 int i, j; 422 423 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 424 425 for (i = 0; i < ARRAY_SIZE(rdtab); i++) { 426 idt77252_write_gp(card, gp | rdtab[i]); 427 udelay(5); 428 } 429 idt77252_write_gp(card, gp | SAR_GP_EECS); 430 udelay(5); 431 432 for (i = 0, j = 0; i < 8; i++) { 433 idt77252_write_gp(card, gp | clktab[j++] | 434 (offset & 1 ? SAR_GP_EEDO : 0)); 435 udelay(5); 436 437 idt77252_write_gp(card, gp | clktab[j++] | 438 (offset & 1 ? SAR_GP_EEDO : 0)); 439 udelay(5); 440 441 offset >>= 1; 442 } 443 idt77252_write_gp(card, gp | SAR_GP_EECS); 444 udelay(5); 445 446 byte = 0; 447 for (i = 0, j = 0; i < 8; i++) { 448 byte <<= 1; 449 450 idt77252_write_gp(card, gp | clktab[j++]); 451 udelay(5); 452 453 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; 454 455 idt77252_write_gp(card, gp | clktab[j++]); 456 udelay(5); 457 } 458 idt77252_write_gp(card, gp | SAR_GP_EECS); 459 udelay(5); 460 461 return byte; 462 } 463 464 static void 465 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) 466 { 467 u32 gp; 468 int i, j; 469 470 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 471 472 for (i = 0; i < ARRAY_SIZE(wrentab); i++) { 473 idt77252_write_gp(card, gp | wrentab[i]); 474 udelay(5); 475 } 476 idt77252_write_gp(card, gp | SAR_GP_EECS); 477 udelay(5); 478 479 for (i = 0; i < ARRAY_SIZE(wrtab); i++) { 480 idt77252_write_gp(card, gp | wrtab[i]); 481 udelay(5); 482 } 483 idt77252_write_gp(card, gp | SAR_GP_EECS); 484 udelay(5); 485 486 for (i = 0, j = 0; i < 8; i++) { 487 idt77252_write_gp(card, gp | clktab[j++] | 488 (offset & 1 ? SAR_GP_EEDO : 0)); 489 udelay(5); 490 491 idt77252_write_gp(card, gp | clktab[j++] | 492 (offset & 1 ? SAR_GP_EEDO : 0)); 493 udelay(5); 494 495 offset >>= 1; 496 } 497 idt77252_write_gp(card, gp | SAR_GP_EECS); 498 udelay(5); 499 500 for (i = 0, j = 0; i < 8; i++) { 501 idt77252_write_gp(card, gp | clktab[j++] | 502 (data & 1 ? SAR_GP_EEDO : 0)); 503 udelay(5); 504 505 idt77252_write_gp(card, gp | clktab[j++] | 506 (data & 1 ? SAR_GP_EEDO : 0)); 507 udelay(5); 508 509 data >>= 1; 510 } 511 idt77252_write_gp(card, gp | SAR_GP_EECS); 512 udelay(5); 513 } 514 515 static void 516 idt77252_eeprom_init(struct idt77252_dev *card) 517 { 518 u32 gp; 519 520 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); 521 522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 523 udelay(5); 524 idt77252_write_gp(card, gp | SAR_GP_EECS); 525 udelay(5); 526 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); 527 udelay(5); 528 idt77252_write_gp(card, gp | SAR_GP_EECS); 529 udelay(5); 530 } 531 #endif /* HAVE_EEPROM */ 532 533 534 #ifdef CONFIG_ATM_IDT77252_DEBUG 535 static void 536 dump_tct(struct idt77252_dev *card, int index) 537 { 538 unsigned long tct; 539 int i; 540 541 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); 542 543 printk("%s: TCT %x:", card->name, index); 544 for (i = 0; i < 8; i++) { 545 printk(" %08x", read_sram(card, tct + i)); 546 } 547 printk("\n"); 548 } 549 550 static void 551 idt77252_tx_dump(struct idt77252_dev *card) 552 { 553 struct atm_vcc *vcc; 554 struct vc_map *vc; 555 int i; 556 557 printk("%s\n", __FUNCTION__); 558 for (i = 0; i < card->tct_size; i++) { 559 vc = card->vcs[i]; 560 if (!vc) 561 continue; 562 563 vcc = NULL; 564 if (vc->rx_vcc) 565 vcc = vc->rx_vcc; 566 else if (vc->tx_vcc) 567 vcc = vc->tx_vcc; 568 569 if (!vcc) 570 continue; 571 572 printk("%s: Connection %d:\n", card->name, vc->index); 573 dump_tct(card, vc->index); 574 } 575 } 576 #endif 577 578 579 /*****************************************************************************/ 580 /* */ 581 /* SCQ Handling */ 582 /* */ 583 /*****************************************************************************/ 584 585 static int 586 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) 587 { 588 struct sb_pool *pool = &card->sbpool[queue]; 589 int index; 590 591 index = pool->index; 592 while (pool->skb[index]) { 593 index = (index + 1) & FBQ_MASK; 594 if (index == pool->index) 595 return -ENOBUFS; 596 } 597 598 pool->skb[index] = skb; 599 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); 600 601 pool->index = (index + 1) & FBQ_MASK; 602 return 0; 603 } 604 605 static void 606 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) 607 { 608 unsigned int queue, index; 609 u32 handle; 610 611 handle = IDT77252_PRV_POOL(skb); 612 613 queue = POOL_QUEUE(handle); 614 if (queue > 3) 615 return; 616 617 index = POOL_INDEX(handle); 618 if (index > FBQ_SIZE - 1) 619 return; 620 621 card->sbpool[queue].skb[index] = NULL; 622 } 623 624 static struct sk_buff * 625 sb_pool_skb(struct idt77252_dev *card, u32 handle) 626 { 627 unsigned int queue, index; 628 629 queue = POOL_QUEUE(handle); 630 if (queue > 3) 631 return NULL; 632 633 index = POOL_INDEX(handle); 634 if (index > FBQ_SIZE - 1) 635 return NULL; 636 637 return card->sbpool[queue].skb[index]; 638 } 639 640 static struct scq_info * 641 alloc_scq(struct idt77252_dev *card, int class) 642 { 643 struct scq_info *scq; 644 645 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); 646 if (!scq) 647 return NULL; 648 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE, 649 &scq->paddr); 650 if (scq->base == NULL) { 651 kfree(scq); 652 return NULL; 653 } 654 memset(scq->base, 0, SCQ_SIZE); 655 656 scq->next = scq->base; 657 scq->last = scq->base + (SCQ_ENTRIES - 1); 658 atomic_set(&scq->used, 0); 659 660 spin_lock_init(&scq->lock); 661 spin_lock_init(&scq->skblock); 662 663 skb_queue_head_init(&scq->transmit); 664 skb_queue_head_init(&scq->pending); 665 666 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", 667 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); 668 669 return scq; 670 } 671 672 static void 673 free_scq(struct idt77252_dev *card, struct scq_info *scq) 674 { 675 struct sk_buff *skb; 676 struct atm_vcc *vcc; 677 678 pci_free_consistent(card->pcidev, SCQ_SIZE, 679 scq->base, scq->paddr); 680 681 while ((skb = skb_dequeue(&scq->transmit))) { 682 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 683 skb->len, PCI_DMA_TODEVICE); 684 685 vcc = ATM_SKB(skb)->vcc; 686 if (vcc->pop) 687 vcc->pop(vcc, skb); 688 else 689 dev_kfree_skb(skb); 690 } 691 692 while ((skb = skb_dequeue(&scq->pending))) { 693 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 694 skb->len, PCI_DMA_TODEVICE); 695 696 vcc = ATM_SKB(skb)->vcc; 697 if (vcc->pop) 698 vcc->pop(vcc, skb); 699 else 700 dev_kfree_skb(skb); 701 } 702 703 kfree(scq); 704 } 705 706 707 static int 708 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) 709 { 710 struct scq_info *scq = vc->scq; 711 unsigned long flags; 712 struct scqe *tbd; 713 int entries; 714 715 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); 716 717 atomic_inc(&scq->used); 718 entries = atomic_read(&scq->used); 719 if (entries > (SCQ_ENTRIES - 1)) { 720 atomic_dec(&scq->used); 721 goto out; 722 } 723 724 skb_queue_tail(&scq->transmit, skb); 725 726 spin_lock_irqsave(&vc->lock, flags); 727 if (vc->estimator) { 728 struct atm_vcc *vcc = vc->tx_vcc; 729 struct sock *sk = sk_atm(vcc); 730 731 vc->estimator->cells += (skb->len + 47) / 48; 732 if (atomic_read(&sk->sk_wmem_alloc) > 733 (sk->sk_sndbuf >> 1)) { 734 u32 cps = vc->estimator->maxcps; 735 736 vc->estimator->cps = cps; 737 vc->estimator->avcps = cps << 5; 738 if (vc->lacr < vc->init_er) { 739 vc->lacr = vc->init_er; 740 writel(TCMDQ_LACR | (vc->lacr << 16) | 741 vc->index, SAR_REG_TCMDQ); 742 } 743 } 744 } 745 spin_unlock_irqrestore(&vc->lock, flags); 746 747 tbd = &IDT77252_PRV_TBD(skb); 748 749 spin_lock_irqsave(&scq->lock, flags); 750 scq->next->word_1 = cpu_to_le32(tbd->word_1 | 751 SAR_TBD_TSIF | SAR_TBD_GTSI); 752 scq->next->word_2 = cpu_to_le32(tbd->word_2); 753 scq->next->word_3 = cpu_to_le32(tbd->word_3); 754 scq->next->word_4 = cpu_to_le32(tbd->word_4); 755 756 if (scq->next == scq->last) 757 scq->next = scq->base; 758 else 759 scq->next++; 760 761 write_sram(card, scq->scd, 762 scq->paddr + 763 (u32)((unsigned long)scq->next - (unsigned long)scq->base)); 764 spin_unlock_irqrestore(&scq->lock, flags); 765 766 scq->trans_start = jiffies; 767 768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { 769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, 770 SAR_REG_TCMDQ); 771 } 772 773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); 774 775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", 776 card->name, atomic_read(&scq->used), 777 read_sram(card, scq->scd + 1), scq->next); 778 779 return 0; 780 781 out: 782 if (time_after(jiffies, scq->trans_start + HZ)) { 783 printk("%s: Error pushing TBD for %d.%d\n", 784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); 785 #ifdef CONFIG_ATM_IDT77252_DEBUG 786 idt77252_tx_dump(card); 787 #endif 788 scq->trans_start = jiffies; 789 } 790 791 return -ENOBUFS; 792 } 793 794 795 static void 796 drain_scq(struct idt77252_dev *card, struct vc_map *vc) 797 { 798 struct scq_info *scq = vc->scq; 799 struct sk_buff *skb; 800 struct atm_vcc *vcc; 801 802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", 803 card->name, atomic_read(&scq->used), scq->next); 804 805 skb = skb_dequeue(&scq->transmit); 806 if (skb) { 807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); 808 809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 810 skb->len, PCI_DMA_TODEVICE); 811 812 vcc = ATM_SKB(skb)->vcc; 813 814 if (vcc->pop) 815 vcc->pop(vcc, skb); 816 else 817 dev_kfree_skb(skb); 818 819 atomic_inc(&vcc->stats->tx); 820 } 821 822 atomic_dec(&scq->used); 823 824 spin_lock(&scq->skblock); 825 while ((skb = skb_dequeue(&scq->pending))) { 826 if (push_on_scq(card, vc, skb)) { 827 skb_queue_head(&vc->scq->pending, skb); 828 break; 829 } 830 } 831 spin_unlock(&scq->skblock); 832 } 833 834 static int 835 queue_skb(struct idt77252_dev *card, struct vc_map *vc, 836 struct sk_buff *skb, int oam) 837 { 838 struct atm_vcc *vcc; 839 struct scqe *tbd; 840 unsigned long flags; 841 int error; 842 int aal; 843 844 if (skb->len == 0) { 845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len); 846 return -EINVAL; 847 } 848 849 TXPRINTK("%s: Sending %d bytes of data.\n", 850 card->name, skb->len); 851 852 tbd = &IDT77252_PRV_TBD(skb); 853 vcc = ATM_SKB(skb)->vcc; 854 855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data, 856 skb->len, PCI_DMA_TODEVICE); 857 858 error = -EINVAL; 859 860 if (oam) { 861 if (skb->len != 52) 862 goto errout; 863 864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; 865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 866 tbd->word_3 = 0x00000000; 867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 868 (skb->data[2] << 8) | (skb->data[3] << 0); 869 870 if (test_bit(VCF_RSV, &vc->flags)) 871 vc = card->vcs[0]; 872 873 goto done; 874 } 875 876 if (test_bit(VCF_RSV, &vc->flags)) { 877 printk("%s: Trying to transmit on reserved VC\n", card->name); 878 goto errout; 879 } 880 881 aal = vcc->qos.aal; 882 883 switch (aal) { 884 case ATM_AAL0: 885 case ATM_AAL34: 886 if (skb->len > 52) 887 goto errout; 888 889 if (aal == ATM_AAL0) 890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | 891 ATM_CELL_PAYLOAD; 892 else 893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | 894 ATM_CELL_PAYLOAD; 895 896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; 897 tbd->word_3 = 0x00000000; 898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) | 899 (skb->data[2] << 8) | (skb->data[3] << 0); 900 break; 901 902 case ATM_AAL5: 903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; 904 tbd->word_2 = IDT77252_PRV_PADDR(skb); 905 tbd->word_3 = skb->len; 906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | 907 (vcc->vci << SAR_TBD_VCI_SHIFT); 908 break; 909 910 case ATM_AAL1: 911 case ATM_AAL2: 912 default: 913 printk("%s: Traffic type not supported.\n", card->name); 914 error = -EPROTONOSUPPORT; 915 goto errout; 916 } 917 918 done: 919 spin_lock_irqsave(&vc->scq->skblock, flags); 920 skb_queue_tail(&vc->scq->pending, skb); 921 922 while ((skb = skb_dequeue(&vc->scq->pending))) { 923 if (push_on_scq(card, vc, skb)) { 924 skb_queue_head(&vc->scq->pending, skb); 925 break; 926 } 927 } 928 spin_unlock_irqrestore(&vc->scq->skblock, flags); 929 930 return 0; 931 932 errout: 933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 934 skb->len, PCI_DMA_TODEVICE); 935 return error; 936 } 937 938 static unsigned long 939 get_free_scd(struct idt77252_dev *card, struct vc_map *vc) 940 { 941 int i; 942 943 for (i = 0; i < card->scd_size; i++) { 944 if (!card->scd2vc[i]) { 945 card->scd2vc[i] = vc; 946 vc->scd_index = i; 947 return card->scd_base + i * SAR_SRAM_SCD_SIZE; 948 } 949 } 950 return 0; 951 } 952 953 static void 954 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 955 { 956 write_sram(card, scq->scd, scq->paddr); 957 write_sram(card, scq->scd + 1, 0x00000000); 958 write_sram(card, scq->scd + 2, 0xffffffff); 959 write_sram(card, scq->scd + 3, 0x00000000); 960 } 961 962 static void 963 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) 964 { 965 return; 966 } 967 968 /*****************************************************************************/ 969 /* */ 970 /* RSQ Handling */ 971 /* */ 972 /*****************************************************************************/ 973 974 static int 975 init_rsq(struct idt77252_dev *card) 976 { 977 struct rsq_entry *rsqe; 978 979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 980 &card->rsq.paddr); 981 if (card->rsq.base == NULL) { 982 printk("%s: can't allocate RSQ.\n", card->name); 983 return -1; 984 } 985 memset(card->rsq.base, 0, RSQSIZE); 986 987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; 988 card->rsq.next = card->rsq.last; 989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) 990 rsqe->word_4 = 0; 991 992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, 993 SAR_REG_RSQH); 994 writel(card->rsq.paddr, SAR_REG_RSQB); 995 996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, 997 (unsigned long) card->rsq.base, 998 readl(SAR_REG_RSQB)); 999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", 1000 card->name, 1001 readl(SAR_REG_RSQH), 1002 readl(SAR_REG_RSQB), 1003 readl(SAR_REG_RSQT)); 1004 1005 return 0; 1006 } 1007 1008 static void 1009 deinit_rsq(struct idt77252_dev *card) 1010 { 1011 pci_free_consistent(card->pcidev, RSQSIZE, 1012 card->rsq.base, card->rsq.paddr); 1013 } 1014 1015 static void 1016 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) 1017 { 1018 struct atm_vcc *vcc; 1019 struct sk_buff *skb; 1020 struct rx_pool *rpp; 1021 struct vc_map *vc; 1022 u32 header, vpi, vci; 1023 u32 stat; 1024 int i; 1025 1026 stat = le32_to_cpu(rsqe->word_4); 1027 1028 if (stat & SAR_RSQE_IDLE) { 1029 RXPRINTK("%s: message about inactive connection.\n", 1030 card->name); 1031 return; 1032 } 1033 1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); 1035 if (skb == NULL) { 1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", 1037 card->name, __FUNCTION__, 1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), 1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); 1040 return; 1041 } 1042 1043 header = le32_to_cpu(rsqe->word_1); 1044 vpi = (header >> 16) & 0x00ff; 1045 vci = (header >> 0) & 0xffff; 1046 1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", 1048 card->name, vpi, vci, skb, skb->data); 1049 1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { 1051 printk("%s: SDU received for out-of-range vc %u.%u\n", 1052 card->name, vpi, vci); 1053 recycle_rx_skb(card, skb); 1054 return; 1055 } 1056 1057 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1059 printk("%s: SDU received on non RX vc %u.%u\n", 1060 card->name, vpi, vci); 1061 recycle_rx_skb(card, skb); 1062 return; 1063 } 1064 1065 vcc = vc->rx_vcc; 1066 1067 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb), 1068 skb_end_pointer(skb) - skb->data, 1069 PCI_DMA_FROMDEVICE); 1070 1071 if ((vcc->qos.aal == ATM_AAL0) || 1072 (vcc->qos.aal == ATM_AAL34)) { 1073 struct sk_buff *sb; 1074 unsigned char *cell; 1075 u32 aal0; 1076 1077 cell = skb->data; 1078 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { 1079 if ((sb = dev_alloc_skb(64)) == NULL) { 1080 printk("%s: Can't allocate buffers for aal0.\n", 1081 card->name); 1082 atomic_add(i, &vcc->stats->rx_drop); 1083 break; 1084 } 1085 if (!atm_charge(vcc, sb->truesize)) { 1086 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", 1087 card->name); 1088 atomic_add(i - 1, &vcc->stats->rx_drop); 1089 dev_kfree_skb(sb); 1090 break; 1091 } 1092 aal0 = (vpi << ATM_HDR_VPI_SHIFT) | 1093 (vci << ATM_HDR_VCI_SHIFT); 1094 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; 1095 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; 1096 1097 *((u32 *) sb->data) = aal0; 1098 skb_put(sb, sizeof(u32)); 1099 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), 1100 cell, ATM_CELL_PAYLOAD); 1101 1102 ATM_SKB(sb)->vcc = vcc; 1103 __net_timestamp(sb); 1104 vcc->push(vcc, sb); 1105 atomic_inc(&vcc->stats->rx); 1106 1107 cell += ATM_CELL_PAYLOAD; 1108 } 1109 1110 recycle_rx_skb(card, skb); 1111 return; 1112 } 1113 if (vcc->qos.aal != ATM_AAL5) { 1114 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", 1115 card->name, vcc->qos.aal); 1116 recycle_rx_skb(card, skb); 1117 return; 1118 } 1119 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; 1120 1121 rpp = &vc->rcv.rx_pool; 1122 1123 rpp->len += skb->len; 1124 if (!rpp->count++) 1125 rpp->first = skb; 1126 *rpp->last = skb; 1127 rpp->last = &skb->next; 1128 1129 if (stat & SAR_RSQE_EPDU) { 1130 unsigned char *l1l2; 1131 unsigned int len; 1132 1133 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); 1134 1135 len = (l1l2[0] << 8) | l1l2[1]; 1136 len = len ? len : 0x10000; 1137 1138 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); 1139 1140 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { 1141 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " 1142 "(CDC: %08x)\n", 1143 card->name, len, rpp->len, readl(SAR_REG_CDC)); 1144 recycle_rx_pool_skb(card, rpp); 1145 atomic_inc(&vcc->stats->rx_err); 1146 return; 1147 } 1148 if (stat & SAR_RSQE_CRC) { 1149 RXPRINTK("%s: AAL5 CRC error.\n", card->name); 1150 recycle_rx_pool_skb(card, rpp); 1151 atomic_inc(&vcc->stats->rx_err); 1152 return; 1153 } 1154 if (rpp->count > 1) { 1155 struct sk_buff *sb; 1156 1157 skb = dev_alloc_skb(rpp->len); 1158 if (!skb) { 1159 RXPRINTK("%s: Can't alloc RX skb.\n", 1160 card->name); 1161 recycle_rx_pool_skb(card, rpp); 1162 atomic_inc(&vcc->stats->rx_err); 1163 return; 1164 } 1165 if (!atm_charge(vcc, skb->truesize)) { 1166 recycle_rx_pool_skb(card, rpp); 1167 dev_kfree_skb(skb); 1168 return; 1169 } 1170 sb = rpp->first; 1171 for (i = 0; i < rpp->count; i++) { 1172 memcpy(skb_put(skb, sb->len), 1173 sb->data, sb->len); 1174 sb = sb->next; 1175 } 1176 1177 recycle_rx_pool_skb(card, rpp); 1178 1179 skb_trim(skb, len); 1180 ATM_SKB(skb)->vcc = vcc; 1181 __net_timestamp(skb); 1182 1183 vcc->push(vcc, skb); 1184 atomic_inc(&vcc->stats->rx); 1185 1186 return; 1187 } 1188 1189 skb->next = NULL; 1190 flush_rx_pool(card, rpp); 1191 1192 if (!atm_charge(vcc, skb->truesize)) { 1193 recycle_rx_skb(card, skb); 1194 return; 1195 } 1196 1197 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1198 skb_end_pointer(skb) - skb->data, 1199 PCI_DMA_FROMDEVICE); 1200 sb_pool_remove(card, skb); 1201 1202 skb_trim(skb, len); 1203 ATM_SKB(skb)->vcc = vcc; 1204 __net_timestamp(skb); 1205 1206 vcc->push(vcc, skb); 1207 atomic_inc(&vcc->stats->rx); 1208 1209 if (skb->truesize > SAR_FB_SIZE_3) 1210 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); 1211 else if (skb->truesize > SAR_FB_SIZE_2) 1212 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); 1213 else if (skb->truesize > SAR_FB_SIZE_1) 1214 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); 1215 else 1216 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); 1217 return; 1218 } 1219 } 1220 1221 static void 1222 idt77252_rx(struct idt77252_dev *card) 1223 { 1224 struct rsq_entry *rsqe; 1225 1226 if (card->rsq.next == card->rsq.last) 1227 rsqe = card->rsq.base; 1228 else 1229 rsqe = card->rsq.next + 1; 1230 1231 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { 1232 RXPRINTK("%s: no entry in RSQ.\n", card->name); 1233 return; 1234 } 1235 1236 do { 1237 dequeue_rx(card, rsqe); 1238 rsqe->word_4 = 0; 1239 card->rsq.next = rsqe; 1240 if (card->rsq.next == card->rsq.last) 1241 rsqe = card->rsq.base; 1242 else 1243 rsqe = card->rsq.next + 1; 1244 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); 1245 1246 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, 1247 SAR_REG_RSQH); 1248 } 1249 1250 static void 1251 idt77252_rx_raw(struct idt77252_dev *card) 1252 { 1253 struct sk_buff *queue; 1254 u32 head, tail; 1255 struct atm_vcc *vcc; 1256 struct vc_map *vc; 1257 struct sk_buff *sb; 1258 1259 if (card->raw_cell_head == NULL) { 1260 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); 1261 card->raw_cell_head = sb_pool_skb(card, handle); 1262 } 1263 1264 queue = card->raw_cell_head; 1265 if (!queue) 1266 return; 1267 1268 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); 1269 tail = readl(SAR_REG_RAWCT); 1270 1271 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue), 1272 skb_end_pointer(queue) - queue->head - 16, 1273 PCI_DMA_FROMDEVICE); 1274 1275 while (head != tail) { 1276 unsigned int vpi, vci, pti; 1277 u32 header; 1278 1279 header = le32_to_cpu(*(u32 *) &queue->data[0]); 1280 1281 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; 1282 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; 1283 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT; 1284 1285 #ifdef CONFIG_ATM_IDT77252_DEBUG 1286 if (debug & DBG_RAW_CELL) { 1287 int i; 1288 1289 printk("%s: raw cell %x.%02x.%04x.%x.%x\n", 1290 card->name, (header >> 28) & 0x000f, 1291 (header >> 20) & 0x00ff, 1292 (header >> 4) & 0xffff, 1293 (header >> 1) & 0x0007, 1294 (header >> 0) & 0x0001); 1295 for (i = 16; i < 64; i++) 1296 printk(" %02x", queue->data[i]); 1297 printk("\n"); 1298 } 1299 #endif 1300 1301 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { 1302 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", 1303 card->name, vpi, vci); 1304 goto drop; 1305 } 1306 1307 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1308 if (!vc || !test_bit(VCF_RX, &vc->flags)) { 1309 RPRINTK("%s: SDU received on non RX vc %u.%u\n", 1310 card->name, vpi, vci); 1311 goto drop; 1312 } 1313 1314 vcc = vc->rx_vcc; 1315 1316 if (vcc->qos.aal != ATM_AAL0) { 1317 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", 1318 card->name, vpi, vci); 1319 atomic_inc(&vcc->stats->rx_drop); 1320 goto drop; 1321 } 1322 1323 if ((sb = dev_alloc_skb(64)) == NULL) { 1324 printk("%s: Can't allocate buffers for AAL0.\n", 1325 card->name); 1326 atomic_inc(&vcc->stats->rx_err); 1327 goto drop; 1328 } 1329 1330 if (!atm_charge(vcc, sb->truesize)) { 1331 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", 1332 card->name); 1333 dev_kfree_skb(sb); 1334 goto drop; 1335 } 1336 1337 *((u32 *) sb->data) = header; 1338 skb_put(sb, sizeof(u32)); 1339 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]), 1340 ATM_CELL_PAYLOAD); 1341 1342 ATM_SKB(sb)->vcc = vcc; 1343 __net_timestamp(sb); 1344 vcc->push(vcc, sb); 1345 atomic_inc(&vcc->stats->rx); 1346 1347 drop: 1348 skb_pull(queue, 64); 1349 1350 head = IDT77252_PRV_PADDR(queue) 1351 + (queue->data - queue->head - 16); 1352 1353 if (queue->len < 128) { 1354 struct sk_buff *next; 1355 u32 handle; 1356 1357 head = le32_to_cpu(*(u32 *) &queue->data[0]); 1358 handle = le32_to_cpu(*(u32 *) &queue->data[4]); 1359 1360 next = sb_pool_skb(card, handle); 1361 recycle_rx_skb(card, queue); 1362 1363 if (next) { 1364 card->raw_cell_head = next; 1365 queue = card->raw_cell_head; 1366 pci_dma_sync_single_for_cpu(card->pcidev, 1367 IDT77252_PRV_PADDR(queue), 1368 (skb_end_pointer(queue) - 1369 queue->data), 1370 PCI_DMA_FROMDEVICE); 1371 } else { 1372 card->raw_cell_head = NULL; 1373 printk("%s: raw cell queue overrun\n", 1374 card->name); 1375 break; 1376 } 1377 } 1378 } 1379 } 1380 1381 1382 /*****************************************************************************/ 1383 /* */ 1384 /* TSQ Handling */ 1385 /* */ 1386 /*****************************************************************************/ 1387 1388 static int 1389 init_tsq(struct idt77252_dev *card) 1390 { 1391 struct tsq_entry *tsqe; 1392 1393 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE, 1394 &card->tsq.paddr); 1395 if (card->tsq.base == NULL) { 1396 printk("%s: can't allocate TSQ.\n", card->name); 1397 return -1; 1398 } 1399 memset(card->tsq.base, 0, TSQSIZE); 1400 1401 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; 1402 card->tsq.next = card->tsq.last; 1403 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) 1404 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1405 1406 writel(card->tsq.paddr, SAR_REG_TSQB); 1407 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, 1408 SAR_REG_TSQH); 1409 1410 return 0; 1411 } 1412 1413 static void 1414 deinit_tsq(struct idt77252_dev *card) 1415 { 1416 pci_free_consistent(card->pcidev, TSQSIZE, 1417 card->tsq.base, card->tsq.paddr); 1418 } 1419 1420 static void 1421 idt77252_tx(struct idt77252_dev *card) 1422 { 1423 struct tsq_entry *tsqe; 1424 unsigned int vpi, vci; 1425 struct vc_map *vc; 1426 u32 conn, stat; 1427 1428 if (card->tsq.next == card->tsq.last) 1429 tsqe = card->tsq.base; 1430 else 1431 tsqe = card->tsq.next + 1; 1432 1433 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, 1434 card->tsq.base, card->tsq.next, card->tsq.last); 1435 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", 1436 readl(SAR_REG_TSQB), 1437 readl(SAR_REG_TSQT), 1438 readl(SAR_REG_TSQH)); 1439 1440 stat = le32_to_cpu(tsqe->word_2); 1441 1442 if (stat & SAR_TSQE_INVALID) 1443 return; 1444 1445 do { 1446 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, 1447 le32_to_cpu(tsqe->word_1), 1448 le32_to_cpu(tsqe->word_2)); 1449 1450 switch (stat & SAR_TSQE_TYPE) { 1451 case SAR_TSQE_TYPE_TIMER: 1452 TXPRINTK("%s: Timer RollOver detected.\n", card->name); 1453 break; 1454 1455 case SAR_TSQE_TYPE_IDLE: 1456 1457 conn = le32_to_cpu(tsqe->word_1); 1458 1459 if (SAR_TSQE_TAG(stat) == 0x10) { 1460 #ifdef NOTDEF 1461 printk("%s: Connection %d halted.\n", 1462 card->name, 1463 le32_to_cpu(tsqe->word_1) & 0x1fff); 1464 #endif 1465 break; 1466 } 1467 1468 vc = card->vcs[conn & 0x1fff]; 1469 if (!vc) { 1470 printk("%s: could not find VC from conn %d\n", 1471 card->name, conn & 0x1fff); 1472 break; 1473 } 1474 1475 printk("%s: Connection %d IDLE.\n", 1476 card->name, vc->index); 1477 1478 set_bit(VCF_IDLE, &vc->flags); 1479 break; 1480 1481 case SAR_TSQE_TYPE_TSR: 1482 1483 conn = le32_to_cpu(tsqe->word_1); 1484 1485 vc = card->vcs[conn & 0x1fff]; 1486 if (!vc) { 1487 printk("%s: no VC at index %d\n", 1488 card->name, 1489 le32_to_cpu(tsqe->word_1) & 0x1fff); 1490 break; 1491 } 1492 1493 drain_scq(card, vc); 1494 break; 1495 1496 case SAR_TSQE_TYPE_TBD_COMP: 1497 1498 conn = le32_to_cpu(tsqe->word_1); 1499 1500 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; 1501 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; 1502 1503 if (vpi >= (1 << card->vpibits) || 1504 vci >= (1 << card->vcibits)) { 1505 printk("%s: TBD complete: " 1506 "out of range VPI.VCI %u.%u\n", 1507 card->name, vpi, vci); 1508 break; 1509 } 1510 1511 vc = card->vcs[VPCI2VC(card, vpi, vci)]; 1512 if (!vc) { 1513 printk("%s: TBD complete: " 1514 "no VC at VPI.VCI %u.%u\n", 1515 card->name, vpi, vci); 1516 break; 1517 } 1518 1519 drain_scq(card, vc); 1520 break; 1521 } 1522 1523 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); 1524 1525 card->tsq.next = tsqe; 1526 if (card->tsq.next == card->tsq.last) 1527 tsqe = card->tsq.base; 1528 else 1529 tsqe = card->tsq.next + 1; 1530 1531 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, 1532 card->tsq.base, card->tsq.next, card->tsq.last); 1533 1534 stat = le32_to_cpu(tsqe->word_2); 1535 1536 } while (!(stat & SAR_TSQE_INVALID)); 1537 1538 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, 1539 SAR_REG_TSQH); 1540 1541 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", 1542 card->index, readl(SAR_REG_TSQH), 1543 readl(SAR_REG_TSQT), card->tsq.next); 1544 } 1545 1546 1547 static void 1548 tst_timer(unsigned long data) 1549 { 1550 struct idt77252_dev *card = (struct idt77252_dev *)data; 1551 unsigned long base, idle, jump; 1552 unsigned long flags; 1553 u32 pc; 1554 int e; 1555 1556 spin_lock_irqsave(&card->tst_lock, flags); 1557 1558 base = card->tst[card->tst_index]; 1559 idle = card->tst[card->tst_index ^ 1]; 1560 1561 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { 1562 jump = base + card->tst_size - 2; 1563 1564 pc = readl(SAR_REG_NOW) >> 2; 1565 if ((pc ^ idle) & ~(card->tst_size - 1)) { 1566 mod_timer(&card->tst_timer, jiffies + 1); 1567 goto out; 1568 } 1569 1570 clear_bit(TST_SWITCH_WAIT, &card->tst_state); 1571 1572 card->tst_index ^= 1; 1573 write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); 1574 1575 base = card->tst[card->tst_index]; 1576 idle = card->tst[card->tst_index ^ 1]; 1577 1578 for (e = 0; e < card->tst_size - 2; e++) { 1579 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { 1580 write_sram(card, idle + e, 1581 card->soft_tst[e].tste & TSTE_MASK); 1582 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); 1583 } 1584 } 1585 } 1586 1587 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { 1588 1589 for (e = 0; e < card->tst_size - 2; e++) { 1590 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { 1591 write_sram(card, idle + e, 1592 card->soft_tst[e].tste & TSTE_MASK); 1593 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); 1594 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1595 } 1596 } 1597 1598 jump = base + card->tst_size - 2; 1599 1600 write_sram(card, jump, TSTE_OPC_NULL); 1601 set_bit(TST_SWITCH_WAIT, &card->tst_state); 1602 1603 mod_timer(&card->tst_timer, jiffies + 1); 1604 } 1605 1606 out: 1607 spin_unlock_irqrestore(&card->tst_lock, flags); 1608 } 1609 1610 static int 1611 __fill_tst(struct idt77252_dev *card, struct vc_map *vc, 1612 int n, unsigned int opc) 1613 { 1614 unsigned long cl, avail; 1615 unsigned long idle; 1616 int e, r; 1617 u32 data; 1618 1619 avail = card->tst_size - 2; 1620 for (e = 0; e < avail; e++) { 1621 if (card->soft_tst[e].vc == NULL) 1622 break; 1623 } 1624 if (e >= avail) { 1625 printk("%s: No free TST entries found\n", card->name); 1626 return -1; 1627 } 1628 1629 NPRINTK("%s: conn %d: first TST entry at %d.\n", 1630 card->name, vc ? vc->index : -1, e); 1631 1632 r = n; 1633 cl = avail; 1634 data = opc & TSTE_OPC_MASK; 1635 if (vc && (opc != TSTE_OPC_NULL)) 1636 data = opc | vc->index; 1637 1638 idle = card->tst[card->tst_index ^ 1]; 1639 1640 /* 1641 * Fill Soft TST. 1642 */ 1643 while (r > 0) { 1644 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { 1645 if (vc) 1646 card->soft_tst[e].vc = vc; 1647 else 1648 card->soft_tst[e].vc = (void *)-1; 1649 1650 card->soft_tst[e].tste = data; 1651 if (timer_pending(&card->tst_timer)) 1652 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1653 else { 1654 write_sram(card, idle + e, data); 1655 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1656 } 1657 1658 cl -= card->tst_size; 1659 r--; 1660 } 1661 1662 if (++e == avail) 1663 e = 0; 1664 cl += n; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int 1671 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) 1672 { 1673 unsigned long flags; 1674 int res; 1675 1676 spin_lock_irqsave(&card->tst_lock, flags); 1677 1678 res = __fill_tst(card, vc, n, opc); 1679 1680 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1681 if (!timer_pending(&card->tst_timer)) 1682 mod_timer(&card->tst_timer, jiffies + 1); 1683 1684 spin_unlock_irqrestore(&card->tst_lock, flags); 1685 return res; 1686 } 1687 1688 static int 1689 __clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1690 { 1691 unsigned long idle; 1692 int e; 1693 1694 idle = card->tst[card->tst_index ^ 1]; 1695 1696 for (e = 0; e < card->tst_size - 2; e++) { 1697 if (card->soft_tst[e].vc == vc) { 1698 card->soft_tst[e].vc = NULL; 1699 1700 card->soft_tst[e].tste = TSTE_OPC_VAR; 1701 if (timer_pending(&card->tst_timer)) 1702 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; 1703 else { 1704 write_sram(card, idle + e, TSTE_OPC_VAR); 1705 card->soft_tst[e].tste |= TSTE_PUSH_IDLE; 1706 } 1707 } 1708 } 1709 1710 return 0; 1711 } 1712 1713 static int 1714 clear_tst(struct idt77252_dev *card, struct vc_map *vc) 1715 { 1716 unsigned long flags; 1717 int res; 1718 1719 spin_lock_irqsave(&card->tst_lock, flags); 1720 1721 res = __clear_tst(card, vc); 1722 1723 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1724 if (!timer_pending(&card->tst_timer)) 1725 mod_timer(&card->tst_timer, jiffies + 1); 1726 1727 spin_unlock_irqrestore(&card->tst_lock, flags); 1728 return res; 1729 } 1730 1731 static int 1732 change_tst(struct idt77252_dev *card, struct vc_map *vc, 1733 int n, unsigned int opc) 1734 { 1735 unsigned long flags; 1736 int res; 1737 1738 spin_lock_irqsave(&card->tst_lock, flags); 1739 1740 __clear_tst(card, vc); 1741 res = __fill_tst(card, vc, n, opc); 1742 1743 set_bit(TST_SWITCH_PENDING, &card->tst_state); 1744 if (!timer_pending(&card->tst_timer)) 1745 mod_timer(&card->tst_timer, jiffies + 1); 1746 1747 spin_unlock_irqrestore(&card->tst_lock, flags); 1748 return res; 1749 } 1750 1751 1752 static int 1753 set_tct(struct idt77252_dev *card, struct vc_map *vc) 1754 { 1755 unsigned long tct; 1756 1757 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); 1758 1759 switch (vc->class) { 1760 case SCHED_CBR: 1761 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1762 card->name, tct, vc->scq->scd); 1763 1764 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); 1765 write_sram(card, tct + 1, 0); 1766 write_sram(card, tct + 2, 0); 1767 write_sram(card, tct + 3, 0); 1768 write_sram(card, tct + 4, 0); 1769 write_sram(card, tct + 5, 0); 1770 write_sram(card, tct + 6, 0); 1771 write_sram(card, tct + 7, 0); 1772 break; 1773 1774 case SCHED_UBR: 1775 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", 1776 card->name, tct, vc->scq->scd); 1777 1778 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); 1779 write_sram(card, tct + 1, 0); 1780 write_sram(card, tct + 2, TCT_TSIF); 1781 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); 1782 write_sram(card, tct + 4, 0); 1783 write_sram(card, tct + 5, vc->init_er); 1784 write_sram(card, tct + 6, 0); 1785 write_sram(card, tct + 7, TCT_FLAG_UBR); 1786 break; 1787 1788 case SCHED_VBR: 1789 case SCHED_ABR: 1790 default: 1791 return -ENOSYS; 1792 } 1793 1794 return 0; 1795 } 1796 1797 /*****************************************************************************/ 1798 /* */ 1799 /* FBQ Handling */ 1800 /* */ 1801 /*****************************************************************************/ 1802 1803 static __inline__ int 1804 idt77252_fbq_level(struct idt77252_dev *card, int queue) 1805 { 1806 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f; 1807 } 1808 1809 static __inline__ int 1810 idt77252_fbq_full(struct idt77252_dev *card, int queue) 1811 { 1812 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; 1813 } 1814 1815 static int 1816 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) 1817 { 1818 unsigned long flags; 1819 u32 handle; 1820 u32 addr; 1821 1822 skb->data = skb->head; 1823 skb_reset_tail_pointer(skb); 1824 skb->len = 0; 1825 1826 skb_reserve(skb, 16); 1827 1828 switch (queue) { 1829 case 0: 1830 skb_put(skb, SAR_FB_SIZE_0); 1831 break; 1832 case 1: 1833 skb_put(skb, SAR_FB_SIZE_1); 1834 break; 1835 case 2: 1836 skb_put(skb, SAR_FB_SIZE_2); 1837 break; 1838 case 3: 1839 skb_put(skb, SAR_FB_SIZE_3); 1840 break; 1841 default: 1842 return -1; 1843 } 1844 1845 if (idt77252_fbq_full(card, queue)) 1846 return -1; 1847 1848 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); 1849 1850 handle = IDT77252_PRV_POOL(skb); 1851 addr = IDT77252_PRV_PADDR(skb); 1852 1853 spin_lock_irqsave(&card->cmd_lock, flags); 1854 writel(handle, card->fbq[queue]); 1855 writel(addr, card->fbq[queue]); 1856 spin_unlock_irqrestore(&card->cmd_lock, flags); 1857 1858 return 0; 1859 } 1860 1861 static void 1862 add_rx_skb(struct idt77252_dev *card, int queue, 1863 unsigned int size, unsigned int count) 1864 { 1865 struct sk_buff *skb; 1866 dma_addr_t paddr; 1867 u32 handle; 1868 1869 while (count--) { 1870 skb = dev_alloc_skb(size); 1871 if (!skb) 1872 return; 1873 1874 if (sb_pool_add(card, skb, queue)) { 1875 printk("%s: SB POOL full\n", __FUNCTION__); 1876 goto outfree; 1877 } 1878 1879 paddr = pci_map_single(card->pcidev, skb->data, 1880 skb_end_pointer(skb) - skb->data, 1881 PCI_DMA_FROMDEVICE); 1882 IDT77252_PRV_PADDR(skb) = paddr; 1883 1884 if (push_rx_skb(card, skb, queue)) { 1885 printk("%s: FB QUEUE full\n", __FUNCTION__); 1886 goto outunmap; 1887 } 1888 } 1889 1890 return; 1891 1892 outunmap: 1893 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1894 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE); 1895 1896 handle = IDT77252_PRV_POOL(skb); 1897 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; 1898 1899 outfree: 1900 dev_kfree_skb(skb); 1901 } 1902 1903 1904 static void 1905 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) 1906 { 1907 u32 handle = IDT77252_PRV_POOL(skb); 1908 int err; 1909 1910 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb), 1911 skb_end_pointer(skb) - skb->data, 1912 PCI_DMA_FROMDEVICE); 1913 1914 err = push_rx_skb(card, skb, POOL_QUEUE(handle)); 1915 if (err) { 1916 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb), 1917 skb_end_pointer(skb) - skb->data, 1918 PCI_DMA_FROMDEVICE); 1919 sb_pool_remove(card, skb); 1920 dev_kfree_skb(skb); 1921 } 1922 } 1923 1924 static void 1925 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) 1926 { 1927 rpp->len = 0; 1928 rpp->count = 0; 1929 rpp->first = NULL; 1930 rpp->last = &rpp->first; 1931 } 1932 1933 static void 1934 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) 1935 { 1936 struct sk_buff *skb, *next; 1937 int i; 1938 1939 skb = rpp->first; 1940 for (i = 0; i < rpp->count; i++) { 1941 next = skb->next; 1942 skb->next = NULL; 1943 recycle_rx_skb(card, skb); 1944 skb = next; 1945 } 1946 flush_rx_pool(card, rpp); 1947 } 1948 1949 /*****************************************************************************/ 1950 /* */ 1951 /* ATM Interface */ 1952 /* */ 1953 /*****************************************************************************/ 1954 1955 static void 1956 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) 1957 { 1958 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); 1959 } 1960 1961 static unsigned char 1962 idt77252_phy_get(struct atm_dev *dev, unsigned long addr) 1963 { 1964 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); 1965 } 1966 1967 static inline int 1968 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) 1969 { 1970 struct atm_dev *dev = vcc->dev; 1971 struct idt77252_dev *card = dev->dev_data; 1972 struct vc_map *vc = vcc->dev_data; 1973 int err; 1974 1975 if (vc == NULL) { 1976 printk("%s: NULL connection in send().\n", card->name); 1977 atomic_inc(&vcc->stats->tx_err); 1978 dev_kfree_skb(skb); 1979 return -EINVAL; 1980 } 1981 if (!test_bit(VCF_TX, &vc->flags)) { 1982 printk("%s: Trying to transmit on a non-tx VC.\n", card->name); 1983 atomic_inc(&vcc->stats->tx_err); 1984 dev_kfree_skb(skb); 1985 return -EINVAL; 1986 } 1987 1988 switch (vcc->qos.aal) { 1989 case ATM_AAL0: 1990 case ATM_AAL1: 1991 case ATM_AAL5: 1992 break; 1993 default: 1994 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 1995 atomic_inc(&vcc->stats->tx_err); 1996 dev_kfree_skb(skb); 1997 return -EINVAL; 1998 } 1999 2000 if (skb_shinfo(skb)->nr_frags != 0) { 2001 printk("%s: No scatter-gather yet.\n", card->name); 2002 atomic_inc(&vcc->stats->tx_err); 2003 dev_kfree_skb(skb); 2004 return -EINVAL; 2005 } 2006 ATM_SKB(skb)->vcc = vcc; 2007 2008 err = queue_skb(card, vc, skb, oam); 2009 if (err) { 2010 atomic_inc(&vcc->stats->tx_err); 2011 dev_kfree_skb(skb); 2012 return err; 2013 } 2014 2015 return 0; 2016 } 2017 2018 int 2019 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) 2020 { 2021 return idt77252_send_skb(vcc, skb, 0); 2022 } 2023 2024 static int 2025 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) 2026 { 2027 struct atm_dev *dev = vcc->dev; 2028 struct idt77252_dev *card = dev->dev_data; 2029 struct sk_buff *skb; 2030 2031 skb = dev_alloc_skb(64); 2032 if (!skb) { 2033 printk("%s: Out of memory in send_oam().\n", card->name); 2034 atomic_inc(&vcc->stats->tx_err); 2035 return -ENOMEM; 2036 } 2037 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); 2038 2039 memcpy(skb_put(skb, 52), cell, 52); 2040 2041 return idt77252_send_skb(vcc, skb, 1); 2042 } 2043 2044 static __inline__ unsigned int 2045 idt77252_fls(unsigned int x) 2046 { 2047 int r = 1; 2048 2049 if (x == 0) 2050 return 0; 2051 if (x & 0xffff0000) { 2052 x >>= 16; 2053 r += 16; 2054 } 2055 if (x & 0xff00) { 2056 x >>= 8; 2057 r += 8; 2058 } 2059 if (x & 0xf0) { 2060 x >>= 4; 2061 r += 4; 2062 } 2063 if (x & 0xc) { 2064 x >>= 2; 2065 r += 2; 2066 } 2067 if (x & 0x2) 2068 r += 1; 2069 return r; 2070 } 2071 2072 static u16 2073 idt77252_int_to_atmfp(unsigned int rate) 2074 { 2075 u16 m, e; 2076 2077 if (rate == 0) 2078 return 0; 2079 e = idt77252_fls(rate) - 1; 2080 if (e < 9) 2081 m = (rate - (1 << e)) << (9 - e); 2082 else if (e == 9) 2083 m = (rate - (1 << e)); 2084 else /* e > 9 */ 2085 m = (rate - (1 << e)) >> (e - 9); 2086 return 0x4000 | (e << 9) | m; 2087 } 2088 2089 static u8 2090 idt77252_rate_logindex(struct idt77252_dev *card, int pcr) 2091 { 2092 u16 afp; 2093 2094 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); 2095 if (pcr < 0) 2096 return rate_to_log[(afp >> 5) & 0x1ff]; 2097 return rate_to_log[((afp >> 5) + 1) & 0x1ff]; 2098 } 2099 2100 static void 2101 idt77252_est_timer(unsigned long data) 2102 { 2103 struct vc_map *vc = (struct vc_map *)data; 2104 struct idt77252_dev *card = vc->card; 2105 struct rate_estimator *est; 2106 unsigned long flags; 2107 u32 rate, cps; 2108 u64 ncells; 2109 u8 lacr; 2110 2111 spin_lock_irqsave(&vc->lock, flags); 2112 est = vc->estimator; 2113 if (!est) 2114 goto out; 2115 2116 ncells = est->cells; 2117 2118 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); 2119 est->last_cells = ncells; 2120 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; 2121 est->cps = (est->avcps + 0x1f) >> 5; 2122 2123 cps = est->cps; 2124 if (cps < (est->maxcps >> 4)) 2125 cps = est->maxcps >> 4; 2126 2127 lacr = idt77252_rate_logindex(card, cps); 2128 if (lacr > vc->max_er) 2129 lacr = vc->max_er; 2130 2131 if (lacr != vc->lacr) { 2132 vc->lacr = lacr; 2133 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); 2134 } 2135 2136 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2137 add_timer(&est->timer); 2138 2139 out: 2140 spin_unlock_irqrestore(&vc->lock, flags); 2141 } 2142 2143 static struct rate_estimator * 2144 idt77252_init_est(struct vc_map *vc, int pcr) 2145 { 2146 struct rate_estimator *est; 2147 2148 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); 2149 if (!est) 2150 return NULL; 2151 est->maxcps = pcr < 0 ? -pcr : pcr; 2152 est->cps = est->maxcps; 2153 est->avcps = est->cps << 5; 2154 2155 est->interval = 2; /* XXX: make this configurable */ 2156 est->ewma_log = 2; /* XXX: make this configurable */ 2157 init_timer(&est->timer); 2158 est->timer.data = (unsigned long)vc; 2159 est->timer.function = idt77252_est_timer; 2160 2161 est->timer.expires = jiffies + ((HZ / 4) << est->interval); 2162 add_timer(&est->timer); 2163 2164 return est; 2165 } 2166 2167 static int 2168 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, 2169 struct atm_vcc *vcc, struct atm_qos *qos) 2170 { 2171 int tst_free, tst_used, tst_entries; 2172 unsigned long tmpl, modl; 2173 int tcr, tcra; 2174 2175 if ((qos->txtp.max_pcr == 0) && 2176 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { 2177 printk("%s: trying to open a CBR VC with cell rate = 0\n", 2178 card->name); 2179 return -EINVAL; 2180 } 2181 2182 tst_used = 0; 2183 tst_free = card->tst_free; 2184 if (test_bit(VCF_TX, &vc->flags)) 2185 tst_used = vc->ntste; 2186 tst_free += tst_used; 2187 2188 tcr = atm_pcr_goal(&qos->txtp); 2189 tcra = tcr >= 0 ? tcr : -tcr; 2190 2191 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); 2192 2193 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); 2194 modl = tmpl % (unsigned long)card->utopia_pcr; 2195 2196 tst_entries = (int) (tmpl / card->utopia_pcr); 2197 if (tcr > 0) { 2198 if (modl > 0) 2199 tst_entries++; 2200 } else if (tcr == 0) { 2201 tst_entries = tst_free - SAR_TST_RESERVED; 2202 if (tst_entries <= 0) { 2203 printk("%s: no CBR bandwidth free.\n", card->name); 2204 return -ENOSR; 2205 } 2206 } 2207 2208 if (tst_entries == 0) { 2209 printk("%s: selected CBR bandwidth < granularity.\n", 2210 card->name); 2211 return -EINVAL; 2212 } 2213 2214 if (tst_entries > (tst_free - SAR_TST_RESERVED)) { 2215 printk("%s: not enough CBR bandwidth free.\n", card->name); 2216 return -ENOSR; 2217 } 2218 2219 vc->ntste = tst_entries; 2220 2221 card->tst_free = tst_free - tst_entries; 2222 if (test_bit(VCF_TX, &vc->flags)) { 2223 if (tst_used == tst_entries) 2224 return 0; 2225 2226 OPRINTK("%s: modify %d -> %d entries in TST.\n", 2227 card->name, tst_used, tst_entries); 2228 change_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2229 return 0; 2230 } 2231 2232 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); 2233 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); 2234 return 0; 2235 } 2236 2237 static int 2238 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, 2239 struct atm_vcc *vcc, struct atm_qos *qos) 2240 { 2241 unsigned long flags; 2242 int tcr; 2243 2244 spin_lock_irqsave(&vc->lock, flags); 2245 if (vc->estimator) { 2246 del_timer(&vc->estimator->timer); 2247 kfree(vc->estimator); 2248 vc->estimator = NULL; 2249 } 2250 spin_unlock_irqrestore(&vc->lock, flags); 2251 2252 tcr = atm_pcr_goal(&qos->txtp); 2253 if (tcr == 0) 2254 tcr = card->link_pcr; 2255 2256 vc->estimator = idt77252_init_est(vc, tcr); 2257 2258 vc->class = SCHED_UBR; 2259 vc->init_er = idt77252_rate_logindex(card, tcr); 2260 vc->lacr = vc->init_er; 2261 if (tcr < 0) 2262 vc->max_er = vc->init_er; 2263 else 2264 vc->max_er = 0xff; 2265 2266 return 0; 2267 } 2268 2269 static int 2270 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, 2271 struct atm_vcc *vcc, struct atm_qos *qos) 2272 { 2273 int error; 2274 2275 if (test_bit(VCF_TX, &vc->flags)) 2276 return -EBUSY; 2277 2278 switch (qos->txtp.traffic_class) { 2279 case ATM_CBR: 2280 vc->class = SCHED_CBR; 2281 break; 2282 2283 case ATM_UBR: 2284 vc->class = SCHED_UBR; 2285 break; 2286 2287 case ATM_VBR: 2288 case ATM_ABR: 2289 default: 2290 return -EPROTONOSUPPORT; 2291 } 2292 2293 vc->scq = alloc_scq(card, vc->class); 2294 if (!vc->scq) { 2295 printk("%s: can't get SCQ.\n", card->name); 2296 return -ENOMEM; 2297 } 2298 2299 vc->scq->scd = get_free_scd(card, vc); 2300 if (vc->scq->scd == 0) { 2301 printk("%s: no SCD available.\n", card->name); 2302 free_scq(card, vc->scq); 2303 return -ENOMEM; 2304 } 2305 2306 fill_scd(card, vc->scq, vc->class); 2307 2308 if (set_tct(card, vc)) { 2309 printk("%s: class %d not supported.\n", 2310 card->name, qos->txtp.traffic_class); 2311 2312 card->scd2vc[vc->scd_index] = NULL; 2313 free_scq(card, vc->scq); 2314 return -EPROTONOSUPPORT; 2315 } 2316 2317 switch (vc->class) { 2318 case SCHED_CBR: 2319 error = idt77252_init_cbr(card, vc, vcc, qos); 2320 if (error) { 2321 card->scd2vc[vc->scd_index] = NULL; 2322 free_scq(card, vc->scq); 2323 return error; 2324 } 2325 2326 clear_bit(VCF_IDLE, &vc->flags); 2327 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); 2328 break; 2329 2330 case SCHED_UBR: 2331 error = idt77252_init_ubr(card, vc, vcc, qos); 2332 if (error) { 2333 card->scd2vc[vc->scd_index] = NULL; 2334 free_scq(card, vc->scq); 2335 return error; 2336 } 2337 2338 set_bit(VCF_IDLE, &vc->flags); 2339 break; 2340 } 2341 2342 vc->tx_vcc = vcc; 2343 set_bit(VCF_TX, &vc->flags); 2344 return 0; 2345 } 2346 2347 static int 2348 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, 2349 struct atm_vcc *vcc, struct atm_qos *qos) 2350 { 2351 unsigned long flags; 2352 unsigned long addr; 2353 u32 rcte = 0; 2354 2355 if (test_bit(VCF_RX, &vc->flags)) 2356 return -EBUSY; 2357 2358 vc->rx_vcc = vcc; 2359 set_bit(VCF_RX, &vc->flags); 2360 2361 if ((vcc->vci == 3) || (vcc->vci == 4)) 2362 return 0; 2363 2364 flush_rx_pool(card, &vc->rcv.rx_pool); 2365 2366 rcte |= SAR_RCTE_CONNECTOPEN; 2367 rcte |= SAR_RCTE_RAWCELLINTEN; 2368 2369 switch (qos->aal) { 2370 case ATM_AAL0: 2371 rcte |= SAR_RCTE_RCQ; 2372 break; 2373 case ATM_AAL1: 2374 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ 2375 break; 2376 case ATM_AAL34: 2377 rcte |= SAR_RCTE_AAL34; 2378 break; 2379 case ATM_AAL5: 2380 rcte |= SAR_RCTE_AAL5; 2381 break; 2382 default: 2383 rcte |= SAR_RCTE_RCQ; 2384 break; 2385 } 2386 2387 if (qos->aal != ATM_AAL5) 2388 rcte |= SAR_RCTE_FBP_1; 2389 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) 2390 rcte |= SAR_RCTE_FBP_3; 2391 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) 2392 rcte |= SAR_RCTE_FBP_2; 2393 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) 2394 rcte |= SAR_RCTE_FBP_1; 2395 else 2396 rcte |= SAR_RCTE_FBP_01; 2397 2398 addr = card->rct_base + (vc->index << 2); 2399 2400 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); 2401 write_sram(card, addr, rcte); 2402 2403 spin_lock_irqsave(&card->cmd_lock, flags); 2404 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); 2405 waitfor_idle(card); 2406 spin_unlock_irqrestore(&card->cmd_lock, flags); 2407 2408 return 0; 2409 } 2410 2411 static int 2412 idt77252_open(struct atm_vcc *vcc) 2413 { 2414 struct atm_dev *dev = vcc->dev; 2415 struct idt77252_dev *card = dev->dev_data; 2416 struct vc_map *vc; 2417 unsigned int index; 2418 unsigned int inuse; 2419 int error; 2420 int vci = vcc->vci; 2421 short vpi = vcc->vpi; 2422 2423 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) 2424 return 0; 2425 2426 if (vpi >= (1 << card->vpibits)) { 2427 printk("%s: unsupported VPI: %d\n", card->name, vpi); 2428 return -EINVAL; 2429 } 2430 2431 if (vci >= (1 << card->vcibits)) { 2432 printk("%s: unsupported VCI: %d\n", card->name, vci); 2433 return -EINVAL; 2434 } 2435 2436 set_bit(ATM_VF_ADDR, &vcc->flags); 2437 2438 down(&card->mutex); 2439 2440 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); 2441 2442 switch (vcc->qos.aal) { 2443 case ATM_AAL0: 2444 case ATM_AAL1: 2445 case ATM_AAL5: 2446 break; 2447 default: 2448 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); 2449 up(&card->mutex); 2450 return -EPROTONOSUPPORT; 2451 } 2452 2453 index = VPCI2VC(card, vpi, vci); 2454 if (!card->vcs[index]) { 2455 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2456 if (!card->vcs[index]) { 2457 printk("%s: can't alloc vc in open()\n", card->name); 2458 up(&card->mutex); 2459 return -ENOMEM; 2460 } 2461 card->vcs[index]->card = card; 2462 card->vcs[index]->index = index; 2463 2464 spin_lock_init(&card->vcs[index]->lock); 2465 } 2466 vc = card->vcs[index]; 2467 2468 vcc->dev_data = vc; 2469 2470 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", 2471 card->name, vc->index, vcc->vpi, vcc->vci, 2472 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", 2473 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", 2474 vcc->qos.rxtp.max_sdu); 2475 2476 inuse = 0; 2477 if (vcc->qos.txtp.traffic_class != ATM_NONE && 2478 test_bit(VCF_TX, &vc->flags)) 2479 inuse = 1; 2480 if (vcc->qos.rxtp.traffic_class != ATM_NONE && 2481 test_bit(VCF_RX, &vc->flags)) 2482 inuse += 2; 2483 2484 if (inuse) { 2485 printk("%s: %s vci already in use.\n", card->name, 2486 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); 2487 up(&card->mutex); 2488 return -EADDRINUSE; 2489 } 2490 2491 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2492 error = idt77252_init_tx(card, vc, vcc, &vcc->qos); 2493 if (error) { 2494 up(&card->mutex); 2495 return error; 2496 } 2497 } 2498 2499 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2500 error = idt77252_init_rx(card, vc, vcc, &vcc->qos); 2501 if (error) { 2502 up(&card->mutex); 2503 return error; 2504 } 2505 } 2506 2507 set_bit(ATM_VF_READY, &vcc->flags); 2508 2509 up(&card->mutex); 2510 return 0; 2511 } 2512 2513 static void 2514 idt77252_close(struct atm_vcc *vcc) 2515 { 2516 struct atm_dev *dev = vcc->dev; 2517 struct idt77252_dev *card = dev->dev_data; 2518 struct vc_map *vc = vcc->dev_data; 2519 unsigned long flags; 2520 unsigned long addr; 2521 unsigned long timeout; 2522 2523 down(&card->mutex); 2524 2525 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", 2526 card->name, vc->index, vcc->vpi, vcc->vci); 2527 2528 clear_bit(ATM_VF_READY, &vcc->flags); 2529 2530 if (vcc->qos.rxtp.traffic_class != ATM_NONE) { 2531 2532 spin_lock_irqsave(&vc->lock, flags); 2533 clear_bit(VCF_RX, &vc->flags); 2534 vc->rx_vcc = NULL; 2535 spin_unlock_irqrestore(&vc->lock, flags); 2536 2537 if ((vcc->vci == 3) || (vcc->vci == 4)) 2538 goto done; 2539 2540 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2541 2542 spin_lock_irqsave(&card->cmd_lock, flags); 2543 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); 2544 waitfor_idle(card); 2545 spin_unlock_irqrestore(&card->cmd_lock, flags); 2546 2547 if (vc->rcv.rx_pool.count) { 2548 DPRINTK("%s: closing a VC with pending rx buffers.\n", 2549 card->name); 2550 2551 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2552 } 2553 } 2554 2555 done: 2556 if (vcc->qos.txtp.traffic_class != ATM_NONE) { 2557 2558 spin_lock_irqsave(&vc->lock, flags); 2559 clear_bit(VCF_TX, &vc->flags); 2560 clear_bit(VCF_IDLE, &vc->flags); 2561 clear_bit(VCF_RSV, &vc->flags); 2562 vc->tx_vcc = NULL; 2563 2564 if (vc->estimator) { 2565 del_timer(&vc->estimator->timer); 2566 kfree(vc->estimator); 2567 vc->estimator = NULL; 2568 } 2569 spin_unlock_irqrestore(&vc->lock, flags); 2570 2571 timeout = 5 * 1000; 2572 while (atomic_read(&vc->scq->used) > 0) { 2573 timeout = msleep_interruptible(timeout); 2574 if (!timeout) 2575 break; 2576 } 2577 if (!timeout) 2578 printk("%s: SCQ drain timeout: %u used\n", 2579 card->name, atomic_read(&vc->scq->used)); 2580 2581 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); 2582 clear_scd(card, vc->scq, vc->class); 2583 2584 if (vc->class == SCHED_CBR) { 2585 clear_tst(card, vc); 2586 card->tst_free += vc->ntste; 2587 vc->ntste = 0; 2588 } 2589 2590 card->scd2vc[vc->scd_index] = NULL; 2591 free_scq(card, vc->scq); 2592 } 2593 2594 up(&card->mutex); 2595 } 2596 2597 static int 2598 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) 2599 { 2600 struct atm_dev *dev = vcc->dev; 2601 struct idt77252_dev *card = dev->dev_data; 2602 struct vc_map *vc = vcc->dev_data; 2603 int error = 0; 2604 2605 down(&card->mutex); 2606 2607 if (qos->txtp.traffic_class != ATM_NONE) { 2608 if (!test_bit(VCF_TX, &vc->flags)) { 2609 error = idt77252_init_tx(card, vc, vcc, qos); 2610 if (error) 2611 goto out; 2612 } else { 2613 switch (qos->txtp.traffic_class) { 2614 case ATM_CBR: 2615 error = idt77252_init_cbr(card, vc, vcc, qos); 2616 if (error) 2617 goto out; 2618 break; 2619 2620 case ATM_UBR: 2621 error = idt77252_init_ubr(card, vc, vcc, qos); 2622 if (error) 2623 goto out; 2624 2625 if (!test_bit(VCF_IDLE, &vc->flags)) { 2626 writel(TCMDQ_LACR | (vc->lacr << 16) | 2627 vc->index, SAR_REG_TCMDQ); 2628 } 2629 break; 2630 2631 case ATM_VBR: 2632 case ATM_ABR: 2633 error = -EOPNOTSUPP; 2634 goto out; 2635 } 2636 } 2637 } 2638 2639 if ((qos->rxtp.traffic_class != ATM_NONE) && 2640 !test_bit(VCF_RX, &vc->flags)) { 2641 error = idt77252_init_rx(card, vc, vcc, qos); 2642 if (error) 2643 goto out; 2644 } 2645 2646 memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); 2647 2648 set_bit(ATM_VF_HASQOS, &vcc->flags); 2649 2650 out: 2651 up(&card->mutex); 2652 return error; 2653 } 2654 2655 static int 2656 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) 2657 { 2658 struct idt77252_dev *card = dev->dev_data; 2659 int i, left; 2660 2661 left = (int) *pos; 2662 if (!left--) 2663 return sprintf(page, "IDT77252 Interrupts:\n"); 2664 if (!left--) 2665 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); 2666 if (!left--) 2667 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); 2668 if (!left--) 2669 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); 2670 if (!left--) 2671 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); 2672 if (!left--) 2673 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); 2674 if (!left--) 2675 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); 2676 if (!left--) 2677 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); 2678 if (!left--) 2679 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); 2680 if (!left--) 2681 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); 2682 if (!left--) 2683 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); 2684 if (!left--) 2685 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); 2686 if (!left--) 2687 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); 2688 if (!left--) 2689 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); 2690 if (!left--) 2691 return sprintf(page, "IDT77252 Transmit Connection Table:\n"); 2692 2693 for (i = 0; i < card->tct_size; i++) { 2694 unsigned long tct; 2695 struct atm_vcc *vcc; 2696 struct vc_map *vc; 2697 char *p; 2698 2699 vc = card->vcs[i]; 2700 if (!vc) 2701 continue; 2702 2703 vcc = NULL; 2704 if (vc->tx_vcc) 2705 vcc = vc->tx_vcc; 2706 if (!vcc) 2707 continue; 2708 if (left--) 2709 continue; 2710 2711 p = page; 2712 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); 2713 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); 2714 2715 for (i = 0; i < 8; i++) 2716 p += sprintf(p, " %08x", read_sram(card, tct + i)); 2717 p += sprintf(p, "\n"); 2718 return p - page; 2719 } 2720 return 0; 2721 } 2722 2723 /*****************************************************************************/ 2724 /* */ 2725 /* Interrupt handler */ 2726 /* */ 2727 /*****************************************************************************/ 2728 2729 static void 2730 idt77252_collect_stat(struct idt77252_dev *card) 2731 { 2732 u32 cdc, vpec, icc; 2733 2734 cdc = readl(SAR_REG_CDC); 2735 vpec = readl(SAR_REG_VPEC); 2736 icc = readl(SAR_REG_ICC); 2737 2738 #ifdef NOTDEF 2739 printk("%s:", card->name); 2740 2741 if (cdc & 0x7f0000) { 2742 char *s = ""; 2743 2744 printk(" ["); 2745 if (cdc & (1 << 22)) { 2746 printk("%sRM ID", s); 2747 s = " | "; 2748 } 2749 if (cdc & (1 << 21)) { 2750 printk("%sCON TAB", s); 2751 s = " | "; 2752 } 2753 if (cdc & (1 << 20)) { 2754 printk("%sNO FB", s); 2755 s = " | "; 2756 } 2757 if (cdc & (1 << 19)) { 2758 printk("%sOAM CRC", s); 2759 s = " | "; 2760 } 2761 if (cdc & (1 << 18)) { 2762 printk("%sRM CRC", s); 2763 s = " | "; 2764 } 2765 if (cdc & (1 << 17)) { 2766 printk("%sRM FIFO", s); 2767 s = " | "; 2768 } 2769 if (cdc & (1 << 16)) { 2770 printk("%sRX FIFO", s); 2771 s = " | "; 2772 } 2773 printk("]"); 2774 } 2775 2776 printk(" CDC %04x, VPEC %04x, ICC: %04x\n", 2777 cdc & 0xffff, vpec & 0xffff, icc & 0xffff); 2778 #endif 2779 } 2780 2781 static irqreturn_t 2782 idt77252_interrupt(int irq, void *dev_id) 2783 { 2784 struct idt77252_dev *card = dev_id; 2785 u32 stat; 2786 2787 stat = readl(SAR_REG_STAT) & 0xffff; 2788 if (!stat) /* no interrupt for us */ 2789 return IRQ_NONE; 2790 2791 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { 2792 printk("%s: Re-entering irq_handler()\n", card->name); 2793 goto out; 2794 } 2795 2796 writel(stat, SAR_REG_STAT); /* reset interrupt */ 2797 2798 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ 2799 INTPRINTK("%s: TSIF\n", card->name); 2800 card->irqstat[15]++; 2801 idt77252_tx(card); 2802 } 2803 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ 2804 INTPRINTK("%s: TXICP\n", card->name); 2805 card->irqstat[14]++; 2806 #ifdef CONFIG_ATM_IDT77252_DEBUG 2807 idt77252_tx_dump(card); 2808 #endif 2809 } 2810 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ 2811 INTPRINTK("%s: TSQF\n", card->name); 2812 card->irqstat[12]++; 2813 idt77252_tx(card); 2814 } 2815 if (stat & SAR_STAT_TMROF) { /* Timer overflow */ 2816 INTPRINTK("%s: TMROF\n", card->name); 2817 card->irqstat[11]++; 2818 idt77252_collect_stat(card); 2819 } 2820 2821 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ 2822 INTPRINTK("%s: EPDU\n", card->name); 2823 card->irqstat[5]++; 2824 idt77252_rx(card); 2825 } 2826 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ 2827 INTPRINTK("%s: RSQAF\n", card->name); 2828 card->irqstat[1]++; 2829 idt77252_rx(card); 2830 } 2831 if (stat & SAR_STAT_RSQF) { /* RSQ is full */ 2832 INTPRINTK("%s: RSQF\n", card->name); 2833 card->irqstat[6]++; 2834 idt77252_rx(card); 2835 } 2836 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ 2837 INTPRINTK("%s: RAWCF\n", card->name); 2838 card->irqstat[4]++; 2839 idt77252_rx_raw(card); 2840 } 2841 2842 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ 2843 INTPRINTK("%s: PHYI", card->name); 2844 card->irqstat[10]++; 2845 if (card->atmdev->phy && card->atmdev->phy->interrupt) 2846 card->atmdev->phy->interrupt(card->atmdev); 2847 } 2848 2849 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | 2850 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { 2851 2852 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); 2853 2854 INTPRINTK("%s: FBQA: %04x\n", card->name, stat); 2855 2856 if (stat & SAR_STAT_FBQ0A) 2857 card->irqstat[2]++; 2858 if (stat & SAR_STAT_FBQ1A) 2859 card->irqstat[3]++; 2860 if (stat & SAR_STAT_FBQ2A) 2861 card->irqstat[7]++; 2862 if (stat & SAR_STAT_FBQ3A) 2863 card->irqstat[8]++; 2864 2865 schedule_work(&card->tqueue); 2866 } 2867 2868 out: 2869 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); 2870 return IRQ_HANDLED; 2871 } 2872 2873 static void 2874 idt77252_softint(struct work_struct *work) 2875 { 2876 struct idt77252_dev *card = 2877 container_of(work, struct idt77252_dev, tqueue); 2878 u32 stat; 2879 int done; 2880 2881 for (done = 1; ; done = 1) { 2882 stat = readl(SAR_REG_STAT) >> 16; 2883 2884 if ((stat & 0x0f) < SAR_FBQ0_HIGH) { 2885 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); 2886 done = 0; 2887 } 2888 2889 stat >>= 4; 2890 if ((stat & 0x0f) < SAR_FBQ1_HIGH) { 2891 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); 2892 done = 0; 2893 } 2894 2895 stat >>= 4; 2896 if ((stat & 0x0f) < SAR_FBQ2_HIGH) { 2897 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); 2898 done = 0; 2899 } 2900 2901 stat >>= 4; 2902 if ((stat & 0x0f) < SAR_FBQ3_HIGH) { 2903 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); 2904 done = 0; 2905 } 2906 2907 if (done) 2908 break; 2909 } 2910 2911 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); 2912 } 2913 2914 2915 static int 2916 open_card_oam(struct idt77252_dev *card) 2917 { 2918 unsigned long flags; 2919 unsigned long addr; 2920 struct vc_map *vc; 2921 int vpi, vci; 2922 int index; 2923 u32 rcte; 2924 2925 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2926 for (vci = 3; vci < 5; vci++) { 2927 index = VPCI2VC(card, vpi, vci); 2928 2929 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2930 if (!vc) { 2931 printk("%s: can't alloc vc\n", card->name); 2932 return -ENOMEM; 2933 } 2934 vc->index = index; 2935 card->vcs[index] = vc; 2936 2937 flush_rx_pool(card, &vc->rcv.rx_pool); 2938 2939 rcte = SAR_RCTE_CONNECTOPEN | 2940 SAR_RCTE_RAWCELLINTEN | 2941 SAR_RCTE_RCQ | 2942 SAR_RCTE_FBP_1; 2943 2944 addr = card->rct_base + (vc->index << 2); 2945 write_sram(card, addr, rcte); 2946 2947 spin_lock_irqsave(&card->cmd_lock, flags); 2948 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), 2949 SAR_REG_CMD); 2950 waitfor_idle(card); 2951 spin_unlock_irqrestore(&card->cmd_lock, flags); 2952 } 2953 } 2954 2955 return 0; 2956 } 2957 2958 static void 2959 close_card_oam(struct idt77252_dev *card) 2960 { 2961 unsigned long flags; 2962 unsigned long addr; 2963 struct vc_map *vc; 2964 int vpi, vci; 2965 int index; 2966 2967 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { 2968 for (vci = 3; vci < 5; vci++) { 2969 index = VPCI2VC(card, vpi, vci); 2970 vc = card->vcs[index]; 2971 2972 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; 2973 2974 spin_lock_irqsave(&card->cmd_lock, flags); 2975 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), 2976 SAR_REG_CMD); 2977 waitfor_idle(card); 2978 spin_unlock_irqrestore(&card->cmd_lock, flags); 2979 2980 if (vc->rcv.rx_pool.count) { 2981 DPRINTK("%s: closing a VC " 2982 "with pending rx buffers.\n", 2983 card->name); 2984 2985 recycle_rx_pool_skb(card, &vc->rcv.rx_pool); 2986 } 2987 } 2988 } 2989 } 2990 2991 static int 2992 open_card_ubr0(struct idt77252_dev *card) 2993 { 2994 struct vc_map *vc; 2995 2996 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); 2997 if (!vc) { 2998 printk("%s: can't alloc vc\n", card->name); 2999 return -ENOMEM; 3000 } 3001 card->vcs[0] = vc; 3002 vc->class = SCHED_UBR0; 3003 3004 vc->scq = alloc_scq(card, vc->class); 3005 if (!vc->scq) { 3006 printk("%s: can't get SCQ.\n", card->name); 3007 return -ENOMEM; 3008 } 3009 3010 card->scd2vc[0] = vc; 3011 vc->scd_index = 0; 3012 vc->scq->scd = card->scd_base; 3013 3014 fill_scd(card, vc->scq, vc->class); 3015 3016 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); 3017 write_sram(card, card->tct_base + 1, 0); 3018 write_sram(card, card->tct_base + 2, 0); 3019 write_sram(card, card->tct_base + 3, 0); 3020 write_sram(card, card->tct_base + 4, 0); 3021 write_sram(card, card->tct_base + 5, 0); 3022 write_sram(card, card->tct_base + 6, 0); 3023 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); 3024 3025 clear_bit(VCF_IDLE, &vc->flags); 3026 writel(TCMDQ_START | 0, SAR_REG_TCMDQ); 3027 return 0; 3028 } 3029 3030 static int 3031 idt77252_dev_open(struct idt77252_dev *card) 3032 { 3033 u32 conf; 3034 3035 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3036 printk("%s: SAR not yet initialized.\n", card->name); 3037 return -1; 3038 } 3039 3040 conf = SAR_CFG_RXPTH| /* enable receive path */ 3041 SAR_RX_DELAY | /* interrupt on complete PDU */ 3042 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3043 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3044 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3045 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3046 SAR_CFG_TXEN | /* transmit operation enable */ 3047 SAR_CFG_TXINT | /* interrupt on transmit status */ 3048 SAR_CFG_TXUIE | /* interrupt on transmit underrun */ 3049 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ 3050 SAR_CFG_PHYIE /* enable PHY interrupts */ 3051 ; 3052 3053 #ifdef CONFIG_ATM_IDT77252_RCV_ALL 3054 /* Test RAW cell receive. */ 3055 conf |= SAR_CFG_VPECA; 3056 #endif 3057 3058 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3059 3060 if (open_card_oam(card)) { 3061 printk("%s: Error initializing OAM.\n", card->name); 3062 return -1; 3063 } 3064 3065 if (open_card_ubr0(card)) { 3066 printk("%s: Error initializing UBR0.\n", card->name); 3067 return -1; 3068 } 3069 3070 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); 3071 return 0; 3072 } 3073 3074 void 3075 idt77252_dev_close(struct atm_dev *dev) 3076 { 3077 struct idt77252_dev *card = dev->dev_data; 3078 u32 conf; 3079 3080 close_card_oam(card); 3081 3082 conf = SAR_CFG_RXPTH | /* enable receive path */ 3083 SAR_RX_DELAY | /* interrupt on complete PDU */ 3084 SAR_CFG_RAWIE | /* interrupt enable on raw cells */ 3085 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ 3086 SAR_CFG_TMOIE | /* interrupt on timer overflow */ 3087 SAR_CFG_FBIE | /* interrupt on low free buffers */ 3088 SAR_CFG_TXEN | /* transmit operation enable */ 3089 SAR_CFG_TXINT | /* interrupt on transmit status */ 3090 SAR_CFG_TXUIE | /* interrupt on xmit underrun */ 3091 SAR_CFG_TXSFI /* interrupt on TSQ almost full */ 3092 ; 3093 3094 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); 3095 3096 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); 3097 } 3098 3099 3100 /*****************************************************************************/ 3101 /* */ 3102 /* Initialisation and Deinitialization of IDT77252 */ 3103 /* */ 3104 /*****************************************************************************/ 3105 3106 3107 static void 3108 deinit_card(struct idt77252_dev *card) 3109 { 3110 struct sk_buff *skb; 3111 int i, j; 3112 3113 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { 3114 printk("%s: SAR not yet initialized.\n", card->name); 3115 return; 3116 } 3117 DIPRINTK("idt77252: deinitialize card %u\n", card->index); 3118 3119 writel(0, SAR_REG_CFG); 3120 3121 if (card->atmdev) 3122 atm_dev_deregister(card->atmdev); 3123 3124 for (i = 0; i < 4; i++) { 3125 for (j = 0; j < FBQ_SIZE; j++) { 3126 skb = card->sbpool[i].skb[j]; 3127 if (skb) { 3128 pci_unmap_single(card->pcidev, 3129 IDT77252_PRV_PADDR(skb), 3130 (skb_end_pointer(skb) - 3131 skb->data), 3132 PCI_DMA_FROMDEVICE); 3133 card->sbpool[i].skb[j] = NULL; 3134 dev_kfree_skb(skb); 3135 } 3136 } 3137 } 3138 3139 vfree(card->soft_tst); 3140 3141 vfree(card->scd2vc); 3142 3143 vfree(card->vcs); 3144 3145 if (card->raw_cell_hnd) { 3146 pci_free_consistent(card->pcidev, 2 * sizeof(u32), 3147 card->raw_cell_hnd, card->raw_cell_paddr); 3148 } 3149 3150 if (card->rsq.base) { 3151 DIPRINTK("%s: Release RSQ ...\n", card->name); 3152 deinit_rsq(card); 3153 } 3154 3155 if (card->tsq.base) { 3156 DIPRINTK("%s: Release TSQ ...\n", card->name); 3157 deinit_tsq(card); 3158 } 3159 3160 DIPRINTK("idt77252: Release IRQ.\n"); 3161 free_irq(card->pcidev->irq, card); 3162 3163 for (i = 0; i < 4; i++) { 3164 if (card->fbq[i]) 3165 iounmap(card->fbq[i]); 3166 } 3167 3168 if (card->membase) 3169 iounmap(card->membase); 3170 3171 clear_bit(IDT77252_BIT_INIT, &card->flags); 3172 DIPRINTK("%s: Card deinitialized.\n", card->name); 3173 } 3174 3175 3176 static int __devinit 3177 init_sram(struct idt77252_dev *card) 3178 { 3179 int i; 3180 3181 for (i = 0; i < card->sramsize; i += 4) 3182 write_sram(card, (i >> 2), 0); 3183 3184 /* set SRAM layout for THIS card */ 3185 if (card->sramsize == (512 * 1024)) { 3186 card->tct_base = SAR_SRAM_TCT_128_BASE; 3187 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) 3188 / SAR_SRAM_TCT_SIZE; 3189 card->rct_base = SAR_SRAM_RCT_128_BASE; 3190 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) 3191 / SAR_SRAM_RCT_SIZE; 3192 card->rt_base = SAR_SRAM_RT_128_BASE; 3193 card->scd_base = SAR_SRAM_SCD_128_BASE; 3194 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) 3195 / SAR_SRAM_SCD_SIZE; 3196 card->tst[0] = SAR_SRAM_TST1_128_BASE; 3197 card->tst[1] = SAR_SRAM_TST2_128_BASE; 3198 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; 3199 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; 3200 card->abrst_size = SAR_ABRSTD_SIZE_8K; 3201 card->fifo_base = SAR_SRAM_FIFO_128_BASE; 3202 card->fifo_size = SAR_RXFD_SIZE_32K; 3203 } else { 3204 card->tct_base = SAR_SRAM_TCT_32_BASE; 3205 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) 3206 / SAR_SRAM_TCT_SIZE; 3207 card->rct_base = SAR_SRAM_RCT_32_BASE; 3208 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) 3209 / SAR_SRAM_RCT_SIZE; 3210 card->rt_base = SAR_SRAM_RT_32_BASE; 3211 card->scd_base = SAR_SRAM_SCD_32_BASE; 3212 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) 3213 / SAR_SRAM_SCD_SIZE; 3214 card->tst[0] = SAR_SRAM_TST1_32_BASE; 3215 card->tst[1] = SAR_SRAM_TST2_32_BASE; 3216 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); 3217 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; 3218 card->abrst_size = SAR_ABRSTD_SIZE_1K; 3219 card->fifo_base = SAR_SRAM_FIFO_32_BASE; 3220 card->fifo_size = SAR_RXFD_SIZE_4K; 3221 } 3222 3223 /* Initialize TCT */ 3224 for (i = 0; i < card->tct_size; i++) { 3225 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); 3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); 3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); 3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); 3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); 3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); 3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); 3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); 3233 } 3234 3235 /* Initialize RCT */ 3236 for (i = 0; i < card->rct_size; i++) { 3237 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, 3238 (u32) SAR_RCTE_RAWCELLINTEN); 3239 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, 3240 (u32) 0); 3241 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, 3242 (u32) 0); 3243 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, 3244 (u32) 0xffffffff); 3245 } 3246 3247 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 | 3248 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); 3249 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 | 3250 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); 3251 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 | 3252 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); 3253 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 | 3254 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); 3255 3256 /* Initialize rate table */ 3257 for (i = 0; i < 256; i++) { 3258 write_sram(card, card->rt_base + i, log_to_rate[i]); 3259 } 3260 3261 for (i = 0; i < 128; i++) { 3262 unsigned int tmp; 3263 3264 tmp = rate_to_log[(i << 2) + 0] << 0; 3265 tmp |= rate_to_log[(i << 2) + 1] << 8; 3266 tmp |= rate_to_log[(i << 2) + 2] << 16; 3267 tmp |= rate_to_log[(i << 2) + 3] << 24; 3268 write_sram(card, card->rt_base + 256 + i, tmp); 3269 } 3270 3271 #if 0 /* Fill RDF and AIR tables. */ 3272 for (i = 0; i < 128; i++) { 3273 unsigned int tmp; 3274 3275 tmp = RDF[0][(i << 1) + 0] << 16; 3276 tmp |= RDF[0][(i << 1) + 1] << 0; 3277 write_sram(card, card->rt_base + 512 + i, tmp); 3278 } 3279 3280 for (i = 0; i < 128; i++) { 3281 unsigned int tmp; 3282 3283 tmp = AIR[0][(i << 1) + 0] << 16; 3284 tmp |= AIR[0][(i << 1) + 1] << 0; 3285 write_sram(card, card->rt_base + 640 + i, tmp); 3286 } 3287 #endif 3288 3289 IPRINTK("%s: initialize rate table ...\n", card->name); 3290 writel(card->rt_base << 2, SAR_REG_RTBL); 3291 3292 /* Initialize TSTs */ 3293 IPRINTK("%s: initialize TST ...\n", card->name); 3294 card->tst_free = card->tst_size - 2; /* last two are jumps */ 3295 3296 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) 3297 write_sram(card, i, TSTE_OPC_VAR); 3298 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3299 idt77252_sram_write_errors = 1; 3300 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3301 idt77252_sram_write_errors = 0; 3302 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) 3303 write_sram(card, i, TSTE_OPC_VAR); 3304 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); 3305 idt77252_sram_write_errors = 1; 3306 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); 3307 idt77252_sram_write_errors = 0; 3308 3309 card->tst_index = 0; 3310 writel(card->tst[0] << 2, SAR_REG_TSTB); 3311 3312 /* Initialize ABRSTD and Receive FIFO */ 3313 IPRINTK("%s: initialize ABRSTD ...\n", card->name); 3314 writel(card->abrst_size | (card->abrst_base << 2), 3315 SAR_REG_ABRSTD); 3316 3317 IPRINTK("%s: initialize receive fifo ...\n", card->name); 3318 writel(card->fifo_size | (card->fifo_base << 2), 3319 SAR_REG_RXFD); 3320 3321 IPRINTK("%s: SRAM initialization complete.\n", card->name); 3322 return 0; 3323 } 3324 3325 static int __devinit 3326 init_card(struct atm_dev *dev) 3327 { 3328 struct idt77252_dev *card = dev->dev_data; 3329 struct pci_dev *pcidev = card->pcidev; 3330 unsigned long tmpl, modl; 3331 unsigned int linkrate, rsvdcr; 3332 unsigned int tst_entries; 3333 struct net_device *tmp; 3334 char tname[10]; 3335 3336 u32 size; 3337 u_char pci_byte; 3338 u32 conf; 3339 int i, k; 3340 3341 if (test_bit(IDT77252_BIT_INIT, &card->flags)) { 3342 printk("Error: SAR already initialized.\n"); 3343 return -1; 3344 } 3345 3346 /*****************************************************************/ 3347 /* P C I C O N F I G U R A T I O N */ 3348 /*****************************************************************/ 3349 3350 /* Set PCI Retry-Timeout and TRDY timeout */ 3351 IPRINTK("%s: Checking PCI retries.\n", card->name); 3352 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { 3353 printk("%s: can't read PCI retry timeout.\n", card->name); 3354 deinit_card(card); 3355 return -1; 3356 } 3357 if (pci_byte != 0) { 3358 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", 3359 card->name, pci_byte); 3360 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { 3361 printk("%s: can't set PCI retry timeout.\n", 3362 card->name); 3363 deinit_card(card); 3364 return -1; 3365 } 3366 } 3367 IPRINTK("%s: Checking PCI TRDY.\n", card->name); 3368 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { 3369 printk("%s: can't read PCI TRDY timeout.\n", card->name); 3370 deinit_card(card); 3371 return -1; 3372 } 3373 if (pci_byte != 0) { 3374 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", 3375 card->name, pci_byte); 3376 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { 3377 printk("%s: can't set PCI TRDY timeout.\n", card->name); 3378 deinit_card(card); 3379 return -1; 3380 } 3381 } 3382 /* Reset Timer register */ 3383 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { 3384 printk("%s: resetting timer overflow.\n", card->name); 3385 writel(SAR_STAT_TMROF, SAR_REG_STAT); 3386 } 3387 IPRINTK("%s: Request IRQ ... ", card->name); 3388 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED, 3389 card->name, card) != 0) { 3390 printk("%s: can't allocate IRQ.\n", card->name); 3391 deinit_card(card); 3392 return -1; 3393 } 3394 IPRINTK("got %d.\n", pcidev->irq); 3395 3396 /*****************************************************************/ 3397 /* C H E C K A N D I N I T S R A M */ 3398 /*****************************************************************/ 3399 3400 IPRINTK("%s: Initializing SRAM\n", card->name); 3401 3402 /* preset size of connecton table, so that init_sram() knows about it */ 3403 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ 3404 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ 3405 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ 3406 #ifndef CONFIG_ATM_IDT77252_SEND_IDLE 3407 SAR_CFG_NO_IDLE | /* Do not send idle cells */ 3408 #endif 3409 0; 3410 3411 if (card->sramsize == (512 * 1024)) 3412 conf |= SAR_CFG_CNTBL_1k; 3413 else 3414 conf |= SAR_CFG_CNTBL_512; 3415 3416 switch (vpibits) { 3417 case 0: 3418 conf |= SAR_CFG_VPVCS_0; 3419 break; 3420 default: 3421 case 1: 3422 conf |= SAR_CFG_VPVCS_1; 3423 break; 3424 case 2: 3425 conf |= SAR_CFG_VPVCS_2; 3426 break; 3427 case 8: 3428 conf |= SAR_CFG_VPVCS_8; 3429 break; 3430 } 3431 3432 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); 3433 3434 if (init_sram(card) < 0) 3435 return -1; 3436 3437 /********************************************************************/ 3438 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ 3439 /********************************************************************/ 3440 /* Initialize TSQ */ 3441 if (0 != init_tsq(card)) { 3442 deinit_card(card); 3443 return -1; 3444 } 3445 /* Initialize RSQ */ 3446 if (0 != init_rsq(card)) { 3447 deinit_card(card); 3448 return -1; 3449 } 3450 3451 card->vpibits = vpibits; 3452 if (card->sramsize == (512 * 1024)) { 3453 card->vcibits = 10 - card->vpibits; 3454 } else { 3455 card->vcibits = 9 - card->vpibits; 3456 } 3457 3458 card->vcimask = 0; 3459 for (k = 0, i = 1; k < card->vcibits; k++) { 3460 card->vcimask |= i; 3461 i <<= 1; 3462 } 3463 3464 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); 3465 writel(0, SAR_REG_VPM); 3466 3467 /* Little Endian Order */ 3468 writel(0, SAR_REG_GP); 3469 3470 /* Initialize RAW Cell Handle Register */ 3471 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32), 3472 &card->raw_cell_paddr); 3473 if (!card->raw_cell_hnd) { 3474 printk("%s: memory allocation failure.\n", card->name); 3475 deinit_card(card); 3476 return -1; 3477 } 3478 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32)); 3479 writel(card->raw_cell_paddr, SAR_REG_RAWHND); 3480 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, 3481 card->raw_cell_hnd); 3482 3483 size = sizeof(struct vc_map *) * card->tct_size; 3484 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); 3485 if (NULL == (card->vcs = vmalloc(size))) { 3486 printk("%s: memory allocation failure.\n", card->name); 3487 deinit_card(card); 3488 return -1; 3489 } 3490 memset(card->vcs, 0, size); 3491 3492 size = sizeof(struct vc_map *) * card->scd_size; 3493 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", 3494 card->name, size); 3495 if (NULL == (card->scd2vc = vmalloc(size))) { 3496 printk("%s: memory allocation failure.\n", card->name); 3497 deinit_card(card); 3498 return -1; 3499 } 3500 memset(card->scd2vc, 0, size); 3501 3502 size = sizeof(struct tst_info) * (card->tst_size - 2); 3503 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", 3504 card->name, size); 3505 if (NULL == (card->soft_tst = vmalloc(size))) { 3506 printk("%s: memory allocation failure.\n", card->name); 3507 deinit_card(card); 3508 return -1; 3509 } 3510 for (i = 0; i < card->tst_size - 2; i++) { 3511 card->soft_tst[i].tste = TSTE_OPC_VAR; 3512 card->soft_tst[i].vc = NULL; 3513 } 3514 3515 if (dev->phy == NULL) { 3516 printk("%s: No LT device defined.\n", card->name); 3517 deinit_card(card); 3518 return -1; 3519 } 3520 if (dev->phy->ioctl == NULL) { 3521 printk("%s: LT had no IOCTL funtion defined.\n", card->name); 3522 deinit_card(card); 3523 return -1; 3524 } 3525 3526 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3527 /* 3528 * this is a jhs hack to get around special functionality in the 3529 * phy driver for the atecom hardware; the functionality doesn't 3530 * exist in the linux atm suni driver 3531 * 3532 * it isn't the right way to do things, but as the guy from NIST 3533 * said, talking about their measurement of the fine structure 3534 * constant, "it's good enough for government work." 3535 */ 3536 linkrate = 149760000; 3537 #endif 3538 3539 card->link_pcr = (linkrate / 8 / 53); 3540 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", 3541 card->name, linkrate, card->link_pcr); 3542 3543 #ifdef CONFIG_ATM_IDT77252_SEND_IDLE 3544 card->utopia_pcr = card->link_pcr; 3545 #else 3546 card->utopia_pcr = (160000000 / 8 / 54); 3547 #endif 3548 3549 rsvdcr = 0; 3550 if (card->utopia_pcr > card->link_pcr) 3551 rsvdcr = card->utopia_pcr - card->link_pcr; 3552 3553 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); 3554 modl = tmpl % (unsigned long)card->utopia_pcr; 3555 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); 3556 if (modl) 3557 tst_entries++; 3558 card->tst_free -= tst_entries; 3559 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); 3560 3561 #ifdef HAVE_EEPROM 3562 idt77252_eeprom_init(card); 3563 printk("%s: EEPROM: %02x:", card->name, 3564 idt77252_eeprom_read_status(card)); 3565 3566 for (i = 0; i < 0x80; i++) { 3567 printk(" %02x", 3568 idt77252_eeprom_read_byte(card, i) 3569 ); 3570 } 3571 printk("\n"); 3572 #endif /* HAVE_EEPROM */ 3573 3574 /* 3575 * XXX: <hack> 3576 */ 3577 sprintf(tname, "eth%d", card->index); 3578 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */ 3579 if (tmp) { 3580 memcpy(card->atmdev->esi, tmp->dev_addr, 6); 3581 3582 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n", 3583 card->name, card->atmdev->esi[0], card->atmdev->esi[1], 3584 card->atmdev->esi[2], card->atmdev->esi[3], 3585 card->atmdev->esi[4], card->atmdev->esi[5]); 3586 } 3587 /* 3588 * XXX: </hack> 3589 */ 3590 3591 /* Set Maximum Deficit Count for now. */ 3592 writel(0xffff, SAR_REG_MDFCT); 3593 3594 set_bit(IDT77252_BIT_INIT, &card->flags); 3595 3596 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); 3597 return 0; 3598 } 3599 3600 3601 /*****************************************************************************/ 3602 /* */ 3603 /* Probing of IDT77252 ABR SAR */ 3604 /* */ 3605 /*****************************************************************************/ 3606 3607 3608 static int __devinit 3609 idt77252_preset(struct idt77252_dev *card) 3610 { 3611 u16 pci_command; 3612 3613 /*****************************************************************/ 3614 /* P C I C O N F I G U R A T I O N */ 3615 /*****************************************************************/ 3616 3617 XPRINTK("%s: Enable PCI master and memory access for SAR.\n", 3618 card->name); 3619 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { 3620 printk("%s: can't read PCI_COMMAND.\n", card->name); 3621 deinit_card(card); 3622 return -1; 3623 } 3624 if (!(pci_command & PCI_COMMAND_IO)) { 3625 printk("%s: PCI_COMMAND: %04x (???)\n", 3626 card->name, pci_command); 3627 deinit_card(card); 3628 return (-1); 3629 } 3630 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 3631 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { 3632 printk("%s: can't write PCI_COMMAND.\n", card->name); 3633 deinit_card(card); 3634 return -1; 3635 } 3636 /*****************************************************************/ 3637 /* G E N E R I C R E S E T */ 3638 /*****************************************************************/ 3639 3640 /* Software reset */ 3641 writel(SAR_CFG_SWRST, SAR_REG_CFG); 3642 mdelay(1); 3643 writel(0, SAR_REG_CFG); 3644 3645 IPRINTK("%s: Software resetted.\n", card->name); 3646 return 0; 3647 } 3648 3649 3650 static unsigned long __devinit 3651 probe_sram(struct idt77252_dev *card) 3652 { 3653 u32 data, addr; 3654 3655 writel(0, SAR_REG_DR0); 3656 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); 3657 3658 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { 3659 writel(ATM_POISON, SAR_REG_DR0); 3660 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); 3661 3662 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); 3663 data = readl(SAR_REG_DR0); 3664 3665 if (data != 0) 3666 break; 3667 } 3668 3669 return addr * sizeof(u32); 3670 } 3671 3672 static int __devinit 3673 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id) 3674 { 3675 static struct idt77252_dev **last = &idt77252_chain; 3676 static int index = 0; 3677 3678 unsigned long membase, srambase; 3679 struct idt77252_dev *card; 3680 struct atm_dev *dev; 3681 ushort revision = 0; 3682 int i, err; 3683 3684 3685 if ((err = pci_enable_device(pcidev))) { 3686 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); 3687 return err; 3688 } 3689 3690 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) { 3691 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index); 3692 err = -ENODEV; 3693 goto err_out_disable_pdev; 3694 } 3695 3696 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); 3697 if (!card) { 3698 printk("idt77252-%d: can't allocate private data\n", index); 3699 err = -ENOMEM; 3700 goto err_out_disable_pdev; 3701 } 3702 card->revision = revision; 3703 card->index = index; 3704 card->pcidev = pcidev; 3705 sprintf(card->name, "idt77252-%d", card->index); 3706 3707 INIT_WORK(&card->tqueue, idt77252_softint); 3708 3709 membase = pci_resource_start(pcidev, 1); 3710 srambase = pci_resource_start(pcidev, 2); 3711 3712 init_MUTEX(&card->mutex); 3713 spin_lock_init(&card->cmd_lock); 3714 spin_lock_init(&card->tst_lock); 3715 3716 init_timer(&card->tst_timer); 3717 card->tst_timer.data = (unsigned long)card; 3718 card->tst_timer.function = tst_timer; 3719 3720 /* Do the I/O remapping... */ 3721 card->membase = ioremap(membase, 1024); 3722 if (!card->membase) { 3723 printk("%s: can't ioremap() membase\n", card->name); 3724 err = -EIO; 3725 goto err_out_free_card; 3726 } 3727 3728 if (idt77252_preset(card)) { 3729 printk("%s: preset failed\n", card->name); 3730 err = -EIO; 3731 goto err_out_iounmap; 3732 } 3733 3734 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL); 3735 if (!dev) { 3736 printk("%s: can't register atm device\n", card->name); 3737 err = -EIO; 3738 goto err_out_iounmap; 3739 } 3740 dev->dev_data = card; 3741 card->atmdev = dev; 3742 3743 #ifdef CONFIG_ATM_IDT77252_USE_SUNI 3744 suni_init(dev); 3745 if (!dev->phy) { 3746 printk("%s: can't init SUNI\n", card->name); 3747 err = -EIO; 3748 goto err_out_deinit_card; 3749 } 3750 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ 3751 3752 card->sramsize = probe_sram(card); 3753 3754 for (i = 0; i < 4; i++) { 3755 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); 3756 if (!card->fbq[i]) { 3757 printk("%s: can't ioremap() FBQ%d\n", card->name, i); 3758 err = -EIO; 3759 goto err_out_deinit_card; 3760 } 3761 } 3762 3763 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", 3764 card->name, ((revision > 1) && (revision < 25)) ? 3765 'A' + revision - 1 : '?', membase, srambase, 3766 card->sramsize / 1024); 3767 3768 if (init_card(dev)) { 3769 printk("%s: init_card failed\n", card->name); 3770 err = -EIO; 3771 goto err_out_deinit_card; 3772 } 3773 3774 dev->ci_range.vpi_bits = card->vpibits; 3775 dev->ci_range.vci_bits = card->vcibits; 3776 dev->link_rate = card->link_pcr; 3777 3778 if (dev->phy->start) 3779 dev->phy->start(dev); 3780 3781 if (idt77252_dev_open(card)) { 3782 printk("%s: dev_open failed\n", card->name); 3783 err = -EIO; 3784 goto err_out_stop; 3785 } 3786 3787 *last = card; 3788 last = &card->next; 3789 index++; 3790 3791 return 0; 3792 3793 err_out_stop: 3794 if (dev->phy->stop) 3795 dev->phy->stop(dev); 3796 3797 err_out_deinit_card: 3798 deinit_card(card); 3799 3800 err_out_iounmap: 3801 iounmap(card->membase); 3802 3803 err_out_free_card: 3804 kfree(card); 3805 3806 err_out_disable_pdev: 3807 pci_disable_device(pcidev); 3808 return err; 3809 } 3810 3811 static struct pci_device_id idt77252_pci_tbl[] = 3812 { 3813 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252, 3814 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 3815 { 0, } 3816 }; 3817 3818 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); 3819 3820 static struct pci_driver idt77252_driver = { 3821 .name = "idt77252", 3822 .id_table = idt77252_pci_tbl, 3823 .probe = idt77252_init_one, 3824 }; 3825 3826 static int __init idt77252_init(void) 3827 { 3828 struct sk_buff *skb; 3829 3830 printk("%s: at %p\n", __FUNCTION__, idt77252_init); 3831 3832 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) + 3833 sizeof(struct idt77252_skb_prv)) { 3834 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n", 3835 __FUNCTION__, (unsigned long) sizeof(skb->cb), 3836 (unsigned long) sizeof(struct atm_skb_data) + 3837 sizeof(struct idt77252_skb_prv)); 3838 return -EIO; 3839 } 3840 3841 return pci_register_driver(&idt77252_driver); 3842 } 3843 3844 static void __exit idt77252_exit(void) 3845 { 3846 struct idt77252_dev *card; 3847 struct atm_dev *dev; 3848 3849 pci_unregister_driver(&idt77252_driver); 3850 3851 while (idt77252_chain) { 3852 card = idt77252_chain; 3853 dev = card->atmdev; 3854 idt77252_chain = card->next; 3855 3856 if (dev->phy->stop) 3857 dev->phy->stop(dev); 3858 deinit_card(card); 3859 pci_disable_device(card->pcidev); 3860 kfree(card); 3861 } 3862 3863 DIPRINTK("idt77252: finished cleanup-module().\n"); 3864 } 3865 3866 module_init(idt77252_init); 3867 module_exit(idt77252_exit); 3868 3869 MODULE_LICENSE("GPL"); 3870 3871 module_param(vpibits, uint, 0); 3872 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); 3873 #ifdef CONFIG_ATM_IDT77252_DEBUG 3874 module_param(debug, ulong, 0644); 3875 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); 3876 #endif 3877 3878 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); 3879 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); 3880