1*1da177e4SLinus Torvalds /* $Id: fore200e.h,v 1.4 2000/04/14 10:10:34 davem Exp $ */ 2*1da177e4SLinus Torvalds #ifndef _FORE200E_H 3*1da177e4SLinus Torvalds #define _FORE200E_H 4*1da177e4SLinus Torvalds 5*1da177e4SLinus Torvalds #ifdef __KERNEL__ 6*1da177e4SLinus Torvalds #include <linux/config.h> 7*1da177e4SLinus Torvalds 8*1da177e4SLinus Torvalds /* rx buffer sizes */ 9*1da177e4SLinus Torvalds 10*1da177e4SLinus Torvalds #define SMALL_BUFFER_SIZE 384 /* size of small buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */ 11*1da177e4SLinus Torvalds #define LARGE_BUFFER_SIZE 4032 /* size of large buffers (multiple of 48 (PCA) and 64 (SBA) bytes) */ 12*1da177e4SLinus Torvalds 13*1da177e4SLinus Torvalds 14*1da177e4SLinus Torvalds #define RBD_BLK_SIZE 32 /* nbr of supplied rx buffers per rbd */ 15*1da177e4SLinus Torvalds 16*1da177e4SLinus Torvalds 17*1da177e4SLinus Torvalds #define MAX_PDU_SIZE 65535 /* maximum PDU size supported by AALs */ 18*1da177e4SLinus Torvalds 19*1da177e4SLinus Torvalds 20*1da177e4SLinus Torvalds #define BUFFER_S1_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 1 */ 21*1da177e4SLinus Torvalds #define BUFFER_L1_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 1 */ 22*1da177e4SLinus Torvalds 23*1da177e4SLinus Torvalds #define BUFFER_S2_SIZE SMALL_BUFFER_SIZE /* size of small buffers, scheme 2 */ 24*1da177e4SLinus Torvalds #define BUFFER_L2_SIZE LARGE_BUFFER_SIZE /* size of large buffers, scheme 2 */ 25*1da177e4SLinus Torvalds 26*1da177e4SLinus Torvalds #define BUFFER_S1_NBR (RBD_BLK_SIZE * 6) 27*1da177e4SLinus Torvalds #define BUFFER_L1_NBR (RBD_BLK_SIZE * 4) 28*1da177e4SLinus Torvalds 29*1da177e4SLinus Torvalds #define BUFFER_S2_NBR (RBD_BLK_SIZE * 6) 30*1da177e4SLinus Torvalds #define BUFFER_L2_NBR (RBD_BLK_SIZE * 4) 31*1da177e4SLinus Torvalds 32*1da177e4SLinus Torvalds 33*1da177e4SLinus Torvalds #define QUEUE_SIZE_CMD 16 /* command queue capacity */ 34*1da177e4SLinus Torvalds #define QUEUE_SIZE_RX 64 /* receive queue capacity */ 35*1da177e4SLinus Torvalds #define QUEUE_SIZE_TX 256 /* transmit queue capacity */ 36*1da177e4SLinus Torvalds #define QUEUE_SIZE_BS 32 /* buffer supply queue capacity */ 37*1da177e4SLinus Torvalds 38*1da177e4SLinus Torvalds #define FORE200E_VPI_BITS 0 39*1da177e4SLinus Torvalds #define FORE200E_VCI_BITS 10 40*1da177e4SLinus Torvalds #define NBR_CONNECT (1 << (FORE200E_VPI_BITS + FORE200E_VCI_BITS)) /* number of connections */ 41*1da177e4SLinus Torvalds 42*1da177e4SLinus Torvalds 43*1da177e4SLinus Torvalds #define TSD_FIXED 2 44*1da177e4SLinus Torvalds #define TSD_EXTENSION 0 45*1da177e4SLinus Torvalds #define TSD_NBR (TSD_FIXED + TSD_EXTENSION) 46*1da177e4SLinus Torvalds 47*1da177e4SLinus Torvalds 48*1da177e4SLinus Torvalds /* the cp starts putting a received PDU into one *small* buffer, 49*1da177e4SLinus Torvalds then it uses a number of *large* buffers for the trailing data. 50*1da177e4SLinus Torvalds we compute here the total number of receive segment descriptors 51*1da177e4SLinus Torvalds required to hold the largest possible PDU */ 52*1da177e4SLinus Torvalds 53*1da177e4SLinus Torvalds #define RSD_REQUIRED (((MAX_PDU_SIZE - SMALL_BUFFER_SIZE + LARGE_BUFFER_SIZE) / LARGE_BUFFER_SIZE) + 1) 54*1da177e4SLinus Torvalds 55*1da177e4SLinus Torvalds #define RSD_FIXED 3 56*1da177e4SLinus Torvalds 57*1da177e4SLinus Torvalds /* RSD_REQUIRED receive segment descriptors are enough to describe a max-sized PDU, 58*1da177e4SLinus Torvalds but we have to keep the size of the receive PDU descriptor multiple of 32 bytes, 59*1da177e4SLinus Torvalds so we add one extra RSD to RSD_EXTENSION 60*1da177e4SLinus Torvalds (WARNING: THIS MAY CHANGE IF BUFFER SIZES ARE MODIFIED) */ 61*1da177e4SLinus Torvalds 62*1da177e4SLinus Torvalds #define RSD_EXTENSION ((RSD_REQUIRED - RSD_FIXED) + 1) 63*1da177e4SLinus Torvalds #define RSD_NBR (RSD_FIXED + RSD_EXTENSION) 64*1da177e4SLinus Torvalds 65*1da177e4SLinus Torvalds 66*1da177e4SLinus Torvalds #define FORE200E_DEV(d) ((struct fore200e*)((d)->dev_data)) 67*1da177e4SLinus Torvalds #define FORE200E_VCC(d) ((struct fore200e_vcc*)((d)->dev_data)) 68*1da177e4SLinus Torvalds 69*1da177e4SLinus Torvalds /* bitfields endian games */ 70*1da177e4SLinus Torvalds 71*1da177e4SLinus Torvalds #if defined(__LITTLE_ENDIAN_BITFIELD) 72*1da177e4SLinus Torvalds #define BITFIELD2(b1, b2) b1; b2; 73*1da177e4SLinus Torvalds #define BITFIELD3(b1, b2, b3) b1; b2; b3; 74*1da177e4SLinus Torvalds #define BITFIELD4(b1, b2, b3, b4) b1; b2; b3; b4; 75*1da177e4SLinus Torvalds #define BITFIELD5(b1, b2, b3, b4, b5) b1; b2; b3; b4; b5; 76*1da177e4SLinus Torvalds #define BITFIELD6(b1, b2, b3, b4, b5, b6) b1; b2; b3; b4; b5; b6; 77*1da177e4SLinus Torvalds #elif defined(__BIG_ENDIAN_BITFIELD) 78*1da177e4SLinus Torvalds #define BITFIELD2(b1, b2) b2; b1; 79*1da177e4SLinus Torvalds #define BITFIELD3(b1, b2, b3) b3; b2; b1; 80*1da177e4SLinus Torvalds #define BITFIELD4(b1, b2, b3, b4) b4; b3; b2; b1; 81*1da177e4SLinus Torvalds #define BITFIELD5(b1, b2, b3, b4, b5) b5; b4; b3; b2; b1; 82*1da177e4SLinus Torvalds #define BITFIELD6(b1, b2, b3, b4, b5, b6) b6; b5; b4; b3; b2; b1; 83*1da177e4SLinus Torvalds #else 84*1da177e4SLinus Torvalds #error unknown bitfield endianess 85*1da177e4SLinus Torvalds #endif 86*1da177e4SLinus Torvalds 87*1da177e4SLinus Torvalds 88*1da177e4SLinus Torvalds /* ATM cell header (minus HEC byte) */ 89*1da177e4SLinus Torvalds 90*1da177e4SLinus Torvalds typedef struct atm_header { 91*1da177e4SLinus Torvalds BITFIELD5( 92*1da177e4SLinus Torvalds u32 clp : 1, /* cell loss priority */ 93*1da177e4SLinus Torvalds u32 plt : 3, /* payload type */ 94*1da177e4SLinus Torvalds u32 vci : 16, /* virtual channel identifier */ 95*1da177e4SLinus Torvalds u32 vpi : 8, /* virtual path identifier */ 96*1da177e4SLinus Torvalds u32 gfc : 4 /* generic flow control */ 97*1da177e4SLinus Torvalds ) 98*1da177e4SLinus Torvalds } atm_header_t; 99*1da177e4SLinus Torvalds 100*1da177e4SLinus Torvalds 101*1da177e4SLinus Torvalds /* ATM adaptation layer id */ 102*1da177e4SLinus Torvalds 103*1da177e4SLinus Torvalds typedef enum fore200e_aal { 104*1da177e4SLinus Torvalds FORE200E_AAL0 = 0, 105*1da177e4SLinus Torvalds FORE200E_AAL34 = 4, 106*1da177e4SLinus Torvalds FORE200E_AAL5 = 5, 107*1da177e4SLinus Torvalds } fore200e_aal_t; 108*1da177e4SLinus Torvalds 109*1da177e4SLinus Torvalds 110*1da177e4SLinus Torvalds /* transmit PDU descriptor specification */ 111*1da177e4SLinus Torvalds 112*1da177e4SLinus Torvalds typedef struct tpd_spec { 113*1da177e4SLinus Torvalds BITFIELD4( 114*1da177e4SLinus Torvalds u32 length : 16, /* total PDU length */ 115*1da177e4SLinus Torvalds u32 nseg : 8, /* number of transmit segments */ 116*1da177e4SLinus Torvalds enum fore200e_aal aal : 4, /* adaptation layer */ 117*1da177e4SLinus Torvalds u32 intr : 4 /* interrupt requested */ 118*1da177e4SLinus Torvalds ) 119*1da177e4SLinus Torvalds } tpd_spec_t; 120*1da177e4SLinus Torvalds 121*1da177e4SLinus Torvalds 122*1da177e4SLinus Torvalds /* transmit PDU rate control */ 123*1da177e4SLinus Torvalds 124*1da177e4SLinus Torvalds typedef struct tpd_rate 125*1da177e4SLinus Torvalds { 126*1da177e4SLinus Torvalds BITFIELD2( 127*1da177e4SLinus Torvalds u32 idle_cells : 16, /* number of idle cells to insert */ 128*1da177e4SLinus Torvalds u32 data_cells : 16 /* number of data cells to transmit */ 129*1da177e4SLinus Torvalds ) 130*1da177e4SLinus Torvalds } tpd_rate_t; 131*1da177e4SLinus Torvalds 132*1da177e4SLinus Torvalds 133*1da177e4SLinus Torvalds /* transmit segment descriptor */ 134*1da177e4SLinus Torvalds 135*1da177e4SLinus Torvalds typedef struct tsd { 136*1da177e4SLinus Torvalds u32 buffer; /* transmit buffer DMA address */ 137*1da177e4SLinus Torvalds u32 length; /* number of bytes in buffer */ 138*1da177e4SLinus Torvalds } tsd_t; 139*1da177e4SLinus Torvalds 140*1da177e4SLinus Torvalds 141*1da177e4SLinus Torvalds /* transmit PDU descriptor */ 142*1da177e4SLinus Torvalds 143*1da177e4SLinus Torvalds typedef struct tpd { 144*1da177e4SLinus Torvalds struct atm_header atm_header; /* ATM header minus HEC byte */ 145*1da177e4SLinus Torvalds struct tpd_spec spec; /* tpd specification */ 146*1da177e4SLinus Torvalds struct tpd_rate rate; /* tpd rate control */ 147*1da177e4SLinus Torvalds u32 pad; /* reserved */ 148*1da177e4SLinus Torvalds struct tsd tsd[ TSD_NBR ]; /* transmit segment descriptors */ 149*1da177e4SLinus Torvalds } tpd_t; 150*1da177e4SLinus Torvalds 151*1da177e4SLinus Torvalds 152*1da177e4SLinus Torvalds /* receive segment descriptor */ 153*1da177e4SLinus Torvalds 154*1da177e4SLinus Torvalds typedef struct rsd { 155*1da177e4SLinus Torvalds u32 handle; /* host supplied receive buffer handle */ 156*1da177e4SLinus Torvalds u32 length; /* number of bytes in buffer */ 157*1da177e4SLinus Torvalds } rsd_t; 158*1da177e4SLinus Torvalds 159*1da177e4SLinus Torvalds 160*1da177e4SLinus Torvalds /* receive PDU descriptor */ 161*1da177e4SLinus Torvalds 162*1da177e4SLinus Torvalds typedef struct rpd { 163*1da177e4SLinus Torvalds struct atm_header atm_header; /* ATM header minus HEC byte */ 164*1da177e4SLinus Torvalds u32 nseg; /* number of receive segments */ 165*1da177e4SLinus Torvalds struct rsd rsd[ RSD_NBR ]; /* receive segment descriptors */ 166*1da177e4SLinus Torvalds } rpd_t; 167*1da177e4SLinus Torvalds 168*1da177e4SLinus Torvalds 169*1da177e4SLinus Torvalds /* buffer scheme */ 170*1da177e4SLinus Torvalds 171*1da177e4SLinus Torvalds typedef enum buffer_scheme { 172*1da177e4SLinus Torvalds BUFFER_SCHEME_ONE, 173*1da177e4SLinus Torvalds BUFFER_SCHEME_TWO, 174*1da177e4SLinus Torvalds BUFFER_SCHEME_NBR /* always last */ 175*1da177e4SLinus Torvalds } buffer_scheme_t; 176*1da177e4SLinus Torvalds 177*1da177e4SLinus Torvalds 178*1da177e4SLinus Torvalds /* buffer magnitude */ 179*1da177e4SLinus Torvalds 180*1da177e4SLinus Torvalds typedef enum buffer_magn { 181*1da177e4SLinus Torvalds BUFFER_MAGN_SMALL, 182*1da177e4SLinus Torvalds BUFFER_MAGN_LARGE, 183*1da177e4SLinus Torvalds BUFFER_MAGN_NBR /* always last */ 184*1da177e4SLinus Torvalds } buffer_magn_t; 185*1da177e4SLinus Torvalds 186*1da177e4SLinus Torvalds 187*1da177e4SLinus Torvalds /* receive buffer descriptor */ 188*1da177e4SLinus Torvalds 189*1da177e4SLinus Torvalds typedef struct rbd { 190*1da177e4SLinus Torvalds u32 handle; /* host supplied handle */ 191*1da177e4SLinus Torvalds u32 buffer_haddr; /* host DMA address of host buffer */ 192*1da177e4SLinus Torvalds } rbd_t; 193*1da177e4SLinus Torvalds 194*1da177e4SLinus Torvalds 195*1da177e4SLinus Torvalds /* receive buffer descriptor block */ 196*1da177e4SLinus Torvalds 197*1da177e4SLinus Torvalds typedef struct rbd_block { 198*1da177e4SLinus Torvalds struct rbd rbd[ RBD_BLK_SIZE ]; /* receive buffer descriptor */ 199*1da177e4SLinus Torvalds } rbd_block_t; 200*1da177e4SLinus Torvalds 201*1da177e4SLinus Torvalds 202*1da177e4SLinus Torvalds /* tpd DMA address */ 203*1da177e4SLinus Torvalds 204*1da177e4SLinus Torvalds typedef struct tpd_haddr { 205*1da177e4SLinus Torvalds BITFIELD3( 206*1da177e4SLinus Torvalds u32 size : 4, /* tpd size expressed in 32 byte blocks */ 207*1da177e4SLinus Torvalds u32 pad : 1, /* reserved */ 208*1da177e4SLinus Torvalds u32 haddr : 27 /* tpd DMA addr aligned on 32 byte boundary */ 209*1da177e4SLinus Torvalds ) 210*1da177e4SLinus Torvalds } tpd_haddr_t; 211*1da177e4SLinus Torvalds 212*1da177e4SLinus Torvalds #define TPD_HADDR_SHIFT 5 /* addr aligned on 32 byte boundary */ 213*1da177e4SLinus Torvalds 214*1da177e4SLinus Torvalds /* cp resident transmit queue entry */ 215*1da177e4SLinus Torvalds 216*1da177e4SLinus Torvalds typedef struct cp_txq_entry { 217*1da177e4SLinus Torvalds struct tpd_haddr tpd_haddr; /* host DMA address of tpd */ 218*1da177e4SLinus Torvalds u32 status_haddr; /* host DMA address of completion status */ 219*1da177e4SLinus Torvalds } cp_txq_entry_t; 220*1da177e4SLinus Torvalds 221*1da177e4SLinus Torvalds 222*1da177e4SLinus Torvalds /* cp resident receive queue entry */ 223*1da177e4SLinus Torvalds 224*1da177e4SLinus Torvalds typedef struct cp_rxq_entry { 225*1da177e4SLinus Torvalds u32 rpd_haddr; /* host DMA address of rpd */ 226*1da177e4SLinus Torvalds u32 status_haddr; /* host DMA address of completion status */ 227*1da177e4SLinus Torvalds } cp_rxq_entry_t; 228*1da177e4SLinus Torvalds 229*1da177e4SLinus Torvalds 230*1da177e4SLinus Torvalds /* cp resident buffer supply queue entry */ 231*1da177e4SLinus Torvalds 232*1da177e4SLinus Torvalds typedef struct cp_bsq_entry { 233*1da177e4SLinus Torvalds u32 rbd_block_haddr; /* host DMA address of rbd block */ 234*1da177e4SLinus Torvalds u32 status_haddr; /* host DMA address of completion status */ 235*1da177e4SLinus Torvalds } cp_bsq_entry_t; 236*1da177e4SLinus Torvalds 237*1da177e4SLinus Torvalds 238*1da177e4SLinus Torvalds /* completion status */ 239*1da177e4SLinus Torvalds 240*1da177e4SLinus Torvalds typedef volatile enum status { 241*1da177e4SLinus Torvalds STATUS_PENDING = (1<<0), /* initial status (written by host) */ 242*1da177e4SLinus Torvalds STATUS_COMPLETE = (1<<1), /* completion status (written by cp) */ 243*1da177e4SLinus Torvalds STATUS_FREE = (1<<2), /* initial status (written by host) */ 244*1da177e4SLinus Torvalds STATUS_ERROR = (1<<3) /* completion status (written by cp) */ 245*1da177e4SLinus Torvalds } status_t; 246*1da177e4SLinus Torvalds 247*1da177e4SLinus Torvalds 248*1da177e4SLinus Torvalds /* cp operation code */ 249*1da177e4SLinus Torvalds 250*1da177e4SLinus Torvalds typedef enum opcode { 251*1da177e4SLinus Torvalds OPCODE_INITIALIZE = 1, /* initialize board */ 252*1da177e4SLinus Torvalds OPCODE_ACTIVATE_VCIN, /* activate incoming VCI */ 253*1da177e4SLinus Torvalds OPCODE_ACTIVATE_VCOUT, /* activate outgoing VCI */ 254*1da177e4SLinus Torvalds OPCODE_DEACTIVATE_VCIN, /* deactivate incoming VCI */ 255*1da177e4SLinus Torvalds OPCODE_DEACTIVATE_VCOUT, /* deactivate incoing VCI */ 256*1da177e4SLinus Torvalds OPCODE_GET_STATS, /* get board statistics */ 257*1da177e4SLinus Torvalds OPCODE_SET_OC3, /* set OC-3 registers */ 258*1da177e4SLinus Torvalds OPCODE_GET_OC3, /* get OC-3 registers */ 259*1da177e4SLinus Torvalds OPCODE_RESET_STATS, /* reset board statistics */ 260*1da177e4SLinus Torvalds OPCODE_GET_PROM, /* get expansion PROM data (PCI specific) */ 261*1da177e4SLinus Torvalds OPCODE_SET_VPI_BITS, /* set x bits of those decoded by the 262*1da177e4SLinus Torvalds firmware to be low order bits from 263*1da177e4SLinus Torvalds the VPI field of the ATM cell header */ 264*1da177e4SLinus Torvalds OPCODE_REQUEST_INTR = (1<<7) /* request interrupt */ 265*1da177e4SLinus Torvalds } opcode_t; 266*1da177e4SLinus Torvalds 267*1da177e4SLinus Torvalds 268*1da177e4SLinus Torvalds /* virtual path / virtual channel identifers */ 269*1da177e4SLinus Torvalds 270*1da177e4SLinus Torvalds typedef struct vpvc { 271*1da177e4SLinus Torvalds BITFIELD3( 272*1da177e4SLinus Torvalds u32 vci : 16, /* virtual channel identifier */ 273*1da177e4SLinus Torvalds u32 vpi : 8, /* virtual path identifier */ 274*1da177e4SLinus Torvalds u32 pad : 8 /* reserved */ 275*1da177e4SLinus Torvalds ) 276*1da177e4SLinus Torvalds } vpvc_t; 277*1da177e4SLinus Torvalds 278*1da177e4SLinus Torvalds 279*1da177e4SLinus Torvalds /* activate VC command opcode */ 280*1da177e4SLinus Torvalds 281*1da177e4SLinus Torvalds typedef struct activate_opcode { 282*1da177e4SLinus Torvalds BITFIELD4( 283*1da177e4SLinus Torvalds enum opcode opcode : 8, /* cp opcode */ 284*1da177e4SLinus Torvalds enum fore200e_aal aal : 8, /* adaptation layer */ 285*1da177e4SLinus Torvalds enum buffer_scheme scheme : 8, /* buffer scheme */ 286*1da177e4SLinus Torvalds u32 pad : 8 /* reserved */ 287*1da177e4SLinus Torvalds ) 288*1da177e4SLinus Torvalds } activate_opcode_t; 289*1da177e4SLinus Torvalds 290*1da177e4SLinus Torvalds 291*1da177e4SLinus Torvalds /* activate VC command block */ 292*1da177e4SLinus Torvalds 293*1da177e4SLinus Torvalds typedef struct activate_block { 294*1da177e4SLinus Torvalds struct activate_opcode opcode; /* activate VC command opcode */ 295*1da177e4SLinus Torvalds struct vpvc vpvc; /* VPI/VCI */ 296*1da177e4SLinus Torvalds u32 mtu; /* for AAL0 only */ 297*1da177e4SLinus Torvalds 298*1da177e4SLinus Torvalds } activate_block_t; 299*1da177e4SLinus Torvalds 300*1da177e4SLinus Torvalds 301*1da177e4SLinus Torvalds /* deactivate VC command opcode */ 302*1da177e4SLinus Torvalds 303*1da177e4SLinus Torvalds typedef struct deactivate_opcode { 304*1da177e4SLinus Torvalds BITFIELD2( 305*1da177e4SLinus Torvalds enum opcode opcode : 8, /* cp opcode */ 306*1da177e4SLinus Torvalds u32 pad : 24 /* reserved */ 307*1da177e4SLinus Torvalds ) 308*1da177e4SLinus Torvalds } deactivate_opcode_t; 309*1da177e4SLinus Torvalds 310*1da177e4SLinus Torvalds 311*1da177e4SLinus Torvalds /* deactivate VC command block */ 312*1da177e4SLinus Torvalds 313*1da177e4SLinus Torvalds typedef struct deactivate_block { 314*1da177e4SLinus Torvalds struct deactivate_opcode opcode; /* deactivate VC command opcode */ 315*1da177e4SLinus Torvalds struct vpvc vpvc; /* VPI/VCI */ 316*1da177e4SLinus Torvalds } deactivate_block_t; 317*1da177e4SLinus Torvalds 318*1da177e4SLinus Torvalds 319*1da177e4SLinus Torvalds /* OC-3 registers */ 320*1da177e4SLinus Torvalds 321*1da177e4SLinus Torvalds typedef struct oc3_regs { 322*1da177e4SLinus Torvalds u32 reg[ 128 ]; /* see the PMC Sierra PC5346 S/UNI-155-Lite 323*1da177e4SLinus Torvalds Saturn User Network Interface documentation 324*1da177e4SLinus Torvalds for a description of the OC-3 chip registers */ 325*1da177e4SLinus Torvalds } oc3_regs_t; 326*1da177e4SLinus Torvalds 327*1da177e4SLinus Torvalds 328*1da177e4SLinus Torvalds /* set/get OC-3 regs command opcode */ 329*1da177e4SLinus Torvalds 330*1da177e4SLinus Torvalds typedef struct oc3_opcode { 331*1da177e4SLinus Torvalds BITFIELD4( 332*1da177e4SLinus Torvalds enum opcode opcode : 8, /* cp opcode */ 333*1da177e4SLinus Torvalds u32 reg : 8, /* register index */ 334*1da177e4SLinus Torvalds u32 value : 8, /* register value */ 335*1da177e4SLinus Torvalds u32 mask : 8 /* register mask that specifies which 336*1da177e4SLinus Torvalds bits of the register value field 337*1da177e4SLinus Torvalds are significant */ 338*1da177e4SLinus Torvalds ) 339*1da177e4SLinus Torvalds } oc3_opcode_t; 340*1da177e4SLinus Torvalds 341*1da177e4SLinus Torvalds 342*1da177e4SLinus Torvalds /* set/get OC-3 regs command block */ 343*1da177e4SLinus Torvalds 344*1da177e4SLinus Torvalds typedef struct oc3_block { 345*1da177e4SLinus Torvalds struct oc3_opcode opcode; /* set/get OC-3 regs command opcode */ 346*1da177e4SLinus Torvalds u32 regs_haddr; /* host DMA address of OC-3 regs buffer */ 347*1da177e4SLinus Torvalds } oc3_block_t; 348*1da177e4SLinus Torvalds 349*1da177e4SLinus Torvalds 350*1da177e4SLinus Torvalds /* physical encoding statistics */ 351*1da177e4SLinus Torvalds 352*1da177e4SLinus Torvalds typedef struct stats_phy { 353*1da177e4SLinus Torvalds u32 crc_header_errors; /* cells received with bad header CRC */ 354*1da177e4SLinus Torvalds u32 framing_errors; /* cells received with bad framing */ 355*1da177e4SLinus Torvalds u32 pad[ 2 ]; /* i960 padding */ 356*1da177e4SLinus Torvalds } stats_phy_t; 357*1da177e4SLinus Torvalds 358*1da177e4SLinus Torvalds 359*1da177e4SLinus Torvalds /* OC-3 statistics */ 360*1da177e4SLinus Torvalds 361*1da177e4SLinus Torvalds typedef struct stats_oc3 { 362*1da177e4SLinus Torvalds u32 section_bip8_errors; /* section 8 bit interleaved parity */ 363*1da177e4SLinus Torvalds u32 path_bip8_errors; /* path 8 bit interleaved parity */ 364*1da177e4SLinus Torvalds u32 line_bip24_errors; /* line 24 bit interleaved parity */ 365*1da177e4SLinus Torvalds u32 line_febe_errors; /* line far end block errors */ 366*1da177e4SLinus Torvalds u32 path_febe_errors; /* path far end block errors */ 367*1da177e4SLinus Torvalds u32 corr_hcs_errors; /* correctable header check sequence */ 368*1da177e4SLinus Torvalds u32 ucorr_hcs_errors; /* uncorrectable header check sequence */ 369*1da177e4SLinus Torvalds u32 pad[ 1 ]; /* i960 padding */ 370*1da177e4SLinus Torvalds } stats_oc3_t; 371*1da177e4SLinus Torvalds 372*1da177e4SLinus Torvalds 373*1da177e4SLinus Torvalds /* ATM statistics */ 374*1da177e4SLinus Torvalds 375*1da177e4SLinus Torvalds typedef struct stats_atm { 376*1da177e4SLinus Torvalds u32 cells_transmitted; /* cells transmitted */ 377*1da177e4SLinus Torvalds u32 cells_received; /* cells received */ 378*1da177e4SLinus Torvalds u32 vpi_bad_range; /* cell drops: VPI out of range */ 379*1da177e4SLinus Torvalds u32 vpi_no_conn; /* cell drops: no connection for VPI */ 380*1da177e4SLinus Torvalds u32 vci_bad_range; /* cell drops: VCI out of range */ 381*1da177e4SLinus Torvalds u32 vci_no_conn; /* cell drops: no connection for VCI */ 382*1da177e4SLinus Torvalds u32 pad[ 2 ]; /* i960 padding */ 383*1da177e4SLinus Torvalds } stats_atm_t; 384*1da177e4SLinus Torvalds 385*1da177e4SLinus Torvalds /* AAL0 statistics */ 386*1da177e4SLinus Torvalds 387*1da177e4SLinus Torvalds typedef struct stats_aal0 { 388*1da177e4SLinus Torvalds u32 cells_transmitted; /* cells transmitted */ 389*1da177e4SLinus Torvalds u32 cells_received; /* cells received */ 390*1da177e4SLinus Torvalds u32 cells_dropped; /* cells dropped */ 391*1da177e4SLinus Torvalds u32 pad[ 1 ]; /* i960 padding */ 392*1da177e4SLinus Torvalds } stats_aal0_t; 393*1da177e4SLinus Torvalds 394*1da177e4SLinus Torvalds 395*1da177e4SLinus Torvalds /* AAL3/4 statistics */ 396*1da177e4SLinus Torvalds 397*1da177e4SLinus Torvalds typedef struct stats_aal34 { 398*1da177e4SLinus Torvalds u32 cells_transmitted; /* cells transmitted from segmented PDUs */ 399*1da177e4SLinus Torvalds u32 cells_received; /* cells reassembled into PDUs */ 400*1da177e4SLinus Torvalds u32 cells_crc_errors; /* payload CRC error count */ 401*1da177e4SLinus Torvalds u32 cells_protocol_errors; /* SAR or CS layer protocol errors */ 402*1da177e4SLinus Torvalds u32 cells_dropped; /* cells dropped: partial reassembly */ 403*1da177e4SLinus Torvalds u32 cspdus_transmitted; /* CS PDUs transmitted */ 404*1da177e4SLinus Torvalds u32 cspdus_received; /* CS PDUs received */ 405*1da177e4SLinus Torvalds u32 cspdus_protocol_errors; /* CS layer protocol errors */ 406*1da177e4SLinus Torvalds u32 cspdus_dropped; /* reassembled PDUs drop'd (in cells) */ 407*1da177e4SLinus Torvalds u32 pad[ 3 ]; /* i960 padding */ 408*1da177e4SLinus Torvalds } stats_aal34_t; 409*1da177e4SLinus Torvalds 410*1da177e4SLinus Torvalds 411*1da177e4SLinus Torvalds /* AAL5 statistics */ 412*1da177e4SLinus Torvalds 413*1da177e4SLinus Torvalds typedef struct stats_aal5 { 414*1da177e4SLinus Torvalds u32 cells_transmitted; /* cells transmitted from segmented SDUs */ 415*1da177e4SLinus Torvalds u32 cells_received; /* cells reassembled into SDUs */ 416*1da177e4SLinus Torvalds u32 cells_dropped; /* reassembled PDUs dropped (in cells) */ 417*1da177e4SLinus Torvalds u32 congestion_experienced; /* CRC error and length wrong */ 418*1da177e4SLinus Torvalds u32 cspdus_transmitted; /* CS PDUs transmitted */ 419*1da177e4SLinus Torvalds u32 cspdus_received; /* CS PDUs received */ 420*1da177e4SLinus Torvalds u32 cspdus_crc_errors; /* CS PDUs CRC errors */ 421*1da177e4SLinus Torvalds u32 cspdus_protocol_errors; /* CS layer protocol errors */ 422*1da177e4SLinus Torvalds u32 cspdus_dropped; /* reassembled PDUs dropped */ 423*1da177e4SLinus Torvalds u32 pad[ 3 ]; /* i960 padding */ 424*1da177e4SLinus Torvalds } stats_aal5_t; 425*1da177e4SLinus Torvalds 426*1da177e4SLinus Torvalds 427*1da177e4SLinus Torvalds /* auxiliary statistics */ 428*1da177e4SLinus Torvalds 429*1da177e4SLinus Torvalds typedef struct stats_aux { 430*1da177e4SLinus Torvalds u32 small_b1_failed; /* receive BD allocation failures */ 431*1da177e4SLinus Torvalds u32 large_b1_failed; /* receive BD allocation failures */ 432*1da177e4SLinus Torvalds u32 small_b2_failed; /* receive BD allocation failures */ 433*1da177e4SLinus Torvalds u32 large_b2_failed; /* receive BD allocation failures */ 434*1da177e4SLinus Torvalds u32 rpd_alloc_failed; /* receive PDU allocation failures */ 435*1da177e4SLinus Torvalds u32 receive_carrier; /* no carrier = 0, carrier = 1 */ 436*1da177e4SLinus Torvalds u32 pad[ 2 ]; /* i960 padding */ 437*1da177e4SLinus Torvalds } stats_aux_t; 438*1da177e4SLinus Torvalds 439*1da177e4SLinus Torvalds 440*1da177e4SLinus Torvalds /* whole statistics buffer */ 441*1da177e4SLinus Torvalds 442*1da177e4SLinus Torvalds typedef struct stats { 443*1da177e4SLinus Torvalds struct stats_phy phy; /* physical encoding statistics */ 444*1da177e4SLinus Torvalds struct stats_oc3 oc3; /* OC-3 statistics */ 445*1da177e4SLinus Torvalds struct stats_atm atm; /* ATM statistics */ 446*1da177e4SLinus Torvalds struct stats_aal0 aal0; /* AAL0 statistics */ 447*1da177e4SLinus Torvalds struct stats_aal34 aal34; /* AAL3/4 statistics */ 448*1da177e4SLinus Torvalds struct stats_aal5 aal5; /* AAL5 statistics */ 449*1da177e4SLinus Torvalds struct stats_aux aux; /* auxiliary statistics */ 450*1da177e4SLinus Torvalds } stats_t; 451*1da177e4SLinus Torvalds 452*1da177e4SLinus Torvalds 453*1da177e4SLinus Torvalds /* get statistics command opcode */ 454*1da177e4SLinus Torvalds 455*1da177e4SLinus Torvalds typedef struct stats_opcode { 456*1da177e4SLinus Torvalds BITFIELD2( 457*1da177e4SLinus Torvalds enum opcode opcode : 8, /* cp opcode */ 458*1da177e4SLinus Torvalds u32 pad : 24 /* reserved */ 459*1da177e4SLinus Torvalds ) 460*1da177e4SLinus Torvalds } stats_opcode_t; 461*1da177e4SLinus Torvalds 462*1da177e4SLinus Torvalds 463*1da177e4SLinus Torvalds /* get statistics command block */ 464*1da177e4SLinus Torvalds 465*1da177e4SLinus Torvalds typedef struct stats_block { 466*1da177e4SLinus Torvalds struct stats_opcode opcode; /* get statistics command opcode */ 467*1da177e4SLinus Torvalds u32 stats_haddr; /* host DMA address of stats buffer */ 468*1da177e4SLinus Torvalds } stats_block_t; 469*1da177e4SLinus Torvalds 470*1da177e4SLinus Torvalds 471*1da177e4SLinus Torvalds /* expansion PROM data (PCI specific) */ 472*1da177e4SLinus Torvalds 473*1da177e4SLinus Torvalds typedef struct prom_data { 474*1da177e4SLinus Torvalds u32 hw_revision; /* hardware revision */ 475*1da177e4SLinus Torvalds u32 serial_number; /* board serial number */ 476*1da177e4SLinus Torvalds u8 mac_addr[ 8 ]; /* board MAC address */ 477*1da177e4SLinus Torvalds } prom_data_t; 478*1da177e4SLinus Torvalds 479*1da177e4SLinus Torvalds 480*1da177e4SLinus Torvalds /* get expansion PROM data command opcode */ 481*1da177e4SLinus Torvalds 482*1da177e4SLinus Torvalds typedef struct prom_opcode { 483*1da177e4SLinus Torvalds BITFIELD2( 484*1da177e4SLinus Torvalds enum opcode opcode : 8, /* cp opcode */ 485*1da177e4SLinus Torvalds u32 pad : 24 /* reserved */ 486*1da177e4SLinus Torvalds ) 487*1da177e4SLinus Torvalds } prom_opcode_t; 488*1da177e4SLinus Torvalds 489*1da177e4SLinus Torvalds 490*1da177e4SLinus Torvalds /* get expansion PROM data command block */ 491*1da177e4SLinus Torvalds 492*1da177e4SLinus Torvalds typedef struct prom_block { 493*1da177e4SLinus Torvalds struct prom_opcode opcode; /* get PROM data command opcode */ 494*1da177e4SLinus Torvalds u32 prom_haddr; /* host DMA address of PROM buffer */ 495*1da177e4SLinus Torvalds } prom_block_t; 496*1da177e4SLinus Torvalds 497*1da177e4SLinus Torvalds 498*1da177e4SLinus Torvalds /* cp command */ 499*1da177e4SLinus Torvalds 500*1da177e4SLinus Torvalds typedef union cmd { 501*1da177e4SLinus Torvalds enum opcode opcode; /* operation code */ 502*1da177e4SLinus Torvalds struct activate_block activate_block; /* activate VC */ 503*1da177e4SLinus Torvalds struct deactivate_block deactivate_block; /* deactivate VC */ 504*1da177e4SLinus Torvalds struct stats_block stats_block; /* get statistics */ 505*1da177e4SLinus Torvalds struct prom_block prom_block; /* get expansion PROM data */ 506*1da177e4SLinus Torvalds struct oc3_block oc3_block; /* get/set OC-3 registers */ 507*1da177e4SLinus Torvalds u32 pad[ 4 ]; /* i960 padding */ 508*1da177e4SLinus Torvalds } cmd_t; 509*1da177e4SLinus Torvalds 510*1da177e4SLinus Torvalds 511*1da177e4SLinus Torvalds /* cp resident command queue */ 512*1da177e4SLinus Torvalds 513*1da177e4SLinus Torvalds typedef struct cp_cmdq_entry { 514*1da177e4SLinus Torvalds union cmd cmd; /* command */ 515*1da177e4SLinus Torvalds u32 status_haddr; /* host DMA address of completion status */ 516*1da177e4SLinus Torvalds u32 pad[ 3 ]; /* i960 padding */ 517*1da177e4SLinus Torvalds } cp_cmdq_entry_t; 518*1da177e4SLinus Torvalds 519*1da177e4SLinus Torvalds 520*1da177e4SLinus Torvalds /* host resident transmit queue entry */ 521*1da177e4SLinus Torvalds 522*1da177e4SLinus Torvalds typedef struct host_txq_entry { 523*1da177e4SLinus Torvalds struct cp_txq_entry __iomem *cp_entry; /* addr of cp resident tx queue entry */ 524*1da177e4SLinus Torvalds enum status* status; /* addr of host resident status */ 525*1da177e4SLinus Torvalds struct tpd* tpd; /* addr of transmit PDU descriptor */ 526*1da177e4SLinus Torvalds u32 tpd_dma; /* DMA address of tpd */ 527*1da177e4SLinus Torvalds struct sk_buff* skb; /* related skb */ 528*1da177e4SLinus Torvalds void* data; /* copy of misaligned data */ 529*1da177e4SLinus Torvalds unsigned long incarn; /* vc_map incarnation when submitted for tx */ 530*1da177e4SLinus Torvalds struct fore200e_vc_map* vc_map; 531*1da177e4SLinus Torvalds 532*1da177e4SLinus Torvalds } host_txq_entry_t; 533*1da177e4SLinus Torvalds 534*1da177e4SLinus Torvalds 535*1da177e4SLinus Torvalds /* host resident receive queue entry */ 536*1da177e4SLinus Torvalds 537*1da177e4SLinus Torvalds typedef struct host_rxq_entry { 538*1da177e4SLinus Torvalds struct cp_rxq_entry __iomem *cp_entry; /* addr of cp resident rx queue entry */ 539*1da177e4SLinus Torvalds enum status* status; /* addr of host resident status */ 540*1da177e4SLinus Torvalds struct rpd* rpd; /* addr of receive PDU descriptor */ 541*1da177e4SLinus Torvalds u32 rpd_dma; /* DMA address of rpd */ 542*1da177e4SLinus Torvalds } host_rxq_entry_t; 543*1da177e4SLinus Torvalds 544*1da177e4SLinus Torvalds 545*1da177e4SLinus Torvalds /* host resident buffer supply queue entry */ 546*1da177e4SLinus Torvalds 547*1da177e4SLinus Torvalds typedef struct host_bsq_entry { 548*1da177e4SLinus Torvalds struct cp_bsq_entry __iomem *cp_entry; /* addr of cp resident buffer supply queue entry */ 549*1da177e4SLinus Torvalds enum status* status; /* addr of host resident status */ 550*1da177e4SLinus Torvalds struct rbd_block* rbd_block; /* addr of receive buffer descriptor block */ 551*1da177e4SLinus Torvalds u32 rbd_block_dma; /* DMA address od rdb */ 552*1da177e4SLinus Torvalds } host_bsq_entry_t; 553*1da177e4SLinus Torvalds 554*1da177e4SLinus Torvalds 555*1da177e4SLinus Torvalds /* host resident command queue entry */ 556*1da177e4SLinus Torvalds 557*1da177e4SLinus Torvalds typedef struct host_cmdq_entry { 558*1da177e4SLinus Torvalds struct cp_cmdq_entry __iomem *cp_entry; /* addr of cp resident cmd queue entry */ 559*1da177e4SLinus Torvalds enum status *status; /* addr of host resident status */ 560*1da177e4SLinus Torvalds } host_cmdq_entry_t; 561*1da177e4SLinus Torvalds 562*1da177e4SLinus Torvalds 563*1da177e4SLinus Torvalds /* chunk of memory */ 564*1da177e4SLinus Torvalds 565*1da177e4SLinus Torvalds typedef struct chunk { 566*1da177e4SLinus Torvalds void* alloc_addr; /* base address of allocated chunk */ 567*1da177e4SLinus Torvalds void* align_addr; /* base address of aligned chunk */ 568*1da177e4SLinus Torvalds dma_addr_t dma_addr; /* DMA address of aligned chunk */ 569*1da177e4SLinus Torvalds int direction; /* direction of DMA mapping */ 570*1da177e4SLinus Torvalds u32 alloc_size; /* length of allocated chunk */ 571*1da177e4SLinus Torvalds u32 align_size; /* length of aligned chunk */ 572*1da177e4SLinus Torvalds } chunk_t; 573*1da177e4SLinus Torvalds 574*1da177e4SLinus Torvalds #define dma_size align_size /* DMA useable size */ 575*1da177e4SLinus Torvalds 576*1da177e4SLinus Torvalds 577*1da177e4SLinus Torvalds /* host resident receive buffer */ 578*1da177e4SLinus Torvalds 579*1da177e4SLinus Torvalds typedef struct buffer { 580*1da177e4SLinus Torvalds struct buffer* next; /* next receive buffer */ 581*1da177e4SLinus Torvalds enum buffer_scheme scheme; /* buffer scheme */ 582*1da177e4SLinus Torvalds enum buffer_magn magn; /* buffer magnitude */ 583*1da177e4SLinus Torvalds struct chunk data; /* data buffer */ 584*1da177e4SLinus Torvalds #ifdef FORE200E_BSQ_DEBUG 585*1da177e4SLinus Torvalds unsigned long index; /* buffer # in queue */ 586*1da177e4SLinus Torvalds int supplied; /* 'buffer supplied' flag */ 587*1da177e4SLinus Torvalds #endif 588*1da177e4SLinus Torvalds } buffer_t; 589*1da177e4SLinus Torvalds 590*1da177e4SLinus Torvalds 591*1da177e4SLinus Torvalds #if (BITS_PER_LONG == 32) 592*1da177e4SLinus Torvalds #define FORE200E_BUF2HDL(buffer) ((u32)(buffer)) 593*1da177e4SLinus Torvalds #define FORE200E_HDL2BUF(handle) ((struct buffer*)(handle)) 594*1da177e4SLinus Torvalds #else /* deal with 64 bit pointers */ 595*1da177e4SLinus Torvalds #define FORE200E_BUF2HDL(buffer) ((u32)((u64)(buffer))) 596*1da177e4SLinus Torvalds #define FORE200E_HDL2BUF(handle) ((struct buffer*)(((u64)(handle)) | PAGE_OFFSET)) 597*1da177e4SLinus Torvalds #endif 598*1da177e4SLinus Torvalds 599*1da177e4SLinus Torvalds 600*1da177e4SLinus Torvalds /* host resident command queue */ 601*1da177e4SLinus Torvalds 602*1da177e4SLinus Torvalds typedef struct host_cmdq { 603*1da177e4SLinus Torvalds struct host_cmdq_entry host_entry[ QUEUE_SIZE_CMD ]; /* host resident cmd queue entries */ 604*1da177e4SLinus Torvalds int head; /* head of cmd queue */ 605*1da177e4SLinus Torvalds struct chunk status; /* array of completion status */ 606*1da177e4SLinus Torvalds } host_cmdq_t; 607*1da177e4SLinus Torvalds 608*1da177e4SLinus Torvalds 609*1da177e4SLinus Torvalds /* host resident transmit queue */ 610*1da177e4SLinus Torvalds 611*1da177e4SLinus Torvalds typedef struct host_txq { 612*1da177e4SLinus Torvalds struct host_txq_entry host_entry[ QUEUE_SIZE_TX ]; /* host resident tx queue entries */ 613*1da177e4SLinus Torvalds int head; /* head of tx queue */ 614*1da177e4SLinus Torvalds int tail; /* tail of tx queue */ 615*1da177e4SLinus Torvalds struct chunk tpd; /* array of tpds */ 616*1da177e4SLinus Torvalds struct chunk status; /* arry of completion status */ 617*1da177e4SLinus Torvalds int txing; /* number of pending PDUs in tx queue */ 618*1da177e4SLinus Torvalds } host_txq_t; 619*1da177e4SLinus Torvalds 620*1da177e4SLinus Torvalds 621*1da177e4SLinus Torvalds /* host resident receive queue */ 622*1da177e4SLinus Torvalds 623*1da177e4SLinus Torvalds typedef struct host_rxq { 624*1da177e4SLinus Torvalds struct host_rxq_entry host_entry[ QUEUE_SIZE_RX ]; /* host resident rx queue entries */ 625*1da177e4SLinus Torvalds int head; /* head of rx queue */ 626*1da177e4SLinus Torvalds struct chunk rpd; /* array of rpds */ 627*1da177e4SLinus Torvalds struct chunk status; /* array of completion status */ 628*1da177e4SLinus Torvalds } host_rxq_t; 629*1da177e4SLinus Torvalds 630*1da177e4SLinus Torvalds 631*1da177e4SLinus Torvalds /* host resident buffer supply queues */ 632*1da177e4SLinus Torvalds 633*1da177e4SLinus Torvalds typedef struct host_bsq { 634*1da177e4SLinus Torvalds struct host_bsq_entry host_entry[ QUEUE_SIZE_BS ]; /* host resident buffer supply queue entries */ 635*1da177e4SLinus Torvalds int head; /* head of buffer supply queue */ 636*1da177e4SLinus Torvalds struct chunk rbd_block; /* array of rbds */ 637*1da177e4SLinus Torvalds struct chunk status; /* array of completion status */ 638*1da177e4SLinus Torvalds struct buffer* buffer; /* array of rx buffers */ 639*1da177e4SLinus Torvalds struct buffer* freebuf; /* list of free rx buffers */ 640*1da177e4SLinus Torvalds volatile int freebuf_count; /* count of free rx buffers */ 641*1da177e4SLinus Torvalds } host_bsq_t; 642*1da177e4SLinus Torvalds 643*1da177e4SLinus Torvalds 644*1da177e4SLinus Torvalds /* header of the firmware image */ 645*1da177e4SLinus Torvalds 646*1da177e4SLinus Torvalds typedef struct fw_header { 647*1da177e4SLinus Torvalds u32 magic; /* magic number */ 648*1da177e4SLinus Torvalds u32 version; /* firmware version id */ 649*1da177e4SLinus Torvalds u32 load_offset; /* fw load offset in board memory */ 650*1da177e4SLinus Torvalds u32 start_offset; /* fw execution start address in board memory */ 651*1da177e4SLinus Torvalds } fw_header_t; 652*1da177e4SLinus Torvalds 653*1da177e4SLinus Torvalds #define FW_HEADER_MAGIC 0x65726f66 /* 'fore' */ 654*1da177e4SLinus Torvalds 655*1da177e4SLinus Torvalds 656*1da177e4SLinus Torvalds /* receive buffer supply queues scheme specification */ 657*1da177e4SLinus Torvalds 658*1da177e4SLinus Torvalds typedef struct bs_spec { 659*1da177e4SLinus Torvalds u32 queue_length; /* queue capacity */ 660*1da177e4SLinus Torvalds u32 buffer_size; /* host buffer size */ 661*1da177e4SLinus Torvalds u32 pool_size; /* number of rbds */ 662*1da177e4SLinus Torvalds u32 supply_blksize; /* num of rbds in I/O block (multiple 663*1da177e4SLinus Torvalds of 4 between 4 and 124 inclusive) */ 664*1da177e4SLinus Torvalds } bs_spec_t; 665*1da177e4SLinus Torvalds 666*1da177e4SLinus Torvalds 667*1da177e4SLinus Torvalds /* initialization command block (one-time command, not in cmd queue) */ 668*1da177e4SLinus Torvalds 669*1da177e4SLinus Torvalds typedef struct init_block { 670*1da177e4SLinus Torvalds enum opcode opcode; /* initialize command */ 671*1da177e4SLinus Torvalds enum status status; /* related status word */ 672*1da177e4SLinus Torvalds u32 receive_threshold; /* not used */ 673*1da177e4SLinus Torvalds u32 num_connect; /* ATM connections */ 674*1da177e4SLinus Torvalds u32 cmd_queue_len; /* length of command queue */ 675*1da177e4SLinus Torvalds u32 tx_queue_len; /* length of transmit queue */ 676*1da177e4SLinus Torvalds u32 rx_queue_len; /* length of receive queue */ 677*1da177e4SLinus Torvalds u32 rsd_extension; /* number of extra 32 byte blocks */ 678*1da177e4SLinus Torvalds u32 tsd_extension; /* number of extra 32 byte blocks */ 679*1da177e4SLinus Torvalds u32 conless_vpvc; /* not used */ 680*1da177e4SLinus Torvalds u32 pad[ 2 ]; /* force quad alignment */ 681*1da177e4SLinus Torvalds struct bs_spec bs_spec[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues spec */ 682*1da177e4SLinus Torvalds } init_block_t; 683*1da177e4SLinus Torvalds 684*1da177e4SLinus Torvalds 685*1da177e4SLinus Torvalds typedef enum media_type { 686*1da177e4SLinus Torvalds MEDIA_TYPE_CAT5_UTP = 0x06, /* unshielded twisted pair */ 687*1da177e4SLinus Torvalds MEDIA_TYPE_MM_OC3_ST = 0x16, /* multimode fiber ST */ 688*1da177e4SLinus Torvalds MEDIA_TYPE_MM_OC3_SC = 0x26, /* multimode fiber SC */ 689*1da177e4SLinus Torvalds MEDIA_TYPE_SM_OC3_ST = 0x36, /* single-mode fiber ST */ 690*1da177e4SLinus Torvalds MEDIA_TYPE_SM_OC3_SC = 0x46 /* single-mode fiber SC */ 691*1da177e4SLinus Torvalds } media_type_t; 692*1da177e4SLinus Torvalds 693*1da177e4SLinus Torvalds #define FORE200E_MEDIA_INDEX(media_type) ((media_type)>>4) 694*1da177e4SLinus Torvalds 695*1da177e4SLinus Torvalds 696*1da177e4SLinus Torvalds /* cp resident queues */ 697*1da177e4SLinus Torvalds 698*1da177e4SLinus Torvalds typedef struct cp_queues { 699*1da177e4SLinus Torvalds u32 cp_cmdq; /* command queue */ 700*1da177e4SLinus Torvalds u32 cp_txq; /* transmit queue */ 701*1da177e4SLinus Torvalds u32 cp_rxq; /* receive queue */ 702*1da177e4SLinus Torvalds u32 cp_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; /* buffer supply queues */ 703*1da177e4SLinus Torvalds u32 imask; /* 1 enables cp to host interrupts */ 704*1da177e4SLinus Torvalds u32 istat; /* 1 for interrupt posted */ 705*1da177e4SLinus Torvalds u32 heap_base; /* offset form beginning of ram */ 706*1da177e4SLinus Torvalds u32 heap_size; /* space available for queues */ 707*1da177e4SLinus Torvalds u32 hlogger; /* non zero for host logging */ 708*1da177e4SLinus Torvalds u32 heartbeat; /* cp heartbeat */ 709*1da177e4SLinus Torvalds u32 fw_release; /* firmware version */ 710*1da177e4SLinus Torvalds u32 mon960_release; /* i960 monitor version */ 711*1da177e4SLinus Torvalds u32 tq_plen; /* transmit throughput measurements */ 712*1da177e4SLinus Torvalds /* make sure the init block remains on a quad word boundary */ 713*1da177e4SLinus Torvalds struct init_block init; /* one time cmd, not in cmd queue */ 714*1da177e4SLinus Torvalds enum media_type media_type; /* media type id */ 715*1da177e4SLinus Torvalds u32 oc3_revision; /* OC-3 revision number */ 716*1da177e4SLinus Torvalds } cp_queues_t; 717*1da177e4SLinus Torvalds 718*1da177e4SLinus Torvalds 719*1da177e4SLinus Torvalds /* boot status */ 720*1da177e4SLinus Torvalds 721*1da177e4SLinus Torvalds typedef enum boot_status { 722*1da177e4SLinus Torvalds BSTAT_COLD_START = (u32) 0xc01dc01d, /* cold start */ 723*1da177e4SLinus Torvalds BSTAT_SELFTEST_OK = (u32) 0x02201958, /* self-test ok */ 724*1da177e4SLinus Torvalds BSTAT_SELFTEST_FAIL = (u32) 0xadbadbad, /* self-test failed */ 725*1da177e4SLinus Torvalds BSTAT_CP_RUNNING = (u32) 0xce11feed, /* cp is running */ 726*1da177e4SLinus Torvalds BSTAT_MON_TOO_BIG = (u32) 0x10aded00 /* i960 monitor is too big */ 727*1da177e4SLinus Torvalds } boot_status_t; 728*1da177e4SLinus Torvalds 729*1da177e4SLinus Torvalds 730*1da177e4SLinus Torvalds /* software UART */ 731*1da177e4SLinus Torvalds 732*1da177e4SLinus Torvalds typedef struct soft_uart { 733*1da177e4SLinus Torvalds u32 send; /* write register */ 734*1da177e4SLinus Torvalds u32 recv; /* read register */ 735*1da177e4SLinus Torvalds } soft_uart_t; 736*1da177e4SLinus Torvalds 737*1da177e4SLinus Torvalds #define FORE200E_CP_MONITOR_UART_FREE 0x00000000 738*1da177e4SLinus Torvalds #define FORE200E_CP_MONITOR_UART_AVAIL 0x01000000 739*1da177e4SLinus Torvalds 740*1da177e4SLinus Torvalds 741*1da177e4SLinus Torvalds /* i960 monitor */ 742*1da177e4SLinus Torvalds 743*1da177e4SLinus Torvalds typedef struct cp_monitor { 744*1da177e4SLinus Torvalds struct soft_uart soft_uart; /* software UART */ 745*1da177e4SLinus Torvalds enum boot_status bstat; /* boot status */ 746*1da177e4SLinus Torvalds u32 app_base; /* application base offset */ 747*1da177e4SLinus Torvalds u32 mon_version; /* i960 monitor version */ 748*1da177e4SLinus Torvalds } cp_monitor_t; 749*1da177e4SLinus Torvalds 750*1da177e4SLinus Torvalds 751*1da177e4SLinus Torvalds /* device state */ 752*1da177e4SLinus Torvalds 753*1da177e4SLinus Torvalds typedef enum fore200e_state { 754*1da177e4SLinus Torvalds FORE200E_STATE_BLANK, /* initial state */ 755*1da177e4SLinus Torvalds FORE200E_STATE_REGISTER, /* device registered */ 756*1da177e4SLinus Torvalds FORE200E_STATE_CONFIGURE, /* bus interface configured */ 757*1da177e4SLinus Torvalds FORE200E_STATE_MAP, /* board space mapped in host memory */ 758*1da177e4SLinus Torvalds FORE200E_STATE_RESET, /* board resetted */ 759*1da177e4SLinus Torvalds FORE200E_STATE_LOAD_FW, /* firmware loaded */ 760*1da177e4SLinus Torvalds FORE200E_STATE_START_FW, /* firmware started */ 761*1da177e4SLinus Torvalds FORE200E_STATE_INITIALIZE, /* initialize command successful */ 762*1da177e4SLinus Torvalds FORE200E_STATE_INIT_CMDQ, /* command queue initialized */ 763*1da177e4SLinus Torvalds FORE200E_STATE_INIT_TXQ, /* transmit queue initialized */ 764*1da177e4SLinus Torvalds FORE200E_STATE_INIT_RXQ, /* receive queue initialized */ 765*1da177e4SLinus Torvalds FORE200E_STATE_INIT_BSQ, /* buffer supply queue initialized */ 766*1da177e4SLinus Torvalds FORE200E_STATE_ALLOC_BUF, /* receive buffers allocated */ 767*1da177e4SLinus Torvalds FORE200E_STATE_IRQ, /* host interrupt requested */ 768*1da177e4SLinus Torvalds FORE200E_STATE_COMPLETE /* initialization completed */ 769*1da177e4SLinus Torvalds } fore200e_state; 770*1da177e4SLinus Torvalds 771*1da177e4SLinus Torvalds 772*1da177e4SLinus Torvalds /* PCA-200E registers */ 773*1da177e4SLinus Torvalds 774*1da177e4SLinus Torvalds typedef struct fore200e_pca_regs { 775*1da177e4SLinus Torvalds volatile u32 __iomem * hcr; /* address of host control register */ 776*1da177e4SLinus Torvalds volatile u32 __iomem * imr; /* address of host interrupt mask register */ 777*1da177e4SLinus Torvalds volatile u32 __iomem * psr; /* address of PCI specific register */ 778*1da177e4SLinus Torvalds } fore200e_pca_regs_t; 779*1da177e4SLinus Torvalds 780*1da177e4SLinus Torvalds 781*1da177e4SLinus Torvalds /* SBA-200E registers */ 782*1da177e4SLinus Torvalds 783*1da177e4SLinus Torvalds typedef struct fore200e_sba_regs { 784*1da177e4SLinus Torvalds volatile u32 __iomem *hcr; /* address of host control register */ 785*1da177e4SLinus Torvalds volatile u32 __iomem *bsr; /* address of burst transfer size register */ 786*1da177e4SLinus Torvalds volatile u32 __iomem *isr; /* address of interrupt level selection register */ 787*1da177e4SLinus Torvalds } fore200e_sba_regs_t; 788*1da177e4SLinus Torvalds 789*1da177e4SLinus Torvalds 790*1da177e4SLinus Torvalds /* model-specific registers */ 791*1da177e4SLinus Torvalds 792*1da177e4SLinus Torvalds typedef union fore200e_regs { 793*1da177e4SLinus Torvalds struct fore200e_pca_regs pca; /* PCA-200E registers */ 794*1da177e4SLinus Torvalds struct fore200e_sba_regs sba; /* SBA-200E registers */ 795*1da177e4SLinus Torvalds } fore200e_regs; 796*1da177e4SLinus Torvalds 797*1da177e4SLinus Torvalds 798*1da177e4SLinus Torvalds struct fore200e; 799*1da177e4SLinus Torvalds 800*1da177e4SLinus Torvalds /* bus-dependent data */ 801*1da177e4SLinus Torvalds 802*1da177e4SLinus Torvalds typedef struct fore200e_bus { 803*1da177e4SLinus Torvalds char* model_name; /* board model name */ 804*1da177e4SLinus Torvalds char* proc_name; /* board name under /proc/atm */ 805*1da177e4SLinus Torvalds int descr_alignment; /* tpd/rpd/rbd DMA alignment requirement */ 806*1da177e4SLinus Torvalds int buffer_alignment; /* rx buffers DMA alignment requirement */ 807*1da177e4SLinus Torvalds int status_alignment; /* status words DMA alignment requirement */ 808*1da177e4SLinus Torvalds const unsigned char* fw_data; /* address of firmware data start */ 809*1da177e4SLinus Torvalds const unsigned int* fw_size; /* address of firmware data size */ 810*1da177e4SLinus Torvalds u32 (*read)(volatile u32 __iomem *); 811*1da177e4SLinus Torvalds void (*write)(u32, volatile u32 __iomem *); 812*1da177e4SLinus Torvalds u32 (*dma_map)(struct fore200e*, void*, int, int); 813*1da177e4SLinus Torvalds void (*dma_unmap)(struct fore200e*, u32, int, int); 814*1da177e4SLinus Torvalds void (*dma_sync_for_cpu)(struct fore200e*, u32, int, int); 815*1da177e4SLinus Torvalds void (*dma_sync_for_device)(struct fore200e*, u32, int, int); 816*1da177e4SLinus Torvalds int (*dma_chunk_alloc)(struct fore200e*, struct chunk*, int, int, int); 817*1da177e4SLinus Torvalds void (*dma_chunk_free)(struct fore200e*, struct chunk*); 818*1da177e4SLinus Torvalds struct fore200e* (*detect)(const struct fore200e_bus*, int); 819*1da177e4SLinus Torvalds int (*configure)(struct fore200e*); 820*1da177e4SLinus Torvalds int (*map)(struct fore200e*); 821*1da177e4SLinus Torvalds void (*reset)(struct fore200e*); 822*1da177e4SLinus Torvalds int (*prom_read)(struct fore200e*, struct prom_data*); 823*1da177e4SLinus Torvalds void (*unmap)(struct fore200e*); 824*1da177e4SLinus Torvalds void (*irq_enable)(struct fore200e*); 825*1da177e4SLinus Torvalds int (*irq_check)(struct fore200e*); 826*1da177e4SLinus Torvalds void (*irq_ack)(struct fore200e*); 827*1da177e4SLinus Torvalds int (*proc_read)(struct fore200e*, char*); 828*1da177e4SLinus Torvalds } fore200e_bus_t; 829*1da177e4SLinus Torvalds 830*1da177e4SLinus Torvalds /* vc mapping */ 831*1da177e4SLinus Torvalds 832*1da177e4SLinus Torvalds typedef struct fore200e_vc_map { 833*1da177e4SLinus Torvalds struct atm_vcc* vcc; /* vcc entry */ 834*1da177e4SLinus Torvalds unsigned long incarn; /* vcc incarnation number */ 835*1da177e4SLinus Torvalds } fore200e_vc_map_t; 836*1da177e4SLinus Torvalds 837*1da177e4SLinus Torvalds #define FORE200E_VC_MAP(fore200e, vpi, vci) \ 838*1da177e4SLinus Torvalds (& (fore200e)->vc_map[ ((vpi) << FORE200E_VCI_BITS) | (vci) ]) 839*1da177e4SLinus Torvalds 840*1da177e4SLinus Torvalds 841*1da177e4SLinus Torvalds /* per-device data */ 842*1da177e4SLinus Torvalds 843*1da177e4SLinus Torvalds typedef struct fore200e { 844*1da177e4SLinus Torvalds struct list_head entry; /* next device */ 845*1da177e4SLinus Torvalds const struct fore200e_bus* bus; /* bus-dependent code and data */ 846*1da177e4SLinus Torvalds union fore200e_regs regs; /* bus-dependent registers */ 847*1da177e4SLinus Torvalds struct atm_dev* atm_dev; /* ATM device */ 848*1da177e4SLinus Torvalds 849*1da177e4SLinus Torvalds enum fore200e_state state; /* device state */ 850*1da177e4SLinus Torvalds 851*1da177e4SLinus Torvalds char name[16]; /* device name */ 852*1da177e4SLinus Torvalds void* bus_dev; /* bus-specific kernel data */ 853*1da177e4SLinus Torvalds int irq; /* irq number */ 854*1da177e4SLinus Torvalds unsigned long phys_base; /* physical base address */ 855*1da177e4SLinus Torvalds void __iomem * virt_base; /* virtual base address */ 856*1da177e4SLinus Torvalds 857*1da177e4SLinus Torvalds unsigned char esi[ ESI_LEN ]; /* end system identifier */ 858*1da177e4SLinus Torvalds 859*1da177e4SLinus Torvalds struct cp_monitor __iomem * cp_monitor; /* i960 monitor address */ 860*1da177e4SLinus Torvalds struct cp_queues __iomem * cp_queues; /* cp resident queues */ 861*1da177e4SLinus Torvalds struct host_cmdq host_cmdq; /* host resident cmd queue */ 862*1da177e4SLinus Torvalds struct host_txq host_txq; /* host resident tx queue */ 863*1da177e4SLinus Torvalds struct host_rxq host_rxq; /* host resident rx queue */ 864*1da177e4SLinus Torvalds /* host resident buffer supply queues */ 865*1da177e4SLinus Torvalds struct host_bsq host_bsq[ BUFFER_SCHEME_NBR ][ BUFFER_MAGN_NBR ]; 866*1da177e4SLinus Torvalds 867*1da177e4SLinus Torvalds u32 available_cell_rate; /* remaining pseudo-CBR bw on link */ 868*1da177e4SLinus Torvalds 869*1da177e4SLinus Torvalds int loop_mode; /* S/UNI loopback mode */ 870*1da177e4SLinus Torvalds 871*1da177e4SLinus Torvalds struct stats* stats; /* last snapshot of the stats */ 872*1da177e4SLinus Torvalds 873*1da177e4SLinus Torvalds struct semaphore rate_sf; /* protects rate reservation ops */ 874*1da177e4SLinus Torvalds spinlock_t q_lock; /* protects queue ops */ 875*1da177e4SLinus Torvalds #ifdef FORE200E_USE_TASKLET 876*1da177e4SLinus Torvalds struct tasklet_struct tx_tasklet; /* performs tx interrupt work */ 877*1da177e4SLinus Torvalds struct tasklet_struct rx_tasklet; /* performs rx interrupt work */ 878*1da177e4SLinus Torvalds #endif 879*1da177e4SLinus Torvalds unsigned long tx_sat; /* tx queue saturation count */ 880*1da177e4SLinus Torvalds 881*1da177e4SLinus Torvalds unsigned long incarn_count; 882*1da177e4SLinus Torvalds struct fore200e_vc_map vc_map[ NBR_CONNECT ]; /* vc mapping */ 883*1da177e4SLinus Torvalds } fore200e_t; 884*1da177e4SLinus Torvalds 885*1da177e4SLinus Torvalds 886*1da177e4SLinus Torvalds /* per-vcc data */ 887*1da177e4SLinus Torvalds 888*1da177e4SLinus Torvalds typedef struct fore200e_vcc { 889*1da177e4SLinus Torvalds enum buffer_scheme scheme; /* rx buffer scheme */ 890*1da177e4SLinus Torvalds struct tpd_rate rate; /* tx rate control data */ 891*1da177e4SLinus Torvalds int rx_min_pdu; /* size of smallest PDU received */ 892*1da177e4SLinus Torvalds int rx_max_pdu; /* size of largest PDU received */ 893*1da177e4SLinus Torvalds int tx_min_pdu; /* size of smallest PDU transmitted */ 894*1da177e4SLinus Torvalds int tx_max_pdu; /* size of largest PDU transmitted */ 895*1da177e4SLinus Torvalds unsigned long tx_pdu; /* nbr of tx pdus */ 896*1da177e4SLinus Torvalds unsigned long rx_pdu; /* nbr of rx pdus */ 897*1da177e4SLinus Torvalds } fore200e_vcc_t; 898*1da177e4SLinus Torvalds 899*1da177e4SLinus Torvalds 900*1da177e4SLinus Torvalds 901*1da177e4SLinus Torvalds /* 200E-series common memory layout */ 902*1da177e4SLinus Torvalds 903*1da177e4SLinus Torvalds #define FORE200E_CP_MONITOR_OFFSET 0x00000400 /* i960 monitor interface */ 904*1da177e4SLinus Torvalds #define FORE200E_CP_QUEUES_OFFSET 0x00004d40 /* cp resident queues */ 905*1da177e4SLinus Torvalds 906*1da177e4SLinus Torvalds 907*1da177e4SLinus Torvalds /* PCA-200E memory layout */ 908*1da177e4SLinus Torvalds 909*1da177e4SLinus Torvalds #define PCA200E_IOSPACE_LENGTH 0x00200000 910*1da177e4SLinus Torvalds 911*1da177e4SLinus Torvalds #define PCA200E_HCR_OFFSET 0x00100000 /* board control register */ 912*1da177e4SLinus Torvalds #define PCA200E_IMR_OFFSET 0x00100004 /* host IRQ mask register */ 913*1da177e4SLinus Torvalds #define PCA200E_PSR_OFFSET 0x00100008 /* PCI specific register */ 914*1da177e4SLinus Torvalds 915*1da177e4SLinus Torvalds 916*1da177e4SLinus Torvalds /* PCA-200E host control register */ 917*1da177e4SLinus Torvalds 918*1da177e4SLinus Torvalds #define PCA200E_HCR_RESET (1<<0) /* read / write */ 919*1da177e4SLinus Torvalds #define PCA200E_HCR_HOLD_LOCK (1<<1) /* read / write */ 920*1da177e4SLinus Torvalds #define PCA200E_HCR_I960FAIL (1<<2) /* read */ 921*1da177e4SLinus Torvalds #define PCA200E_HCR_INTRB (1<<2) /* write */ 922*1da177e4SLinus Torvalds #define PCA200E_HCR_HOLD_ACK (1<<3) /* read */ 923*1da177e4SLinus Torvalds #define PCA200E_HCR_INTRA (1<<3) /* write */ 924*1da177e4SLinus Torvalds #define PCA200E_HCR_OUTFULL (1<<4) /* read */ 925*1da177e4SLinus Torvalds #define PCA200E_HCR_CLRINTR (1<<4) /* write */ 926*1da177e4SLinus Torvalds #define PCA200E_HCR_ESPHOLD (1<<5) /* read */ 927*1da177e4SLinus Torvalds #define PCA200E_HCR_INFULL (1<<6) /* read */ 928*1da177e4SLinus Torvalds #define PCA200E_HCR_TESTMODE (1<<7) /* read */ 929*1da177e4SLinus Torvalds 930*1da177e4SLinus Torvalds 931*1da177e4SLinus Torvalds /* PCA-200E PCI bus interface regs (offsets in PCI config space) */ 932*1da177e4SLinus Torvalds 933*1da177e4SLinus Torvalds #define PCA200E_PCI_LATENCY 0x40 /* maximum slave latenty */ 934*1da177e4SLinus Torvalds #define PCA200E_PCI_MASTER_CTRL 0x41 /* master control */ 935*1da177e4SLinus Torvalds #define PCA200E_PCI_THRESHOLD 0x42 /* burst / continous req threshold */ 936*1da177e4SLinus Torvalds 937*1da177e4SLinus Torvalds /* PBI master control register */ 938*1da177e4SLinus Torvalds 939*1da177e4SLinus Torvalds #define PCA200E_CTRL_DIS_CACHE_RD (1<<0) /* disable cache-line reads */ 940*1da177e4SLinus Torvalds #define PCA200E_CTRL_DIS_WRT_INVAL (1<<1) /* disable writes and invalidates */ 941*1da177e4SLinus Torvalds #define PCA200E_CTRL_2_CACHE_WRT_INVAL (1<<2) /* require 2 cache-lines for writes and invalidates */ 942*1da177e4SLinus Torvalds #define PCA200E_CTRL_IGN_LAT_TIMER (1<<3) /* ignore the latency timer */ 943*1da177e4SLinus Torvalds #define PCA200E_CTRL_ENA_CONT_REQ_MODE (1<<4) /* enable continuous request mode */ 944*1da177e4SLinus Torvalds #define PCA200E_CTRL_LARGE_PCI_BURSTS (1<<5) /* force large PCI bus bursts */ 945*1da177e4SLinus Torvalds #define PCA200E_CTRL_CONVERT_ENDIAN (1<<6) /* convert endianess of slave RAM accesses */ 946*1da177e4SLinus Torvalds 947*1da177e4SLinus Torvalds 948*1da177e4SLinus Torvalds 949*1da177e4SLinus Torvalds #define SBA200E_PROM_NAME "FORE,sba-200e" /* device name in openprom tree */ 950*1da177e4SLinus Torvalds 951*1da177e4SLinus Torvalds 952*1da177e4SLinus Torvalds /* size of SBA-200E registers */ 953*1da177e4SLinus Torvalds 954*1da177e4SLinus Torvalds #define SBA200E_HCR_LENGTH 4 955*1da177e4SLinus Torvalds #define SBA200E_BSR_LENGTH 4 956*1da177e4SLinus Torvalds #define SBA200E_ISR_LENGTH 4 957*1da177e4SLinus Torvalds #define SBA200E_RAM_LENGTH 0x40000 958*1da177e4SLinus Torvalds 959*1da177e4SLinus Torvalds 960*1da177e4SLinus Torvalds /* SBA-200E SBUS burst transfer size register */ 961*1da177e4SLinus Torvalds 962*1da177e4SLinus Torvalds #define SBA200E_BSR_BURST4 0x04 963*1da177e4SLinus Torvalds #define SBA200E_BSR_BURST8 0x08 964*1da177e4SLinus Torvalds #define SBA200E_BSR_BURST16 0x10 965*1da177e4SLinus Torvalds 966*1da177e4SLinus Torvalds 967*1da177e4SLinus Torvalds /* SBA-200E host control register */ 968*1da177e4SLinus Torvalds 969*1da177e4SLinus Torvalds #define SBA200E_HCR_RESET (1<<0) /* read / write (sticky) */ 970*1da177e4SLinus Torvalds #define SBA200E_HCR_HOLD_LOCK (1<<1) /* read / write (sticky) */ 971*1da177e4SLinus Torvalds #define SBA200E_HCR_I960FAIL (1<<2) /* read */ 972*1da177e4SLinus Torvalds #define SBA200E_HCR_I960SETINTR (1<<2) /* write */ 973*1da177e4SLinus Torvalds #define SBA200E_HCR_OUTFULL (1<<3) /* read */ 974*1da177e4SLinus Torvalds #define SBA200E_HCR_INTR_CLR (1<<3) /* write */ 975*1da177e4SLinus Torvalds #define SBA200E_HCR_INTR_ENA (1<<4) /* read / write (sticky) */ 976*1da177e4SLinus Torvalds #define SBA200E_HCR_ESPHOLD (1<<5) /* read */ 977*1da177e4SLinus Torvalds #define SBA200E_HCR_INFULL (1<<6) /* read */ 978*1da177e4SLinus Torvalds #define SBA200E_HCR_TESTMODE (1<<7) /* read */ 979*1da177e4SLinus Torvalds #define SBA200E_HCR_INTR_REQ (1<<8) /* read */ 980*1da177e4SLinus Torvalds 981*1da177e4SLinus Torvalds #define SBA200E_HCR_STICKY (SBA200E_HCR_RESET | SBA200E_HCR_HOLD_LOCK | SBA200E_HCR_INTR_ENA) 982*1da177e4SLinus Torvalds 983*1da177e4SLinus Torvalds 984*1da177e4SLinus Torvalds #endif /* __KERNEL__ */ 985*1da177e4SLinus Torvalds #endif /* _FORE200E_H */ 986